Lines Matching defs:ccsr_gur
92 struct ccsr_gur { struct
93 u32 porsr1; /* POR status 1 */
94 u32 porsr2; /* POR status 2 */
95 u8 res_008[0x20-0x8];
96 u32 gpporcr1; /* General-purpose POR configuration */
97 u32 gpporcr2;
98 u32 dcfg_fusesr; /* Fuse status register */
99 u8 res_02c[0x70-0x2c];
100 u32 devdisr; /* Device disable control */
101 u32 devdisr2; /* Device disable control 2 */
102 u32 devdisr3; /* Device disable control 3 */
103 u32 devdisr4; /* Device disable control 4 */
104 u32 devdisr5; /* Device disable control 5 */
105 u8 res_084[0x94-0x84];
106 u32 coredisru; /* uppper portion for support of 64 cores */
107 u32 coredisrl; /* lower portion for support of 64 cores */
108 u8 res_09c[0xa4-0x9c];
109 u32 svr; /* System version */
110 u8 res_0a8[0xb0-0xa8];
111 u32 rstcr; /* Reset control */
112 u32 rstrqpblsr; /* Reset request preboot loader status */
113 u8 res_0b8[0xc0-0xb8];
114 u32 rstrqmr1; /* Reset request mask */
115 u8 res_0c4[0xc8-0xc4];
116 u32 rstrqsr1; /* Reset request status */
117 u8 res_0cc[0xd4-0xcc];
118 u32 rstrqwdtmrl; /* Reset request WDT mask */
119 u8 res_0d8[0xdc-0xd8];
120 u32 rstrqwdtsrl; /* Reset request WDT status */
121 u8 res_0e0[0xe4-0xe0];
122 u32 brrl; /* Boot release */
123 u8 res_0e8[0x100-0xe8];
124 u32 rcwsr[16]; /* Reset control word status */
127 u8 res_140[0x200-0x140];
128 u32 scratchrw[4]; /* Scratch Read/Write */
129 u8 res_210[0x300-0x210];
130 u32 scratchw1r[4]; /* Scratch Read (Write once) */
131 u8 res_310[0x400-0x310];
132 u32 crstsr;
133 u8 res_404[0x550-0x404];
134 u32 sataliodnr;
135 u8 res_554[0x604-0x554];
136 u32 pamubypenr;
137 u32 dmacr1;
138 u8 res_60c[0x740-0x60c]; /* add more registers when needed */
139 u32 tp_ityp[64]; /* Topology Initiator Type Register */
140 struct {
143 } tp_cluster[1]; /* Core Cluster n Topology Register */
144 u8 res_848[0xe60-0x848];
145 u32 ddrclkdr;
146 u8 res_e60[0xe68-0xe64];
147 u32 ifcclkdr;
148 u8 res_e68[0xe80-0xe6c];
149 u32 sdhcpcr;