Lines Matching refs:val
37 unsigned int val; in ddr3_mem_ctrl_init() local
51 val = (mem->impedance << CA_CK_DRVR_DS_OFFSET) | in ddr3_mem_ctrl_init()
55 writel(val, &phy0_ctrl->phy_con39); in ddr3_mem_ctrl_init()
56 writel(val, &phy1_ctrl->phy_con39); in ddr3_mem_ctrl_init()
59 val = (mem->ctrl_bstlen << PHY_CON42_CTRL_BSTLEN_SHIFT) | in ddr3_mem_ctrl_init()
61 writel(val, &phy0_ctrl->phy_con42); in ddr3_mem_ctrl_init()
62 writel(val, &phy1_ctrl->phy_con42); in ddr3_mem_ctrl_init()
89 val = (mem->ctrl_start_point << PHY_CON12_CTRL_START_POINT_SHIFT) | in ddr3_mem_ctrl_init()
93 writel(val, &phy0_ctrl->phy_con12); in ddr3_mem_ctrl_init()
94 writel(val, &phy1_ctrl->phy_con12); in ddr3_mem_ctrl_init()
97 writel(val | (mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT), in ddr3_mem_ctrl_init()
99 writel(val | (mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT), in ddr3_mem_ctrl_init()
139 val = PHY_CON0_RESET_VAL; in ddr3_mem_ctrl_init()
140 val |= P0_CMD_EN; in ddr3_mem_ctrl_init()
141 writel(val, &phy0_ctrl->phy_con0); in ddr3_mem_ctrl_init()
142 writel(val, &phy1_ctrl->phy_con0); in ddr3_mem_ctrl_init()
144 val = PHY_CON2_RESET_VAL; in ddr3_mem_ctrl_init()
145 val |= INIT_DESKEW_EN; in ddr3_mem_ctrl_init()
146 writel(val, &phy0_ctrl->phy_con2); in ddr3_mem_ctrl_init()
147 writel(val, &phy1_ctrl->phy_con2); in ddr3_mem_ctrl_init()
149 val = PHY_CON0_RESET_VAL; in ddr3_mem_ctrl_init()
150 val |= P0_CMD_EN; in ddr3_mem_ctrl_init()
151 val |= BYTE_RDLVL_EN; in ddr3_mem_ctrl_init()
152 writel(val, &phy0_ctrl->phy_con0); in ddr3_mem_ctrl_init()
153 writel(val, &phy1_ctrl->phy_con0); in ddr3_mem_ctrl_init()
155 val = (mem->ctrl_start_point << in ddr3_mem_ctrl_init()
161 writel(val, &phy0_ctrl->phy_con12); in ddr3_mem_ctrl_init()
162 writel(val, &phy1_ctrl->phy_con12); in ddr3_mem_ctrl_init()
164 val = PHY_CON2_RESET_VAL; in ddr3_mem_ctrl_init()
165 val |= INIT_DESKEW_EN; in ddr3_mem_ctrl_init()
166 val |= RDLVL_GATE_EN; in ddr3_mem_ctrl_init()
167 writel(val, &phy0_ctrl->phy_con2); in ddr3_mem_ctrl_init()
168 writel(val, &phy1_ctrl->phy_con2); in ddr3_mem_ctrl_init()
170 val = PHY_CON0_RESET_VAL; in ddr3_mem_ctrl_init()
171 val |= P0_CMD_EN; in ddr3_mem_ctrl_init()
172 val |= BYTE_RDLVL_EN; in ddr3_mem_ctrl_init()
173 val |= CTRL_SHGATE; in ddr3_mem_ctrl_init()
174 writel(val, &phy0_ctrl->phy_con0); in ddr3_mem_ctrl_init()
175 writel(val, &phy1_ctrl->phy_con0); in ddr3_mem_ctrl_init()
177 val = PHY_CON1_RESET_VAL; in ddr3_mem_ctrl_init()
178 val &= ~(CTRL_GATEDURADJ_MASK); in ddr3_mem_ctrl_init()
179 writel(val, &phy0_ctrl->phy_con1); in ddr3_mem_ctrl_init()
180 writel(val, &phy1_ctrl->phy_con1); in ddr3_mem_ctrl_init()
201 val = (mem->ctrl_start_point << in ddr3_mem_ctrl_init()
208 writel(val, &phy0_ctrl->phy_con12); in ddr3_mem_ctrl_init()
209 writel(val, &phy1_ctrl->phy_con12); in ddr3_mem_ctrl_init()
450 uint32_t val, n_lock_r, n_lock_w_phy0, n_lock_w_phy1; in ddr3_mem_ctrl_init() local
484 val = readl(&clk->mux_stat_cdrex); in ddr3_mem_ctrl_init()
485 val &= BPLL_SEL_MASK; in ddr3_mem_ctrl_init()
486 } while (val != FOUTBPLL); in ddr3_mem_ctrl_init()
491 val = readl(&phy0_ctrl->phy_con0); in ddr3_mem_ctrl_init()
492 val &= ~(PHY_CON0_CTRL_DDR_MODE_MASK << PHY_CON0_CTRL_DDR_MODE_SHIFT); in ddr3_mem_ctrl_init()
493 val |= (DDR_MODE_DDR3 << PHY_CON0_CTRL_DDR_MODE_SHIFT); in ddr3_mem_ctrl_init()
494 writel(val, &phy0_ctrl->phy_con0); in ddr3_mem_ctrl_init()
496 val = readl(&phy1_ctrl->phy_con0); in ddr3_mem_ctrl_init()
497 val &= ~(PHY_CON0_CTRL_DDR_MODE_MASK << PHY_CON0_CTRL_DDR_MODE_SHIFT); in ddr3_mem_ctrl_init()
498 val |= (DDR_MODE_DDR3 << PHY_CON0_CTRL_DDR_MODE_SHIFT); in ddr3_mem_ctrl_init()
499 writel(val, &phy1_ctrl->phy_con0); in ddr3_mem_ctrl_init()
502 val = (mem->ctrl_bstlen << PHY_CON42_CTRL_BSTLEN_SHIFT) | in ddr3_mem_ctrl_init()
504 writel(val, &phy0_ctrl->phy_con42); in ddr3_mem_ctrl_init()
505 writel(val, &phy1_ctrl->phy_con42); in ddr3_mem_ctrl_init()
507 val = readl(&phy0_ctrl->phy_con26); in ddr3_mem_ctrl_init()
508 val &= ~(T_WRDATA_EN_MASK << T_WRDATA_EN_OFFSET); in ddr3_mem_ctrl_init()
509 val |= (T_WRDATA_EN_DDR3 << T_WRDATA_EN_OFFSET); in ddr3_mem_ctrl_init()
510 writel(val, &phy0_ctrl->phy_con26); in ddr3_mem_ctrl_init()
512 val = readl(&phy1_ctrl->phy_con26); in ddr3_mem_ctrl_init()
513 val &= ~(T_WRDATA_EN_MASK << T_WRDATA_EN_OFFSET); in ddr3_mem_ctrl_init()
514 val |= (T_WRDATA_EN_DDR3 << T_WRDATA_EN_OFFSET); in ddr3_mem_ctrl_init()
515 writel(val, &phy1_ctrl->phy_con26); in ddr3_mem_ctrl_init()
521 val = (0x7 << CA_CK_DRVR_DS_OFFSET) | (0x7 << CA_CKE_DRVR_DS_OFFSET) | in ddr3_mem_ctrl_init()
523 val |= (0x7 << DA_3_DS_OFFSET) | (0x7 << DA_2_DS_OFFSET) | in ddr3_mem_ctrl_init()
525 writel(val, &phy0_ctrl->phy_con39); in ddr3_mem_ctrl_init()
526 writel(val, &phy1_ctrl->phy_con39); in ddr3_mem_ctrl_init()
537 val = readl(&phy0_ctrl->phy_con14); in ddr3_mem_ctrl_init()
538 val |= mem->phy0_pulld_dqs; in ddr3_mem_ctrl_init()
539 writel(val, &phy0_ctrl->phy_con14); in ddr3_mem_ctrl_init()
540 val = readl(&phy1_ctrl->phy_con14); in ddr3_mem_ctrl_init()
541 val |= mem->phy1_pulld_dqs; in ddr3_mem_ctrl_init()
542 writel(val, &phy1_ctrl->phy_con14); in ddr3_mem_ctrl_init()
544 val = MEM_TERM_EN | PHY_TERM_EN; in ddr3_mem_ctrl_init()
545 writel(val, &drex0->phycontrol0); in ddr3_mem_ctrl_init()
546 writel(val, &drex1->phycontrol0); in ddr3_mem_ctrl_init()
558 val = readl(&drex0->phystatus); in ddr3_mem_ctrl_init()
559 } while ((val & DFI_INIT_COMPLETE) != DFI_INIT_COMPLETE); in ddr3_mem_ctrl_init()
561 val = readl(&drex1->phystatus); in ddr3_mem_ctrl_init()
562 } while ((val & DFI_INIT_COMPLETE) != DFI_INIT_COMPLETE); in ddr3_mem_ctrl_init()
576 val = DMC_MEMBASECONFIGX_CHIP_BASE(DMC_CHIP_BASE_0) | in ddr3_mem_ctrl_init()
578 writel(val, &tzasc0->membaseconfig0); in ddr3_mem_ctrl_init()
579 writel(val, &tzasc1->membaseconfig0); in ddr3_mem_ctrl_init()
582 val = DMC_MEMBASECONFIGX_CHIP_BASE(DMC_CHIP_BASE_1) | in ddr3_mem_ctrl_init()
584 writel(val, &tzasc0->membaseconfig1); in ddr3_mem_ctrl_init()
585 writel(val, &tzasc1->membaseconfig1); in ddr3_mem_ctrl_init()
637 val = readl(&clk->gate_bus_cdrex); in ddr3_mem_ctrl_init()
639 writel(val & ~0x1, &clk->gate_bus_cdrex); in ddr3_mem_ctrl_init()
641 writel(val, &clk->gate_bus_cdrex); in ddr3_mem_ctrl_init()
649 writel(val & ~0x2, &clk->gate_bus_cdrex); in ddr3_mem_ctrl_init()
651 writel(val, &clk->gate_bus_cdrex); in ddr3_mem_ctrl_init()
671 val = readl(&power->pad_retention_dram_status); in ddr3_mem_ctrl_init()
672 } while (val != 0x1); in ddr3_mem_ctrl_init()
697 val = PHY_CON2_RESET_VAL; in ddr3_mem_ctrl_init()
698 val |= INIT_DESKEW_EN; in ddr3_mem_ctrl_init()
699 writel(val, &phy0_ctrl->phy_con2); in ddr3_mem_ctrl_init()
700 writel(val, &phy1_ctrl->phy_con2); in ddr3_mem_ctrl_init()
702 val = readl(&phy0_ctrl->phy_con1); in ddr3_mem_ctrl_init()
703 val |= (RDLVL_PASS_ADJ_VAL << RDLVL_PASS_ADJ_OFFSET); in ddr3_mem_ctrl_init()
704 writel(val, &phy0_ctrl->phy_con1); in ddr3_mem_ctrl_init()
706 val = readl(&phy1_ctrl->phy_con1); in ddr3_mem_ctrl_init()
707 val |= (RDLVL_PASS_ADJ_VAL << RDLVL_PASS_ADJ_OFFSET); in ddr3_mem_ctrl_init()
708 writel(val, &phy1_ctrl->phy_con1); in ddr3_mem_ctrl_init()
722 val = (0x3 << DIRECT_CMD_BANK_SHIFT) | 0x4; in ddr3_mem_ctrl_init()
724 writel(val | (chip << DIRECT_CMD_CHIP_SHIFT), in ddr3_mem_ctrl_init()
726 writel(val | (chip << DIRECT_CMD_CHIP_SHIFT), in ddr3_mem_ctrl_init()
736 val = readl(&phy0_ctrl->phy_con1); in ddr3_mem_ctrl_init()
737 val &= ~(CTRL_GATEDURADJ_MASK); in ddr3_mem_ctrl_init()
738 writel(val, &phy0_ctrl->phy_con1); in ddr3_mem_ctrl_init()
740 val = readl(&phy1_ctrl->phy_con1); in ddr3_mem_ctrl_init()
741 val &= ~(CTRL_GATEDURADJ_MASK); in ddr3_mem_ctrl_init()
742 writel(val, &phy1_ctrl->phy_con1); in ddr3_mem_ctrl_init()
777 val = (0x3 << DIRECT_CMD_BANK_SHIFT); in ddr3_mem_ctrl_init()
779 writel(val | (chip << DIRECT_CMD_CHIP_SHIFT), in ddr3_mem_ctrl_init()
781 writel(val | (chip << DIRECT_CMD_CHIP_SHIFT), in ddr3_mem_ctrl_init()
786 val = PHY_CON12_RESET_VAL; in ddr3_mem_ctrl_init()
787 writel((val + n_lock_w_phy0), &phy0_ctrl->phy_con12); in ddr3_mem_ctrl_init()
788 writel((val + n_lock_w_phy1), &phy1_ctrl->phy_con12); in ddr3_mem_ctrl_init()
856 val = readl(&drex0->concontrol); in ddr3_mem_ctrl_init()
857 val |= CONCONTROL_UPDATE_MODE; in ddr3_mem_ctrl_init()
858 writel(val, &drex0->concontrol); in ddr3_mem_ctrl_init()
859 val = readl(&drex1->concontrol); in ddr3_mem_ctrl_init()
860 val |= CONCONTROL_UPDATE_MODE; in ddr3_mem_ctrl_init()
861 writel(val, &drex1->concontrol); in ddr3_mem_ctrl_init()