Lines Matching refs:start
243 sc_faddr_t start, end; in get_owned_memreg() local
249 ret = sc_rm_get_memreg_info(-1, mr, &start, &end); in get_owned_memreg()
254 debug("0x%llx -- 0x%llx\n", start, end); in get_owned_memreg()
255 *addr_start = start; in get_owned_memreg()
278 sc_faddr_t start, end, end1, start_aligned; in get_effective_memsize() local
289 err = get_owned_memreg(mr, &start, &end); in get_effective_memsize()
291 start_aligned = roundup(start, MEMSTART_ALIGNMENT); in get_effective_memsize()
297 if (start >= phys_sdram_1_start && start <= end1 && in get_effective_memsize()
298 (start <= CONFIG_SYS_TEXT_BASE && in get_effective_memsize()
316 sc_faddr_t start, end, end1, end2; in dram_init() local
327 err = get_owned_memreg(mr, &start, &end); in dram_init()
329 start = roundup(start, MEMSTART_ALIGNMENT); in dram_init()
331 if (start > end) in dram_init()
334 if (start >= phys_sdram_1_start && start <= end1) { in dram_init()
336 gd->ram_size += end - start + 1; in dram_init()
338 gd->ram_size += end1 - start; in dram_init()
339 } else if (start >= phys_sdram_2_start && in dram_init()
340 start <= end2) { in dram_init()
342 gd->ram_size += end - start + 1; in dram_init()
344 gd->ram_size += end2 - start; in dram_init()
359 phys_addr_t start; in dram_bank_sort() local
363 if (gd->bd->bi_dram[current_bank - 1].start > in dram_bank_sort()
364 gd->bd->bi_dram[current_bank].start) { in dram_bank_sort()
365 start = gd->bd->bi_dram[current_bank - 1].start; in dram_bank_sort()
368 gd->bd->bi_dram[current_bank - 1].start = in dram_bank_sort()
369 gd->bd->bi_dram[current_bank].start; in dram_bank_sort()
373 gd->bd->bi_dram[current_bank].start = start; in dram_bank_sort()
383 sc_faddr_t start, end, end1, end2; in dram_init_banksize() local
395 err = get_owned_memreg(mr, &start, &end); in dram_init_banksize()
397 start = roundup(start, MEMSTART_ALIGNMENT); in dram_init_banksize()
398 if (start > end) /* Small memory region, no use it */ in dram_init_banksize()
401 if (start >= phys_sdram_1_start && start <= end1) { in dram_init_banksize()
402 gd->bd->bi_dram[i].start = start; in dram_init_banksize()
406 end - start + 1; in dram_init_banksize()
408 gd->bd->bi_dram[i].size = end1 - start; in dram_init_banksize()
412 } else if (start >= phys_sdram_2_start && start <= end2) { in dram_init_banksize()
413 gd->bd->bi_dram[i].start = start; in dram_init_banksize()
417 end - start + 1; in dram_init_banksize()
419 gd->bd->bi_dram[i].size = end2 - start; in dram_init_banksize()
429 gd->bd->bi_dram[0].start = phys_sdram_1_start; in dram_init_banksize()
431 gd->bd->bi_dram[1].start = phys_sdram_2_start; in dram_init_banksize()
490 sc_faddr_t start, end; in enable_caches() local
502 err = get_owned_memreg(mr, &start, &end); in enable_caches()
504 imx8_mem_map[i].virt = start; in enable_caches()
505 imx8_mem_map[i].phys = start; in enable_caches()
506 imx8_mem_map[i].size = get_block_size(start, end); in enable_caches()
507 imx8_mem_map[i].attrs = get_block_attrs(start); in enable_caches()