Lines Matching refs:con
180 uint32_t con; in rkclk_pll_get_rate() local
194 con = readl(&cru->cru_mode_con); in rkclk_pll_get_rate()
198 switch ((con & mask) >> shift) { in rkclk_pll_get_rate()
204 con = readl(&pll->con0); in rkclk_pll_get_rate()
205 postdiv1 = (con & PLL_POSTDIV1_MASK) >> PLL_POSTDIV1_SHIFT; in rkclk_pll_get_rate()
206 fbdiv = (con & PLL_FBDIV_MASK) >> PLL_FBDIV_SHIFT; in rkclk_pll_get_rate()
207 con = readl(&pll->con1); in rkclk_pll_get_rate()
208 postdiv2 = (con & PLL_POSTDIV2_MASK) >> PLL_POSTDIV2_SHIFT; in rkclk_pll_get_rate()
209 refdiv = (con & PLL_REFDIV_MASK) >> PLL_REFDIV_SHIFT; in rkclk_pll_get_rate()
221 u32 con; in rockchip_mmc_get_clk() local
227 con = readl(&cru->cru_clksel_con[11]); in rockchip_mmc_get_clk()
228 mux = (con & EMMC_PLL_MASK) >> EMMC_PLL_SHIFT; in rockchip_mmc_get_clk()
229 con = readl(&cru->cru_clksel_con[12]); in rockchip_mmc_get_clk()
230 div = (con & EMMC_DIV_MASK) >> EMMC_DIV_SHIFT; in rockchip_mmc_get_clk()
234 con = readl(&cru->cru_clksel_con[11]); in rockchip_mmc_get_clk()
235 mux = (con & MMC0_PLL_MASK) >> MMC0_PLL_SHIFT; in rockchip_mmc_get_clk()
236 div = (con & MMC0_DIV_MASK) >> MMC0_DIV_SHIFT; in rockchip_mmc_get_clk()
258 u32 con = readl(&cru->cru_clksel_con[5]); in rk322x_mac_set_clk() local
262 if ((con >> MAC_PLL_SEL_SHIFT) & MAC_PLL_SEL_MASK) in rk322x_mac_set_clk()