Lines Matching refs:MASK_ALL_BITS
121 {0x1034, 0x38000, MASK_ALL_BITS},
122 {0x1038, 0x0, MASK_ALL_BITS},
123 {0x10b0, 0x0, MASK_ALL_BITS},
124 {0x10b8, 0x0, MASK_ALL_BITS},
125 {0x10c0, 0x0, MASK_ALL_BITS},
126 {0x10f0, 0x0, MASK_ALL_BITS},
127 {0x10f4, 0x0, MASK_ALL_BITS},
128 {0x10f8, 0xff, MASK_ALL_BITS},
129 {0x10fc, 0xffff, MASK_ALL_BITS},
130 {0x1130, 0x0, MASK_ALL_BITS},
131 {0x1830, 0x2000000, MASK_ALL_BITS},
132 {0x14d0, 0x0, MASK_ALL_BITS},
133 {0x14d4, 0x0, MASK_ALL_BITS},
134 {0x14d8, 0x0, MASK_ALL_BITS},
135 {0x14dc, 0x0, MASK_ALL_BITS},
136 {0x1454, 0x0, MASK_ALL_BITS},
137 {0x1594, 0x0, MASK_ALL_BITS},
138 {0x1598, 0x0, MASK_ALL_BITS},
139 {0x159c, 0x0, MASK_ALL_BITS},
140 {0x15a0, 0x0, MASK_ALL_BITS},
141 {0x15a4, 0x0, MASK_ALL_BITS},
142 {0x15a8, 0x0, MASK_ALL_BITS},
143 {0x15ac, 0x0, MASK_ALL_BITS},
144 {0x1600, 0x0, MASK_ALL_BITS},
145 {0x1604, 0x0, MASK_ALL_BITS},
146 {0x1608, 0x0, MASK_ALL_BITS},
147 {0x160c, 0x0, MASK_ALL_BITS},
148 {0x1610, 0x0, MASK_ALL_BITS},
149 {0x1614, 0x0, MASK_ALL_BITS},
150 {0x1618, 0x0, MASK_ALL_BITS},
151 {0x1624, 0x0, MASK_ALL_BITS},
152 {0x1690, 0x0, MASK_ALL_BITS},
153 {0x1694, 0x0, MASK_ALL_BITS},
154 {0x1698, 0x0, MASK_ALL_BITS},
155 {0x169c, 0x0, MASK_ALL_BITS},
156 {0x14b8, 0x6f67, MASK_ALL_BITS},
157 {0x1630, 0x0, MASK_ALL_BITS},
158 {0x1634, 0x0, MASK_ALL_BITS},
159 {0x1638, 0x0, MASK_ALL_BITS},
160 {0x163c, 0x0, MASK_ALL_BITS},
161 {0x16b0, 0x0, MASK_ALL_BITS},
162 {0x16b4, 0x0, MASK_ALL_BITS},
163 {0x16b8, 0x0, MASK_ALL_BITS},
164 {0x16bc, 0x0, MASK_ALL_BITS},
165 {0x16c0, 0x0, MASK_ALL_BITS},
166 {0x16c4, 0x0, MASK_ALL_BITS},
167 {0x16c8, 0x0, MASK_ALL_BITS},
168 {0x16cc, 0x1, MASK_ALL_BITS},
169 {0x16f0, 0x1, MASK_ALL_BITS},
170 {0x16f4, 0x0, MASK_ALL_BITS},
171 {0x16f8, 0x0, MASK_ALL_BITS},
172 {0x16fc, 0x0, MASK_ALL_BITS}
459 DDR3_RANK_CTRL_REG, 0x27, MASK_ALL_BITS)); in hws_ddr3_tip_init_controller()
636 MASK_ALL_BITS)); in hws_ddr3_tip_init_controller()
1967 0xffff, MASK_ALL_BITS)); in ddr3_tip_restore_dunit_regs()