Lines Matching refs:MV_OK
239 return MV_OK; in ddr3_tip_a38x_get_freq_config()
303 return MV_OK; in mv_ddr_is_odpg_done()
348 return MV_OK; in mv_ddr_is_training_done()
378 return MV_OK; in ddr3_tip_a38x_select_ddr_controller()
480 return MV_OK; in mv_ddr_sar_freq_get()
557 return MV_OK; in ddr3_tip_a38x_get_medium_freq()
565 return MV_OK; in ddr3_tip_a38x_get_device_info()
584 return MV_OK; in is_prfa_done()
604 if (is_prfa_done() != MV_OK) in prfa_write()
607 return MV_OK; in prfa_write()
621 if (prfa_write(ACCESS_TYPE_UNICAST, i, phy_type, addr, 0, OPERATION_READ) != MV_OK) in prfa_read()
627 if (prfa_write(phy_access, phy, phy_type, addr, 0, OPERATION_READ) != MV_OK) in prfa_read()
633 return MV_OK; in prfa_read()
674 return MV_OK; in mv_ddr_sw_db_init()
717 return MV_OK; in mv_ddr_training_mask_set()
840 return MV_OK; in ddr3_tip_a38x_set_divider()
854 return MV_OK; in ddr3_tip_ext_read()
867 return MV_OK; in ddr3_tip_ext_write()
888 return MV_OK; in mv_ddr_early_init()
895 return MV_OK; in mv_ddr_early_init2()
910 return MV_OK; in ddr3_post_run_alg()
924 return MV_OK; in ddr3_silicon_post_init()
1013 return MV_OK; in ddr3_calc_mem_cs_size()
1035 if (ddr3_calc_mem_cs_size(cs, &cs_mem_size_mb) != MV_OK) in ddr3_fast_path_dynamic_cs_size_config()
1098 return MV_OK; in ddr3_fast_path_dynamic_cs_size_config()
1118 if (ddr3_fast_path_dynamic_cs_size_config(cs_ena) != MV_OK) in ddr3_restore_and_set_final_windows()
1133 return MV_OK; in ddr3_restore_and_set_final_windows()
1204 return MV_OK; in ddr3_save_and_set_training_windows()
1247 return MV_OK; in mv_ddr_pre_training_soc_config()
1284 return MV_OK; in mv_ddr_pre_training_soc_config()
1316 return MV_OK; in ddr3_new_tip_dlb_config()
1334 return MV_OK; in mv_ddr_post_training_soc_config()
1348 if (status != MV_OK) in mv_ddr_mc_config()
1352 if (status != MV_OK) in mv_ddr_mc_config()
1362 return MV_OK; in mv_ddr_mc_init()
1439 return MV_OK; in ddr3_tip_configure_phy()