Lines Matching refs:BIT_ULL
44 #define CMR_PKT_TX_EN BIT_ULL(13)
45 #define CMR_PKT_RX_EN BIT_ULL(14)
46 #define CMR_EN BIT_ULL(15)
48 #define CMR_GLOBAL_CFG_FCS_STRIP BIT_ULL(6)
64 #define RX_DMACX_CAM_EN BIT_ULL(48)
93 #define SPU_CTL_LOW_POWER BIT_ULL(11)
94 #define SPU_CTL_LOOPBACK BIT_ULL(14)
95 #define SPU_CTL_RESET BIT_ULL(15)
97 #define SPU_STATUS1_RCV_LNK BIT_ULL(2)
99 #define SPU_STATUS2_RCVFLT BIT_ULL(10)
101 #define SPU_BX_STATUS_RX_ALIGN BIT_ULL(12)
103 #define SPU_BR_STATUS_BLK_LOCK BIT_ULL(0)
104 #define SPU_BR_STATUS_RCV_LNK BIT_ULL(12)
106 #define SPU_PMD_CRTL_TRAIN_EN BIT_ULL(1)
111 #define SPU_FEC_CTL_FEC_EN BIT_ULL(0)
112 #define SPU_FEC_CTL_ERR_EN BIT_ULL(1)
114 #define SPU_AN_CTL_AN_EN BIT_ULL(12)
115 #define SPU_AN_CTL_XNP_EN BIT_ULL(13)
116 #define SPU_AN_CTL_AN_RESTART BIT_ULL(15)
118 #define SPU_AN_STS_AN_COMPLETE BIT_ULL(5)
121 #define SPU_MISC_CTL_INTLV_RDISP BIT_ULL(10)
122 #define SPU_MISC_CTL_RX_DIS BIT_ULL(12)
128 #define SPU_DBG_CTL_AN_ARB_LINK_CHK_EN BIT_ULL(18)
129 #define SPU_DBG_CTL_AN_NONCE_MCT_DIS BIT_ULL(29)
136 #define SMU_TX_APPEND_FCS_D BIT_ULL(2)
140 #define SMU_TX_CTL_DIC_EN BIT_ULL(0)
141 #define SMU_TX_CTL_UNI_EN BIT_ULL(1)
145 #define SMU_CTL_RX_IDLE BIT_ULL(0)
146 #define SMU_CTL_TX_IDLE BIT_ULL(1)
149 #define PCS_MRX_CTL_RST_AN BIT_ULL(9)
150 #define PCS_MRX_CTL_PWR_DN BIT_ULL(11)
151 #define PCS_MRX_CTL_AN_EN BIT_ULL(12)
152 #define PCS_MRX_CTL_LOOPBACK1 BIT_ULL(14)
153 #define PCS_MRX_CTL_RESET BIT_ULL(15)
155 #define PCS_MRX_STATUS_AN_CPT BIT_ULL(5)
159 #define PCS_MISCX_CTL_DISP_EN BIT_ULL(13)
160 #define PCS_MISC_CTL_GMX_ENO BIT_ULL(11)
162 #define PCS_MISC_CTL_MODE BIT_ULL(8)
164 #define GMI_PORT_CFG_SPEED BIT_ULL(1)
165 #define GMI_PORT_CFG_DUPLEX BIT_ULL(2)
166 #define GMI_PORT_CFG_SLOT_TIME BIT_ULL(3)
167 #define GMI_PORT_CFG_SPEED_MSB BIT_ULL(8)