Lines Matching refs:phy_base
14 static void sdram_phy_dll_bypass_set(void __iomem *phy_base, u32 freq) in sdram_phy_dll_bypass_set() argument
20 setbits_le32(PHY_REG(phy_base, 0x13), 1 << 4); in sdram_phy_dll_bypass_set()
21 clrbits_le32(PHY_REG(phy_base, 0x14), 1 << 3); in sdram_phy_dll_bypass_set()
24 setbits_le32(PHY_REG(phy_base, j), 1 << 4); in sdram_phy_dll_bypass_set()
25 clrbits_le32(PHY_REG(phy_base, j + 0x1), 1 << 3); in sdram_phy_dll_bypass_set()
30 setbits_le32(PHY_REG(phy_base, 0xa4), 0x1f); in sdram_phy_dll_bypass_set()
32 clrbits_le32(PHY_REG(phy_base, 0xa4), 0x1f); in sdram_phy_dll_bypass_set()
47 writel(tmp, PHY_REG(phy_base, j)); in sdram_phy_dll_bypass_set()
51 static void sdram_phy_set_ds_odt(void __iomem *phy_base, in sdram_phy_set_ds_odt() argument
72 writel(cmd_drv, PHY_REG(phy_base, 0x11)); in sdram_phy_set_ds_odt()
73 clrsetbits_le32(PHY_REG(phy_base, 0x12), 0x1f << 3, cmd_drv << 3); in sdram_phy_set_ds_odt()
74 writel(clk_drv, PHY_REG(phy_base, 0x16)); in sdram_phy_set_ds_odt()
75 writel(clk_drv, PHY_REG(phy_base, 0x18)); in sdram_phy_set_ds_odt()
79 writel(dqs_drv, PHY_REG(phy_base, j)); in sdram_phy_set_ds_odt()
80 writel(dqs_drv, PHY_REG(phy_base, j + 0xf)); in sdram_phy_set_ds_odt()
82 writel(dqs_odt, PHY_REG(phy_base, j + 0x1)); in sdram_phy_set_ds_odt()
83 writel(dqs_odt, PHY_REG(phy_base, j + 0xe)); in sdram_phy_set_ds_odt()
87 void phy_soft_reset(void __iomem *phy_base) in phy_soft_reset() argument
89 clrbits_le32(PHY_REG(phy_base, 0), 0x3 << 2); in phy_soft_reset()
91 setbits_le32(PHY_REG(phy_base, 0), ANALOG_DERESET); in phy_soft_reset()
93 setbits_le32(PHY_REG(phy_base, 0), DIGITAL_DERESET); in phy_soft_reset()
97 void phy_dram_set_bw(void __iomem *phy_base, u32 bw) in phy_dram_set_bw() argument
100 clrsetbits_le32(PHY_REG(phy_base, 0), 0xf << 4, 0xf << 4); in phy_dram_set_bw()
101 setbits_le32(PHY_REG(phy_base, 0x46), 1 << 3); in phy_dram_set_bw()
102 setbits_le32(PHY_REG(phy_base, 0x56), 1 << 3); in phy_dram_set_bw()
104 clrsetbits_le32(PHY_REG(phy_base, 0), 0xf << 4, 3 << 4); in phy_dram_set_bw()
105 clrbits_le32(PHY_REG(phy_base, 0x46), 1 << 3); in phy_dram_set_bw()
106 clrbits_le32(PHY_REG(phy_base, 0x56), 1 << 3); in phy_dram_set_bw()
108 clrsetbits_le32(PHY_REG(phy_base, 0), 0xf << 4, 1 << 4); in phy_dram_set_bw()
109 clrbits_le32(PHY_REG(phy_base, 0x36), 1 << 3); in phy_dram_set_bw()
110 clrbits_le32(PHY_REG(phy_base, 0x46), 1 << 3); in phy_dram_set_bw()
111 clrbits_le32(PHY_REG(phy_base, 0x56), 1 << 3); in phy_dram_set_bw()
114 phy_soft_reset(phy_base); in phy_dram_set_bw()
117 int phy_data_training(void __iomem *phy_base, u32 cs, u32 dramtype) in phy_data_training() argument
123 odt_val = readl(PHY_REG(phy_base, 0x2e)); in phy_data_training()
127 writel(PHY_DDR3_RON_RTT_225ohm, PHY_REG(phy_base, j + 0x1)); in phy_data_training()
128 writel(0, PHY_REG(phy_base, j + 0xe)); in phy_data_training()
132 clrsetbits_le32(PHY_REG(phy_base, 0x29), 0x3, 0); in phy_data_training()
133 clrsetbits_le32(PHY_REG(phy_base, 0x39), 0x3, 0); in phy_data_training()
134 clrsetbits_le32(PHY_REG(phy_base, 0x49), 0x3, 0); in phy_data_training()
135 clrsetbits_le32(PHY_REG(phy_base, 0x59), 0x3, 0); in phy_data_training()
138 clrsetbits_le32(PHY_REG(phy_base, 2), 0x33, (0x20 >> cs)); in phy_data_training()
140 clrsetbits_le32(PHY_REG(phy_base, 2), 0x33, (0x20 >> cs) | 1); in phy_data_training()
142 ret = readl(PHY_REG(phy_base, 0xff)); in phy_data_training()
144 clrsetbits_le32(PHY_REG(phy_base, 2), 0x33, (0x20 >> cs) | 0); in phy_data_training()
146 clrbits_le32(PHY_REG(phy_base, 2), 0x30); in phy_data_training()
150 clrsetbits_le32(PHY_REG(phy_base, 0x29), 0x3, 0x2); in phy_data_training()
151 clrsetbits_le32(PHY_REG(phy_base, 0x39), 0x3, 0x2); in phy_data_training()
152 clrsetbits_le32(PHY_REG(phy_base, 0x49), 0x3, 0x2); in phy_data_training()
153 clrsetbits_le32(PHY_REG(phy_base, 0x59), 0x3, 0x2); in phy_data_training()
159 ret = (ret & 0xf) ^ (readl(PHY_REG(phy_base, 0)) >> 4); in phy_data_training()
165 writel(odt_val, PHY_REG(phy_base, j + 0x1)); in phy_data_training()
166 writel(odt_val, PHY_REG(phy_base, j + 0xe)); in phy_data_training()
171 void phy_cfg(void __iomem *phy_base, in phy_cfg() argument
177 sdram_phy_dll_bypass_set(phy_base, base->ddr_freq); in phy_cfg()
180 phy_base + phy_regs->phy[i][0]); in phy_cfg()
183 clrsetbits_le32(PHY_REG(phy_base, 0), 0xf << 4, 0xf << 4); in phy_cfg()
185 clrsetbits_le32(PHY_REG(phy_base, 0), 0xf << 4, 3 << 4); in phy_cfg()
187 clrbits_le32(PHY_REG(phy_base, 0x46), 1 << 3); in phy_cfg()
188 clrbits_le32(PHY_REG(phy_base, 0x56), 1 << 3); in phy_cfg()
190 clrsetbits_le32(PHY_REG(phy_base, 0), 0xf << 4, 1 << 4); in phy_cfg()
192 clrbits_le32(PHY_REG(phy_base, 0x36), 1 << 3); in phy_cfg()
193 clrbits_le32(PHY_REG(phy_base, 0x46), 1 << 3); in phy_cfg()
194 clrbits_le32(PHY_REG(phy_base, 0x56), 1 << 3); in phy_cfg()
196 sdram_phy_set_ds_odt(phy_base, base->dramtype); in phy_cfg()
199 setbits_le32(PHY_REG(phy_base, 2), 8); in phy_cfg()
200 sdram_copy_to_reg(PHY_REG(phy_base, 0xb0), in phy_cfg()
202 sdram_copy_to_reg(PHY_REG(phy_base, 0x70), in phy_cfg()
204 sdram_copy_to_reg(PHY_REG(phy_base, 0xc0), in phy_cfg()