Lines Matching refs:cfg
107 unsigned int cfg = 0; in exynos_fimd_set_dualrgb() local
110 cfg = EXYNOS_DUALRGB_BYPASS_DUAL | EXYNOS_DUALRGB_LINESPLIT | in exynos_fimd_set_dualrgb()
114 cfg |= EXYNOS_DUALRGB_SUB_CNT(priv->vl_col / 2) | in exynos_fimd_set_dualrgb()
118 writel(cfg, ®->dualrgb); in exynos_fimd_set_dualrgb()
125 unsigned int cfg = 0; in exynos_fimd_set_dp_clkcon() local
128 cfg = EXYNOS_DP_CLK_ENABLE; in exynos_fimd_set_dp_clkcon()
130 writel(cfg, ®->dp_mie_clkcon); in exynos_fimd_set_dp_clkcon()
137 unsigned int cfg = 0; in exynos_fimd_set_par() local
140 cfg = readl((unsigned int)®->wincon0 + in exynos_fimd_set_par()
143 cfg &= ~(EXYNOS_WINCON_BITSWP_ENABLE | EXYNOS_WINCON_BYTESWP_ENABLE | in exynos_fimd_set_par()
149 cfg |= EXYNOS_WINCON_DATAPATH_DMA; in exynos_fimd_set_par()
151 cfg |= EXYNOS_WINCON_HAWSWP_ENABLE; in exynos_fimd_set_par()
154 cfg |= EXYNOS_WINCON_BURSTLEN_16WORD; in exynos_fimd_set_par()
158 cfg |= EXYNOS_WINCON_BPPMODE_16BPP_565; in exynos_fimd_set_par()
161 cfg |= EXYNOS_WINCON_BPPMODE_24BPP_888; in exynos_fimd_set_par()
165 writel(cfg, (unsigned int)®->wincon0 + in exynos_fimd_set_par()
169 cfg = EXYNOS_VIDOSD_LEFT_X(0) | EXYNOS_VIDOSD_TOP_Y(0); in exynos_fimd_set_par()
170 writel(cfg, (unsigned int)®->vidosd0a + in exynos_fimd_set_par()
173 cfg = EXYNOS_VIDOSD_RIGHT_X(priv->vl_col - 1) | in exynos_fimd_set_par()
178 writel(cfg, (unsigned int)®->vidosd0b + in exynos_fimd_set_par()
182 cfg = EXYNOS_VIDOSD_SIZE(priv->vl_col * priv->vl_row); in exynos_fimd_set_par()
183 writel(cfg, (unsigned int)®->vidosd0c + in exynos_fimd_set_par()
207 unsigned int cfg = 0, div = 0, remainder, remainder_div; in exynos_fimd_set_clock() local
230 cfg = readl(®->vidcon0); in exynos_fimd_set_clock()
231 cfg &= ~(EXYNOS_VIDCON0_CLKSEL_MASK | EXYNOS_VIDCON0_CLKVALUP_MASK | in exynos_fimd_set_clock()
234 cfg |= (EXYNOS_VIDCON0_CLKSEL_SCLK | EXYNOS_VIDCON0_CLKVALUP_ALWAYS | in exynos_fimd_set_clock()
254 cfg |= EXYNOS_VIDCON0_CLKVAL_F(div - 1); in exynos_fimd_set_clock()
255 writel(cfg, ®->vidcon0); in exynos_fimd_set_clock()
261 unsigned int cfg = 0; in exynos_set_trigger() local
263 cfg = readl(®->trigcon); in exynos_set_trigger()
265 cfg |= (EXYNOS_I80SOFT_TRIG_EN | EXYNOS_I80START_TRIG); in exynos_set_trigger()
267 writel(cfg, ®->trigcon); in exynos_set_trigger()
273 unsigned int cfg = 0; in exynos_is_i80_frame_done() local
276 cfg = readl(®->trigcon); in exynos_is_i80_frame_done()
279 status = (cfg & EXYNOS_I80STATUS_TRIG_DONE) == in exynos_is_i80_frame_done()
288 unsigned int cfg = 0; in exynos_fimd_lcd_on() local
291 cfg = readl(®->vidcon0); in exynos_fimd_lcd_on()
292 cfg |= (EXYNOS_VIDCON0_ENVID_ENABLE | EXYNOS_VIDCON0_ENVID_F_ENABLE); in exynos_fimd_lcd_on()
293 writel(cfg, ®->vidcon0); in exynos_fimd_lcd_on()
300 unsigned int cfg = 0; in exynos_fimd_window_on() local
303 cfg = readl((unsigned int)®->wincon0 + in exynos_fimd_window_on()
305 cfg |= EXYNOS_WINCON_ENWIN_ENABLE; in exynos_fimd_window_on()
306 writel(cfg, (unsigned int)®->wincon0 + in exynos_fimd_window_on()
309 cfg = readl(®->winshmap); in exynos_fimd_window_on()
310 cfg |= EXYNOS_WINSHMAP_CH_ENABLE(win_id); in exynos_fimd_window_on()
311 writel(cfg, ®->winshmap); in exynos_fimd_window_on()
317 unsigned int cfg = 0; in exynos_fimd_lcd_off() local
319 cfg = readl(®->vidcon0); in exynos_fimd_lcd_off()
320 cfg &= (EXYNOS_VIDCON0_ENVID_DISABLE | EXYNOS_VIDCON0_ENVID_F_DISABLE); in exynos_fimd_lcd_off()
321 writel(cfg, ®->vidcon0); in exynos_fimd_lcd_off()
327 unsigned int cfg = 0; in exynos_fimd_window_off() local
329 cfg = readl((unsigned int)®->wincon0 + in exynos_fimd_window_off()
331 cfg &= EXYNOS_WINCON_ENWIN_DISABLE; in exynos_fimd_window_off()
332 writel(cfg, (unsigned int)®->wincon0 + in exynos_fimd_window_off()
335 cfg = readl(®->winshmap); in exynos_fimd_window_off()
336 cfg &= ~EXYNOS_WINSHMAP_CH_DISABLE(win_id); in exynos_fimd_window_off()
337 writel(cfg, ®->winshmap); in exynos_fimd_window_off()
383 unsigned int cfg = 0, rgb_mode; in exynos_fimd_lcd_init() local
396 cfg |= EXYNOS_VIDCON0_VIDOUT_RGB; in exynos_fimd_lcd_init()
397 writel(cfg, ®->vidcon0); in exynos_fimd_lcd_init()
399 cfg = readl(®->vidcon2); in exynos_fimd_lcd_init()
400 cfg &= ~(EXYNOS_VIDCON2_WB_MASK | in exynos_fimd_lcd_init()
403 cfg |= EXYNOS_VIDCON2_WB_DISABLE; in exynos_fimd_lcd_init()
404 writel(cfg, ®->vidcon2); in exynos_fimd_lcd_init()
407 cfg = 0; in exynos_fimd_lcd_init()
409 cfg |= EXYNOS_VIDCON1_IVCLK_RISING_EDGE; in exynos_fimd_lcd_init()
411 cfg |= EXYNOS_VIDCON1_IHSYNC_INVERT; in exynos_fimd_lcd_init()
413 cfg |= EXYNOS_VIDCON1_IVSYNC_INVERT; in exynos_fimd_lcd_init()
415 cfg |= EXYNOS_VIDCON1_IVDEN_INVERT; in exynos_fimd_lcd_init()
417 writel(cfg, (unsigned int)®->vidcon1 + offset); in exynos_fimd_lcd_init()
420 cfg = EXYNOS_VIDTCON0_VFPD(priv->vl_vfpd - 1); in exynos_fimd_lcd_init()
421 cfg |= EXYNOS_VIDTCON0_VBPD(priv->vl_vbpd - 1); in exynos_fimd_lcd_init()
422 cfg |= EXYNOS_VIDTCON0_VSPW(priv->vl_vspw - 1); in exynos_fimd_lcd_init()
423 writel(cfg, (unsigned int)®->vidtcon0 + offset); in exynos_fimd_lcd_init()
425 cfg = EXYNOS_VIDTCON1_HFPD(priv->vl_hfpd - 1); in exynos_fimd_lcd_init()
426 cfg |= EXYNOS_VIDTCON1_HBPD(priv->vl_hbpd - 1); in exynos_fimd_lcd_init()
427 cfg |= EXYNOS_VIDTCON1_HSPW(priv->vl_hspw - 1); in exynos_fimd_lcd_init()
429 writel(cfg, (unsigned int)®->vidtcon1 + offset); in exynos_fimd_lcd_init()
432 cfg = EXYNOS_VIDTCON2_HOZVAL(priv->vl_col - 1) | in exynos_fimd_lcd_init()
437 writel(cfg, (unsigned int)®->vidtcon2 + offset); in exynos_fimd_lcd_init()
441 cfg = readl(®->vidcon0); in exynos_fimd_lcd_init()
442 cfg &= ~EXYNOS_VIDCON0_PNRMODE_MASK; in exynos_fimd_lcd_init()
443 cfg |= (rgb_mode << EXYNOS_VIDCON0_PNRMODE_SHIFT); in exynos_fimd_lcd_init()
444 writel(cfg, ®->vidcon0); in exynos_fimd_lcd_init()
453 cfg = EXYNOS_VIDADDR_PAGEWIDTH(priv->vl_col * in exynos_fimd_lcd_init()
460 writel(cfg, (unsigned int)®->vidw00add2 + in exynos_fimd_lcd_init()