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:term:`SVE`”h]”h)”}”(hŒ:term:`SVE`”h]”h)”}”(hj h]”hŒSVE”…””}”(hhh!j ubah"}”(h$]”h&]”(h(Œstd”Œstd-term”eh+]”h-]”h/]”uh1hh!j ubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”j Œreftype”Œterm”Œrefexplicit”‰Œrefwarn”ˆh?ŒSVE”uh1hhAhBhCK6h!j ubah"}”(h$]”h&]”h+]”ŒSVE”ah-]”h/]”uh1h hAhBhCK6h!hhhubh)”}”(hŒ.. |TBB| replace:: :term:`TBB`”h]”h)”}”(hŒ:term:`TBB`”h]”h)”}”(hj8 h]”hŒTBB”…””}”(hhh!j: ubah"}”(h$]”h&]”(h(Œstd”Œstd-term”eh+]”h-]”h/]”uh1hh!j6 ubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”jD Œreftype”Œterm”Œrefexplicit”‰Œrefwarn”ˆh?ŒTBB”uh1hhAhBhCK7h!j2 ubah"}”(h$]”h&]”h+]”ŒTBB”ah-]”h/]”uh1h hAhBhCK7h!hhhubh)”}”(hŒ .. |TBBR| replace:: :term:`TBBR`”h]”h)”}”(hŒ:term:`TBBR`”h]”h)”}”(hjc h]”hŒTBBR”…””}”(hhh!je ubah"}”(h$]”h&]”(h(Œstd”Œstd-term”eh+]”h-]”h/]”uh1hh!ja ubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”jo Œreftype”Œterm”Œrefexplicit”‰Œrefwarn”ˆh?ŒTBBR”uh1hhAhBhCK8h!j] ubah"}”(h$]”h&]”h+]”ŒTBBR”ah-]”h/]”uh1h hAhBhCK8h!hhhubh)”}”(hŒ.. |TEE| replace:: :term:`TEE`”h]”h)”}”(hŒ:term:`TEE`”h]”h)”}”(hjŽ h]”hŒTEE”…””}”(hhh!j ubah"}”(h$]”h&]”(h(Œstd”Œstd-term”eh+]”h-]”h/]”uh1hh!jŒ ubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”jš Œreftype”Œterm”Œrefexplicit”‰Œrefwarn”ˆh?ŒTEE”uh1hhAhBhCK9h!jˆ ubah"}”(h$]”h&]”h+]”ŒTEE”ah-]”h/]”uh1h hAhBhCK9h!hhhubh)”}”(hŒ .. |TF-A| replace:: :term:`TF-A`”h]”h)”}”(hŒ:term:`TF-A`”h]”h)”}”(hj¹ h]”hŒTF-A”…””}”(hhh!j» ubah"}”(h$]”h&]”(h(Œstd”Œstd-term”eh+]”h-]”h/]”uh1hh!j· ubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”jÅ Œreftype”Œterm”Œrefexplicit”‰Œrefwarn”ˆh?ŒTF-A”uh1hhAhBhCK:h!j³ ubah"}”(h$]”h&]”h+]”ŒTF-A”ah-]”h/]”uh1h hAhBhCK:h!hhhubh)”}”(hŒ .. |TF-M| replace:: :term:`TF-M`”h]”h)”}”(hŒ:term:`TF-M`”h]”h)”}”(hjä h]”hŒTF-M”…””}”(hhh!jæ ubah"}”(h$]”h&]”(h(Œstd”Œstd-term”eh+]”h-]”h/]”uh1hh!jâ ubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”jð Œreftype”Œterm”Œrefexplicit”‰Œrefwarn”ˆh?ŒTF-M”uh1hhAhBhCK;h!jÞ ubah"}”(h$]”h&]”h+]”ŒTF-M”ah-]”h/]”uh1h hAhBhCK;h!hhhubh)”}”(hŒ.. |TLB| replace:: :term:`TLB`”h]”h)”}”(hŒ:term:`TLB`”h]”h)”}”(hj h]”hŒTLB”…””}”(hhh!j ubah"}”(h$]”h&]”(h(Œstd”Œstd-term”eh+]”h-]”h/]”uh1hh!j ubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”j Œreftype”Œterm”Œrefexplicit”‰Œrefwarn”ˆh?ŒTLB”uh1hhAhBhCKh!j_ ubah"}”(h$]”h&]”h+]”ŒTRNG”ah-]”h/]”uh1h hAhBhCK>h!hhhubh)”}”(hŒ.. |TSP| replace:: :term:`TSP`”h]”h)”}”(hŒ:term:`TSP`”h]”h)”}”(hj h]”hŒTSP”…””}”(hhh!j’ ubah"}”(h$]”h&]”(h(Œstd”Œstd-term”eh+]”h-]”h/]”uh1hh!jŽ ubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”jœ Œreftype”Œterm”Œrefexplicit”‰Œrefwarn”ˆh?ŒTSP”uh1hhAhBhCK?h!jŠ ubah"}”(h$]”h&]”h+]”ŒTSP”ah-]”h/]”uh1h hAhBhCK?h!hhhubh)”}”(hŒ.. |TZC| replace:: :term:`TZC`”h]”h)”}”(hŒ:term:`TZC`”h]”h)”}”(hj» h]”hŒTZC”…””}”(hhh!j½ ubah"}”(h$]”h&]”(h(Œstd”Œstd-term”eh+]”h-]”h/]”uh1hh!j¹ ubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”jÇ Œreftype”Œterm”Œrefexplicit”‰Œrefwarn”ˆh?ŒTZC”uh1hhAhBhCK@h!jµ ubah"}”(h$]”h&]”h+]”ŒTZC”ah-]”h/]”uh1h hAhBhCK@h!hhhubh)”}”(hŒ".. |UBSAN| replace:: :term:`UBSAN`”h]”h)”}”(hŒ :term:`UBSAN`”h]”h)”}”(hjæ h]”hŒUBSAN”…””}”(hhh!jè ubah"}”(h$]”h&]”(h(Œstd”Œstd-term”eh+]”h-]”h/]”uh1hh!jä ubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”jò Œreftype”Œterm”Œrefexplicit”‰Œrefwarn”ˆh?ŒUBSAN”uh1hhAhBhCKAh!jà ubah"}”(h$]”h&]”h+]”ŒUBSAN”ah-]”h/]”uh1h hAhBhCKAh!hhhubh)”}”(hŒ .. |UEFI| replace:: :term:`UEFI`”h]”h)”}”(hŒ:term:`UEFI`”h]”h)”}”(hjh]”hŒUEFI”…””}”(hhh!jubah"}”(h$]”h&]”(h(Œstd”Œstd-term”eh+]”h-]”h/]”uh1hh!jubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”jŒreftype”Œterm”Œrefexplicit”‰Œrefwarn”ˆh?ŒUEFI”uh1hhAhBhCKBh!jubah"}”(h$]”h&]”h+]”ŒUEFI”ah-]”h/]”uh1h hAhBhCKBh!hhhubh)”}”(hŒ .. |WDOG| replace:: :term:`WDOG`”h]”h)”}”(hŒ:term:`WDOG`”h]”h)”}”(hj<h]”hŒWDOG”…””}”(hhh!j>ubah"}”(h$]”h&]”(h(Œstd”Œstd-term”eh+]”h-]”h/]”uh1hh!j:ubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”jHŒreftype”Œterm”Œrefexplicit”‰Œrefwarn”ˆh?ŒWDOG”uh1hhAhBhCKCh!j6ubah"}”(h$]”h&]”h+]”ŒWDOG”ah-]”h/]”uh1h hAhBhCKCh!hhhubh)”}”(hŒ!.. |XLAT| replace:: :term:`XLAT` ”h]”h)”}”(hŒ:term:`XLAT`”h]”h)”}”(hjgh]”hŒXLAT”…””}”(hhh!jiubah"}”(h$]”h&]”(h(Œstd”Œstd-term”eh+]”h-]”h/]”uh1hh!jeubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”jsŒreftype”Œterm”Œrefexplicit”‰Œrefwarn”ˆh?ŒXLAT”uh1hhAhBhCKDh!jaubah"}”(h$]”h&]”h+]”ŒXLAT”ah-]”h/]”uh1h hAhBhCKDh!hhhubh Œsection”“”)”}”(hhh]”(h Œtitle”“”)”}”(hŒException Handling Framework”h]”hŒException Handling Framework”…””}”(hj•h!j“hhhANhCNubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j‘h!jŽhhhAŒ^/home/test/workspace/code/optee_3.16/trusted-firmware-a/docs/components/exception-handling.rst”hCKubh Œ paragraph”“”)”}”(hŒËThis document describes various aspects of handling exceptions by Runtime Firmware (BL31) that are targeted at EL3, other than SMCs. The |EHF| takes care of the following exceptions when targeted at EL3:”h]”(hŒ‰This document describes various aspects of handling exceptions by Runtime Firmware (BL31) that are targeted at EL3, other than SMCs. The ”…””}”(hŒ‰This document describes various aspects of handling exceptions by Runtime Firmware (BL31) that are targeted at EL3, other than SMCs. The ”h!j¤hhhANhCNubh)”}”(hj«h]”h)”}”(hj«h]”hŒEHF”…””}”(hhh!j°ubah"}”(h$]”h&]”(h(j·j¸eh+]”h-]”h/]”uh1hhANhCNh!jubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”j·Œreftype”jÅŒrefexplicit”‰Œrefwarn”ˆŒ reftarget”jÈuh1hhAhBhCKh!j¤hhubhŒ= takes care of the following exceptions when targeted at EL3:”…””}”(hŒ= takes care of the following exceptions when targeted at EL3:”h!j¤hhhANhCNubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKh!jŽhhubh Œbullet_list”“”)”}”(hhh]”(h Œ list_item”“”)”}”(hŒ Interrupts”h]”j£)”}”(hjÝh]”hŒ Interrupts”…””}”(hjÝh!jßubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKh!jÛubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÙh!jÖhhhAj¡hCNubjÚ)”}”(hŒSynchronous External Aborts”h]”j£)”}”(hjôh]”hŒSynchronous External Aborts”…””}”(hjôh!jöubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCK h!jòubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÙh!jÖhhhAj¡hCNubjÚ)”}”(hŒAsynchronous External Aborts ”h]”j£)”}”(hŒAsynchronous External Aborts”h]”hŒAsynchronous External Aborts”…””}”(hjh!j ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCK h!j ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÙh!jÖhhhAj¡hCNubeh"}”(h$]”h&]”h+]”h-]”h/]”Œbullet”Œ-”uh1jÔhAj¡hCKh!jŽhhubj£)”}”(hX|TF-A|'s handling of synchronous ``SMC`` exceptions raised from lower ELs is described in the :ref:`Firmware Design document `. However, the |EHF| changes the semantics of `Interrupt handling`_ and :ref:`synchronous exceptions ` other than SMCs.”h]”(h)”}”(hj¹ h]”h)”}”(hj¹ h]”hŒTF-A”…””}”(hhh!j0ubah"}”(h$]”h&]”(h(jÅ jÆ eh+]”h-]”h/]”uh1hhANhCNh!j-ubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”jÅ Œreftype”jÓ Œrefexplicit”‰Œrefwarn”ˆŒ reftarget”jÖ uh1hhAhBhCK:h!j)hhubhŒâ€™s handling of synchronous ”…””}”(hŒ's handling of synchronous ”h!j)hhhANhCNubh Œliteral”“”)”}”(hŒ``SMC``”h]”hŒSMC”…””}”(hhh!jPubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jNh!j)ubhŒ6 exceptions raised from lower ELs is described in the ”…””}”(hŒ6 exceptions raised from lower ELs is described in the ”h!j)hhhANhCNubh)”}”(hŒ1:ref:`Firmware Design document `”h]”h)”}”(hjeh]”hŒFirmware Design document”…””}”(hhh!jgubah"}”(h$]”h&]”(h(Œstd”Œstd-ref”eh+]”h-]”h/]”uh1hh!jcubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”jqŒreftype”Œref”Œrefexplicit”ˆŒrefwarn”ˆh?Œhandling-an-smc”uh1hhAj¡hCKh!j)ubhŒ. However, the ”…””}”(hŒ. However, the ”h!j)hhhANhCNubh)”}”(hj«h]”h)”}”(hj«h]”hŒEHF”…””}”(hhh!j‹ubah"}”(h$]”h&]”(h(j·j¸eh+]”h-]”h/]”uh1hhANhCNh!jˆubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”j·Œreftype”jÅŒrefexplicit”‰Œrefwarn”ˆŒ reftarget”jÈuh1hhAhBhCKh!j)hhubhŒ changes the semantics of ”…””}”(hŒ changes the semantics of ”h!j)hhhANhCNubh Œ reference”“”)”}”(hŒ`Interrupt handling`_”h]”hŒInterrupt handling”…””}”(hŒInterrupt handling”h!j«ubah"}”(h$]”h&]”h+]”h-]”h/]”Œname”ŒInterrupt handling”Œrefid”Œid3”uh1j©h!j)Œresolved”KubhŒ and ”…””}”(hŒ and ”h!j)hhhANhCNubh)”}”(hŒ3:ref:`synchronous exceptions `”h]”h)”}”(hjÆh]”hŒsynchronous exceptions”…””}”(hhh!jÈubah"}”(h$]”h&]”(h(Œstd”Œstd-ref”eh+]”h-]”h/]”uh1hh!jÄubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”jÒŒreftype”Œref”Œrefexplicit”ˆŒrefwarn”ˆh?Œeffect on smc calls”uh1hhAj¡hCKh!j)ubhŒ other than SMCs.”…””}”(hŒ other than SMCs.”h!j)hhhANhCNubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKh!jŽhhubj£)”}”(hŒThe |EHF| is selected by setting the build option ``EL3_EXCEPTION_HANDLING`` to ``1``, and is only available for AArch64 systems.”h]”(hŒThe ”…””}”(hŒThe ”h!jïhhhANhCNubh)”}”(hj«h]”h)”}”(hj«h]”hŒEHF”…””}”(hhh!jûubah"}”(h$]”h&]”(h(j·j¸eh+]”h-]”h/]”uh1hhANhCNh!jøubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”j·Œreftype”jÅŒrefexplicit”‰Œrefwarn”ˆŒ reftarget”jÈuh1hhAhBhCKh!jïhhubhŒ) is selected by setting the build option ”…””}”(hŒ) is selected by setting the build option ”h!jïhhhANhCNubjO)”}”(hŒ``EL3_EXCEPTION_HANDLING``”h]”hŒEL3_EXCEPTION_HANDLING”…””}”(hhh!j ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jNh!jïubhŒ to ”…””}”(hŒ to ”h!jïhhhANhCNubjO)”}”(hŒ``1``”h]”hŒ1”…””}”(hhh!j, ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jNh!jïubhŒ,, and is only available for AArch64 systems.”…””}”(hŒ,, and is only available for AArch64 systems.”h!jïhhhANhCNubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKh!jŽhhubj)”}”(hhh]”(j’)”}”(hŒIntroduction”h]”hŒIntroduction”…””}”(hjJ h!jH hhhANhCNubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j‘h!jE hhhAj¡hCKubj£)”}”(hXThrough various control bits in the ``SCR_EL3`` register, the Arm architecture allows for asynchronous exceptions to be routed to EL3. As described in the :ref:`Interrupt Management Framework` document, depending on the chosen interrupt routing model, TF-A appropriately sets the ``FIQ`` and ``IRQ`` bits of ``SCR_EL3`` register to effect this routing. For most use cases, other than for the purpose of facilitating context switch between Normal and Secure worlds, FIQs and IRQs routed to EL3 are not required to be handled in EL3.”h]”(hŒ$Through various control bits in the ”…””}”(hŒ$Through various control bits in the ”h!jV hhhANhCNubjO)”}”(hŒ``SCR_EL3``”h]”hŒSCR_EL3”…””}”(hhh!j_ ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jNh!jV ubhŒl register, the Arm architecture allows for asynchronous exceptions to be routed to EL3. As described in the ”…””}”(hŒl register, the Arm architecture allows for asynchronous exceptions to be routed to EL3. As described in the ”h!jV hhhANhCNubh)”}”(hŒ%:ref:`Interrupt Management Framework`”h]”h)”}”(hjt h]”hŒInterrupt Management Framework”…””}”(hhh!jv ubah"}”(h$]”h&]”(h(Œstd”Œstd-ref”eh+]”h-]”h/]”uh1hh!jr ubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”j€ Œreftype”Œref”Œrefexplicit”‰Œrefwarn”ˆh?Œinterrupt management framework”uh1hhAj¡hCKh!jV ubhŒX document, depending on the chosen interrupt routing model, TF-A appropriately sets the ”…””}”(hŒX document, depending on the chosen interrupt routing model, TF-A appropriately sets the ”h!jV hhhANhCNubjO)”}”(hŒ``FIQ``”h]”hŒFIQ”…””}”(hhh!j— ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jNh!jV ubhŒ and ”…””}”(hŒ and ”h!jV hhhANhCNubjO)”}”(hŒ``IRQ``”h]”hŒIRQ”…””}”(hhh!jª ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jNh!jV ubhŒ bits of ”…””}”(hŒ bits of ”h!jV hhhANhCNubjO)”}”(hŒ``SCR_EL3``”h]”hŒSCR_EL3”…””}”(hhh!j½ ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jNh!jV ubhŒÔ register to effect this routing. For most use cases, other than for the purpose of facilitating context switch between Normal and Secure worlds, FIQs and IRQs routed to EL3 are not required to be handled in EL3.”…””}”(hŒÔ register to effect this routing. For most use cases, other than for the purpose of facilitating context switch between Normal and Secure worlds, FIQs and IRQs routed to EL3 are not required to be handled in EL3.”h!jV hhhANhCNubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKh!jE hhubj£)”}”(hŒ†However, the evolving system and standards landscape demands that various exceptions are targeted at and handled in EL3. For instance:”h]”hŒ†However, the evolving system and standards landscape demands that various exceptions are targeted at and handled in EL3. For instance:”…””}”(hjØ h!jÖ hhhANhCNubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKh!jE hhubjÕ)”}”(hhh]”(jÚ)”}”(hXùStarting with ARMv8.2 architecture extension, many RAS features have been introduced to the Arm architecture. With RAS features implemented, various components of the system may use one of the asynchronous exceptions to signal error conditions to PEs. These error conditions are of critical nature, and it's imperative that corrective or remedial actions are taken at the earliest opportunity. Therefore, a *Firmware-first Handling* approach is generally followed in response to RAS events in the system. ”h]”j£)”}”(hXøStarting with ARMv8.2 architecture extension, many RAS features have been introduced to the Arm architecture. With RAS features implemented, various components of the system may use one of the asynchronous exceptions to signal error conditions to PEs. These error conditions are of critical nature, and it's imperative that corrective or remedial actions are taken at the earliest opportunity. Therefore, a *Firmware-first Handling* approach is generally followed in response to RAS events in the system.”h]”(hX™Starting with ARMv8.2 architecture extension, many RAS features have been introduced to the Arm architecture. With RAS features implemented, various components of the system may use one of the asynchronous exceptions to signal error conditions to PEs. These error conditions are of critical nature, and itâ€™s imperative that corrective or remedial actions are taken at the earliest opportunity. Therefore, a ”…””}”(hX—Starting with ARMv8.2 architecture extension, many RAS features have been introduced to the Arm architecture. With RAS features implemented, various components of the system may use one of the asynchronous exceptions to signal error conditions to PEs. These error conditions are of critical nature, and it's imperative that corrective or remedial actions are taken at the earliest opportunity. Therefore, a ”h!jë ubh Œemphasis”“”)”}”(hŒ*Firmware-first Handling*”h]”hŒFirmware-first Handling”…””}”(hhh!jö ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jô h!jë ubhŒH approach is generally followed in response to RAS events in the system.”…””}”(hŒH approach is generally followed in response to RAS events in the system.”h!jë ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCK"h!jç ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÙh!jä hhhAj¡hCNubjÚ)”}”(hXßThe Arm `SDEI specification`_ defines interfaces through which Normal world interacts with the Runtime Firmware in order to request notification of system events. The |SDEI| specification requires that these events are notified even when the Normal world executes with the exceptions masked. This too implies that firmware-first handling is required, where the events are first received by the EL3 firmware, and then dispatched to Normal world through purely software mechanism. ”h]”j£)”}”(hXÞThe Arm `SDEI specification`_ defines interfaces through which Normal world interacts with the Runtime Firmware in order to request notification of system events. The |SDEI| specification requires that these events are notified even when the Normal world executes with the exceptions masked. This too implies that firmware-first handling is required, where the events are first received by the EL3 firmware, and then dispatched to Normal world through purely software mechanism.”h]”(hŒThe Arm ”…””}”(hŒThe Arm ”h!jubjª)”}”(hŒ`SDEI specification`_”h]”hŒSDEI specification”…””}”(hŒSDEI specification”h!j"ubah"}”(h$]”h&]”h+]”h-]”h/]”Œname”ŒSDEI specification”Œrefuri”Œqhttp://infocenter.arm.com/help/topic/com.arm.doc.den0054a/ARM_DEN0054A_Software_Delegated_Exception_Interface.pdf”uh1j©h!jj¾KubhŒŠ defines interfaces through which Normal world interacts with the Runtime Firmware in order to request notification of system events. The ”…””}”(hŒŠ defines interfaces through which Normal world interacts with the Runtime Firmware in order to request notification of system events. The ”h!jubh)”}”(hj h]”h)”}”(hj h]”hŒSDEI”…””}”(hhh!j=ubah"}”(h$]”h&]”(h(jjeh+]”h-]”h/]”uh1hhANhCNh!j:ubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”jŒreftype”j#Œrefexplicit”‰Œrefwarn”ˆŒ reftarget”j&uh1hhAhBhCK*h!jubhX1 specification requires that these events are notified even when the Normal world executes with the exceptions masked. This too implies that firmware-first handling is required, where the events are first received by the EL3 firmware, and then dispatched to Normal world through purely software mechanism.”…””}”(hX1 specification requires that these events are notified even when the Normal world executes with the exceptions masked. This too implies that firmware-first handling is required, where the events are first received by the EL3 firmware, and then dispatched to Normal world through purely software mechanism.”h!jubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCK*h!jubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÙh!jä hhhAj¡hCNubeh"}”(h$]”h&]”h+]”h-]”h/]”j'j(uh1jÔhAj¡hCK"h!jE hhubj£)”}”(hX@For |TF-A|, firmware-first handling means that asynchronous exceptions are suitably routed to EL3, and the Runtime Firmware (BL31) is extended to include software components that are capable of handling those exceptions that target EL3. These componentsâ€”referred to as *dispatchers* [#spd]_ in generalâ€”may choose to:”h]”(hŒFor ”…””}”(hŒFor ”h!jmhhhANhCNubh)”}”(hj¹ h]”h)”}”(hj¹ h]”hŒTF-A”…””}”(hhh!jyubah"}”(h$]”h&]”(h(jÅ jÆ eh+]”h-]”h/]”uh1hhANhCNh!jvubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”jÅ Œreftype”jÓ Œrefexplicit”‰Œrefwarn”ˆŒ reftarget”jÖ uh1hhAhBhCK:h!jmhhubhX, firmware-first handling means that asynchronous exceptions are suitably routed to EL3, and the Runtime Firmware (BL31) is extended to include software components that are capable of handling those exceptions that target EL3. These componentsâ€”referred to as ”…””}”(hX, firmware-first handling means that asynchronous exceptions are suitably routed to EL3, and the Runtime Firmware (BL31) is extended to include software components that are capable of handling those exceptions that target EL3. These componentsâ€”referred to as ”h!jmhhhANhCNubjõ )”}”(hŒ *dispatchers*”h]”hŒdispatchers”…””}”(hhh!j—ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jô h!jmubhŒ ”…””}”(hŒ ”h!jmhhhANhCNubh Œfootnote_reference”“”)”}”(hŒ[#spd]_”h]”hŒ1”…””}”(hhh!j¬ubah"}”(h$]”Œid1”ah&]”h+]”h-]”h/]”Œauto”Kj¼Œspd”Œdocname”h9uh1jªh!jmj¾KubhŒ in generalâ€”may choose to:”…””}”(hŒ in generalâ€”may choose to:”h!jmhhhANhCNubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCK2h!jE hhubh Œtarget”“”)”}”(hŒ.. _delegation-use-cases:”h]”h"}”(h$]”h&]”h+]”h-]”h/]”j¼Œdelegation-use-cases”uh1jÉhCK}h!jE hhhAj¡Œ referenced”KubjÕ)”}”(hhh]”(jÚ)”}”(hŒbReceive and handle exceptions entirely in EL3, meaning the exceptions handling terminates in EL3. ”h]”j£)”}”(hŒaReceive and handle exceptions entirely in EL3, meaning the exceptions handling terminates in EL3.”h]”hŒaReceive and handle exceptions entirely in EL3, meaning the exceptions handling terminates in EL3.”…””}”(hjàh!jÞubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCK:h!jÚubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÙh!j×hhhAj¡hCNubjÚ)”}”(hŒÕReceive exceptions, but handle part of the exception in EL3, and delegate the rest of the handling to a dedicated software stack running at lower Secure ELs. In this scheme, the handling spans various secure ELs. ”h]”j£)”}”(hŒÔReceive exceptions, but handle part of the exception in EL3, and delegate the rest of the handling to a dedicated software stack running at lower Secure ELs. In this scheme, the handling spans various secure ELs.”h]”hŒÔReceive exceptions, but handle part of the exception in EL3, and delegate the rest of the handling to a dedicated software stack running at lower Secure ELs. In this scheme, the handling spans various secure ELs.”…””}”(hjøh!jöubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCK=h!jòubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÙh!j×hhhAj¡hCNubjÚ)”}”(hX¨Receive exceptions, but handle part of the exception in EL3, and delegate processing of the error to dedicated software stack running at lower secure ELs (as above); additionally, the Normal world may also be required to participate in the handling, or be notified of such events (for example, as an |SDEI| event). In this scheme, exception handling potentially and maximally spans all ELs in both Secure and Normal worlds. ”h]”j£)”}”(hX§Receive exceptions, but handle part of the exception in EL3, and delegate processing of the error to dedicated software stack running at lower secure ELs (as above); additionally, the Normal world may also be required to participate in the handling, or be notified of such events (for example, as an |SDEI| event). In this scheme, exception handling potentially and maximally spans all ELs in both Secure and Normal worlds.”h]”(hX,Receive exceptions, but handle part of the exception in EL3, and delegate processing of the error to dedicated software stack running at lower secure ELs (as above); additionally, the Normal world may also be required to participate in the handling, or be notified of such events (for example, as an ”…””}”(hX,Receive exceptions, but handle part of the exception in EL3, and delegate processing of the error to dedicated software stack running at lower secure ELs (as above); additionally, the Normal world may also be required to participate in the handling, or be notified of such events (for example, as an ”h!jubh)”}”(hj h]”h)”}”(hj h]”hŒSDEI”…””}”(hhh!jubah"}”(h$]”h&]”(h(jjeh+]”h-]”h/]”uh1hhANhCNh!jubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”jŒreftype”j#Œrefexplicit”‰Œrefwarn”ˆŒ reftarget”j&uh1hhAhBhCK*h!jubhŒu event). In this scheme, exception handling potentially and maximally spans all ELs in both Secure and Normal worlds.”…””}”(hŒu event). In this scheme, exception handling potentially and maximally spans all ELs in both Secure and Normal worlds.”h!jubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKAh!j ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÙh!j×hhhAj¡hCNubeh"}”(h$]”jÕah&]”h+]”Œdelegation-use-cases”ah-]”h/]”j'j(uh1jÔhAj¡hCK:h!jE hhŒexpect_referenced_by_name”}”jHjËsŒexpect_referenced_by_id”}”jÕjËsjÖKubj£)”}”(hŒšOn any given system, all of the above handling models may be employed independently depending on platform choice and the nature of the exception received.”h]”hŒšOn any given system, all of the above handling models may be employed independently depending on platform choice and the nature of the exception received.”…””}”(hjQh!jOhhhANhCNubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKHh!jE hhubh Œfootnote”“”)”}”(hŒœNot to be confused with :ref:`Secure Payload Dispatcher `, which is an EL3 component that operates in EL3 on behalf of Secure OS. ”h]”(h Œlabel”“”)”}”(hhh]”hŒ1”…””}”(hhh!jehhhANhCNubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jch!j_hhhANhCNubj£)”}”(hŒ›Not to be confused with :ref:`Secure Payload Dispatcher `, which is an EL3 component that operates in EL3 on behalf of Secure OS.”h]”(hŒNot to be confused with ”…””}”(hŒNot to be confused with ”h!jrubh)”}”(hŒ;:ref:`Secure Payload Dispatcher `”h]”h)”}”(hj}h]”hŒSecure Payload Dispatcher”…””}”(hhh!jubah"}”(h$]”h&]”(h(Œstd”Œstd-ref”eh+]”h-]”h/]”uh1hh!j{ubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”j‰Œreftype”Œref”Œrefexplicit”ˆŒrefwarn”ˆh?Œfirmware_design_sel1_spd”uh1hhAj¡hCKLh!jrubhŒH, which is an EL3 component that operates in EL3 on behalf of Secure OS.”…””}”(hŒH, which is an EL3 component that operates in EL3 on behalf of Secure OS.”h!jrubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKLh!j_ubeh"}”(h$]”j¼ah&]”h+]”Œspd”ah-]”h/]”j¶aj»Kj½h9uh1j]hAj¡hCKLh!jE hhubeh"}”(h$]”Œintroduction”ah&]”h+]”Œintroduction”ah-]”h/]”uh1jŒh!jŽhhhAj¡hCKubj)”}”(hhh]”(j’)”}”(hŒ(The role of Exception Handling Framework”h]”hŒ(The role of Exception Handling Framework”…””}”(hjºh!j¸hhhANhCNubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j‘h!jµhhhAj¡hCKQubj£)”}”(hX‚Corollary to the use cases cited above, the primary role of the |EHF| is to facilitate firmware-first handling of exceptions on Arm systems. The |EHF| thus enables multiple exception dispatchers in runtime firmware to co-exist, register for, and handle exceptions targeted at EL3. This section outlines the basics, and the rest of this document expands the various aspects of the |EHF|.”h]”(hŒ@Corollary to the use cases cited above, the primary role of the ”…””}”(hŒ@Corollary to the use cases cited above, the primary role of the ”h!jÆhhhANhCNubh)”}”(hj«h]”h)”}”(hj«h]”hŒEHF”…””}”(hhh!jÒubah"}”(h$]”h&]”(h(j·j¸eh+]”h-]”h/]”uh1hhANhCNh!jÏubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”j·Œreftype”jÅŒrefexplicit”‰Œrefwarn”ˆŒ reftarget”jÈuh1hhAhBhCKh!jÆhhubhŒL is to facilitate firmware-first handling of exceptions on Arm systems. The ”…””}”(hŒL is to facilitate firmware-first handling of exceptions on Arm systems. The ”h!jÆhhhANhCNubh)”}”(hj«h]”h)”}”(hj«h]”hŒEHF”…””}”(hhh!jóubah"}”(h$]”h&]”(h(j·j¸eh+]”h-]”h/]”uh1hhANhCNh!jðubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”j·Œreftype”jÅŒrefexplicit”‰Œrefwarn”ˆŒ reftarget”jÈuh1hhAhBhCKh!jÆhhubhŒæ thus enables multiple exception dispatchers in runtime firmware to co-exist, register for, and handle exceptions targeted at EL3. This section outlines the basics, and the rest of this document expands the various aspects of the ”…””}”(hŒæ thus enables multiple exception dispatchers in runtime firmware to co-exist, register for, and handle exceptions targeted at EL3. This section outlines the basics, and the rest of this document expands the various aspects of the ”h!jÆhhhANhCNubh)”}”(hj«h]”h)”}”(hj«h]”hŒEHF”…””}”(hhh!jubah"}”(h$]”h&]”(h(j·j¸eh+]”h-]”h/]”uh1hhANhCNh!jubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”j·Œreftype”jÅŒrefexplicit”‰Œrefwarn”ˆŒ reftarget”jÈuh1hhAhBhCKh!jÆhhubhŒ.”…””}”(hŒ.”h!jÆhhhANhCNubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKSh!jµhhubj£)”}”(hX In order to arbitrate exception handling among dispatchers, the |EHF| operation is based on a priority scheme. This priority scheme is closely tied to how the Arm GIC architecture defines it, although it's applied to non-interrupt exceptions too (SErrors, for example).”h]”(hŒ@In order to arbitrate exception handling among dispatchers, the ”…””}”(hŒ@In order to arbitrate exception handling among dispatchers, the ”h!j8hhhANhCNubh)”}”(hj«h]”h)”}”(hj«h]”hŒEHF”…””}”(hhh!jDubah"}”(h$]”h&]”(h(j·j¸eh+]”h-]”h/]”uh1hhANhCNh!jAubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”j·Œreftype”jÅŒrefexplicit”‰Œrefwarn”ˆŒ reftarget”jÈuh1hhAhBhCKh!j8hhubhŒÊ operation is based on a priority scheme. This priority scheme is closely tied to how the Arm GIC architecture defines it, although itâ€™s applied to non-interrupt exceptions too (SErrors, for example).”…””}”(hŒÈ operation is based on a priority scheme. This priority scheme is closely tied to how the Arm GIC architecture defines it, although it's applied to non-interrupt exceptions too (SErrors, for example).”h!j8hhhANhCNubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKYh!jµhhubj£)”}”(hXUThe platform is required to `partition`__ the Secure priority space into priority levels as applicable for the Secure software stack. It then assigns the dispatchers to one or more priority levels. The dispatchers then register handlers for the priority levels at runtime. A dispatcher can register handlers for more than one priority level.”h]”(hŒThe platform is required to ”…””}”(hŒThe platform is required to ”h!jhhhhANhCNubjª)”}”(hŒ `partition`__”h]”hŒ partition”…””}”(hŒ partition”h!jqubah"}”(h$]”h&]”h+]”h-]”h/]”Œname”jyŒ anonymous”Kj¼Œpartitioning-priority-levels”uh1j©h!jhj¾KubhX, the Secure priority space into priority levels as applicable for the Secure software stack. It then assigns the dispatchers to one or more priority levels. The dispatchers then register handlers for the priority levels at runtime. A dispatcher can register handlers for more than one priority level.”…””}”(hX, the Secure priority space into priority levels as applicable for the Secure software stack. It then assigns the dispatchers to one or more priority levels. The dispatchers then register handlers for the priority levels at runtime. A dispatcher can register handlers for more than one priority level.”h!jhhhhANhCNubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCK^h!jµhhubjÊ)”}”(hŒ&.. __: `Partitioning priority levels`_”h]”h"}”(h$]”Œid2”ah&]”h+]”h-]”h/]”jKj¼j‚uh1jÉŒindirect_reference_name”ŒPartitioning priority levels”hCK©h!jµhhhAj¡jÖKj¾KubjÊ)”}”(hŒ.. _ehf-figure:”h]”h"}”(h$]”h&]”h+]”h-]”h/]”j¼Œ ehf-figure”uh1jÉhCK¬h!jµhhhAj¡jÖKubh Œimage”“”)”}”(hŒ1.. image:: ../resources/diagrams/draw.io/ehf.svg ”h]”h"}”(h$]”j¥ah&]”h+]”Œ ehf-figure”ah-]”h/]”Œuri”Œ"resources/diagrams/draw.io/ehf.svg”Œ candidates”}”Œ*”j´suh1j¦h!jµhhhAj¡hCKjjK}”j°j›sjM}”j¥j›sjÖKubj£)”}”(hX´A priority level is *active* when a handler at that priority level is currently executing in EL3, or has delegated the execution to a lower EL. For interrupts, this is implicit when an interrupt is targeted and acknowledged at EL3, and the priority of the acknowledged interrupt is used to match its registered handler. The priority level is likewise implicitly deactivated when the interrupt handling concludes by EOIing the interrupt.”h]”(hŒA priority level is ”…””}”(hŒA priority level is ”h!jºhhhANhCNubjõ )”}”(hŒ*active*”h]”hŒactive”…””}”(hhh!jÃubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jô h!jºubhX˜ when a handler at that priority level is currently executing in EL3, or has delegated the execution to a lower EL. For interrupts, this is implicit when an interrupt is targeted and acknowledged at EL3, and the priority of the acknowledged interrupt is used to match its registered handler. The priority level is likewise implicitly deactivated when the interrupt handling concludes by EOIing the interrupt.”…””}”(hX˜ when a handler at that priority level is currently executing in EL3, or has delegated the execution to a lower EL. For interrupts, this is implicit when an interrupt is targeted and acknowledged at EL3, and the priority of the acknowledged interrupt is used to match its registered handler. The priority level is likewise implicitly deactivated when the interrupt handling concludes by EOIing the interrupt.”h!jºhhhANhCNubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKkh!jµhhubj£)”}”(hXšNon-interrupt exceptions (SErrors, for example) don't have a notion of priority. In order for the priority arbitration to work, the |EHF| provides APIs in order for these non-interrupt exceptions to assume a priority, and to interwork with interrupts. Dispatchers handling such exceptions must therefore explicitly activate and deactivate the respective priority level as and when they're handled or delegated.”h]”(hŒ†Non-interrupt exceptions (SErrors, for example) donâ€™t have a notion of priority. In order for the priority arbitration to work, the ”…””}”(hŒ„Non-interrupt exceptions (SErrors, for example) don't have a notion of priority. In order for the priority arbitration to work, the ”h!jÜhhhANhCNubh)”}”(hj«h]”h)”}”(hj«h]”hŒEHF”…””}”(hhh!jèubah"}”(h$]”h&]”(h(j·j¸eh+]”h-]”h/]”uh1hhANhCNh!jåubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”j·Œreftype”jÅŒrefexplicit”‰Œrefwarn”ˆŒ reftarget”jÈuh1hhAhBhCKh!jÜhhubhX provides APIs in order for these non-interrupt exceptions to assume a priority, and to interwork with interrupts. Dispatchers handling such exceptions must therefore explicitly activate and deactivate the respective priority level as and when theyâ€™re handled or delegated.”…””}”(hX provides APIs in order for these non-interrupt exceptions to assume a priority, and to interwork with interrupts. Dispatchers handling such exceptions must therefore explicitly activate and deactivate the respective priority level as and when they're handled or delegated.”h!jÜhhhANhCNubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKrh!jµhhubj£)”}”(hXBecause priority activation and deactivation for interrupt handling is implicit and involves GIC priority masking, it's impossible for a lower priority interrupt to preempt a higher priority one. By extension, this means that a lower priority dispatcher cannot preempt a higher-priority one. Priority activation and deactivation for non-interrupt exceptions, however, has to be explicit. The |EHF| therefore disallows for lower priority level to be activated whilst a higher priority level is active, and would result in a panic. Likewise, a panic would result if it's attempted to deactivate a lower priority level when a higher priority level is active.”h]”(hXŠBecause priority activation and deactivation for interrupt handling is implicit and involves GIC priority masking, itâ€™s impossible for a lower priority interrupt to preempt a higher priority one. By extension, this means that a lower priority dispatcher cannot preempt a higher-priority one. Priority activation and deactivation for non-interrupt exceptions, however, has to be explicit. The ”…””}”(hXˆBecause priority activation and deactivation for interrupt handling is implicit and involves GIC priority masking, it's impossible for a lower priority interrupt to preempt a higher priority one. By extension, this means that a lower priority dispatcher cannot preempt a higher-priority one. Priority activation and deactivation for non-interrupt exceptions, however, has to be explicit. The ”h!jhhhANhCNubh)”}”(hj«h]”h)”}”(hj«h]”hŒEHF”…””}”(hhh!jubah"}”(h$]”h&]”(h(j·j¸eh+]”h-]”h/]”uh1hhANhCNh!jubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”j·Œreftype”jÅŒrefexplicit”‰Œrefwarn”ˆŒ reftarget”jÈuh1hhAhBhCKh!jhhubhX therefore disallows for lower priority level to be activated whilst a higher priority level is active, and would result in a panic. Likewise, a panic would result if itâ€™s attempted to deactivate a lower priority level when a higher priority level is active.”…””}”(hX therefore disallows for lower priority level to be activated whilst a higher priority level is active, and would result in a panic. Likewise, a panic would result if it's attempted to deactivate a lower priority level when a higher priority level is active.”h!jhhhANhCNubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKyh!jµhhubj£)”}”(hXZIn essence, priority level activation and deactivation conceptually works like a stackâ€”priority levels stack up in strictly increasing fashion, and need to be unstacked in strictly the reverse order. For interrupts, the GIC ensures this is the case; for non-interrupts, the |EHF| monitors and asserts this. See `Transition of priority levels`_.”h]”(hXIn essence, priority level activation and deactivation conceptually works like a stackâ€”priority levels stack up in strictly increasing fashion, and need to be unstacked in strictly the reverse order. For interrupts, the GIC ensures this is the case; for non-interrupts, the ”…””}”(hXIn essence, priority level activation and deactivation conceptually works like a stackâ€”priority levels stack up in strictly increasing fashion, and need to be unstacked in strictly the reverse order. For interrupts, the GIC ensures this is the case; for non-interrupts, the ”h!j<hhhANhCNubh)”}”(hj«h]”h)”}”(hj«h]”hŒEHF”…””}”(hhh!jHubah"}”(h$]”h&]”(h(j·j¸eh+]”h-]”h/]”uh1hhANhCNh!jEubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”j·Œreftype”jÅŒrefexplicit”‰Œrefwarn”ˆŒ reftarget”jÈuh1hhAhBhCKh!j<hhubhŒ monitors and asserts this. See ”…””}”(hŒ monitors and asserts this. See ”h!j<hhhANhCNubjª)”}”(hŒ `Transition of priority levels`_”h]”hŒTransition of priority levels”…””}”(hŒTransition of priority levels”h!jfubah"}”(h$]”h&]”h+]”h-]”h/]”Œname”ŒTransition of priority levels”j¼Œtransition-of-priority-levels”uh1j©h!j<j¾KubhŒ.”…””}”(hj1h!j<hhhANhCNubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKƒh!jµhhubjÊ)”}”(hŒ.. _interrupt-handling:”h]”h"}”(h$]”h&]”h+]”h-]”h/]”j¼Œinterrupt-handling”uh1jÉhCKÎh!jµhhhAj¡ubeh"}”(h$]”Œ(the-role-of-exception-handling-framework”ah&]”h+]”Œ(the role of exception handling framework”ah-]”h/]”uh1jŒh!jŽhhhAj¡hCKQubj)”}”(hhh]”(j’)”}”(hŒInterrupt handling”h]”hŒInterrupt handling”…””}”(hjšh!j˜hhhANhCNubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j‘h!j•hhhAj¡hCKŒubj£)”}”(hŒçThe |EHF| is a client of *Interrupt Management Framework*, and registers the top-level handler for interrupts that target EL3, as described in the :ref:`Interrupt Management Framework` document. This has the following implications:”h]”(hŒThe ”…””}”(hŒThe ”h!j¦hhhANhCNubh)”}”(hj«h]”h)”}”(hj«h]”hŒEHF”…””}”(hhh!j²ubah"}”(h$]”h&]”(h(j·j¸eh+]”h-]”h/]”uh1hhANhCNh!j¯ubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”j·Œreftype”jÅŒrefexplicit”‰Œrefwarn”ˆŒ reftarget”jÈuh1hhAhBhCKh!j¦hhubhŒ is a client of ”…””}”(hŒ is a client of ”h!j¦hhhANhCNubjõ )”}”(hŒ *Interrupt Management Framework*”h]”hŒInterrupt Management Framework”…””}”(hhh!jÐubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jô h!j¦ubhŒZ, and registers the top-level handler for interrupts that target EL3, as described in the ”…””}”(hŒZ, and registers the top-level handler for interrupts that target EL3, as described in the ”h!j¦hhhANhCNubh)”}”(hŒ%:ref:`Interrupt Management Framework`”h]”h)”}”(hjåh]”hŒInterrupt Management Framework”…””}”(hhh!jçubah"}”(h$]”h&]”(h(Œstd”Œstd-ref”eh+]”h-]”h/]”uh1hh!jãubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”jñŒreftype”Œref”Œrefexplicit”‰Œrefwarn”ˆh?Œinterrupt management framework”uh1hhAj¡hCKŽh!j¦ubhŒ/ document. This has the following implications:”…””}”(hŒ/ document. This has the following implications:”h!j¦hhhANhCNubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKŽh!j•hhubjÕ)”}”(hhh]”(jÚ)”}”(hXLOn GICv3 systems, when executing in S-EL1, pending Non-secure interrupts of sufficient priority are signalled as FIQs, and therefore will be routed to EL3. As a result, S-EL1 software cannot expect to handle Non-secure interrupts at S-EL1. Essentially, this deprecates the routing mode described as :ref:`CSS=0, TEL3=0 `. In order for S-EL1 software to handle Non-secure interrupts while having |EHF| enabled, the dispatcher must adopt a model where Non-secure interrupts are received at EL3, but are then :ref:`synchronously ` handled over to S-EL1. ”h]”(j£)”}”(hXQOn GICv3 systems, when executing in S-EL1, pending Non-secure interrupts of sufficient priority are signalled as FIQs, and therefore will be routed to EL3. As a result, S-EL1 software cannot expect to handle Non-secure interrupts at S-EL1. Essentially, this deprecates the routing mode described as :ref:`CSS=0, TEL3=0 `.”h]”(hX+On GICv3 systems, when executing in S-EL1, pending Non-secure interrupts of sufficient priority are signalled as FIQs, and therefore will be routed to EL3. As a result, S-EL1 software cannot expect to handle Non-secure interrupts at S-EL1. Essentially, this deprecates the routing mode described as ”…””}”(hX+On GICv3 systems, when executing in S-EL1, pending Non-secure interrupts of sufficient priority are signalled as FIQs, and therefore will be routed to EL3. As a result, S-EL1 software cannot expect to handle Non-secure interrupts at S-EL1. Essentially, this deprecates the routing mode described as ”h!jubh)”}”(hŒ%:ref:`CSS=0, TEL3=0 `”h]”h)”}”(hj h]”hŒ CSS=0, TEL3=0”…””}”(hhh!j"ubah"}”(h$]”h&]”(h(Œstd”Œstd-ref”eh+]”h-]”h/]”uh1hh!jubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”j,Œreftype”Œref”Œrefexplicit”ˆŒrefwarn”ˆh?Œel3 interrupts”uh1hhAj¡hCK“h!jubhŒ.”…””}”(hj1h!jubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCK“h!jubj£)”}”(hŒøIn order for S-EL1 software to handle Non-secure interrupts while having |EHF| enabled, the dispatcher must adopt a model where Non-secure interrupts are received at EL3, but are then :ref:`synchronously ` handled over to S-EL1.”h]”(hŒIIn order for S-EL1 software to handle Non-secure interrupts while having ”…””}”(hŒIIn order for S-EL1 software to handle Non-secure interrupts while having ”h!jHubh)”}”(hj«h]”h)”}”(hj«h]”hŒEHF”…””}”(hhh!jTubah"}”(h$]”h&]”(h(j·j¸eh+]”h-]”h/]”uh1hhANhCNh!jQubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”j·Œreftype”jÅŒrefexplicit”‰Œrefwarn”ˆŒ reftarget”jÈuh1hhAhBhCKh!jHubhŒj enabled, the dispatcher must adopt a model where Non-secure interrupts are received at EL3, but are then ”…””}”(hŒj enabled, the dispatcher must adopt a model where Non-secure interrupts are received at EL3, but are then ”h!jHubh)”}”(hŒ):ref:`synchronously `”h]”h)”}”(hjth]”hŒ synchronously”…””}”(hhh!jvubah"}”(h$]”h&]”(h(Œstd”Œstd-ref”eh+]”h-]”h/]”uh1hh!jrubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”j€Œreftype”Œref”Œrefexplicit”ˆŒrefwarn”ˆh?Œsp-synchronous-int”uh1hhAj¡hCK™h!jHubhŒ handled over to S-EL1.”…””}”(hŒ handled over to S-EL1.”h!jHubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCK™h!jubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1jÙh!jhhhAj¡hCNubjÚ)”}”(hŒ„On GICv2 systems, it's required that the build option ``GICV2_G0_FOR_EL3`` is set to ``1`` so that *Group 0* interrupts target EL3. ”h]”j£)”}”(hŒƒOn GICv2 systems, it's required that the build option ``GICV2_G0_FOR_EL3`` is set to ``1`` so that *Group 0* interrupts target EL3.”h]”(hŒ8On GICv2 systems, itâ€™s required that the build option ”…””}”(hŒ6On GICv2 systems, it's required that the build option ”h!j§ubjO)”}”(hŒ``GICV2_G0_FOR_EL3``”h]”hŒGICV2_G0_FOR_EL3”…””}”(hhh!j°ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jNh!j§ubhŒ is set to ”…””}”(hŒ is set to ”h!j§ubjO)”}”(hŒ``1``”h]”hŒ1”…””}”(hhh!jÃubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jNh!j§ubhŒ so that ”…””}”(hŒ so that ”h!j§ubjõ )”}”(hŒ *Group 0*”h]”hŒGroup 0”…””}”(hhh!jÖubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jô h!j§ubhŒ interrupts target EL3.”…””}”(hŒ interrupts target EL3.”h!j§ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKžh!j£ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÙh!jhhhAj¡hCNubjÚ)”}”(hŒÚWhile executing in Secure world, |EHF| sets GIC Priority Mask Register to the lowest Secure priority. This means that no Non-secure interrupts can preempt Secure execution. See `Effect on SMC calls`_ for more details. ”•h]”j£)”}”(hŒÙWhile executing in Secure world, |EHF| sets GIC Priority Mask Register to the lowest Secure priority. This means that no Non-secure interrupts can preempt Secure execution. See `Effect on SMC calls`_ for more details.”h]”(hŒ!While executing in Secure world, ”…””}”(hŒ!While executing in Secure world, ”h!jùubh)”}”(hj«h]”h)”}”(hj«h]”hŒEHF”…””}”(hhh!jubah"}”(h$]”h&]”(h(j·j¸eh+]”h-]”h/]”uh1hhANhCNh!jubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”j·Œreftype”jÅŒrefexplicit”‰Œrefwarn”ˆŒ reftarget”jÈuh1hhAhBhCKh!jùubhŒ‹ sets GIC Priority Mask Register to the lowest Secure priority. This means that no Non-secure interrupts can preempt Secure execution. See ”…””}”(hŒ‹ sets GIC Priority Mask Register to the lowest Secure priority. This means that no Non-secure interrupts can preempt Secure execution. See ”h!jùubjª)”}”(hŒ`Effect on SMC calls`_”h]”hŒEffect on SMC calls”…””}”(hŒEffect on SMC calls”h!j#ubah"}”(h$]”h&]”h+]”h-]”h/]”Œname”ŒEffect on SMC calls”j¼Œeffect-on-smc-calls”uh1j©h!jùj¾KubhŒ for more details.”…””}”(hŒ for more details.”h!jùubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCK¡h!jõubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÙh!jhhhAj¡hCNubeh"}”(h$]”h&]”h+]”h-]”h/]”j'j(uh1jÔhAj¡hCK“h!j•hhubj£)”}”(hXsAs mentioned above, with |EHF|, the platform is required to partition *Group 0* interrupts into distinct priority levels. A dispatcher that chooses to receive interrupts can then *own* one or more priority levels, and register interrupt handlers for them. A given priority level can be assigned to only one handler. A dispatcher may register more than one priority level.”h]”(hŒAs mentioned above, with ”…””}”(hŒAs mentioned above, with ”h!jLhhhANhCNubh)”}”(hj«h]”h)”}”(hj«h]”hŒEHF”…””}”(hhh!jXubah"}”(h$]”h&]”(h(j·j¸eh+]”h-]”h/]”uh1hhANhCNh!jUubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”j·Œreftype”jÅŒrefexplicit”‰Œrefwarn”ˆŒ reftarget”jÈuh1hhAhBhCKh!jLhhubhŒ(, the platform is required to partition ”…””}”(hŒ(, the platform is required to partition ”h!jLhhhANhCNubjõ )”}”(hŒ *Group 0*”h]”hŒGroup 0”…””}”(hhh!jvubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jô h!jLubhŒd interrupts into distinct priority levels. A dispatcher that chooses to receive interrupts can then ”…””}”(hŒd interrupts into distinct priority levels. A dispatcher that chooses to receive interrupts can then ”h!jLhhhANhCNubjõ )”}”(hŒ*own*”h]”hŒown”…””}”(hhh!j‰ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jô h!jLubhŒ» one or more priority levels, and register interrupt handlers for them. A given priority level can be assigned to only one handler. A dispatcher may register more than one priority level.”…””}”(hŒ» one or more priority levels, and register interrupt handlers for them. A given priority level can be assigned to only one handler. A dispatcher may register more than one priority level.”h!jLhhhANhCNubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCK¥h!j•hhubj£)”}”(hŒ@Dispatchers are assigned interrupt priority levels in two steps:”h]”hŒ@Dispatchers are assigned interrupt priority levels in two steps:”…””}”(hj¤h!j¢hhhANhCNubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCK«h!j•hhubjÊ)”}”(hŒ!.. _Partitioning priority levels:”h]”h"}”(h$]”h&]”h+]”h-]”h/]”j¼j‚uh1jÉhCKòh!j•hhhAj¡jÖKubj)”}”(hhh]”(j’)”}”(hŒPartitioning priority levels”h]”hŒPartitioning priority levels”…””}”(hj¿h!j½hhhANhCNubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j‘h!jºhhhAj¡hCK°ubj£)”}”(hŒøInterrupts are associated to dispatchers by way of grouping and assigning interrupts to a priority level. In other words, all interrupts that are to target a particular dispatcher should fall in a particular priority level. For priority assignment:”h]”hŒøInterrupts are associated to dispatchers by way of grouping and assigning interrupts to a priority level. In other words, all interrupts that are to target a particular dispatcher should fall in a particular priority level. For priority assignment:”…””}”(hjÍh!jËhhhANhCNubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCK²h!jºhhubjÕ)”}”(hhh]”(jÚ)”}”(hŒ]Of the 8 bits of priority that Arm GIC architecture permits, bit 7 must be 0 (secure space). ”h]”j£)”}”(hŒ\Of the 8 bits of priority that Arm GIC architecture permits, bit 7 must be 0 (secure space).”h]”hŒ\Of the 8 bits of priority that Arm GIC architecture permits, bit 7 must be 0 (secure space).”…””}”(hjâh!jàubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCK·h!jÜubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÙh!jÙhhhAj¡hCNubjÚ)”}”(hXÀDepending on the number of dispatchers to support, the platform must choose to use the top *n* of the 7 remaining bits to identify and assign interrupts to individual dispatchers. Choosing *n* bits supports up to 2\ :sup:`n` distinct dispatchers. For example, by choosing 2 additional bits (i.e., bits 6 and 5), the platform can partition into 4 secure priority ranges: ``0x0``, ``0x20``, ``0x40``, and ``0x60``. See `Interrupt handling example`_. ”h]”j£)”}”(hX¿Depending on the number of dispatchers to support, the platform must choose to use the top *n* of the 7 remaining bits to identify and assign interrupts to individual dispatchers. Choosing *n* bits supports up to 2\ :sup:`n` distinct dispatchers. For example, by choosing 2 additional bits (i.e., bits 6 and 5), the platform can partition into 4 secure priority ranges: ``0x0``, ``0x20``, ``0x40``, and ``0x60``. See `Interrupt handling example`_.”h]”(hŒ[Depending on the number of dispatchers to support, the platform must choose to use the top ”…””}”(hŒ[Depending on the number of dispatchers to support, the platform must choose to use the top ”h!jøubjõ )”}”(hŒ*n*”h]”hŒn”…””}”(hhh!jubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jô h!jøubhŒ_ of the 7 remaining bits to identify and assign interrupts to individual dispatchers. Choosing ”…””}”(hŒ_ of the 7 remaining bits to identify and assign interrupts to individual dispatchers. Choosing ”h!jøubjõ )”}”(hŒ*n*”h]”hŒn”…””}”(hhh!jubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jô h!jøubhŒ bits supports up to 2 ”…””}”(hŒ bits supports up to 2\ ”h!jøubh Œsuperscript”“”)”}”(hŒ:sup:`n`”h]”hŒn”…””}”(hhh!j)ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j'h!jøubhŒ’ distinct dispatchers. For example, by choosing 2 additional bits (i.e., bits 6 and 5), the platform can partition into 4 secure priority ranges: ”…””}”(hŒ’ distinct dispatchers. For example, by choosing 2 additional bits (i.e., bits 6 and 5), the platform can partition into 4 secure priority ranges: ”h!jøubjO)”}”(hŒ``0x0``”h]”hŒ0x0”…””}”(hhh!j<ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jNh!jøubhŒ, ”…””}”(hŒ, ”h!jøubjO)”}”(hŒ``0x20``”h]”hŒ0x20”…””}”(hhh!jOubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jNh!jøubhŒ, ”…””}”(hŒ, ”h!jøubjO)”}”(hŒ``0x40``”h]”hŒ0x40”…””}”(hhh!jbubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jNh!jøubhŒ, and ”…””}”(hŒ, and ”h!jøubjO)”}”(hŒ``0x60``”h]”hŒ0x60”…””}”(hhh!juubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jNh!jøubhŒ. See ”…””}”(hŒ. See ”h!jøubjª)”}”(hŒ`Interrupt handling example`_”h]”hŒInterrupt handling example”…””}”(hŒInterrupt handling example”h!jˆubah"}”(h$]”h&]”h+]”h-]”h/]”Œname”ŒInterrupt handling example”j¼Œinterrupt-handling-example”uh1j©h!jøj¾KubhŒ.”…””}”(hj1h!jøubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKºh!jôubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÙh!jÙhhhAj¡hCNubeh"}”(h$]”h&]”h+]”h-]”h/]”j'j(uh1jÔhAj¡hCK·h!jºhhubh Œnote”“”)”}”(hXnThe Arm GIC architecture requires that a GIC implementation that supports two security states must implement at least 32 priority levels; i.e., at least 5 upper bits of the 8 bits are writeable. In the scheme described above, when choosing *n* bits for priority range assignment, the platform must ensure that at least ``n+1`` top bits of GIC priority are writeable.”h]”j£)”}”(hXnThe Arm GIC architecture requires that a GIC implementation that supports two security states must implement at least 32 priority levels; i.e., at least 5 upper bits of the 8 bits are writeable. In the scheme described above, when choosing *n* bits for priority range assignment, the platform must ensure that at least ``n+1`` top bits of GIC priority are writeable.”h]”(hŒðThe Arm GIC architecture requires that a GIC implementation that supports two security states must implement at least 32 priority levels; i.e., at least 5 upper bits of the 8 bits are writeable. In the scheme described above, when choosing ”…””}”(hŒðThe Arm GIC architecture requires that a GIC implementation that supports two security states must implement at least 32 priority levels; i.e., at least 5 upper bits of the 8 bits are writeable. In the scheme described above, when choosing ”h!j¶ubjõ )”}”(hŒ*n*”h]”hŒn”…””}”(hhh!j¿ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jô h!j¶ubhŒL bits for priority range assignment, the platform must ensure that at least ”…””}”(hŒL bits for priority range assignment, the platform must ensure that at least ”h!j¶ubjO)”}”(hŒ``n+1``”h]”hŒn+1”…””}”(hhh!jÒubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jNh!j¶ubhŒ( top bits of GIC priority are writeable.”…””}”(hŒ( top bits of GIC priority are writeable.”h!j¶ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKÃh!j²ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j°h!jºhhhAj¡hCNubj£)”}”(hX’The priority thus assigned to an interrupt is also used to determine the priority of delegated execution in lower ELs. Delegated execution in lower EL is associated with a priority level chosen with ``ehf_activate_priority()`` API (described `later`__). The chosen priority level also determines the interrupts masked while executing in a lower EL, therefore controls preemption of delegated execution.”h]”(hŒÇThe priority thus assigned to an interrupt is also used to determine the priority of delegated execution in lower ELs. Delegated execution in lower EL is associated with a priority level chosen with ”…””}”(hŒÇThe priority thus assigned to an interrupt is also used to determine the priority of delegated execution in lower ELs. Delegated execution in lower EL is associated with a priority level chosen with ”h!jñhhhANhCNubjO)”}”(hŒ``ehf_activate_priority()``”h]”hŒehf_activate_priority()”…””}”(hhh!júubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jNh!jñubhŒ API (described ”…””}”(hŒ API (described ”h!jñhhhANhCNubjª)”}”(hŒ `later`__”h]”hŒlater”…””}”(hŒlater”h!j ubah"}”(h$]”h&]”h+]”h-]”h/]”Œname”jjKj¼Œehf-apis”uh1j©h!jñj¾KubhŒ—). The chosen priority level also determines the interrupts masked while executing in a lower EL, therefore controls preemption of delegated execution.”…””}”(hŒ—). The chosen priority level also determines the interrupts masked while executing in a lower EL, therefore controls preemption of delegated execution.”h!jñhhhANhCNubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKÉh!jºhhubjÊ)”}”(hŒ.. __: `ehf-apis`_”h]”h"}”(h$]”Œid5”ah&]”h+]”h-]”h/]”jKj¼juh1jÉj™Œehf-apis”hCMh!jºhhhAj¡jÖKj¾Kubj£)”}”(hŒôThe platform expresses the chosen priority levels by declaring an array of priority level descriptors. Each entry in the array is of type ``ehf_pri_desc_t``, and declares a priority level, and shall be populated by the ``EHF_PRI_DESC()`` macro.”h]”(hŒŠThe platform expresses the chosen priority levels by declaring an array of priority level descriptors. Each entry in the array is of type ”…””}”(hŒŠThe platform expresses the chosen priority levels by declaring an array of priority level descriptors. Each entry in the array is of type ”h!j5hhhANhCNubjO)”}”(hŒ``ehf_pri_desc_t``”h]”hŒehf_pri_desc_t”…””}”(hhh!j>ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jNh!j5ubhŒ?, and declares a priority level, and shall be populated by the ”…””}”(hŒ?, and declares a priority level, and shall be populated by the ”h!j5hhhANhCNubjO)”}”(hŒ``EHF_PRI_DESC()``”h]”hŒEHF_PRI_DESC()”…””}”(hhh!jQubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jNh!j5ubhŒ macro.”…””}”(hŒ macro.”h!j5hhhANhCNubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKÒh!jºhhubh Œwarning”“”)”}”(hX3The macro ``EHF_PRI_DESC()`` installs the descriptors in the array at a computed index, and not necessarily where the macro is placed in the array. The size of the array might therefore be larger than what it appears to be. The ``ARRAY_SIZE()`` macro therefore should be used to determine the size of array.”h]”j£)”}”(hX3The macro ``EHF_PRI_DESC()`` installs the descriptors in the array at a computed index, and not necessarily where the macro is placed in the array. The size of the array might therefore be larger than what it appears to be. The ``ARRAY_SIZE()`` macro therefore should be used to determine the size of array.”h]”(hŒ The macro ”…””}”(hŒ The macro ”h!jpubjO)”}”(hŒ``EHF_PRI_DESC()``”h]”hŒEHF_PRI_DESC()”…””}”(hhh!jyubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jNh!jpubhŒÈ installs the descriptors in the array at a computed index, and not necessarily where the macro is placed in the array. The size of the array might therefore be larger than what it appears to be. The ”…””}”(hŒÈ installs the descriptors in the array at a computed index, and not necessarily where the macro is placed in the array. The size of the array might therefore be larger than what it appears to be. The ”h!jpubjO)”}”(hŒ``ARRAY_SIZE()``”h]”hŒARRAY_SIZE()”…””}”(hhh!jŒubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jNh!jpubhŒ? macro therefore should be used to determine the size of array.”…””}”(hŒ? macro therefore should be used to determine the size of array.”h!jpubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKÙh!jlubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jjh!jºhhhAj¡hCNubj£)”}”(hŒcFinally, this array of descriptors is exposed to |EHF| via the ``EHF_REGISTER_PRIORITIES()`` macro.”h]”(hŒ1Finally, this array of descriptors is exposed to ”…””}”(hŒ1Finally, this array of descriptors is exposed to ”h!j«hhhANhCNubh)”}”(hj«h]”h)”}”(hj«h]”hŒEHF”…””}”(hhh!j·ubah"}”(h$]”h&]”(h(j·j¸eh+]”h-]”h/]”uh1hhANhCNh!j´ubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”j·Œreftype”jÅŒrefexplicit”‰Œrefwarn”ˆŒ reftarget”jÈuh1hhAhBhCKh!j«hhubhŒ via the ”…””}”(hŒ via the ”h!j«hhhANhCNubjO)”}”(hŒ``EHF_REGISTER_PRIORITIES()``”h]”hŒEHF_REGISTER_PRIORITIES()”…””}”(hhh!jÕubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jNh!j«ubhŒ macro.”…””}”(hŒ macro.”h!j«hhhANhCNubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKßh!jºhhubj£)”}”(hŒkRefer to the `Interrupt handling example`_ for usage. See also: `Interrupt Prioritisation Considerations`_.”h]”(hŒ Refer to the ”…””}”(hŒ Refer to the ”h!jîhhhANhCNubjª)”}”(hŒ`Interrupt handling example`_”h]”hŒInterrupt handling example”…””}”(hŒInterrupt handling example”h!j÷ubah"}”(h$]”h&]”h+]”h-]”h/]”Œname”ŒInterrupt handling example”j¼j™uh1j©h!jîj¾KubhŒ for usage. See also: ”…””}”(hŒ for usage. See also: ”h!jîhhhANhCNubjª)”}”(hŒ*`Interrupt Prioritisation Considerations`_”h]”hŒ'Interrupt Prioritisation Considerations”…””}”(hŒ'Interrupt Prioritisation Considerations”h!j ubah"}”(h$]”h&]”h+]”h-]”h/]”Œname”Œ'Interrupt Prioritisation Considerations”j¼Œ'interrupt-prioritisation-considerations”uh1j©h!jîj¾KubhŒ.”…””}”(hj1h!jîhhhANhCNubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKâh!jºhhubeh"}”(h$]”(j‚Œid4”eh&]”h+]”Œpartitioning priority levels”ah-]”Œpartitioning priority levels”ah/]”uh1jŒh!j•hhhAj¡hCK°jÖKjK}”j.j°sjM}”j‚j°subj)”}”(hhh]”(j’)”}”(hŒProgramming priority”h]”hŒProgramming priority”…””}”(hj9h!j7hhhANhCNubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j‘h!j4hhhAj¡hCKæubj£)”}”(hŒÅThe text in `Partitioning priority levels`_ only describes how the platform expresses the required levels of priority. It however doesn't choose interrupts nor program the required priority in GIC.”h]”(hŒThe text in ”…””}”(hŒThe text in ”h!jEhhhANhCNubjª)”}”(hŒ`Partitioning priority levels`_”h]”hŒPartitioning priority levels”…””}”(hŒPartitioning priority levels”h!jNubah"}”(h$]”h&]”h+]”h-]”h/]”Œname”ŒPartitioning priority levels”j¼j‚uh1j©h!jEj¾KubhŒœ only describes how the platform expresses the required levels of priority. It however doesnâ€™t choose interrupts nor program the required priority in GIC.”…””}”(hŒš only describes how the platform expresses the required levels of priority. It however doesn't choose interrupts nor program the required priority in GIC.”h!jEhhhANhCNubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKèh!j4hhubj£)”}”(hXZThe :ref:`Firmware Design guide` explains methods for configuring secure interrupts. |EHF| requires the platform to enumerate interrupt properties (as opposed to just numbers) of Secure interrupts. The priority of secure interrupts must match that as determined in the `Partitioning priority levels`_ section above.”h]”(hŒThe ”…””}”(hŒThe ”h!jjhhhANhCNubh)”}”(hŒ;:ref:`Firmware Design guide`”h]”h)”}”(hjuh]”hŒFirmware Design guide”…””}”(hhh!jwubah"}”(h$]”h&]”(h(Œstd”Œstd-ref”eh+]”h-]”h/]”uh1hh!jsubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”jŒreftype”Œref”Œrefexplicit”ˆŒrefwarn”ˆh?Œconfiguring-secure-interrupts”uh1hhAj¡hCKìh!jjubhŒ5 explains methods for configuring secure interrupts. ”…””}”(hŒ5 explains methods for configuring secure interrupts. ”h!jjhhhANhCNubh)”}”(hj«h]”h)”}”(hj«h]”hŒEHF”…””}”(hhh!j›ubah"}”(h$]”h&]”(h(j·j¸eh+]”h-]”h/]”uh1hhANhCNh!j˜ubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”j·Œreftype”jÅŒrefexplicit”‰Œrefwarn”ˆŒ reftarget”jÈuh1hhAhBhCKh!jjhhubhŒ³ requires the platform to enumerate interrupt properties (as opposed to just numbers) of Secure interrupts. The priority of secure interrupts must match that as determined in the ”…””}”(hŒ³ requires the platform to enumerate interrupt properties (as opposed to just numbers) of Secure interrupts. The priority of secure interrupts must match that as determined in the ”h!jjhhhANhCNubjª)”}”(hŒ`Partitioning priority levels`_”h]”hŒPartitioning priority levels”…””}”(hŒPartitioning priority levels”h!j¹ubah"}”(h$]”h&]”h+]”h-]”h/]”Œname”ŒPartitioning priority levels”j¼j‚uh1j©h!jjj¾KubhŒ section above.”…””}”(hŒ section above.”h!jjhhhANhCNubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKìh!j4hhubj£)”}”(hŒUSee `Limitations`_, and also refer to `Interrupt handling example`_ for illustration.”h]”(hŒSee ”…””}”(hŒSee ”h!jÕhhhANhCNubjª)”}”(hŒ`Limitations`_”h]”hŒLimitations”…””}”(hŒLimitations”h!jÞubah"}”(h$]”h&]”h+]”h-]”h/]”Œname”jæj¼Œlimitations”uh1j©h!jÕj¾KubhŒ, and also refer to ”…””}”(hŒ, and also refer to ”h!jÕhhhANhCNubjª)”}”(hŒ`Interrupt handling example`_”h]”hŒInterrupt handling example”…””}”(hŒInterrupt handling example”h!jôubah"}”(h$]”h&]”h+]”h-]”h/]”Œname”ŒInterrupt handling example”j¼j™uh1j©h!jÕj¾KubhŒ for illustration.”…””}”(hŒ for illustration.”h!jÕhhhANhCNubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKòh!j4hhubeh"}”(h$]”Œprogramming-priority”ah&]”h+]”Œprogramming priority”ah-]”h/]”uh1jŒh!j•hhhAj¡hCKæjÖKubeh"}”(h$]”(jŒj½eh&]”h+]”(Œinterrupt handling”Œinterrupt-handling”eh-]”h/]”uh1jŒh!jŽhhhAj¡hCKŒjK}”jj‚sjM}”jŒj‚sjÖKubj)”}”(hhh]”(j’)”}”(hŒRegistering handler”h]”hŒRegistering handler”…””}”(hj'h!j%hhhANhCNubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j‘h!j"hhhAj¡hCKöubj£)”}”(hŒRDispatchers register handlers for their priority levels through the following API:”h]”hŒRDispatchers register handlers for their priority levels through the following API:”…””}”(hj5h!j3hhhANhCNubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKøh!j"hhubh Œ literal_block”“”)”}”(hŒAint ehf_register_priority_handler(int pri, ehf_handler_t handler)”h]”hŒAint ehf_register_priority_handler(int pri, ehf_handler_t handler)”…””}”(hhh!jCubah"}”(h$]”h&]”h+]”h-]”h/]”Œforce”‰Œhighlight_args”}”Œ xml:space”Œpreserve”Œlanguage”Œc”uh1jAhAj¡hCKûh!j"hhubj£)”}”(hŒThe API takes two arguments:”h]”hŒThe API takes two arguments:”…””}”(hjZh!jXhhhANhCNubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKÿh!j"hhubjÕ)”}”(hhh]”(jÚ)”}”(hŒ>The priority level for which the handler is being registered; ”h]”j£)”}”(hŒ=The priority level for which the handler is being registered;”h]”hŒ=The priority level for which the handler is being registered;”…””}”(hjoh!jmubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMh!jiubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÙh!jfhhhAj¡hCNubjÚ)”}”(hŒFThe handler to be registered. The handler must be aligned to 4 bytes. ”h]”j£)”}”(hŒEThe handler to be registered. The handler must be aligned to 4 bytes.”h]”hŒEThe handler to be registered. The handler must be aligned to 4 bytes.”…””}”(hj‡h!j…ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMh!jubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÙh!jfhhhAj¡hCNubeh"}”(h$]”h&]”h+]”h-]”h/]”j'j(uh1jÔhAj¡hCMh!j"hhubj£)”}”(hŒ\If a dispatcher owns more than one priority levels, it has to call the API for each of them.”h]”hŒ\If a dispatcher owns more than one priority levels, it has to call the API for each of them.”…””}”(hj¡h!jŸhhhANhCNubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMh!j"hhubj£)”}”(hŒ0The API will succeed, and return ``0``, only if:”h]”(hŒ!The API will succeed, and return ”…””}”(hŒ!The API will succeed, and return ”h!jhhhANhCNubjO)”}”(hŒ``0``”h]”hŒ0”…””}”(hhh!j¶ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jNh!jubhŒ , only if:”…””}”(hŒ , only if:”h!jhhhANhCNubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMh!j"hhubjÕ)”}”(hhh]”(jÚ)”}”(hŒ=There exists a descriptor with the priority level requested. ”h]”j£)”}”(hŒ`.”h]”(hŒ2The parameters are as obtained from the top-level ”…””}”(hŒ2The parameters are as obtained from the top-level ”h!jHhhhANhCNubh)”}”(hŒ3:ref:`EL3 interrupt handler `”h]”h)”}”(hjSh]”hŒEL3 interrupt handler”…””}”(hhh!jUubah"}”(h$]”h&]”(h(Œstd”Œstd-ref”eh+]”h-]”h/]”uh1hh!jQubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”j_Œreftype”Œref”Œrefexplicit”ˆŒrefwarn”ˆh?Œel3-runtime-firmware”uh1hhAj¡hCMh!jHubhŒ.”…””}”(hj1h!jHhhhANhCNubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMh!j"hhubj£)”}”(hX The :ref:`SDEI dispatcher`, for example, expects the platform to allocate two different priority levelsâ€” ``PLAT_SDEI_CRITICAL_PRI``, and ``PLAT_SDEI_NORMAL_PRI`` â€”and registers the same handler to handle both levels.”h]”(hŒThe ”…””}”(hŒThe ”h!j{hhhANhCNubh)”}”(hŒD:ref:`SDEI dispatcher`”h]”h)”}”(hj†h]”hŒSDEI dispatcher”…””}”(hhh!jˆubah"}”(h$]”h&]”(h(Œstd”Œstd-ref”eh+]”h-]”h/]”uh1hh!j„ubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”j’Œreftype”Œref”Œrefexplicit”ˆŒrefwarn”ˆh?Œ,sdei: software delegated exception interface”uh1hhAj¡hCMh!j{ubhŒQ, for example, expects the platform to allocate two different priority levelsâ€” ”…””}”(hŒQ, for example, expects the platform to allocate two different priority levelsâ€” ”h!j{hhhANhCNubjO)”}”(hŒ``PLAT_SDEI_CRITICAL_PRI``”h]”hŒPLAT_SDEI_CRITICAL_PRI”…””}”(hhh!j©ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jNh!j{ubhŒ, and ”…””}”(hŒ, and ”h!j{hhhANhCNubjO)”}”(hŒ``PLAT_SDEI_NORMAL_PRI``”h]”hŒPLAT_SDEI_NORMAL_PRI”…””}”(hhh!j¼ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jNh!j{ubhŒ9 â€”and registers the same handler to handle both levels.”…””}”(hŒ9 â€”and registers the same handler to handle both levels.”h!j{hhhANhCNubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMh!j"hhubeh"}”(h$]”Œregistering-handler”ah&]”h+]”Œregistering handler”ah-]”h/]”uh1jŒh!jŽhhhAj¡hCKöubj)”}”(hhh]”(j’)”}”(hŒInterrupt handling example”h]”hŒInterrupt handling example”…””}”(hjâh!jàhhhANhCNubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j‘h!jÝhhhAj¡hCM ubj£)”}”(hŒxThe following annotated snippet demonstrates how a platform might choose to assign interrupts to fictitious dispatchers:”h]”hŒxThe following annotated snippet demonstrates how a platform might choose to assign interrupts to fictitious dispatchers:”…””}”(hjðh!jîhhhANhCNubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCM"h!jÝhhubjB)”}”(hX#include #include #include ... /* * This platform uses 2 bits for interrupt association. In total, 3 upper * bits are in use. * * 7 6 5 3 0 * .-.-.-.----------. * |0|b|b| ..0.. | * '-'-'-'----------' */ #define PLAT_PRI_BITS 2 /* Priorities for individual dispatchers */ #define DISP0_PRIO 0x00 /* Not used */ #define DISP1_PRIO 0x20 #define DISP2_PRIO 0x40 #define DISP3_PRIO 0x60 /* Install priority level descriptors for each dispatcher */ ehf_pri_desc_t plat_exceptions[] = { EHF_PRI_DESC(PLAT_PRI_BITS, DISP1_PRIO), EHF_PRI_DESC(PLAT_PRI_BITS, DISP2_PRIO), EHF_PRI_DESC(PLAT_PRI_BITS, DISP3_PRIO), }; /* Expose priority descriptors to Exception Handling Framework */ EHF_REGISTER_PRIORITIES(plat_exceptions, ARRAY_SIZE(plat_exceptions), PLAT_PRI_BITS); ... /* List interrupt properties for GIC driver. All interrupts target EL3 */ const interrupt_prop_t plat_interrupts[] = { /* Dispatcher 1 owns interrupts d1_0 and d1_1, so assigns priority DISP1_PRIO */ INTR_PROP_DESC(d1_0, DISP1_PRIO, INTR_TYPE_EL3, GIC_INTR_CFG_LEVEL), INTR_PROP_DESC(d1_1, DISP1_PRIO, INTR_TYPE_EL3, GIC_INTR_CFG_LEVEL), /* Dispatcher 2 owns interrupts d2_0 and d2_1, so assigns priority DISP2_PRIO */ INTR_PROP_DESC(d2_0, DISP2_PRIO, INTR_TYPE_EL3, GIC_INTR_CFG_LEVEL), INTR_PROP_DESC(d2_1, DISP2_PRIO, INTR_TYPE_EL3, GIC_INTR_CFG_LEVEL), /* Dispatcher 3 owns interrupts d3_0 and d3_1, so assigns priority DISP3_PRIO */ INTR_PROP_DESC(d3_0, DISP3_PRIO, INTR_TYPE_EL3, GIC_INTR_CFG_LEVEL), INTR_PROP_DESC(d3_1, DISP3_PRIO, INTR_TYPE_EL3, GIC_INTR_CFG_LEVEL), }; ... /* Dispatcher 1 registers its handler */ ehf_register_priority_handler(DISP1_PRIO, disp1_handler); /* Dispatcher 2 registers its handler */ ehf_register_priority_handler(DISP2_PRIO, disp2_handler); /* Dispatcher 3 registers its handler */ ehf_register_priority_handler(DISP3_PRIO, disp3_handler); ...”h]”hX#include #include #include ... /* * This platform uses 2 bits for interrupt association. In total, 3 upper * bits are in use. * * 7 6 5 3 0 * .-.-.-.----------. * |0|b|b| ..0.. | * '-'-'-'----------' */ #define PLAT_PRI_BITS 2 /* Priorities for individual dispatchers */ #define DISP0_PRIO 0x00 /* Not used */ #define DISP1_PRIO 0x20 #define DISP2_PRIO 0x40 #define DISP3_PRIO 0x60 /* Install priority level descriptors for each dispatcher */ ehf_pri_desc_t plat_exceptions[] = { EHF_PRI_DESC(PLAT_PRI_BITS, DISP1_PRIO), EHF_PRI_DESC(PLAT_PRI_BITS, DISP2_PRIO), EHF_PRI_DESC(PLAT_PRI_BITS, DISP3_PRIO), }; /* Expose priority descriptors to Exception Handling Framework */ EHF_REGISTER_PRIORITIES(plat_exceptions, ARRAY_SIZE(plat_exceptions), PLAT_PRI_BITS); ... /* List interrupt properties for GIC driver. All interrupts target EL3 */ const interrupt_prop_t plat_interrupts[] = { /* Dispatcher 1 owns interrupts d1_0 and d1_1, so assigns priority DISP1_PRIO */ INTR_PROP_DESC(d1_0, DISP1_PRIO, INTR_TYPE_EL3, GIC_INTR_CFG_LEVEL), INTR_PROP_DESC(d1_1, DISP1_PRIO, INTR_TYPE_EL3, GIC_INTR_CFG_LEVEL), /* Dispatcher 2 owns interrupts d2_0 and d2_1, so assigns priority DISP2_PRIO */ INTR_PROP_DESC(d2_0, DISP2_PRIO, INTR_TYPE_EL3, GIC_INTR_CFG_LEVEL), INTR_PROP_DESC(d2_1, DISP2_PRIO, INTR_TYPE_EL3, GIC_INTR_CFG_LEVEL), /* Dispatcher 3 owns interrupts d3_0 and d3_1, so assigns priority DISP3_PRIO */ INTR_PROP_DESC(d3_0, DISP3_PRIO, INTR_TYPE_EL3, GIC_INTR_CFG_LEVEL), INTR_PROP_DESC(d3_1, DISP3_PRIO, INTR_TYPE_EL3, GIC_INTR_CFG_LEVEL), }; ... /* Dispatcher 1 registers its handler */ ehf_register_priority_handler(DISP1_PRIO, disp1_handler); /* Dispatcher 2 registers its handler */ ehf_register_priority_handler(DISP2_PRIO, disp2_handler); /* Dispatcher 3 registers its handler */ ehf_register_priority_handler(DISP3_PRIO, disp3_handler); ...”…””}”(hhh!jüubah"}”(h$]”h&]”h+]”h-]”h/]”Œforce”‰Œhighlight_args”}”jTjUjVjWuh1jAhAj¡hCM%h!jÝhhubj£)”}”(hŒ9See also the `Build-time flow`_ and the `Run-time flow`_.”h]”(hŒ See also the ”…””}”(hŒ See also the ”h!j hhhANhCNubjª)”}”(hŒ`Build-time flow`_”h]”hŒBuild-time flow”…””}”(hŒBuild-time flow”h!jubah"}”(h$]”h&]”h+]”h-]”h/]”Œname”ŒBuild-time flow”j¼Œbuild-time-flow”uh1j©h!j j¾KubhŒ and the ”…””}”(hŒ and the ”h!j hhhANhCNubjª)”}”(hŒ`Run-time flow`_”h]”hŒ Run-time flow”…””}”(hŒ Run-time flow”h!j-ubah"}”(h$]”h&]”h+]”h-]”h/]”Œname”Œ Run-time flow”j¼Œ run-time-flow”uh1j©h!j j¾KubhŒ.”…””}”(hj1h!j hhhANhCNubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMgh!jÝhhubjÊ)”}”(hŒ+.. _Activating and Deactivating priorities:”h]”h"}”(h$]”h&]”h+]”h-]”h/]”j¼Œ&activating-and-deactivating-priorities”uh1jÉhCM®h!jÝhhhAj¡ubeh"}”(h$]”j™ah&]”h+]”Œinterrupt handling example”ah-]”h/]”uh1jŒh!jŽhhhAj¡hCM jÖKubj)”}”(hhh]”(j’)”}”(hŒ&Activating and Deactivating priorities”h]”hŒ&Activating and Deactivating priorities”…””}”(hj`h!j^hhhANhCNubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j‘h!j[hhhAj¡hCMlubj£)”}”(hXcA priority level is said to be *active* when an exception of that priority is being handled: for interrupts, this is implied when the interrupt is acknowledged; for non-interrupt exceptions, such as SErrors or :ref:`SDEI explicit dispatches `, this has to be done via calling ``ehf_activate_priority()``. See `Run-time flow`_.”h]”(hŒA priority level is said to be ”…””}”(hŒA priority level is said to be ”h!jlhhhANhCNubjõ )”}”(hŒ*active*”h]”hŒactive”…””}”(hhh!juubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jô h!jlubhŒ« when an exception of that priority is being handled: for interrupts, this is implied when the interrupt is acknowledged; for non-interrupt exceptions, such as SErrors or ”…””}”(hŒ« when an exception of that priority is being handled: for interrupts, this is implied when the interrupt is acknowledged; for non-interrupt exceptions, such as SErrors or ”h!jlhhhANhCNubh)”}”(hŒ=:ref:`SDEI explicit dispatches `”h]”h)”}”(hjŠh]”hŒSDEI explicit dispatches”…””}”(hhh!jŒubah"}”(h$]”h&]”(h(Œstd”Œstd-ref”eh+]”h-]”h/]”uh1hh!jˆubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”j–Œreftype”Œref”Œrefexplicit”ˆŒrefwarn”ˆh?Œexplicit-dispatch-of-events”uh1hhAj¡hCMnh!jlubhŒ", this has to be done via calling ”…””}”(hŒ", this has to be done via calling ”h!jlhhhANhCNubjO)”}”(hŒ``ehf_activate_priority()``”h]”hŒehf_activate_priority()”…””}”(hhh!jubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jNh!jlubhŒ. See ”…””}”(hŒ. See ”h!jlhhhANhCNubjª)”}”(hŒ`Run-time flow`_”h]”hŒ Run-time flow”…””}”(hŒ Run-time flow”h!jÀubah"}”(h$]”h&]”h+]”h-]”h/]”Œname”Œ Run-time flow”j¼j>uh1j©h!jlj¾KubhŒ.”…””}”(hj1h!jlhhhANhCNubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMnh!j[hhubj£)”}”(hX@Conversely, when the dispatcher has reached a logical resolution for the cause of the exception, the corresponding priority level ought to be deactivated. As above, for interrupts, this is implied when the interrupt is EOId in the GIC; for other exceptions, this has to be done via calling ``ehf_deactivate_priority()``.”h]”(hX"Conversely, when the dispatcher has reached a logical resolution for the cause of the exception, the corresponding priority level ought to be deactivated. As above, for interrupts, this is implied when the interrupt is EOId in the GIC; for other exceptions, this has to be done via calling ”…””}”(hX"Conversely, when the dispatcher has reached a logical resolution for the cause of the exception, the corresponding priority level ought to be deactivated. As above, for interrupts, this is implied when the interrupt is EOId in the GIC; for other exceptions, this has to be done via calling ”h!jÛhhhANhCNubjO)”}”(hŒ``ehf_deactivate_priority()``”h]”hŒehf_deactivate_priority()”…””}”(hhh!jäubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jNh!jÛubhŒ.”…””}”(hj1h!jÛhhhANhCNubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMth!j[hhubj£)”}”(hŒ|Thanks to `different provisions`__ for exception delegation, there are potentially more than one work flow for deactivation:”h]”(hŒ Thanks to ”…””}”(hŒ Thanks to ”h!jühhhANhCNubjª)”}”(hŒ`different provisions`__”h]”hŒdifferent provisions”…””}”(hŒdifferent provisions”h!jubah"}”(h$]”h&]”h+]”h-]”h/]”Œname”Œdifferent provisions”jKj¼jÕuh1j©h!jüj¾KubhŒZ for exception delegation, there are potentially more than one work flow for deactivation:”…””}”(hŒZ for exception delegation, there are potentially more than one work flow for deactivation:”h!jühhhANhCNubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMzh!j[hhubjÊ)”}”(hŒ.. __: `delegation-use-cases`_”h]”h"}”(h$]”Œid7”ah&]”h+]”h-]”h/]”jKj¼jÕuh1jÉj™Œdelegation-use-cases”hCMÂh!j[hhhAj¡jÖKj¾KubjÊ)”}”(hŒ.. _deactivation workflows:”h]”h"}”(h$]”h&]”h+]”h-]”h/]”j¼Œdeactivation-workflows”uh1jÉhCMÄh!j[hhhAj¡jÖKubjÕ)”}”(hhh]”(jÚ)”}”(hX'The dispatcher has addressed the cause of the exception, and decided to take no further action. In this case, the dispatcher's handler deactivates the priority level before returning to the |EHF|. Runtime firmware, upon exit through an ``ERET``, resumes execution before the interrupt occurred. ”h]”j£)”}”(hX&The dispatcher has addressed the cause of the exception, and decided to take no further action. In this case, the dispatcher's handler deactivates the priority level before returning to the |EHF|. Runtime firmware, upon exit through an ``ERET``, resumes execution before the interrupt occurred.”h]”(hŒÀThe dispatcher has addressed the cause of the exception, and decided to take no further action. In this case, the dispatcherâ€™s handler deactivates the priority level before returning to the ”…””}”(hŒ¾The dispatcher has addressed the cause of the exception, and decided to take no further action. In this case, the dispatcher's handler deactivates the priority level before returning to the ”h!j?ubh)”}”(hj«h]”h)”}”(hj«h]”hŒEHF”…””}”(hhh!jKubah"}”(h$]”h&]”(h(j·j¸eh+]”h-]”h/]”uh1hhANhCNh!jHubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”j·Œreftype”jÅŒrefexplicit”‰Œrefwarn”ˆŒ reftarget”jÈuh1hhAhBhCKh!j?ubhŒ). Runtime firmware, upon exit through an ”…””}”(hŒ). Runtime firmware, upon exit through an ”h!j?ubjO)”}”(hŒ``ERET``”h]”hŒERET”…””}”(hhh!jiubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jNh!j?ubhŒ2, resumes execution before the interrupt occurred.”…””}”(hŒ2, resumes execution before the interrupt occurred.”h!j?ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMh!j;ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÙh!j8hhhAj¡hCNubjÚ)”}”(hXøThe dispatcher has to delegate the execution to lower ELs, and the cause of the exception can be considered resolved only when the lower EL returns signals complete (via an ``SMC``) at a future point in time. The following sequence ensues: #. The dispatcher calls ``setjmp()`` to setup a jump point, and arranges to enter a lower EL upon the next ``ERET``. #. Through the ensuing ``ERET`` from runtime firmware, execution is delegated to a lower EL. #. The lower EL completes its execution, and signals completion via an ``SMC``. #. The ``SMC`` is handled by the same dispatcher that handled the exception previously. Noticing the conclusion of exception handling, the dispatcher does ``longjmp()`` to resume beyond the previous jump point. ”h]”(j£)”}”(hŒïThe dispatcher has to delegate the execution to lower ELs, and the cause of the exception can be considered resolved only when the lower EL returns signals complete (via an ``SMC``) at a future point in time. The following sequence ensues:”h]”(hŒThe dispatcher has to delegate the execution to lower ELs, and the cause of the exception can be considered resolved only when the lower EL returns signals complete (via an ”…””}”(hŒThe dispatcher has to delegate the execution to lower ELs, and the cause of the exception can be considered resolved only when the lower EL returns signals complete (via an ”h!jŒubjO)”}”(hŒ``SMC``”h]”hŒSMC”…””}”(hhh!j•ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jNh!jŒubhŒ;) at a future point in time. The following sequence ensues:”…””}”(hŒ;) at a future point in time. The following sequence ensues:”h!jŒubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCM†h!jˆubh Œenumerated_list”“”)”}”(hhh]”(jÚ)”}”(hŒrThe dispatcher calls ``setjmp()`` to setup a jump point, and arranges to enter a lower EL upon the next ``ERET``. ”h]”j£)”}”(hŒqThe dispatcher calls ``setjmp()`` to setup a jump point, and arranges to enter a lower EL upon the next ``ERET``.”h]”(hŒThe dispatcher calls ”…””}”(hŒThe dispatcher calls ”h!j·ubjO)”}”(hŒ``setjmp()``”h]”hŒsetjmp()”…””}”(hhh!jÀubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jNh!j·ubhŒG to setup a jump point, and arranges to enter a lower EL upon the next ”…””}”(hŒG to setup a jump point, and arranges to enter a lower EL upon the next ”h!j·ubjO)”}”(hŒ``ERET``”h]”hŒERET”…””}”(hhh!jÓubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jNh!j·ubhŒ.”…””}”(hj1h!j·ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCM‹h!j³ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÙh!j°ubjÚ)”}”(hŒZThrough the ensuing ``ERET`` from runtime firmware, execution is delegated to a lower EL. ”h]”j£)”}”(hŒYThrough the ensuing ``ERET`` from runtime firmware, execution is delegated to a lower EL.”h]”(hŒThrough the ensuing ”…””}”(hŒThrough the ensuing ”h!jõubjO)”}”(hŒ``ERET``”h]”hŒERET”…””}”(hhh!jþubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jNh!jõubhŒ= from runtime firmware, execution is delegated to a lower EL.”…””}”(hŒ= from runtime firmware, execution is delegated to a lower EL.”h!jõubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMŽh!jñubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÙh!j°ubjÚ)”}”(hŒMThe lower EL completes its execution, and signals completion via an ``SMC``. ”h]”j£)”}”(hŒLThe lower EL completes its execution, and signals completion via an ``SMC``.”h]”(hŒDThe lower EL completes its execution, and signals completion via an ”…””}”(hŒDThe lower EL completes its execution, and signals completion via an ”h!j!ubjO)”}”(hŒ``SMC``”h]”hŒSMC”…””}”(hhh!j*ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jNh!j!ubhŒ.”…””}”(hj1h!j!ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCM‘h!jubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÙh!j°ubjÚ)”}”(hŒÐThe ``SMC`` is handled by the same dispatcher that handled the exception previously. Noticing the conclusion of exception handling, the dispatcher does ``longjmp()`` to resume beyond the previous jump point. ”h]”j£)”}”(hŒÏThe ``SMC`` is handled by the same dispatcher that handled the exception previously. Noticing the conclusion of exception handling, the dispatcher does ``longjmp()`` to resume beyond the previous jump point.”h]”(hŒThe ”…””}”(hŒThe ”h!jLubjO)”}”(hŒ``SMC``”h]”hŒSMC”…””}”(hhh!jUubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jNh!jLubhŒ is handled by the same dispatcher that handled the exception previously. Noticing the conclusion of exception handling, the dispatcher does ”…””}”(hŒ is handled by the same dispatcher that handled the exception previously. Noticing the conclusion of exception handling, the dispatcher does ”h!jLubjO)”}”(hŒ ``longjmp()``”h]”hŒ longjmp()”…””}”(hhh!jhubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jNh!jLubhŒ* to resume beyond the previous jump point.”…””}”(hŒ* to resume beyond the previous jump point.”h!jLubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCM”h!jHubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÙh!j°ubeh"}”(h$]”h&]”h+]”h-]”h/]”Œenumtype”Œarabic”Œprefix”hŒsuffix”j1uh1j®h!jˆubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1jÙh!j8hhhANhCNubeh"}”(h$]”j7ah&]”h+]”Œdeactivation workflows”ah-]”h/]”j'j(uh1jÔhAj¡hCMh!j[hhjK}”j›j-sjM}”j7j-sjÖKubj£)”}”(hŒdAs mentioned above, the |EHF| provides the following APIs for activating and deactivating interrupt:”h]”(hŒAs mentioned above, the ”…””}”(hŒAs mentioned above, the ”h!j hhhANhCNubh)”}”(hj«h]”h)”}”(hj«h]”hŒEHF”…””}”(hhh!j¬ubah"}”(h$]”h&]”(h(j·j¸eh+]”h-]”h/]”uh1hhANhCNh!j©ubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”j·Œreftype”jÅŒrefexplicit”‰Œrefwarn”ˆŒ reftarget”jÈuh1hhAhBhCKh!j hhubhŒG provides the following APIs for activating and deactivating interrupt:”…””}”(hŒG provides the following APIs for activating and deactivating interrupt:”h!j hhhANhCNubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCM˜h!j[hhubjÊ)”}”(hŒ .. _ehf-apis:”h]”h"}”(h$]”h&]”h+]”h-]”h/]”j¼juh1jÉhCMàh!j[hhhAj¡jÖKubjÕ)”}”(hhh]”(jÚ)”}”(hXø``ehf_activate_priority()`` activates the supplied priority level, but only if the current active priority is higher than the given one; otherwise panics. Also, to prevent interruption by physical interrupts of lower priority, the |EHF| programs the *Priority Mask Register* corresponding to the PE to the priority being activated. Dispatchers typically only need to call this when handling exceptions other than interrupts, and it needs to delegate execution to a lower EL at a desired priority level. ”h]”j£)”}”(hX÷``ehf_activate_priority()`` activates the supplied priority level, but only if the current active priority is higher than the given one; otherwise panics. Also, to prevent interruption by physical interrupts of lower priority, the |EHF| programs the *Priority Mask Register* corresponding to the PE to the priority being activated. Dispatchers typically only need to call this when handling exceptions other than interrupts, and it needs to delegate execution to a lower EL at a desired priority level.”h]”(jO)”}”(hŒ``ehf_activate_priority()``”h]”hŒehf_activate_priority()”…””}”(hhh!jåubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jNh!jáubhŒÌ activates the supplied priority level, but only if the current active priority is higher than the given one; otherwise panics. Also, to prevent interruption by physical interrupts of lower priority, the ”…””}”(hŒÌ activates the supplied priority level, but only if the current active priority is higher than the given one; otherwise panics. Also, to prevent interruption by physical interrupts of lower priority, the ”h!jáubh)”}”(hj«h]”h)”}”(hj«h]”hŒEHF”…””}”(hhh!jûubah"}”(h$]”h&]”(h(j·j¸eh+]”h-]”h/]”uh1hhANhCNh!jøubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”j·Œreftype”jÅŒrefexplicit”‰Œrefwarn”ˆŒ reftarget”jÈuh1hhAhBhCKh!jáubhŒ programs the ”…””}”(hŒ programs the ”h!jáubjõ )”}”(hŒ*Priority Mask Register*”h]”hŒPriority Mask Register”…””}”(hhh!jubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jô h!jáubhŒå corresponding to the PE to the priority being activated. Dispatchers typically only need to call this when handling exceptions other than interrupts, and it needs to delegate execution to a lower EL at a desired priority level.”…””}”(hŒå corresponding to the PE to the priority being activated. Dispatchers typically only need to call this when handling exceptions other than interrupts, and it needs to delegate execution to a lower EL at a desired priority level.”h!jáubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMh!jÝubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÙh!jÚhhhAj¡hCNubjÚ)”}”(hXx``ehf_deactivate_priority()`` deactivates a given priority, but only if the current active priority is equal to the given one; otherwise panics. |EHF| also restores the *Priority Mask Register* corresponding to the PE to the priority before the call to ``ehf_activate_priority()``. Dispatchers typically only need to call this after handling exceptions other than interrupts. ”h]”j£)”}”(hXw``ehf_deactivate_priority()`` deactivates a given priority, but only if the current active priority is equal to the given one; otherwise panics. |EHF| also restores the *Priority Mask Register* corresponding to the PE to the priority before the call to ``ehf_activate_priority()``. Dispatchers typically only need to call this after handling exceptions other than interrupts.”h]”(jO)”}”(hŒ``ehf_deactivate_priority()``”h]”hŒehf_deactivate_priority()”…””}”(hhh!j@ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jNh!j<ubhŒt deactivates a given priority, but only if the current active priority is equal to the given one; otherwise panics. ”…””}”(hŒt deactivates a given priority, but only if the current active priority is equal to the given one; otherwise panics. ”h!j<ubh)”}”(hj«h]”h)”}”(hj«h]”hŒEHF”…””}”(hhh!jVubah"}”(h$]”h&]”(h(j·j¸eh+]”h-]”h/]”uh1hhANhCNh!jSubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”j·Œreftype”jÅŒrefexplicit”‰Œrefwarn”ˆŒ reftarget”jÈuh1hhAhBhCKh!j<ubhŒ also restores the ”…””}”(hŒ also restores the ”h!j<ubjõ )”}”(hŒ*Priority Mask Register*”h]”hŒPriority Mask Register”…””}”(hhh!jtubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jô h!j<ubhŒ< corresponding to the PE to the priority before the call to ”…””}”(hŒ< corresponding to the PE to the priority before the call to ”h!j<ubjO)”}”(hŒ``ehf_activate_priority()``”h]”hŒehf_activate_priority()”…””}”(hhh!j‡ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jNh!j<ubhŒ_. Dispatchers typically only need to call this after handling exceptions other than interrupts.”…””}”(hŒ_. Dispatchers typically only need to call this after handling exceptions other than interrupts.”h!j<ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCM¥h!j8ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÙh!jÚhhhAj¡hCNubeh"}”(h$]”jah&]”h+]”Œehf-apis”ah-]”h/]”j'j(uh1jÔhAj¡hCMh!j[hhjK}”jªjÐsjM}”jjÐsjÖKubj£)”}”(hŒZThe calling of APIs are subject to allowed `transitions`__. See also the `Run-time flow`_.”h]”(hŒ+The calling of APIs are subject to allowed ”…””}”(hŒ+The calling of APIs are subject to allowed ”h!j¯hhhANhCNubjª)”}”(hŒ`transitions`__”h]”hŒtransitions”…””}”(hŒtransitions”h!j¸ubah"}”(h$]”h&]”h+]”h-]”h/]”Œname”jÀjKj¼jwuh1j©h!j¯j¾KubhŒ. See also the ”…””}”(hŒ. See also the ”h!j¯hhhANhCNubjª)”}”(hŒ`Run-time flow`_”h]”hŒ Run-time flow”…””}”(hŒ Run-time flow”h!jÍubah"}”(h$]”h&]”h+]”h-]”h/]”Œname”Œ Run-time flow”j¼j>uh1j©h!j¯j¾KubhŒ.”…””}”(hj1h!j¯hhhANhCNubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCM¬h!j[hhubjÊ)”}”(hŒ'.. __: `Transition of priority levels`_”h]”h"}”(h$]”Œid8”ah&]”h+]”h-]”h/]”jKj¼jwuh1jÉj™ŒTransition of priority levels”hCMôh!j[hhhAj¡jÖKj¾Kubeh"}”(h$]”(jSŒid6”eh&]”h+]”Œ&activating and deactivating priorities”ah-]”Œ&activating and deactivating priorities”ah/]”uh1jŒh!jŽhhhAj¡hCMljÖKjK}”jùjIsjM}”jSjIsubj)”}”(hhh]”(j’)”}”(hŒTransition of priority levels”h]”hŒTransition of priority levels”…””}”(hjh!jhhhANhCNubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j‘h!jÿhhhAj¡hCM²ubj£)”}”(hŒÝThe |EHF| APIs ``ehf_activate_priority()`` and ``ehf_deactivate_priority()`` can be called to transition the current priority level on a PE. A given sequence of calls to these APIs are subject to the following conditions:”h]”(hŒThe ”…””}”(hŒThe ”h!jhhhANhCNubh)”}”(hj«h]”h)”}”(hj«h]”hŒEHF”…””}”(hhh!jubah"}”(h$]”h&]”(h(j·j¸eh+]”h-]”h/]”uh1hhANhCNh!jubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”j·Œreftype”jÅŒrefexplicit”‰Œrefwarn”ˆŒ reftarget”jÈuh1hhAhBhCKh!jhhubhŒ APIs ”…””}”(hŒ APIs ”h!jhhhANhCNubjO)”}”(hŒ``ehf_activate_priority()``”h]”hŒehf_activate_priority()”…””}”(hhh!j:ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jNh!jubhŒ and ”…””}”(hŒ and ”h!jhhhANhCNubjO)”}”(hŒ``ehf_deactivate_priority()``”h]”hŒehf_deactivate_priority()”…””}”(hhh!jMubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jNh!jubhŒ‘ can be called to transition the current priority level on a PE. A given sequence of calls to these APIs are subject to the following conditions:”…””}”(hŒ‘ can be called to transition the current priority level on a PE. A given sequence of calls to these APIs are subject to the following conditions:”h!jhhhANhCNubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCM´h!jÿhhubjÕ)”}”(hhh]”(jÚ)”}”(hŒcFor activation, the |EHF| only allows for the priority to increase (i.e. numeric value decreases); ”h]”j£)”}”(hŒbFor activation, the |EHF| only allows for the priority to increase (i.e. numeric value decreases);”h]”(hŒFor activation, the ”…””}”(hŒFor activation, the ”h!jmubh)”}”(hj«h]”h)”}”(hj«h]”hŒEHF”…””}”(hhh!jyubah"}”(h$]”h&]”(h(j·j¸eh+]”h-]”h/]”uh1hhANhCNh!jvubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”j·Œreftype”jÅŒrefexplicit”‰Œrefwarn”ˆŒ reftarget”jÈuh1hhAhBhCKh!jmubhŒI only allows for the priority to increase (i.e. numeric value decreases);”…””}”(hŒI only allows for the priority to increase (i.e. numeric value decreases);”h!jmubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCM¸h!jiubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÙh!jfhhhAj¡hCNubjÚ)”}”(hŒºFor deactivation, the |EHF| only allows for the priority to decrease (i.e. numeric value increases). Additionally, the priority being deactivated is required to be the current priority. ”h]”j£)”}”(hŒ¹For deactivation, the |EHF| only allows for the priority to decrease (i.e. numeric value increases). Additionally, the priority being deactivated is required to be the current priority.”h]”(hŒFor deactivation, the ”…””}”(hŒFor deactivation, the ”h!j§ubh)”}”(hj«h]”h)”}”(hj«h]”hŒEHF”…””}”(hhh!j³ubah"}”(h$]”h&]”(h(j·j¸eh+]”h-]”h/]”uh1hhANhCNh!j°ubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”j·Œreftype”jÅŒrefexplicit”‰Œrefwarn”ˆŒ reftarget”jÈuh1hhAhBhCKh!j§ubhŒž only allows for the priority to decrease (i.e. numeric value increases). Additionally, the priority being deactivated is required to be the current priority.”…””}”(hŒž only allows for the priority to decrease (i.e. numeric value increases). Additionally, the priority being deactivated is required to be the current priority.”h!j§ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCM»h!j£ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÙh!jfhhhAj¡hCNubeh"}”(h$]”h&]”h+]”h-]”h/]”j'j(uh1jÔhAj¡hCM¸h!jÿhhubj£)”}”(hŒ+If these are violated, a panic will result.”h]”hŒ+If these are violated, a panic will result.”…””}”(hjåh!jãhhhANhCNubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCM¿h!jÿhhubjÊ)”}”(hŒ.. _Effect on SMC calls:”h]”h"}”(h$]”h&]”h+]”h-]”h/]”j¼j4uh1jÉhCMh!jÿhhhAj¡jÖKubeh"}”(h$]”jwah&]”h+]”Œtransition of priority levels”ah-]”h/]”uh1jŒh!jŽhhhAj¡hCM²jÖKubj)”}”(hhh]”(j’)”}”(hŒEffect on SMC calls”h]”hŒEffect on SMC calls”…””}”(hjh!jhhhANhCNubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j‘h!jhhhAj¡hCMÄubj£)”}”(hX™In general, Secure execution is regarded as more important than Non-secure execution. As discussed elsewhere in this document, EL3 execution, and any delegated execution thereafter, has the effect of raising GIC's priority maskâ€”either implicitly by acknowledging Secure interrupts, or when dispatchers call ``ehf_activate_priority()``. As a result, Non-secure interrupts cannot preempt any Secure execution.”h]”(hX7In general, Secure execution is regarded as more important than Non-secure execution. As discussed elsewhere in this document, EL3 execution, and any delegated execution thereafter, has the effect of raising GICâ€™s priority maskâ€”either implicitly by acknowledging Secure interrupts, or when dispatchers call ”…””}”(hX5In general, Secure execution is regarded as more important than Non-secure execution. As discussed elsewhere in this document, EL3 execution, and any delegated execution thereafter, has the effect of raising GIC's priority maskâ€”either implicitly by acknowledging Secure interrupts, or when dispatchers call ”h!jhhhANhCNubjO)”}”(hŒ``ehf_activate_priority()``”h]”hŒehf_activate_priority()”…””}”(hhh!jubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jNh!jubhŒI. As a result, Non-secure interrupts cannot preempt any Secure execution.”…””}”(hŒI. As a result, Non-secure interrupts cannot preempt any Secure execution.”h!jhhhANhCNubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMÆh!jhhubj£)”}”(hŒ¾SMCs from Non-secure world are synchronous exceptions, and are mechanisms for Non-secure world to request Secure services. They're broadly classified as *Fast* or *Yielding* (see `SMCCC`__).”h]”(hŒ›SMCs from Non-secure world are synchronous exceptions, and are mechanisms for Non-secure world to request Secure services. Theyâ€™re broadly classified as ”…””}”(hŒ™SMCs from Non-secure world are synchronous exceptions, and are mechanisms for Non-secure world to request Secure services. They're broadly classified as ”h!j5hhhANhCNubjõ )”}”(hŒ*Fast*”h]”hŒFast”…””}”(hhh!j>ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jô h!j5ubhŒ or ”…””}”(hŒ or ”h!j5hhhANhCNubjõ )”}”(hŒ *Yielding*”h]”hŒYielding”…””}”(hhh!jQubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jô h!j5ubhŒ (see ”…””}”(hŒ (see ”h!j5hhhANhCNubjª)”}”(hŒ `SMCCC`__”h]”hŒSMCCC”…””}”(hŒSMCCC”h!jdubah"}”(h$]”h&]”h+]”h-]”h/]”Œname”jljKj3Œ-https://developer.arm.com/docs/den0028/latest”uh1j©h!j5j¾KubhŒ).”…””}”(hŒ).”h!j5hhhANhCNubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMÍh!jhhubjÊ)”}”(hŒ4.. __: https://developer.arm.com/docs/den0028/latest”h]”h"}”(h$]”Œid10”ah&]”h+]”h-]”h/]”j3jtjKuh1jÉhCMh!jhhhAj¡jÖKubjÕ)”}”(hhh]”(jÚ)”}”(hŒî*Fast* SMCs are atomic from the caller's point of view. I.e., they return to the caller only when the Secure world has finished serving the request. Any Non-secure interrupts that become pending meanwhile cannot preempt Secure execution. ”h]”j£)”}”(hŒí*Fast* SMCs are atomic from the caller's point of view. I.e., they return to the caller only when the Secure world has finished serving the request. Any Non-secure interrupts that become pending meanwhile cannot preempt Secure execution.”h]”(jõ )”}”(hŒ*Fast*”h]”hŒFast”…””}”(hhh!j–ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jô h!j’ubhŒé SMCs are atomic from the callerâ€™s point of view. I.e., they return to the caller only when the Secure world has finished serving the request. Any Non-secure interrupts that become pending meanwhile cannot preempt Secure execution.”…””}”(hŒç SMCs are atomic from the caller's point of view. I.e., they return to the caller only when the Secure world has finished serving the request. Any Non-secure interrupts that become pending meanwhile cannot preempt Secure execution.”h!j’ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMÓh!jŽubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÙh!j‹hhhAj¡hCNubjÚ)”}”(hX*Yielding* SMCs carry the semantics of a preemptible, lower-priority request. A pending Non-secure interrupt can preempt Secure execution handling a Yielding SMC. I.e., the caller might observe a Yielding SMC returning when either: #. Secure world completes the request, and the caller would find ``SMC_OK`` as the return code. #. A Non-secure interrupt preempts Secure execution. Non-secure interrupt is handled, and Non-secure execution resumes after ``SMC`` instruction. The dispatcher handling a Yielding SMC must provide a different return code to the Non-secure caller to distinguish the latter case. This return code, however, is not standardised (unlike ``SMC_UNKNOWN`` or ``SMC_OK``, for example), so will vary across dispatchers that handle the request. ”h]”(j£)”}”(hŒç*Yielding* SMCs carry the semantics of a preemptible, lower-priority request. A pending Non-secure interrupt can preempt Secure execution handling a Yielding SMC. I.e., the caller might observe a Yielding SMC returning when either:”h]”(jõ )”}”(hŒ *Yielding*”h]”hŒYielding”…””}”(hhh!j½ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jô h!j¹ubhŒÝ SMCs carry the semantics of a preemptible, lower-priority request. A pending Non-secure interrupt can preempt Secure execution handling a Yielding SMC. I.e., the caller might observe a Yielding SMC returning when either:”…””}”(hŒÝ SMCs carry the semantics of a preemptible, lower-priority request. A pending Non-secure interrupt can preempt Secure execution handling a Yielding SMC. I.e., the caller might observe a Yielding SMC returning when either:”h!j¹ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMØh!jµubj¯)”}”(hhh]”(jÚ)”}”(hŒ]Secure world completes the request, and the caller would find ``SMC_OK`` as the return code. ”h]”j£)”}”(hŒ\Secure world completes the request, and the caller would find ``SMC_OK`` as the return code.”h]”(hŒ>Secure world completes the request, and the caller would find ”…””}”(hŒ>Secure world completes the request, and the caller would find ”h!jÝubjO)”}”(hŒ ``SMC_OK``”h]”hŒSMC_OK”…””}”(hhh!jæubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jNh!jÝubhŒ as the return code.”…””}”(hŒ as the return code.”h!jÝubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMÝh!jÙubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÙh!jÖubjÚ)”}”(hŒA Non-secure interrupt preempts Secure execution. Non-secure interrupt is handled, and Non-secure execution resumes after ``SMC`` instruction. ”h]”j£)”}”(hŒŽA Non-secure interrupt preempts Secure execution. Non-secure interrupt is handled, and Non-secure execution resumes after ``SMC`` instruction.”h]”(hŒzA Non-secure interrupt preempts Secure execution. Non-secure interrupt is handled, and Non-secure execution resumes after ”…””}”(hŒzA Non-secure interrupt preempts Secure execution. Non-secure interrupt is handled, and Non-secure execution resumes after ”h!j ubjO)”}”(hŒ``SMC``”h]”hŒSMC”…””}”(hhh!jubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jNh!j ubhŒ instruction.”…””}”(hŒ instruction.”h!j ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMàh!jubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÙh!jÖubeh"}”(h$]”h&]”h+]”h-]”h/]”jjŽjhjj1uh1j®h!jµubj£)”}”(hX!The dispatcher handling a Yielding SMC must provide a different return code to the Non-secure caller to distinguish the latter case. This return code, however, is not standardised (unlike ``SMC_UNKNOWN`` or ``SMC_OK``, for example), so will vary across dispatchers that handle the request.”h]”(hŒ¼The dispatcher handling a Yielding SMC must provide a different return code to the Non-secure caller to distinguish the latter case. This return code, however, is not standardised (unlike ”…””}”(hŒ¼The dispatcher handling a Yielding SMC must provide a different return code to the Non-secure caller to distinguish the latter case. This return code, however, is not standardised (unlike ”h!j7ubjO)”}”(hŒ``SMC_UNKNOWN``”h]”hŒSMC_UNKNOWN”…””}”(hhh!j@ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jNh!j7ubhŒ or ”…””}”(hŒ or ”h!j7ubjO)”}”(hŒ ``SMC_OK``”h]”hŒSMC_OK”…””}”(hhh!jSubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jNh!j7ubhŒH, for example), so will vary across dispatchers that handle the request.”…””}”(hŒH, for example), so will vary across dispatchers that handle the request.”h!j7ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMãh!jµubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1jÙh!j‹hhhAj¡hCNubeh"}”(h$]”h&]”h+]”h-]”h/]”j'j(uh1jÔhAj¡hCMÓh!jhhubj£)”}”(hŒÙFor the latter case above, dispatchers before |EHF| expect Non-secure interrupts to be taken to S-EL1 [#irq]_, so would get a chance to populate the designated preempted error code before yielding to Non-secure world.”h]”(hŒ.For the latter case above, dispatchers before ”…””}”(hŒ.For the latter case above, dispatchers before ”h!jxhhhANhCNubh)”}”(hj«h]”h)”}”(hj«h]”hŒEHF”…””}”(hhh!j„ubah"}”(h$]”h&]”(h(j·j¸eh+]”h-]”h/]”uh1hhANhCNh!jubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”j·Œreftype”jÅŒrefexplicit”‰Œrefwarn”ˆŒ reftarget”jÈuh1hhAhBhCKh!jxhhubhŒ3 expect Non-secure interrupts to be taken to S-EL1 ”…””}”(hŒ3 expect Non-secure interrupts to be taken to S-EL1 ”h!jxhhhANhCNubj«)”}”(hŒ[#irq]_”h]”hŒ2”…””}”(hhh!j¢ubah"}”(h$]”Œid11”ah&]”h+]”h-]”h/]”j»Kj¼Œirq”j½h9uh1jªh!jxj¾KubhŒl, so would get a chance to populate the designated preempted error code before yielding to Non-secure world.”…””}”(hŒl, so would get a chance to populate the designated preempted error code before yielding to Non-secure world.”h!jxhhhANhCNubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMèh!jhhubj£)”}”(hŒVThe introduction of |EHF| changes the behaviour as described in `Interrupt handling`_.”h]”(hŒThe introduction of ”…””}”(hŒThe introduction of ”h!j½hhhANhCNubh)”}”(hj«h]”h)”}”(hj«h]”hŒEHF”…””}”(hhh!jÉubah"}”(h$]”h&]”(h(j·j¸eh+]”h-]”h/]”uh1hhANhCNh!jÆubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”j·Œreftype”jÅŒrefexplicit”‰Œrefwarn”ˆŒ reftarget”jÈuh1hhAhBhCKh!j½hhubhŒ' changes the behaviour as described in ”…””}”(hŒ' changes the behaviour as described in ”h!j½hhhANhCNubjª)”}”(hŒ`Interrupt handling`_”h]”hŒInterrupt handling”…””}”(hŒInterrupt handling”h!jçubah"}”(h$]”h&]”h+]”h-]”h/]”Œname”ŒInterrupt handling”j¼j½uh1j©h!j½j¾KubhŒ.”…””}”(•žŽhj1h!j½hhhANhCNubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMìh!jhhubj£)”}”(hXWhen |EHF| is enabled, in order to allow Non-secure interrupts to preempt Yielding SMC handling, the dispatcher must call ``ehf_allow_ns_preemption()`` API. The API takes one argument, the error code to be returned to the Non-secure world upon getting preempted.”h]”(hŒWhen ”…””}”(hŒWhen ”h!j hhhANhCNubh)”}”(hj«h]”h)”}”(hj«h]”hŒEHF”…””}”(hhh!j ubah"}”(h$]”h&]”(h(j·j¸eh+]”h-]”h/]”uh1hhANhCNh!j ubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”j·Œreftype”jÅŒrefexplicit”‰Œrefwarn”ˆŒ reftarget”jÈuh1hhAhBhCKh!j hhubhŒp is enabled, in order to allow Non-secure interrupts to preempt Yielding SMC handling, the dispatcher must call ”…””}”(hŒp is enabled, in order to allow Non-secure interrupts to preempt Yielding SMC handling, the dispatcher must call ”h!j hhhANhCNubjO)”}”(hŒ``ehf_allow_ns_preemption()``”h]”hŒehf_allow_ns_preemption()”…””}”(hhh!j, ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jNh!j ubhŒo API. The API takes one argument, the error code to be returned to the Non-secure world upon getting preempted.”…””}”(hŒo API. The API takes one argument, the error code to be returned to the Non-secure world upon getting preempted.”h!j hhhANhCNubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMïh!jhhubj^)”}”(hŒkIn case of GICv2, Non-secure interrupts while in S-EL1 were signalled as IRQs, and in case of GICv3, FIQs. ”h]”(jd)”}”(hhh]”hŒ2”…””}”(hhh!jI hhhANhCNubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jch!jE hhhANhCNubj£)”}”(hŒjIn case of GICv2, Non-secure interrupts while in S-EL1 were signalled as IRQs, and in case of GICv3, FIQs.”h]”hŒjIn case of GICv2, Non-secure interrupts while in S-EL1 were signalled as IRQs, and in case of GICv3, FIQs.”…””}”(hjX h!jV ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMôh!jE ubeh"}”(h$]”j±ah&]”h+]”Œirq”ah-]”h/]”j¬aj»Kj½h9uh1j]hAj¡hCMôh!jhhubeh"}”(h$]”(j4Œid9”eh&]”h+]”Œeffect on smc calls”ah-]”Œeffect on smc calls”ah/]”uh1jŒh!jŽhhhAj¡hCMÄjÖKjK}”jp jñsjM}”j4jñsubj)”}”(hhh]”(j’)”}”(hŒBuild-time flow”h]”hŒBuild-time flow”…””}”(hj{ h!jy hhhANhCNubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j‘h!jv hhhAj¡hCMøubj£)”}”(hŒ%Please refer to the `figure`__ above.”h]”(hŒPlease refer to the ”…””}”(hŒPlease refer to the ”h!j‡ hhhANhCNubjª)”}”(hŒ `figure`__”h]”hŒfigure”…””}”(hŒfigure”h!j ubah"}”(h$]”h&]”h+]”h-]”h/]”Œname”j˜ jKj¼j¥uh1j©h!j‡ j¾KubhŒ above.”…””}”(hŒ above.”h!j‡ hhhANhCNubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMúh!jv hhubjÊ)”}”(hŒ.. __: `ehf-figure`_”h]”h"}”(h$]”Œid12”ah&]”h+]”h-]”h/]”jKj¼j¥uh1jÉj™Œ ehf-figure”hCMAh!jv hhhAj¡jÖKj¾Kubj£)”}”(hŒ1The build-time flow involves the following steps:”h]”hŒ1The build-time flow involves the following steps:”…””}”(hj¹ h!j· hhhANhCNubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMþh!jv hhubj¯)”}”(hhh]”(jÚ)”}”(hŒ’Platform assigns priorities by installing priority level descriptors for individual dispatchers, as described in `Partitioning priority levels`_. ”h]”j£)”}”(hŒ‘Platform assigns priorities by installing priority level descriptors for individual dispatchers, as described in `Partitioning priority levels`_.”h]”(hŒqPlatform assigns priorities by installing priority level descriptors for individual dispatchers, as described in ”…””}”(hŒqPlatform assigns priorities by installing priority level descriptors for individual dispatchers, as described in ”h!jÌ ubjª)”}”(hŒ`Partitioning priority levels`_”h]”hŒPartitioning priority levels”…””}”(hŒPartitioning priority levels”h!jÕ ubah"}”(h$]”h&]”h+]”h-]”h/]”Œname”ŒPartitioning priority levels”j¼j‚uh1j©h!jÌ j¾KubhŒ.”…””}”(hj1h!jÌ ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMh!jÈ ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÙh!jÅ hhhAj¡hCNubjÚ)”}”(hŒ_Platform provides interrupt properties to GIC driver, as described in `Programming priority`_. ”h]”j£)”}”(hŒ^Platform provides interrupt properties to GIC driver, as described in `Programming priority`_.”h]”(hŒFPlatform provides interrupt properties to GIC driver, as described in ”…””}”(hŒFPlatform provides interrupt properties to GIC driver, as described in ”h!jú ubjª)”}”(hŒ`Programming priority`_”h]”hŒProgramming priority”…””}”(hŒProgramming priority”h!j!ubah"}”(h$]”h&]”h+]”h-]”h/]”Œname”ŒProgramming priority”j¼juh1j©h!jú j¾KubhŒ.”…””}”(hj1h!jú ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMh!jö ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÙh!jÅ hhhAj¡hCNubjÚ)”}”(hŒYDispatcher calling ``ehf_register_priority_handler()`` to register an interrupt handler. ”h]”j£)”}”(hŒXDispatcher calling ``ehf_register_priority_handler()`` to register an interrupt handler.”h]”(hŒDispatcher calling ”…””}”(hŒDispatcher calling ”h!j(!ubjO)”}”(hŒ#``ehf_register_priority_handler()``”h]”hŒehf_register_priority_handler()”…””}”(hhh!j1!ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jNh!j(!ubhŒ" to register an interrupt handler.”…””}”(hŒ" to register an interrupt handler.”h!j(!ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMh!j$!ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÙh!jÅ hhhAj¡hCNubeh"}”(h$]”h&]”h+]”h-]”h/]”jjŽjhjj1uh1j®h!jv hhhAj¡hCMubj£)”}”(hŒ0Also refer to the `Interrupt handling example`_.”h]”(hŒAlso refer to the ”…””}”(hŒAlso refer to the ”h!jV!hhhANhCNubjª)”}”(hŒ`Interrupt handling example`_”h]”hŒInterrupt handling example”…””}”(hŒInterrupt handling example”h!j_!ubah"}”(h$]”h&]”h+]”h-]”h/]”Œname”ŒInterrupt handling example”j¼j™uh1j©h!jV!j¾KubhŒ.”…””}”(hj1h!jV!hhhANhCNubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCM h!jv hhubeh"}”(h$]”j'ah&]”h+]”Œbuild-time flow”ah-]”h/]”uh1jŒh!jŽhhhAj¡hCMøjÖKubj)”}”(hhh]”(j’)”}”(hŒ Run-time flow”h]”hŒ Run-time flow”…””}”(hj†!h!j„!hhhANhCNubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j‘h!j!hhhAj¡hCMubjÊ)”}”(hŒ.. _interrupt-flow:”h]”h"}”(h$]”h&]”h+]”h-]”h/]”j¼Œinterrupt-flow”uh1jÉhCMSh!j!hhhAj¡ubj£)”}”(hŒ0The following is an example flow for interrupts:”h]”hŒ0The following is an example flow for interrupts:”…””}”(hjŸ!h!j!hhhANhCNubah"}”(h$]”jœ!ah&]”h+]”Œinterrupt-flow”ah-]”h/]”uh1j¢hAj¡hCMh!j!hhjK}”j©!j’!sjM}”jœ!j’!subj¯)”}”(hhh]”(jÚ)”}”(hXThe GIC driver, during initialization, iterates through the platform-supplied interrupt properties (see `Programming priority`_), and configures the interrupts. This programs the appropriate priority and group (Group 0) on interrupts belonging to different dispatchers. ”h]”j£)”}”(hX The GIC driver, during initialization, iterates through the platform-supplied interrupt properties (see `Programming priority`_), and configures the interrupts. This programs the appropriate priority and group (Group 0) on interrupts belonging to different dispatchers.”h]”(hŒhThe GIC driver, during initialization, iterates through the platform-supplied interrupt properties (see ”…””}”(hŒhThe GIC driver, during initialization, iterates through the platform-supplied interrupt properties (see ”h!jµ!ubjª)”}”(hŒ`Programming priority`_”h]”hŒProgramming priority”…””}”(hŒProgramming priority”h!j¾!ubah"}”(h$]”h&]”h+]”h-]”h/]”Œname”ŒProgramming priority”j¼juh1j©h!jµ!j¾KubhŒŽ), and configures the interrupts. This programs the appropriate priority and group (Group 0) on interrupts belonging to different dispatchers.”…””}”(hŒŽ), and configures the interrupts. This programs the appropriate priority and group (Group 0) on interrupts belonging to different dispatchers.”h!jµ!ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMh!j±!ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÙh!j®!hhhAj¡hCNubjÚ)”}”(hŒåThe |EHF|, during its initialisation, registers a top-level interrupt handler with the :ref:`Interrupt Management Framework` for EL3 interrupts. This also results in setting the routing bits in ``SCR_EL3``. ”h]”j£)”}”(hŒäThe |EHF|, during its initialisation, registers a top-level interrupt handler with the :ref:`Interrupt Management Framework` for EL3 interrupts. This also results in setting the routing bits in ``SCR_EL3``.”h]”(hŒThe ”…””}”(hŒThe ”h!jä!ubh)”}”(hj«h]”h)”}”(hj«h]”hŒEHF”…””}”(hhh!jð!ubah"}”(h$]”h&]”(h(j·j¸eh+]”h-]”h/]”uh1hhANhCNh!jí!ubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”j·Œreftype”jÅŒrefexplicit”‰Œrefwarn”ˆŒ reftarget”jÈuh1hhAhBhCKh!jä!ubhŒN, during its initialisation, registers a top-level interrupt handler with the ”…””}”(hŒN, during its initialisation, registers a top-level interrupt handler with the ”h!jä!ubh)”}”(hŒ;:ref:`Interrupt Management Framework`”h]”h)”}”(hj"h]”hŒInterrupt Management Framework”…””}”(hhh!j"ubah"}”(h$]”h&]”(h(Œstd”Œstd-ref”eh+]”h-]”h/]”uh1hh!j"ubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”j"Œreftype”Œref”Œrefexplicit”ˆŒrefwarn”ˆh?Œel3-runtime-firmware”uh1hhAj¡hCMh!jä!ubhŒF for EL3 interrupts. This also results in setting the routing bits in ”…””}”(hŒF for EL3 interrupts. This also results in setting the routing bits in ”h!jä!ubjO)”}”(hŒ``SCR_EL3``”h]”hŒSCR_EL3”…””}”(hhh!j3"ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jNh!jä!ubhŒ.”…””}”(hj1h!jä!ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMh!jà!ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÙh!j®!hhhAj¡hCNubjÚ)”}”(hŒmWhen an interrupt belonging to a dispatcher fires, GIC raises an EL3/Group 0 interrupt, and is taken to EL3. ”h]”j£)”}”(hŒlWhen an interrupt belonging to a dispatcher fires, GIC raises an EL3/Group 0 interrupt, and is taken to EL3.”h]”hŒlWhen an interrupt belonging to a dispatcher fires, GIC raises an EL3/Group 0 interrupt, and is taken to EL3.”…””}”(hjW"h!jU"ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMh!jQ"ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÙh!j®!hhhAj¡hCNubjÚ)”}”(hŒ¦The top-level EL3 interrupt handler executes. The handler acknowledges the interrupt, reads its *Running Priority*, and from that, determines the dispatcher handler. ”h]”j£)”}”(hŒ¥The top-level EL3 interrupt handler executes. The handler acknowledges the interrupt, reads its *Running Priority*, and from that, determines the dispatcher handler.”h]”(hŒ`The top-level EL3 interrupt handler executes. The handler acknowledges the interrupt, reads its ”…””}”(hŒ`The top-level EL3 interrupt handler executes. The handler acknowledges the interrupt, reads its ”h!jm"ubjõ )”}”(hŒ*Running Priority*”h]”hŒRunning Priority”…””}”(hhh!jv"ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jô h!jm"ubhŒ3, and from that, determines the dispatcher handler.”…””}”(hŒ3, and from that, determines the dispatcher handler.”h!jm"ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMh!ji"ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÙh!j®!hhhAj¡hCNubjÚ)”}”(hŒeThe |EHF| programs the *Priority Mask Register* of the PE to the priority of the interrupt received. ”h]”j£)”}”(hŒdThe |EHF| programs the *Priority Mask Register* of the PE to the priority of the interrupt received.”h]”(hŒThe ”…””}”(hŒThe ”h!j™"ubh)”}”(hj«h]”h)”}”(hj«h]”hŒEHF”…””}”(hhh!j¥"ubah"}”(h$]”h&]”(h(j·j¸eh+]”h-]”h/]”uh1hhANhCNh!j¢"ubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”j·Œreftype”jÅŒrefexplicit”‰Œrefwarn”ˆŒ reftarget”jÈuh1hhAhBhCKh!j™"ubhŒ programs the ”…””}”(hŒ programs the ”h!j™"ubjõ )”}”(hŒ*Priority Mask Register*”h]”hŒPriority Mask Register”…””}”(hhh!jÃ"ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jô h!j™"ubhŒ5 of the PE to the priority of the interrupt received.”…””}”(hŒ5 of the PE to the priority of the interrupt received.”h!j™"ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCM"h!j•"ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÙh!j®!hhhAj¡hCNubjÚ)”}”(hŒSThe |EHF| marks that priority level *active*, and jumps to the dispatcher handler. ”h]”j£)”}”(hŒRThe |EHF| marks that priority level *active*, and jumps to the dispatcher handler.”h]”(hŒThe ”…””}”(hŒThe ”h!jæ"ubh)”}”(hj«h]”h)”}”(hj«h]”hŒEHF”…””}”(hhh!jò"ubah"}”(h$]”h&]”(h(j·j¸eh+]”h-]”h/]”uh1hhANhCNh!jï"ubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”j·Œreftype”jÅŒrefexplicit”‰Œrefwarn”ˆŒ reftarget”jÈuh1hhAhBhCKh!jæ"ubhŒ marks that priority level ”…””}”(hŒ marks that priority level ”h!jæ"ubjõ )”}”(hŒ*active*”h]”hŒactive”…””}”(hhh!j#ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jô h!jæ"ubhŒ&, and jumps to the dispatcher handler.”…””}”(hŒ&, and jumps to the dispatcher handler.”h!jæ"ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCM%h!jâ"ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÙh!j®!hhhAj¡hCNubjÚ)”}”(hŒ¢Once the dispatcher handler finishes its job, it has to immediately *deactivate* the priority level before returning to the |EHF|. See `deactivation workflows`_. ”h]”j£)”}”(hŒ¡Once the dispatcher handler finishes its job, it has to immediately *deactivate* the priority level before returning to the |EHF|. See `deactivation workflows`_.”h]”(hŒDOnce the dispatcher handler finishes its job, it has to immediately ”…””}”(hŒDOnce the dispatcher handler finishes its job, it has to immediately ”h!j3#ubjõ )”}”(hŒ*deactivate*”h]”hŒ deactivate”…””}”(hhh!j<#ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jô h!j3#ubhŒ, the priority level before returning to the ”…””}”(hŒ, the priority level before returning to the ”h!j3#ubh)”}”(hj«h]”h)”}”(hj«h]”hŒEHF”…””}”(hhh!jR#ubah"}”(h$]”h&]”(h(j·j¸eh+]”h-]”h/]”uh1hhANhCNh!jO#ubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”j·Œreftype”jÅŒrefexplicit”‰Œrefwarn”ˆŒ reftarget”jÈuh1hhAhBhCKh!j3#ubhŒ. See ”…””}”(hŒ. See ”h!j3#ubjª)”}”(hŒ`deactivation workflows`_”h]”hŒdeactivation workflows”…””}”(hŒdeactivation workflows”h!jp#ubah"}”(h$]”h&]”h+]”h-]”h/]”Œname”Œdeactivation workflows”j¼j7uh1j©h!j3#j¾KubhŒ.”…””}”(hj1h!j3#ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCM(h!j/#ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÙh!j®!hhhAj¡hCNubeh"}”(h$]”h&]”h+]”h-]”h/]”jjŽjhjj1uh1j®h!j!hhhAj¡hCMubjÊ)”}”(hŒ.. _non-interrupt-flow:”h]”h"}”(h$]”h&]”h+]”h-]”h/]”j¼Œnon-interrupt-flow”uh1jÉhCMqh!j!hhhAj¡ubj£)”}”(hŒVThe following is an example flow for exceptions that targets EL3 other than interrupt:”h]”hŒVThe following is an example flow for exceptions that targets EL3 other than interrupt:”…””}”(hj¤#h!j¢#hhhANhCNubah"}”(h$]”j¡#ah&]”h+]”Œnon-interrupt-flow”ah-]”h/]”uh1j¢hAj¡hCM.h!j!hhjK}”j®#j—#sjM}”j¡#j—#subj¯)”}”(hhh]”(jÚ)”}”(hŒCThe platform provides handlers for the specific kind of exception. ”h]”j£)”}”(hŒBThe platform provides handlers for the specific kind of exception.”h]”hŒBThe platform provides handlers for the specific kind of exception.”…””}”(hj¼#h!jº#ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCM1h!j¶#ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÙh!j³#hhhAj¡hCNubjÚ)”}”(hŒBThe exception arrives, and the corresponding handler is executed. ”h]”j£)”}”(hŒAThe exception arrives, and the corresponding handler is executed.”h]”hŒAThe exception arrives, and the corresponding handler is executed.”…””}”(hjÔ#h!jÒ#ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCM3h!jÎ#ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÙh!j³#hhhAj¡hCNubjÚ)”}”(hX.The handler calls ``ehf_activate_priority()`` to activate the required priority level. This also has the effect of raising GIC priority mask, thus preventing interrupts of lower priority from preempting the handling. The handler may choose to do the handling entirely in EL3 or delegate to a lower EL. ”h]”j£)”}”(hX-The handler calls ``ehf_activate_priority()`` to activate the required priority level. This also has the effect of raising GIC priority mask, thus preventing interrupts of lower priority from preempting the handling. The handler may choose to do the handling entirely in EL3 or delegate to a lower EL.”h]”(hŒThe handler calls ”…””}”(hŒThe handler calls ”h!jê#ubjO)”}”(hŒ``ehf_activate_priority()``”h]”hŒehf_activate_priority()”…””}”(hhh!jó#ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jNh!jê#ubhX to activate the required priority level. This also has the effect of raising GIC priority mask, thus preventing interrupts of lower priority from preempting the handling. The handler may choose to do the handling entirely in EL3 or delegate to a lower EL.”…””}”(hX to activate the required priority level. This also has the effect of raising GIC priority mask, thus preventing interrupts of lower priority from preempting the handling. The handler may choose to do the handling entirely in EL3 or delegate to a lower EL.”h!jê#ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCM5h!jæ#ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÙh!j³#hhhAj¡hCNubjÚ)”}”(hŒÕOnce exception handling concludes, the handler calls ``ehf_deactivate_priority()`` to deactivate the priority level activated earlier. This also has the effect of lowering GIC priority mask to what it was before. ”h]”j£)”}”(hŒÔOnce exception handling concludes, the handler calls ``ehf_deactivate_priority()`` to deactivate the priority level activated earlier. This also has the effect of lowering GIC priority mask to what it was before.”h]”(hŒ5Once exception handling concludes, the handler calls ”…””}”(hŒ5Once exception handling concludes, the handler calls ”h!j$ubjO)”}”(hŒ``ehf_deactivate_priority()``”h]”hŒehf_deactivate_priority()”…””}”(hhh!j$ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jNh!j$ubhŒ‚ to deactivate the priority level activated earlier. This also has the effect of lowering GIC priority mask to what it was before.”…””}”(hŒ‚ to deactivate the priority level activated earlier. This also has the effect of lowering GIC priority mask to what it was before.”h!j$ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCM;h!j$ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÙh!j³#hhhAj¡hCNubeh"}”(h$]”h&]”h+]”h-]”h/]”jjŽjhjj1uh1j®h!j!hhhAj¡hCM1ubeh"}”(h$]”j>ah&]”h+]”Œ run-time flow”ah-]”h/]”uh1jŒh!jŽhhhAj¡hCMjÖKubj)”}”(hhh]”(j’)”}”(hŒ'Interrupt Prioritisation Considerations”h]”hŒ'Interrupt Prioritisation Considerations”…””}”(hjP$h!jN$hhhANhCNubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j‘h!jK$hhhAj¡hCMAubj£)”}”(hŒ´The GIC priority scheme, by design, prioritises Secure interrupts over Normal world ones. The platform further assigns relative priorities amongst Secure dispatchers through |EHF|.”h]”(hŒ®The GIC priority scheme, by design, prioritises Secure interrupts over Normal world ones. The platform further assigns relative priorities amongst Secure dispatchers through ”…””}”(hŒ®The GIC priority scheme, by design, prioritises Secure interrupts over Normal world ones. The platform further assigns relative priorities amongst Secure dispatchers through ”h!j\$hhhANhCNubh)”}”(hj«h]”h)”}”(hj«h]”hŒEHF”…””}”(hhh!jh$ubah"}”(h$]”h&]”(h(j·j¸eh+]”h-]”h/]”uh1hhANhCNh!je$ubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”j·Œreftype”jÅŒrefexplicit”‰Œrefwarn”ˆŒ reftarget”jÈuh1hhAhBhCKh!j\$hhubhŒ.”…””}”(hj1h!j\$hhhANhCNubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMCh!jK$hhubj£)”}”(hXUAs mentioned in `Partitioning priority levels`_, interrupts targeting distinct dispatchers fall in distinct priority levels. Because they're routed via the GIC, interrupt delivery to the PE is subject to GIC prioritisation rules. In particular, when an interrupt is being handled by the PE (i.e., the interrupt is in *Active* state), only interrupts of higher priority are signalled to the PE, even if interrupts of same or lower priority are pending. This has the side effect of one dispatcher being starved of interrupts by virtue of another dispatcher handling its (higher priority) interrupts.”h]”(hŒAs mentioned in ”…””}”(hŒAs mentioned in ”h!j‹$hhhANhCNubjª)”}”(hŒ`Partitioning priority levels`_”h]”hŒPartitioning priority levels”…””}”(hŒPartitioning priority levels”h!j”$ubah"}”(h$]”h&]”h+]”h-]”h/]”Œname”ŒPartitioning priority levels”j¼j‚uh1j©h!j‹$j¾KubhX, interrupts targeting distinct dispatchers fall in distinct priority levels. Because theyâ€™re routed via the GIC, interrupt delivery to the PE is subject to GIC prioritisation rules. In particular, when an interrupt is being handled by the PE (i.e., the interrupt is in ”…””}”(hX, interrupts targeting distinct dispatchers fall in distinct priority levels. Because they're routed via the GIC, interrupt delivery to the PE is subject to GIC prioritisation rules. In particular, when an interrupt is being handled by the PE (i.e., the interrupt is in ”h!j‹$hhhANhCNubjõ )”}”(hŒ*Active*”h]”hŒActive”…””}”(hhh!jª$ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jô h!j‹$ubhX state), only interrupts of higher priority are signalled to the PE, even if interrupts of same or lower priority are pending. This has the side effect of one dispatcher being starved of interrupts by virtue of another dispatcher handling its (higher priority) interrupts.”…””}”(hX state), only interrupts of higher priority are signalled to the PE, even if interrupts of same or lower priority are pending. This has the side effect of one dispatcher being starved of interrupts by virtue of another dispatcher handling its (higher priority) interrupts.”h!j‹$hhhANhCNubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMGh!jK$hhubj£)”}”(hXThe |EHF| doesn't enforce a particular prioritisation policy, but the platform should carefully consider the assignment of priorities to dispatchers integrated into runtime firmware. The platform should sensibly delineate priority to various dispatchers according to their nature. In particular, dispatchers of critical nature (RAS, for example) should be assigned higher priority than others (|SDEI|, for example); and within |SDEI|, Critical priority |SDEI| should be assigned higher priority than Normal ones.”h]”(hŒThe ”…””}”(hŒThe ”h!jÃ$hhhANhCNubh)”}”(hj«h]”h)”}”(hj«h]”hŒEHF”…””}”(hhh!jÏ$ubah"}”(h$]”h&]”(h(j·j¸eh+]”h-]”h/]”uh1hhANhCNh!jÌ$ubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”j·Œreftype”jÅŒrefexplicit”‰Œrefwarn”ˆŒ reftarget”jÈuh1hhAhBhCKh!jÃ$hhubhXƒ doesnâ€™t enforce a particular prioritisation policy, but the platform should carefully consider the assignment of priorities to dispatchers integrated into runtime firmware. The platform should sensibly delineate priority to various dispatchers according to their nature. In particular, dispatchers of critical nature (RAS, for example) should be assigned higher priority than others (”…””}”(hX doesn't enforce a particular prioritisation policy, but the platform should carefully consider the assignment of priorities to dispatchers integrated into runtime firmware. The platform should sensibly delineate priority to various dispatchers according to their nature. In particular, dispatchers of critical nature (RAS, for example) should be assigned higher priority than others (”h!jÃ$hhhANhCNubh)”}”(hj h]”h)”}”(hj h]”hŒSDEI”…””}”(hhh!jð$ubah"}”(h$]”h&]”(h(jjeh+]”h-]”h/]”uh1hhANhCNh!jí$ubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”jŒreftype”j#Œrefexplicit”‰Œrefwarn”ˆŒ reftarget”j&uh1hhAhBhCK*h!jÃ$hhubhŒ, for example); and within ”…””}”(hŒ, for example); and within ”h!jÃ$hhhANhCNubh)”}”(hj h]”h)”}”(hj h]”hŒSDEI”…””}”(hhh!j%ubah"}”(h$]”h&]”(h(jjeh+]”h-]”h/]”uh1hhANhCNh!j%ubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”jŒreftype”j#Œrefexplicit”‰Œrefwarn”ˆŒ reftarget”j&uh1hhAhBhCK*h!jÃ$hhubhŒ, Critical priority ”…””}”(hŒ, Critical priority ”h!jÃ$hhhANhCNubh)”}”(hj h]”h)”}”(hj h]”hŒSDEI”…””}”(hhh!j2%ubah"}”(h$]”h&]”(h(jjeh+]”h-]”h/]”uh1hhANhCNh!j/%ubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”jŒreftype”j#Œrefexplicit”‰Œrefwarn”ˆŒ reftarget”j&uh1hhAhBhCK*h!jÃ$hhubhŒ5 should be assigned higher priority than Normal ones.”…””}”(hŒ5 should be assigned higher priority than Normal ones.”h!jÃ$hhhANhCNubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMPh!jK$hhubeh"}”(h$]”jah&]”h+]”Œ'interrupt prioritisation considerations”ah-]”h/]”uh1jŒh!jŽhhhAj¡hCMAjÖKubj)”}”(hhh]”(j’)”}”(hŒLimitations”h]”hŒLimitations”…””}”(hjb%h!j`%hhhANhCNubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j‘h!j]%hhhAj¡hCMYubj£)”}”(hŒ(The |EHF| has the following limitations:”h]”(hŒThe ”…””}”(hŒThe ”h!jn%hhhANhCNubh)”}”(hj«h]”h)”}”(hj«h]”hŒEHF”…””}”(hhh!jz%ubah"}”(h$]”h&]”(h(j·j¸eh+]”h-]”h/]”uh1hhANhCNh!jw%ubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”j·Œreftype”jÅŒrefexplicit”‰Œrefwarn”ˆŒ reftarget”jÈuh1hhAhBhCKh!jn%hhubhŒ has the following limitations:”…””}”(hŒ has the following limitations:”h!jn%hhhANhCNubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCM[h!j]%hhubjÕ)”}”(hhh]”(jÚ)”}”(hX*Although there could be up to 128 Secure dispatchers supported by the GIC priority scheme, the size of descriptor array exposed with ``EHF_REGISTER_PRIORITIES()`` macro is currently limited to 32. This serves most expected use cases. This may be expanded in the future, should use cases demand so. ”h]”j£)”}”(hX)Although there could be up to 128 Secure dispatchers supported by the GIC priority scheme, the size of descriptor array exposed with ``EHF_REGISTER_PRIORITIES()`` macro is currently limited to 32. This serves most expected use cases. This may be expanded in the future, should use cases demand so.”h]”(hŒ…Although there could be up to 128 Secure dispatchers supported by the GIC priority scheme, the size of descriptor array exposed with ”…””}”(hŒ…Although there could be up to 128 Secure dispatchers supported by the GIC priority scheme, the size of descriptor array exposed with ”h!j¥%ubjO)”}”(hŒ``EHF_REGISTER_PRIORITIES()``”h]”hŒEHF_REGISTER_PRIORITIES()”…””}”(hhh!j®%ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jNh!j¥%ubhŒ‡ macro is currently limited to 32. This serves most expected use cases. This may be expanded in the future, should use cases demand so.”…””}”(hŒ‡ macro is currently limited to 32. This serves most expected use cases. This may be expanded in the future, should use cases demand so.”h!j¥%ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCM]h!j¡%ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÙh!jž%hhhAj¡hCNubjÚ)”}”(hŒâThe platform must ensure that the priority assigned to the dispatcher in the exception descriptor and the programmed priority of interrupts handled by the dispatcher match. The |EHF| cannot verify that this has been followed. ”h]”j£)”}”(hŒáThe platform must ensure that the priority assigned to the dispatcher in the exception descriptor and the programmed priority of interrupts handled by the dispatcher match. The |EHF| cannot verify that this has been followed.”h]”(hŒ±The platform must ensure that the priority assigned to the dispatcher in the exception descriptor and the programmed priority of interrupts handled by the dispatcher match. The ”…””}”(hŒ±The platform must ensure that the priority assigned to the dispatcher in the exception descriptor and the programmed priority of interrupts handled by the dispatcher match. The ”h!jÑ%ubh)”}”(hj«h]”h)”}”(hj«h]”hŒEHF”…””}”(hhh!jÝ%ubah"}”(h$]”h&]”(h(j·j¸eh+]”h-]”h/]”uh1hhANhCNh!jÚ%ubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”j·Œreftype”jÅŒrefexplicit”‰Œrefwarn”ˆŒ reftarget”jÈuh1hhAhBhCKh!jÑ%ubhŒ+ cannot verify that this has been followed.”…””}”(hŒ+ cannot verify that this has been followed.”h!jÑ%ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMch!jÍ%ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÙh!jž%hhhAj¡hCNubeh"}”(h$]”h&]”h+]”h-]”h/]”j'j(uh1jÔhAj¡hCM]h!j]%hhubh Œ transition”“”)”}”(hŒ--------------”h]”h"}”(h$]”h&]”h+]”h-]”h/]”uh1j &hAj¡hCMgh!j]%hhubj£)”}”(hŒM*Copyright (c) 2018-2020, Arm Limited and Contributors. All rights reserved.*”h]”jõ )”}”(hj&h]”hŒKCopyright (c) 2018-2020, Arm Limited and Contributors. All rights reserved.”…””}”(hhh!j&ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jô h!j&ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMih!j]%hhubjÊ)”}”(hŒ‰.. _SDEI specification: http://infocenter.arm.com/help/topic/com.arm.doc.den0054a/ARM_DEN0054A_Software_Delegated_Exception_Interface.pdf”h]”h"}”(h$]”Œsdei-specification”ah&]”h+]”Œsdei specification”ah-]”h/]”j3j4uh1jÉhCM°h!j]%hhhAj¡jÖKubeh"}”(h$]”jîah&]”h+]”Œlimitations”ah-]”h/]”uh1jŒh!jŽhhhAj¡hCMYjÖKubeh"}”(h$]”Œexception-handling-framework”ah&]”h+]”Œexception handling framework”ah-]”h/]”uh1jŒh!hhhhAj¡hCKubeh"}”(h$]”h&]”h+]”h-]”h/]”Œsource”j¡uh1hŒcurrent_source”NŒcurrent_line”NŒsettings”Œdocutils.frontend”ŒValues”“”)”}”(j‘NŒ generator”NŒ datestamp”NŒsource_link”NŒ source_url”NŒ toc_backlinks”Œentry”Œfootnote_backlinks”KŒ sectnum_xform”KŒstrip_comments”NŒstrip_elements_with_classes”NŒ strip_classes”NŒreport_level”KŒ halt_level”KŒexit_status_level”KŒdebug”NŒwarning_stream”NŒ traceback”ˆŒinput_encoding”Œ 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