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:term:`SVE`”h]”h)”}”(hŒ:term:`SVE`”h]”h)”}”(hj h]”hŒSVE”…””}”(hhh!j ubah"}”(h$]”h&]”(h(Œstd”Œstd-term”eh+]”h-]”h/]”uh1hh!j ubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”j Œreftype”Œterm”Œrefexplicit”‰Œrefwarn”ˆh?ŒSVE”uh1hhAhBhCK6h!j ubah"}”(h$]”h&]”h+]”ŒSVE”ah-]”h/]”uh1h hAhBhCK6h!hhhubh)”}”(hŒ.. |TBB| replace:: :term:`TBB`”h]”h)”}”(hŒ:term:`TBB`”h]”h)”}”(hj8 h]”hŒTBB”…””}”(hhh!j: ubah"}”(h$]”h&]”(h(Œstd”Œstd-term”eh+]”h-]”h/]”uh1hh!j6 ubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”jD Œreftype”Œterm”Œrefexplicit”‰Œrefwarn”ˆh?ŒTBB”uh1hhAhBhCK7h!j2 ubah"}”(h$]”h&]”h+]”ŒTBB”ah-]”h/]”uh1h hAhBhCK7h!hhhubh)”}”(hŒ .. |TBBR| replace:: :term:`TBBR`”h]”h)”}”(hŒ:term:`TBBR`”h]”h)”}”(hjc h]”hŒTBBR”…””}”(hhh!je ubah"}”(h$]”h&]”(h(Œstd”Œstd-term”eh+]”h-]”h/]”uh1hh!ja ubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”jo Œreftype”Œterm”Œrefexplicit”‰Œrefwarn”ˆh?ŒTBBR”uh1hhAhBhCK8h!j] ubah"}”(h$]”h&]”h+]”ŒTBBR”ah-]”h/]”uh1h hAhBhCK8h!hhhubh)”}”(hŒ.. |TEE| replace:: :term:`TEE`”h]”h)”}”(hŒ:term:`TEE`”h]”h)”}”(hjŽ h]”hŒTEE”…””}”(hhh!j ubah"}”(h$]”h&]”(h(Œstd”Œstd-term”eh+]”h-]”h/]”uh1hh!jŒ ubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”jš Œreftype”Œterm”Œrefexplicit”‰Œrefwarn”ˆh?ŒTEE”uh1hhAhBhCK9h!jˆ ubah"}”(h$]”h&]”h+]”ŒTEE”ah-]”h/]”uh1h hAhBhCK9h!hhhubh)”}”(hŒ .. |TF-A| replace:: :term:`TF-A`”h]”h)”}”(hŒ:term:`TF-A`”h]”h)”}”(hj¹ h]”hŒTF-A”…””}”(hhh!j» ubah"}”(h$]”h&]”(h(Œstd”Œstd-term”eh+]”h-]”h/]”uh1hh!j· ubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”jÅ Œreftype”Œterm”Œrefexplicit”‰Œrefwarn”ˆh?ŒTF-A”uh1hhAhBhCK:h!j³ ubah"}”(h$]”h&]”h+]”ŒTF-A”ah-]”h/]”uh1h hAhBhCK:h!hhhubh)”}”(hŒ .. |TF-M| replace:: :term:`TF-M`”h]”h)”}”(hŒ:term:`TF-M`”h]”h)”}”(hjä h]”hŒTF-M”…””}”(hhh!jæ ubah"}”(h$]”h&]”(h(Œstd”Œstd-term”eh+]”h-]”h/]”uh1hh!jâ ubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”jð Œreftype”Œterm”Œrefexplicit”‰Œrefwarn”ˆh?ŒTF-M”uh1hhAhBhCK;h!jÞ ubah"}”(h$]”h&]”h+]”ŒTF-M”ah-]”h/]”uh1h hAhBhCK;h!hhhubh)”}”(hŒ.. |TLB| replace:: :term:`TLB`”h]”h)”}”(hŒ:term:`TLB`”h]”h)”}”(hj h]”hŒTLB”…””}”(hhh!j ubah"}”(h$]”h&]”(h(Œstd”Œstd-term”eh+]”h-]”h/]”uh1hh!j ubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”j Œreftype”Œterm”Œrefexplicit”‰Œrefwarn”ˆh?ŒTLB”uh1hhAhBhCKh!j_ ubah"}”(h$]”h&]”h+]”ŒTRNG”ah-]”h/]”uh1h hAhBhCK>h!hhhubh)”}”(hŒ.. |TSP| replace:: :term:`TSP`”h]”h)”}”(hŒ:term:`TSP`”h]”h)”}”(hj h]”hŒTSP”…””}”(hhh!j’ ubah"}”(h$]”h&]”(h(Œstd”Œstd-term”eh+]”h-]”h/]”uh1hh!jŽ ubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”jœ Œreftype”Œterm”Œrefexplicit”‰Œrefwarn”ˆh?ŒTSP”uh1hhAhBhCK?h!jŠ ubah"}”(h$]”h&]”h+]”ŒTSP”ah-]”h/]”uh1h hAhBhCK?h!hhhubh)”}”(hŒ.. |TZC| replace:: :term:`TZC`”h]”h)”}”(hŒ:term:`TZC`”h]”h)”}”(hj» h]”hŒTZC”…””}”(hhh!j½ ubah"}”(h$]”h&]”(h(Œstd”Œstd-term”eh+]”h-]”h/]”uh1hh!j¹ ubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”jÇ Œreftype”Œterm”Œrefexplicit”‰Œrefwarn”ˆh?ŒTZC”uh1hhAhBhCK@h!jµ ubah"}”(h$]”h&]”h+]”ŒTZC”ah-]”h/]”uh1h hAhBhCK@h!hhhubh)”}”(hŒ".. |UBSAN| replace:: :term:`UBSAN`”h]”h)”}”(hŒ :term:`UBSAN`”h]”h)”}”(hjæ h]”hŒUBSAN”…””}”(hhh!jè ubah"}”(h$]”h&]”(h(Œstd”Œstd-term”eh+]”h-]”h/]”uh1hh!jä ubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”jò Œreftype”Œterm”Œrefexplicit”‰Œrefwarn”ˆh?ŒUBSAN”uh1hhAhBhCKAh!jà ubah"}”(h$]”h&]”h+]”ŒUBSAN”ah-]”h/]”uh1h hAhBhCKAh!hhhubh)”}”(hŒ .. |UEFI| replace:: :term:`UEFI`”h]”h)”}”(hŒ:term:`UEFI`”h]”h)”}”(hjh]”hŒUEFI”…””}”(hhh!jubah"}”(h$]”h&]”(h(Œstd”Œstd-term”eh+]”h-]”h/]”uh1hh!jubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”jŒreftype”Œterm”Œrefexplicit”‰Œrefwarn”ˆh?ŒUEFI”uh1hhAhBhCKBh!jubah"}”(h$]”h&]”h+]”ŒUEFI”ah-]”h/]”uh1h hAhBhCKBh!hhhubh)”}”(hŒ .. |WDOG| replace:: :term:`WDOG`”h]”h)”}”(hŒ:term:`WDOG`”h]”h)”}”(hj<h]”hŒWDOG”…””}”(hhh!j>ubah"}”(h$]”h&]”(h(Œstd”Œstd-term”eh+]”h-]”h/]”uh1hh!j:ubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”jHŒreftype”Œterm”Œrefexplicit”‰Œrefwarn”ˆh?ŒWDOG”uh1hhAhBhCKCh!j6ubah"}”(h$]”h&]”h+]”ŒWDOG”ah-]”h/]”uh1h hAhBhCKCh!hhhubh)”}”(hŒ!.. |XLAT| replace:: :term:`XLAT` ”h]”h)”}”(hŒ:term:`XLAT`”h]”h)”}”(hjgh]”hŒXLAT”…””}”(hhh!jiubah"}”(h$]”h&]”(h(Œstd”Œstd-term”eh+]”h-]”h/]”uh1hh!jeubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”jsŒreftype”Œterm”Œrefexplicit”‰Œrefwarn”ˆh?ŒXLAT”uh1hhAhBhCKDh!jaubah"}”(h$]”h&]”h+]”ŒXLAT”ah-]”h/]”uh1h hAhBhCKDh!hhhubh Œsection”“”)”}”(hhh]”(h Œtitle”“”)”}”(hŒArm CPU Specific Build Macros”h]”hŒArm CPU Specific Build Macros”…””}”(hj•h!j“hhhANhCNubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j‘h!jŽhhhAŒa/home/test/workspace/code/optee_3.16/trusted-firmware-a/docs/design/cpu-specific-build-macros.rst”hCKubh Œ paragraph”“”)”}”(hŒ½This document describes the various build options present in the CPU specific operations framework to enable errata workarounds and to enable optimizations for a specific CPU on a platform.”h]”hŒ½This document describes the various build options present in the CPU specific operations framework to enable errata workarounds and to enable optimizations for a specific CPU on a platform.”…””}”(hj¦h!j¤hhhANhCNubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKh!jŽhhubj)”}”(hhh]”(j’)”}”(hŒ"Security Vulnerability Workarounds”h]”hŒ"Security Vulnerability Workarounds”…””}”(hj·h!jµhhhANhCNubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j‘h!j²hhhAj¡hCK ubj£)”}”(hŒyTF-A exports a series of build flags which control which security vulnerability workarounds should be applied at runtime.”h]”hŒyTF-A exports a series of build flags which control which security vulnerability workarounds should be applied at runtime.”…””}”(hjÅh!jÃhhhANhCNubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKh!j²hhubh Œbullet_list”“”)”}”(hhh]”(h Œ list_item”“”)”}”(hXr``WORKAROUND_CVE_2017_5715``: Enables the security workaround for `CVE-2017-5715`_. This flag can be set to 0 by the platform if none of the PEs in the system need the workaround. Setting this flag to 0 provides no performance benefit for non-affected platforms, it just helps to comply with the recommendation in the spec regarding workaround discovery. Defaults to 1. ”h]”j£)”}”(hXq``WORKAROUND_CVE_2017_5715``: Enables the security workaround for `CVE-2017-5715`_. This flag can be set to 0 by the platform if none of the PEs in the system need the workaround. Setting this flag to 0 provides no performance benefit for non-affected platforms, it just helps to comply with the recommendation in the spec regarding workaround discovery. Defaults to 1.”h]”(h Œliteral”“”)”}”(hŒ``WORKAROUND_CVE_2017_5715``”h]”hŒWORKAROUND_CVE_2017_5715”…””}”(hhh!jâubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jÜubhŒ&: Enables the security workaround for ”…””}”(hŒ&: Enables the security workaround for ”h!jÜubh Œ reference”“”)”}”(hŒ`CVE-2017-5715`_”h]”hŒ CVE-2017-5715”…””}”(hŒ CVE-2017-5715”h!j÷ubah"}”(h$]”h&]”h+]”h-]”h/]”Œname”jÿŒrefuri”Œ;http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2017-5715”uh1jõh!jÜŒresolved”KubhX. This flag can be set to 0 by the platform if none of the PEs in the system need the workaround. Setting this flag to 0 provides no performance benefit for non-affected platforms, it just helps to comply with the recommendation in the spec regarding workaround discovery. Defaults to 1.”…””}”(hX. This flag can be set to 0 by the platform if none of the PEs in the system need the workaround. Setting this flag to 0 provides no performance benefit for non-affected platforms, it just helps to comply with the recommendation in the spec regarding workaround discovery. Defaults to 1.”h!jÜubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKh!jØubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hX-``WORKAROUND_CVE_2018_3639``: Enables the security workaround for `CVE-2018-3639`_. Defaults to 1. The TF-A project recommends to keep the default value of 1 even on platforms that are unaffected by CVE-2018-3639, in order to comply with the recommendation in the spec regarding workaround discovery. ”h]”j£)”}”(hX,``WORKAROUND_CVE_2018_3639``: Enables the security workaround for `CVE-2018-3639`_. Defaults to 1. The TF-A project recommends to keep the default value of 1 even on platforms that are unaffected by CVE-2018-3639, in order to comply with the recommendation in the spec regarding workaround discovery.”h]”(já)”}”(hŒ``WORKAROUND_CVE_2018_3639``”h]”hŒWORKAROUND_CVE_2018_3639”…””}”(hhh!j#ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jubhŒ&: Enables the security workaround for ”…””}”(hŒ&: Enables the security workaround for ”h!jubjö)”}”(hŒ`CVE-2018-3639`_”h]”hŒ CVE-2018-3639”…””}”(hŒ CVE-2018-3639”h!j6ubah"}”(h$]”h&]”h+]”h-]”h/]”Œname”j>jŒ;http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2018-3639”uh1jõh!jj KubhŒÚ. Defaults to 1. The TF-A project recommends to keep the default value of 1 even on platforms that are unaffected by CVE-2018-3639, in order to comply with the recommendation in the spec regarding workaround discovery.”…””}”(hŒÚ. Defaults to 1. The TF-A project recommends to keep the default value of 1 even on platforms that are unaffected by CVE-2018-3639, in order to comply with the recommendation in the spec regarding workaround discovery.”h!jubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKh!jubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hŒÜ``DYNAMIC_WORKAROUND_CVE_2018_3639``: Enables dynamic mitigation for `CVE-2018-3639`_. This build option should be set to 1 if the target platform contains at least 1 CPU that requires dynamic mitigation. Defaults to 0. ”h]”j£)”}”(hŒÛ``DYNAMIC_WORKAROUND_CVE_2018_3639``: Enables dynamic mitigation for `CVE-2018-3639`_. This build option should be set to 1 if the target platform contains at least 1 CPU that requires dynamic mitigation. Defaults to 0.”h]”(já)”}”(hŒ$``DYNAMIC_WORKAROUND_CVE_2018_3639``”h]”hŒ DYNAMIC_WORKAROUND_CVE_2018_3639”…””}”(hhh!j`ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j\ubhŒ!: Enables dynamic mitigation for ”…””}”(hŒ!: Enables dynamic mitigation for ”h!j\ubjö)”}”(hŒ`CVE-2018-3639`_”h]”hŒ CVE-2018-3639”…””}”(hŒ CVE-2018-3639”h!jsubah"}”(h$]”h&]”h+]”h-]”h/]”Œname”j{jjFuh1jõh!j\j KubhŒ†. This build option should be set to 1 if the target platform contains at least 1 CPU that requires dynamic mitigation. Defaults to 0.”…””}”(hŒ†. This build option should be set to 1 if the target platform contains at least 1 CPU that requires dynamic mitigation. Defaults to 0.”h!j\ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKh!jXubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubeh"}”(h$]”h&]”h+]”h-]”h/]”Œbullet”Œ-”uh1jÑhAj¡hCKh!j²hhubh Œtarget”“”)”}”(hŒ&.. _arm_cpu_macros_errata_workarounds:”h]”h"}”(h$]”h&]”h+]”h-]”h/]”Œrefid”Œ!arm-cpu-macros-errata-workarounds”uh1jœhCKeh!j²hhhAj¡ubeh"}”(h$]”Œ"security-vulnerability-workarounds”ah&]”h+]”Œ"security vulnerability workarounds”ah-]”h/]”uh1jŒh!jŽhhhAj¡hCK ubj)”}”(hhh]”(j’)”}”(hŒCPU Errata Workarounds”h]”hŒCPU Errata Workarounds”…””}”(hj·h!jµhhhANhCNubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j‘h!j²hhhAj¡hCK#ubj£)”}”(hŒÓTF-A exports a series of build flags which control the errata workarounds that are applied to each CPU by the reset handler. The errata details can be found in the CPU specific errata documents published by Arm:”h]”hŒÓTF-A exports a series of build flags which control the errata workarounds that are applied to each CPU by the reset handler. The errata details can be found in the CPU specific errata documents published by Arm:”…””}”(hjÅh!jÃhhhANhCNubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCK%h!j²hhubjÒ)”}”(hhh]”(j×)”}”(hŒ6`Cortex-A53 MPCore Software Developers Errata Notice`_”h]”j£)”}”(hjÖh]”jö)”}”(hjÖh]”hŒ3Cortex-A53 MPCore Software Developers Errata Notice”…””}”(hŒ3Cortex-A53 MPCore Software Developers Errata Notice”h!jÛubah"}”(h$]”h&]”h+]”h-]”h/]”Œname”Œ3Cortex-A53 MPCore Software Developers Errata Notice”jŒEhttp://infocenter.arm.com/help/topic/com.arm.doc.epm048406/index.html”uh1jõh!jØj Kubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCK)h!jÔubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÑhhhAj¡hCNubj×)”}”(hŒ6`Cortex-A57 MPCore Software Developers Errata Notice`_”h]”j£)”}”(hjúh]”jö)”}”(hjúh]”hŒ3Cortex-A57 MPCore Software Developers Errata Notice”…””}”(hŒ3Cortex-A57 MPCore Software Developers Errata Notice”h!jÿubah"}”(h$]”h&]”h+]”h-]”h/]”Œname”Œ3Cortex-A57 MPCore Software Developers Errata Notice”jŒEhttp://infocenter.arm.com/help/topic/com.arm.doc.epm049219/index.html”uh1jõh!jüj Kubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCK*h!jøubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÑhhhAj¡hCNubj×)”}”(hŒ7`Cortex-A72 MPCore Software Developers Errata Notice`_ ”h]”j£)”}”(hŒ6`Cortex-A72 MPCore Software Developers Errata Notice`_”h]”jö)”}”(hj" h]”hŒ3Cortex-A72 MPCore Software Developers Errata Notice”…””}”(hŒ3Cortex-A72 MPCore Software Developers Errata Notice”h!j$ ubah"}”(h$]”h&]”h+]”h-]”h/]”Œname”Œ3Cortex-A72 MPCore Software Developers Errata Notice”jŒEhttp://infocenter.arm.com/help/topic/com.arm.doc.epm012079/index.html”uh1jõh!j j Kubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCK+h!j ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÑhhhAj¡hCNubeh"}”(h$]”h&]”h+]”h-]”h/]”jšj›uh1jÑhAj¡hCK)h!j²hhubj£)”}”(hX¸The errata workarounds are implemented for a particular revision or a set of processor revisions. This is checked by the reset handler at runtime. Each errata workaround is identified by its ``ID`` as specified in the processor's errata notice document. The format of the define used to enable/disable the errata workaround is ``ERRATA__``, where the ``Processor name`` is for example ``A57`` for the ``Cortex_A57`` CPU.”h]”(hŒ¿The errata workarounds are implemented for a particular revision or a set of processor revisions. This is checked by the reset handler at runtime. Each errata workaround is identified by its ”…””}”(hŒ¿The errata workarounds are implemented for a particular revision or a set of processor revisions. This is checked by the reset handler at runtime. Each errata workaround is identified by its ”h!jG hhhANhCNubjá)”}”(hŒ``ID``”h]”hŒID”…””}”(hhh!jP ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jG ubhŒ„ as specified in the processorâ€™s errata notice document. The format of the define used to enable/disable the errata workaround is ”…””}”(hŒ‚ as specified in the processor's errata notice document. The format of the define used to enable/disable the errata workaround is ”h!jG hhhANhCNubjá)”}”(hŒ ``ERRATA__``”h]”hŒERRATA__”…””}”(hhh!jc ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jG ubhŒ, where the ”…””}”(hŒ, where the ”h!jG hhhANhCNubjá)”}”(hŒ``Processor name``”h]”hŒProcessor name”…””}”(hhh!jv ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jG ubhŒ is for example ”…””}”(hŒ is for example ”h!jG hhhANhCNubjá)”}”(hŒ``A57``”h]”hŒA57”…””}”(hhh!j‰ ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jG ubhŒ for the ”…””}”(hŒ for the ”h!jG hhhANhCNubjá)”}”(hŒ``Cortex_A57``”h]”hŒ Cortex_A57”…””}”(hhh!jœ ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jG ubhŒ CPU.”…””}”(hŒ CPU.”h!jG hhhANhCNubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCK-h!j²hhubj£)”}”(hŒqRefer to :ref:`firmware_design_cpu_errata_reporting` for information on how to write errata workaround functions.”h]”(hŒ Refer to ”…””}”(hŒ Refer to ”h!jµ hhhANhCNubh)”}”(hŒ+:ref:`firmware_design_cpu_errata_reporting`”h]”h)”}”(hjÀ h]”hŒ$firmware_design_cpu_errata_reporting”…””}”(hhh!jÂ ubah"}”(h$]”h&]”(h(Œstd”Œstd-ref”eh+]”h-]”h/]”uh1hh!j¾ ubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”jÌ Œreftype”Œref”Œrefexplicit”‰Œrefwarn”ˆh?Œ$firmware_design_cpu_errata_reporting”uh1hhAj¡hCK4h!jµ ubhŒ= for information on how to write errata workaround functions.”…””}”(hŒ= for information on how to write errata workaround functions.”h!jµ hhhANhCNubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCK4h!j²hhubj£)”}”(hXAll workarounds are disabled by default. The platform is responsible for enabling these workarounds according to its requirement by defining the errata workaround build flags in the platform specific makefile. In case these workarounds are enabled for the wrong CPU revision then the errata workaround is not applied. In the DEBUG build, this is indicated by printing a warning to the crash console.”h]”hXAll workarounds are disabled by default. The platform is responsible for enabling these workarounds according to its requirement by defining the errata workaround build flags in the platform specific makefile. In case these workarounds are enabled for the wrong CPU revision then the errata workaround is not applied. In the DEBUG build, this is indicated by printing a warning to the crash console.”…””}”(hjë h!jé hhhANhCNubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCK7h!j²hhubj£)”}”(hŒ×In the current implementation, a platform which has more than 1 variant with different revisions of a processor has no runtime mechanism available for it to specify which errata workarounds should be enabled or not.”h]”hŒ×In the current implementation, a platform which has more than 1 variant with different revisions of a processor has no runtime mechanism available for it to specify which errata workarounds should be enabled or not.”…””}”(hjù h!j÷ hhhANhCNubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCK>h!j²hhubj£)”}”(hŒ]The value of the build flags is 0 by default, that is, disabled. A value of 1 will enable it.”h]”hŒ]The value of the build flags is 0 by default, that is, disabled. A value of 1 will enable it.”…””}”(hjh!jhhhANhCNubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKBh!j²hhubj£)”}”(hŒ=For Cortex-A9, the following errata build flags are defined :”h]”hŒ=For Cortex-A9, the following errata build flags are defined :”…””}”(hjh!jhhhANhCNubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKEh!j²hhubjÒ)”}”(hhh]”j×)”}”(hŒ…``ERRATA_A9_794073``: This applies errata 794073 workaround to Cortex-A9 CPU. This needs to be enabled for all revisions of the CPU. ”h]”j£)”}”(hŒ„``ERRATA_A9_794073``: This applies errata 794073 workaround to Cortex-A9 CPU. This needs to be enabled for all revisions of the CPU.”h]”(já)”}”(hŒ``ERRATA_A9_794073``”h]”hŒERRATA_A9_794073”…””}”(hhh!j,ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j(ubhŒp: This applies errata 794073 workaround to Cortex-A9 CPU. This needs to be enabled for all revisions of the CPU.”…””}”(hŒp: This applies errata 794073 workaround to Cortex-A9 CPU. This needs to be enabled for all revisions of the CPU.”h!j(ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKGh!j$ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!j!hhhAj¡hCNubah"}”(h$]”h&]”h+]”h-]”h/]”jšj›uh1jÑhAj¡hCKGh!j²hhubj£)”}”(hŒ>For Cortex-A15, the following errata build flags are defined :”h]”hŒ>For Cortex-A15, the following errata build flags are defined :”…””}”(hjSh!jQhhhANhCNubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKJh!j²hhubjÒ)”}”(hhh]”(j×)”}”(hŒ``ERRATA_A15_816470``: This applies errata 816470 workaround to Cortex-A15 CPU. This needs to be enabled only for revision >= r3p0 of the CPU. ”h]”j£)”}”(hŒŽ``ERRATA_A15_816470``: This applies errata 816470 workaround to Cortex-A15 CPU. This needs to be enabled only for revision >= r3p0 of the CPU.”h]”(já)”}”(hŒ``ERRATA_A15_816470``”h]”hŒERRATA_A15_816470”…””}”(hhh!jjubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jfubhŒy: This applies errata 816470 workaround to Cortex-A15 CPU. This needs to be enabled only for revision >= r3p0 of the CPU.”…””}”(hŒy: This applies errata 816470 workaround to Cortex-A15 CPU. This needs to be enabled only for revision >= r3p0 of the CPU.”h!jfubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKLh!jbubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!j_hhhAj¡hCNubj×)”}”(hŒ``ERRATA_A15_827671``: This applies errata 827671 workaround to Cortex-A15 CPU. This needs to be enabled only for revision >= r3p0 of the CPU. ”h]”j£)”}”(hŒŽ``ERRATA_A15_827671``: This applies errata 827671 workaround to Cortex-A15 CPU. This needs to be enabled only for revision >= r3p0 of the CPU.”h]”(já)”}”(hŒ``ERRATA_A15_827671``”h]”hŒERRATA_A15_827671”…””}”(hhh!j‘ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jubhŒy: This applies errata 827671 workaround to Cortex-A15 CPU. This needs to be enabled only for revision >= r3p0 of the CPU.”…””}”(hŒy: This applies errata 827671 workaround to Cortex-A15 CPU. This needs to be enabled only for revision >= r3p0 of the CPU.”h!jubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKOh!j‰ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!j_hhhAj¡hCNubeh"}”(h$]”h&]”h+]”h-]”h/]”jšj›uh1jÑhAj¡hCKLh!j²hhubj£)”}”(hŒ>For Cortex-A17, the following errata build flags are defined :”h]”hŒ>For Cortex-A17, the following errata build flags are defined :”…””}”(hj¸h!j¶hhhANhCNubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKRh!j²hhubjÒ)”}”(hhh]”(j×)”}”(hŒ``ERRATA_A17_852421``: This applies errata 852421 workaround to Cortex-A17 CPU. This needs to be enabled only for revision <= r1p2 of the CPU. ”h]”j£)”}”(hŒŽ``ERRATA_A17_852421``: This applies errata 852421 workaround to Cortex-A17 CPU. This needs to be enabled only for revision <= r1p2 of the CPU.”h]”(já)”}”(hŒ``ERRATA_A17_852421``”h]”hŒERRATA_A17_852421”…””}”(hhh!jÏubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jËubhŒy: This applies errata 852421 workaround to Cortex-A17 CPU. This needs to be enabled only for revision <= r1p2 of the CPU.”…””}”(hŒy: This applies errata 852421 workaround to Cortex-A17 CPU. This needs to be enabled only for revision <= r1p2 of the CPU.”h!jËubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKTh!jÇubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÄhhhAj¡hCNubj×)”}”(hŒ``ERRATA_A17_852423``: This applies errata 852423 workaround to Cortex-A17 CPU. This needs to be enabled only for revision <= r1p2 of the CPU. ”h]”j£)”}”(hŒŽ``ERRATA_A17_852423``: This applies errata 852423 workaround to Cortex-A17 CPU. This needs to be enabled only for revision <= r1p2 of the CPU.”h]”(já)”}”(hŒ``ERRATA_A17_852423``”h]”hŒERRATA_A17_852423”…””}”(hhh!jöubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jòubhŒy: This applies errata 852423 workaround to Cortex-A17 CPU. This needs to be enabled only for revision <= r1p2 of the CPU.”…””}”(hŒy: This applies errata 852423 workaround to Cortex-A17 CPU. This needs to be enabled only for revision <= r1p2 of the CPU.”h!jòubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKWh!jîubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÄhhhAj¡hCNubeh"}”(h$]”h&]”h+]”h-]”h/]”jšj›uh1jÑhAj¡hCKTh!j²hhubj£)”}”(hŒ>For Cortex-A35, the following errata build flags are defined :”h]”hŒ>For Cortex-A35, the following errata build flags are defined :”…””}”(hjh!jhhhANhCNubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKZh!j²hhubjÒ)”}”(hhh]”j×)”}”(hŒ``ERRATA_A35_855472``: This applies errata 855472 workaround to Cortex-A35 CPUs. This needs to be enabled only for revision r0p0 of Cortex-A35. ”h]”j£)”}”(hŒ``ERRATA_A35_855472``: This applies errata 855472 workaround to Cortex-A35 CPUs. This needs to be enabled only for revision r0p0 of Cortex-A35.”h]”(já)”}”(hŒ``ERRATA_A35_855472``”h]”hŒERRATA_A35_855472”…””}”(hhh!j4ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j0ubhŒz: This applies errata 855472 workaround to Cortex-A35 CPUs. This needs to be enabled only for revision r0p0 of Cortex-A35.”…””}”(hŒz: This applies errata 855472 workaround to Cortex-A35 CPUs. This needs to be enabled only for revision r0p0 of Cortex-A35.”h!j0ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCK\h!j,ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!j)hhhAj¡hCNubah"}”(h$]”h&]”h+]”h-]”h/]”jšj›uh1jÑhAj¡hCK\h!j²hhubj£)”}”(hŒ>For Cortex-A53, the following errata build flags are defined :”h]”hŒ>For Cortex-A53, the following errata build flags are defined :”…””}”(hj[h!jYhhhANhCNubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCK_h!j²hhubjÒ)”}”(hhh]”(j×)”}”(hŒŒ``ERRATA_A53_819472``: This applies errata 819472 workaround to all CPUs. This needs to be enabled only for revision <= r0p1 of Cortex-A53. ”h]”j£)”}”(hŒ‹``ERRATA_A53_819472``: This applies errata 819472 workaround to all CPUs. This needs to be enabled only for revision <= r0p1 of Cortex-A53.”h]”(já)”}”(hŒ``ERRATA_A53_819472``”h]”hŒERRATA_A53_819472”…””}”(hhh!jrubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jnubhŒv: This applies errata 819472 workaround to all CPUs. This needs to be enabled only for revision <= r0p1 of Cortex-A53.”…””}”(hŒv: This applies errata 819472 workaround to all CPUs. This needs to be enabled only for revision <= r0p1 of Cortex-A53.”h!jnubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKah!jjubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jghhhAj¡hCNubj×)”}”(hŒŒ``ERRATA_A53_824069``: This applies errata 824069 workaround to all CPUs. This needs to be enabled only for revision <= r0p2 of Cortex-A53. ”h]”j£)”}”(hŒ‹``ERRATA_A53_824069``: This applies errata 824069 workaround to all CPUs. This needs to be enabled only for revision <= r0p2 of Cortex-A53.”h]”(já)”}”(hŒ``ERRATA_A53_824069``”h]”hŒERRATA_A53_824069”…””}”(hhh!j™ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j•ubhŒv: This applies errata 824069 workaround to all CPUs. This needs to be enabled only for revision <= r0p2 of Cortex-A53.”…””}”(hŒv: This applies errata 824069 workaround to all CPUs. This needs to be enabled only for revision <= r0p2 of Cortex-A53.”h!j•ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKdh!j‘ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jghhhAj¡hCNubj×)”}”(hŒ``ERRATA_A53_826319``: This applies errata 826319 workaround to Cortex-A53 CPU. This needs to be enabled only for revision <= r0p2 of the CPU. ”h]”j£)”}”(hŒŽ``ERRATA_A53_826319``: This applies errata 826319 workaround to Cortex-A53 CPU. This needs to be enabled only for revision <= r0p2 of the CPU.”h]”(já)”}”(hŒ``ERRATA_A53_826319``”h]”hŒERRATA_A53_826319”…””}”(hhh!jÀubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j¼ubhŒy: This applies errata 826319 workaround to Cortex-A53 CPU. This needs to be enabled only for revision <= r0p2 of the CPU.”…””}”(hŒy: This applies errata 826319 workaround to Cortex-A53 CPU. This needs to be enabled only for revision <= r0p2 of the CPU.”h!j¼ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKgh!j¸ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jghhhAj¡hCNubj×)”}”(hŒŒ``ERRATA_A53_827319``: This applies errata 827319 workaround to all CPUs. This needs to be enabled only for revision <= r0p2 of Cortex-A53. ”h]”j£)”}”(hŒ‹``ERRATA_A53_827319``: This applies errata 827319 workaround to all CPUs. This needs to be enabled only for revision <= r0p2 of Cortex-A53.”h]”(já)”}”(hŒ``ERRATA_A53_827319``”h]”hŒERRATA_A53_827319”…””}”(hhh!jçubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jãubhŒv: This applies errata 827319 workaround to all CPUs. This needs to be enabled only for revision <= r0p2 of Cortex-A53.”…””}”(hŒv: This applies errata 827319 workaround to all CPUs. This needs to be enabled only for revision <= r0p2 of Cortex-A53.”h!jãubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKjh!jßubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jghhhAj¡hCNubj×)”}”(hŒí``ERRATA_A53_835769``: This applies erratum 835769 workaround at compile and link time to Cortex-A53 CPU. This needs to be enabled for some variants of revision <= r0p4. This workaround can lead the linker to create ``*.stub`` sections. ”h]”j£)”}”(hŒì``ERRATA_A53_835769``: This applies erratum 835769 workaround at compile and link time to Cortex-A53 CPU. This needs to be enabled for some variants of revision <= r0p4. This workaround can lead the linker to create ``*.stub`` sections.”h]”(já)”}”(hŒ``ERRATA_A53_835769``”h]”hŒERRATA_A53_835769”…””}”(hhh!jubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j ubhŒÃ: This applies erratum 835769 workaround at compile and link time to Cortex-A53 CPU. This needs to be enabled for some variants of revision <= r0p4. This workaround can lead the linker to create ”…””}”(hŒÃ: This applies erratum 835769 workaround at compile and link time to Cortex-A53 CPU. This needs to be enabled for some variants of revision <= r0p4. This workaround can lead the linker to create ”h!j ubjá)”}”(hŒ ``*.stub``”h]”hŒ*.stub”…””}”(hhh!j!ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j ubhŒ sections.”…””}”(hŒ sections.”h!j ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKmh!jubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jghhhAj¡hCNubj×)”}”(hŒÕ``ERRATA_A53_836870``: This applies errata 836870 workaround to Cortex-A53 CPU. This needs to be enabled only for revision <= r0p3 of the CPU. From r0p4 and onwards, this errata is enabled by default in hardware. ”h]”j£)”}”(hŒÔ``ERRATA_A53_836870``: This applies errata 836870 workaround to Cortex-A53 CPU. This needs to be enabled only for revision <= r0p3 of the CPU. From r0p4 and onwards, this errata is enabled by default in hardware.”h]”(já)”}”(hŒ``ERRATA_A53_836870``”h]”hŒERRATA_A53_836870”…””}”(hhh!jHubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jDubhŒ¿: This applies errata 836870 workaround to Cortex-A53 CPU. This needs to be enabled only for revision <= r0p3 of the CPU. From r0p4 and onwards, this errata is enabled by default in hardware.”…””}”(hŒ¿: This applies errata 836870 workaround to Cortex-A53 CPU. This needs to be enabled only for revision <= r0p3 of the CPU. From r0p4 and onwards, this errata is enabled by default in hardware.”h!jDubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKrh!j@ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jghhhAj¡hCNubj×)”}”(hŒö``ERRATA_A53_843419``: This applies erratum 843419 workaround at link time to Cortex-A53 CPU. This needs to be enabled for some variants of revision <= r0p4. This workaround can lead the linker to emit ``*.stub`` sections which are 4kB aligned. ”h]”j£)”}”(hŒõ``ERRATA_A53_843419``: This applies erratum 843419 workaround at link time to Cortex-A53 CPU. This needs to be enabled for some variants of revision <= r0p4. This workaround can lead the linker to emit ``*.stub`` sections which are 4kB aligned.”h]”(já)”}”(hŒ``ERRATA_A53_843419``”h]”hŒERRATA_A53_843419”…””}”(hhh!joubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jkubhŒ¶: This applies erratum 843419 workaround at link time to Cortex-A53 CPU. This needs to be enabled for some variants of revision <= r0p4. This workaround can lead the linker to emit ”…””}”(hŒ¶: This applies erratum 843419 workaround at link time to Cortex-A53 CPU. This needs to be enabled for some variants of revision <= r0p4. This workaround can lead the linker to emit ”h!jkubjá)”}”(hŒ ``*.stub``”h]”hŒ*.stub”…””}”(hhh!j‚ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jkubhŒ sections which are 4kB aligned.”…””}”(hŒ sections which are 4kB aligned.”h!jkubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKvh!jgubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jghhhAj¡hCNubj×)”}”(hX•``ERRATA_A53_855873``: This applies errata 855873 workaround to Cortex-A53 CPUs. Though the erratum is present in every revision of the CPU, this workaround is only applied to CPUs from r0p3 onwards, which feature a chicken bit in CPUACTLR_EL1 to enable a hardware workaround. Earlier revisions of the CPU have other errata which require the same workaround in software, so they should be covered anyway. ”h]”j£)”}”(hX”``ERRATA_A53_855873``: This applies errata 855873 workaround to Cortex-A53 CPUs. Though the erratum is present in every revision of the CPU, this workaround is only applied to CPUs from r0p3 onwards, which feature a chicken bit in CPUACTLR_EL1 to enable a hardware workaround. Earlier revisions of the CPU have other errata which require the same workaround in software, so they should be covered anyway.”h]”(já)”}”(hŒ``ERRATA_A53_855873``”h]”hŒERRATA_A53_855873”…””}”(hhh!j©ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j¥ubhX: This applies errata 855873 workaround to Cortex-A53 CPUs. Though the erratum is present in every revision of the CPU, this workaround is only applied to CPUs from r0p3 onwards, which feature a chicken bit in CPUACTLR_EL1 to enable a hardware workaround. Earlier revisions of the CPU have other errata which require the same workaround in software, so they should be covered anyway.”…””}”(hX: This applies errata 855873 workaround to Cortex-A53 CPUs. Though the erratum is present in every revision of the CPU, this workaround is only applied to CPUs from r0p3 onwards, which feature a chicken bit in CPUACTLR_EL1 to enable a hardware workaround. Earlier revisions of the CPU have other errata which require the same workaround in software, so they should be covered anyway.”h!j¥ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCK{h!j¡ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jghhhAj¡hCNubj×)”}”(hŒc``ERRATA_A53_1530924``: This applies errata 1530924 workaround to all revisions of Cortex-A53 CPU. ”h]”j£)”}”(hŒb``ERRATA_A53_1530924``: This applies errata 1530924 workaround to all revisions of Cortex-A53 CPU.”h]”(já)”}”(hŒ``ERRATA_A53_1530924``”h]”hŒERRATA_A53_1530924”…””}”(hhh!jÐubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jÌubhŒL: This applies errata 1530924 workaround to all revisions of Cortex-A53 CPU.”…””}”(hŒL: This applies errata 1530924 workaround to all revisions of Cortex-A53 CPU.”h!jÌubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCK‚h!jÈubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jghhhAj¡hCNubeh"}”(h$]”h&]”h+]”h-]”h/]”jšj›uh1jÑhAj¡hCKah!j²hhubj£)”}”(hŒ>For Cortex-A55, the following errata build flags are defined :”h]”hŒ>For Cortex-A55, the following errata build flags are defined :”…””}”(hj÷h!jõhhhANhCNubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCK…h!j²hhubjÒ)”}”(hhh]”(j×)”}”(hŒŒ``ERRATA_A55_768277``: This applies errata 768277 workaround to Cortex-A55 CPU. This needs to be enabled only for revision r0p0 of the CPU. ”h]”j£)”}”(hŒ‹``ERRATA_A55_768277``: This applies errata 768277 workaround to Cortex-A55 CPU. This needs to be enabled only for revision r0p0 of the CPU.”h]”(já)”}”(hŒ``ERRATA_A55_768277``”h]”hŒERRATA_A55_768277”…””}”(hhh!jubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j ubhŒv: This applies errata 768277 workaround to Cortex-A55 CPU. This needs to be enabled only for revision r0p0 of the CPU.”…””}”(hŒv: This applies errata 768277 workaround to Cortex-A55 CPU. This needs to be enabled only for revision r0p0 of the CPU.”h!j ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCK‡h!jubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jhhhAj¡hCNubj×)”}”(hŒŒ``ERRATA_A55_778703``: This applies errata 778703 workaround to Cortex-A55 CPU. This needs to be enabled only for revision r0p0 of the CPU. ”h]”j£)”}”(hŒ‹``ERRATA_A55_778703``: This applies errata 778703 workaround to Cortex-A55 CPU. This needs to be enabled only for revision r0p0 of the CPU.”h]”(já)”}”(hŒ``ERRATA_A55_778703``”h]”hŒERRATA_A55_778703”…””}”(hhh!j5ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j1ubhŒv: This applies errata 778703 workaround to Cortex-A55 CPU. This needs to be enabled only for revision r0p0 of the CPU.”…””}”(hŒv: This applies errata 778703 workaround to Cortex-A55 CPU. This needs to be enabled only for revision r0p0 of the CPU.”h!j1ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKŠh!j-ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jhhhAj¡hCNubj×)”}”(hŒŒ``ERRATA_A55_798797``: This applies errata 798797 workaround to Cortex-A55 CPU. This needs to be enabled only for revision r0p0 of the CPU. ”h]”j£)”}”(hŒ‹``ERRATA_A55_798797``: This applies errata 798797 workaround to Cortex-A55 CPU. This needs to be enabled only for revision r0p0 of the CPU.”h]”(já)”}”(hŒ``ERRATA_A55_798797``”h]”hŒERRATA_A55_798797”…””}”(hhh!j\ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jXubhŒv: This applies errata 798797 workaround to Cortex-A55 CPU. This needs to be enabled only for revision r0p0 of the CPU.”…””}”(hŒv: This applies errata 798797 workaround to Cortex-A55 CPU. This needs to be enabled only for revision r0p0 of the CPU.”h!jXubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKh!jTubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jhhhAj¡hCNubj×)”}”(hŒ``ERRATA_A55_846532``: This applies errata 846532 workaround to Cortex-A55 CPU. This needs to be enabled only for revision <= r0p1 of the CPU. ”h]”j£)”}”(hŒŽ``ERRATA_A55_846532``: This applies errata 846532 workaround to Cortex-A55 CPU. This needs to be enabled only for revision <= r0p1 of the CPU.”h]”(já)”}”(hŒ``ERRATA_A55_846532``”h]”hŒERRATA_A55_846532”…””}”(hhh!jƒubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jubhŒy: This applies errata 846532 workaround to Cortex-A55 CPU. This needs to be enabled only for revision <= r0p1 of the CPU.”…””}”(hŒy: This applies errata 846532 workaround to Cortex-A55 CPU. This needs to be enabled only for revision <= r0p1 of the CPU.”h!jubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKh!j{ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jhhhAj¡hCNubj×)”}”(hŒ``ERRATA_A55_903758``: This applies errata 903758 workaround to Cortex-A55 CPU. This needs to be enabled only for revision <= r0p1 of the CPU. ”h]”j£)”}”(hŒŽ``ERRATA_A55_903758``: This applies errata 903758 workaround to Cortex-A55 CPU. This needs to be enabled only for revision <= r0p1 of the CPU.”h]”(já)”}”(hŒ``ERRATA_A55_903758``”h]”hŒERRATA_A55_903758”…””}”(hhh!jªubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j¦ubhŒy: This applies errata 903758 workaround to Cortex-A55 CPU. This needs to be enabled only for revision <= r0p1 of the CPU.”…””}”(hŒy: This applies errata 903758 workaround to Cortex-A55 CPU. This needs to be enabled only for revision <= r0p1 of the CPU.”h!j¦ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCK“h!j¢ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jhhhAj¡hCNubj×)”}”(hŒ‘``ERRATA_A55_1221012``: This applies errata 1221012 workaround to Cortex-A55 CPU. This needs to be enabled only for revision <= r1p0 of the CPU. ”h]”j£)”}”(hŒ``ERRATA_A55_1221012``: This applies errata 1221012 workaround to Cortex-A55 CPU. This needs to be enabled only for revision <= r1p0 of the CPU.”h]”(já)”}”(hŒ``ERRATA_A55_1221012``”h]”hŒERRATA_A55_1221012”…””}”(hhh!jÑubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jÍubhŒz: This applies errata 1221012 workaround to Cortex-A55 CPU. This needs to be enabled only for revision <= r1p0 of the CPU.”…””}”(hŒz: This applies errata 1221012 workaround to Cortex-A55 CPU. This needs to be enabled only for revision <= r1p0 of the CPU.”h!jÍubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCK–h!jÉubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jhhhAj¡hCNubj×)”}”(hŒc``ERRATA_A55_1530923``: This applies errata 1530923 workaround to all revisions of Cortex-A55 CPU. ”h]”j£)”}”(hŒb``ERRATA_A55_1530923``: This applies errata 1530923 workaround to all revisions of Cortex-A55 CPU.”h]”(já)”}”(hŒ``ERRATA_A55_1530923``”h]”hŒERRATA_A55_1530923”…””}”(hhh!jøubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jôubhŒL: This applies errata 1530923 workaround to all revisions of Cortex-A55 CPU.”…””}”(hŒL: This applies errata 1530923 workaround to all revisions of Cortex-A55 CPU.”h!jôubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCK™h!jðubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jhhhAj¡hCNubeh"}”(h$]”h&]”h+]”h-]”h/]”jšj›uh1jÑhAj¡hCK‡h!j²hhubj£)”}”(hŒ>For Cortex-A57, the following errata build flags are defined :”h]”hŒ>For Cortex-A57, the following errata build flags are defined :”…””}”(hjh!jhhhANhCNubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKœh!j²hhubjÒ)”}”(hhh]”(j×)”}”(hŒŒ``ERRATA_A57_806969``: This applies errata 806969 workaround to Cortex-A57 CPU. This needs to be enabled only for revision r0p0 of the CPU. ”h]”j£)”}”(hŒ‹``ERRATA_A57_806969``: This applies errata 806969 workaround to Cortex-A57 CPU. This needs to be enabled only for revision r0p0 of the CPU.”h]”(já)”}”(hŒ``ERRATA_A57_806969``”h]”hŒERRATA_A57_806969”…””}”(hhh!j6ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j2ubhŒv: This applies errata 806969 workaround to Cortex-A57 CPU. This needs to be enabled only for revision r0p0 of the CPU.”…””}”(hŒv: This applies errata 806969 workaround to Cortex-A57 CPU. This needs to be enabled only for revision r0p0 of the CPU.”h!j2ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKžh!j.ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!j+hhhAj¡hCNubj×)”}”(hŒŒ``ERRATA_A57_813419``: This applies errata 813419 workaround to Cortex-A57 CPU. This needs to be enabled only for revision r0p0 of the CPU. ”h]”j£)”}”(hŒ‹``ERRATA_A57_813419``: This applies errata 813419 workaround to Cortex-A57 CPU. This needs to be enabled only for revision r0p0 of the CPU.”h]”(já)”}”(hŒ``ERRATA_A57_813419``”h]”hŒERRATA_A57_813419”…””}”(hhh!j]ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jYubhŒv: This applies errata 813419 workaround to Cortex-A57 CPU. This needs to be enabled only for revision r0p0 of the CPU.”…””}”(hŒv: This applies errata 813419 workaround to Cortex-A57 CPU. This needs to be enabled only for revision r0p0 of the CPU.”h!jYubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCK¡h!jUubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!j+hhhAj¡hCNubj×)”}”(hŒŒ``ERRATA_A57_813420``: This applies errata 813420 workaround to Cortex-A57 CPU. This needs to be enabled only for revision r0p0 of the CPU. ”h]”j£)”}”(hŒ‹``ERRATA_A57_813420``: This applies errata 813420 workaround to Cortex-A57 CPU. This needs to be enabled only for revision r0p0 of the CPU.”h]”(já)”}”(hŒ``ERRATA_A57_813420``”h]”hŒERRATA_A57_813420”…””}”(hhh!j„ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j€ubhŒv: This applies errata 813420 workaround to Cortex-A57 CPU. This needs to be enabled only for revision r0p0 of the CPU.”…””}”(hŒv: This applies errata 813420 workaround to Cortex-A57 CPU. This needs to be enabled only for revision r0p0 of the CPU.”h!j€ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCK¤h!j|ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!j+hhhAj¡hCNubj×)”}”(hŒŒ``ERRATA_A57_814670``: This applies errata 814670 workaround to Cortex-A57 CPU. This needs to be enabled only for revision r0p0 of the CPU. ”h]”j£)”}”(hŒ‹``ERRATA_A57_814670``: This applies errata 814670 workaround to Cortex-A57 CPU. This needs to be enabled only for revision r0p0 of the CPU.”h]”(já)”}”(hŒ``ERRATA_A57_814670``”h]”hŒERRATA_A57_814670”…””}”(hhh!j«ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j§ubhŒv: This applies errata 814670 workaround to Cortex-A57 CPU. This needs to be enabled only for revision r0p0 of the CPU.”…””}”(hŒv: This applies errata 814670 workaround to Cortex-A57 CPU. This needs to be enabled only for revision r0p0 of the CPU.”h!j§ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCK§h!j£ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!j+hhhAj¡hCNubj×)”}”(hŒ``ERRATA_A57_817169``: This applies errata 817169 workaround to Cortex-A57 CPU. This needs to be enabled only for revision <= r0p1 of the CPU. ”h]”j£)”}”(hŒŽ``ERRATA_A57_817169``: This applies errata 817169 workaround to Cortex-A57 CPU. This needs to be enabled only for revision <= r0p1 of the CPU.”h]”(já)”}”(hŒ``ERRATA_A57_817169``”h]”hŒERRATA_A57_817169”…””}”(hhh!jÒubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jÎubhŒy: This applies errata 817169 workaround to Cortex-A57 CPU. This needs to be enabled only for revision <= r0p1 of the CPU.”…””}”(hŒy: This applies errata 817169 workaround to Cortex-A57 CPU. This needs to be enabled only for revision <= r0p1 of the CPU.”h!jÎube•h"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKªh!jÊubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!j+hhhAj¡hCNubj×)”}”(hŒ``ERRATA_A57_826974``: This applies errata 826974 workaround to Cortex-A57 CPU. This needs to be enabled only for revision <= r1p1 of the CPU. ”h]”j£)”}”(hŒŽ``ERRATA_A57_826974``: This applies errata 826974 workaround to Cortex-A57 CPU. This needs to be enabled only for revision <= r1p1 of the CPU.”h]”(já)”}”(hŒ``ERRATA_A57_826974``”h]”hŒERRATA_A57_826974”…””}”(hhh!jùubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jõubhŒy: This applies errata 826974 workaround to Cortex-A57 CPU. This needs to be enabled only for revision <= r1p1 of the CPU.”…””}”(hŒy: This applies errata 826974 workaround to Cortex-A57 CPU. This needs to be enabled only for revision <= r1p1 of the CPU.”h!jõubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKh!jñubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!j+hhhAj¡hCNubj×)”}”(hŒ``ERRATA_A57_826977``: This applies errata 826977 workaround to Cortex-A57 CPU. This needs to be enabled only for revision <= r1p1 of the CPU. ”h]”j£)”}”(hŒŽ``ERRATA_A57_826977``: This applies errata 826977 workaround to Cortex-A57 CPU. This needs to be enabled only for revision <= r1p1 of the CPU.”h]”(já)”}”(hŒ``ERRATA_A57_826977``”h]”hŒERRATA_A57_826977”…””}”(hhh!j ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jubhŒy: This applies errata 826977 workaround to Cortex-A57 CPU. This needs to be enabled only for revision <= r1p1 of the CPU.”…””}”(hŒy: This applies errata 826977 workaround to Cortex-A57 CPU. This needs to be enabled only for revision <= r1p1 of the CPU.”h!jubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCK°h!jubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!j+hhhAj¡hCNubj×)”}”(hŒ``ERRATA_A57_828024``: This applies errata 828024 workaround to Cortex-A57 CPU. This needs to be enabled only for revision <= r1p1 of the CPU. ”h]”j£)”}”(hŒŽ``ERRATA_A57_828024``: This applies errata 828024 workaround to Cortex-A57 CPU. This needs to be enabled only for revision <= r1p1 of the CPU.”h]”(já)”}”(hŒ``ERRATA_A57_828024``”h]”hŒERRATA_A57_828024”…””}”(hhh!jGubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jCubhŒy: This applies errata 828024 workaround to Cortex-A57 CPU. This needs to be enabled only for revision <= r1p1 of the CPU.”…””}”(hŒy: This applies errata 828024 workaround to Cortex-A57 CPU. This needs to be enabled only for revision <= r1p1 of the CPU.”h!jCubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCK³h!j?ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!j+hhhAj¡hCNubj×)”}”(hŒ``ERRATA_A57_829520``: This applies errata 829520 workaround to Cortex-A57 CPU. This needs to be enabled only for revision <= r1p2 of the CPU. ”h]”j£)”}”(hŒŽ``ERRATA_A57_829520``: This applies errata 829520 workaround to Cortex-A57 CPU. This needs to be enabled only for revision <= r1p2 of the CPU.”h]”(já)”}”(hŒ``ERRATA_A57_829520``”h]”hŒERRATA_A57_829520”…””}”(hhh!jnubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jjubhŒy: This applies errata 829520 workaround to Cortex-A57 CPU. This needs to be enabled only for revision <= r1p2 of the CPU.”…””}”(hŒy: This applies errata 829520 workaround to Cortex-A57 CPU. This needs to be enabled only for revision <= r1p2 of the CPU.”h!jjubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCK¶h!jfubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!j+hhhAj¡hCNubj×)”}”(hŒ``ERRATA_A57_833471``: This applies errata 833471 workaround to Cortex-A57 CPU. This needs to be enabled only for revision <= r1p2 of the CPU. ”h]”j£)”}”(hŒŽ``ERRATA_A57_833471``: This applies errata 833471 workaround to Cortex-A57 CPU. This needs to be enabled only for revision <= r1p2 of the CPU.”h]”(já)”}”(hŒ``ERRATA_A57_833471``”h]”hŒERRATA_A57_833471”…””}”(hhh!j•ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j‘ubhŒy: This applies errata 833471 workaround to Cortex-A57 CPU. This needs to be enabled only for revision <= r1p2 of the CPU.”…””}”(hŒy: This applies errata 833471 workaround to Cortex-A57 CPU. This needs to be enabled only for revision <= r1p2 of the CPU.”h!j‘ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCK¹h!jubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!j+hhhAj¡hCNubj×)”}”(hŒ``ERRATA_A57_859972``: This applies errata 859972 workaround to Cortex-A57 CPU. This needs to be enabled only for revision <= r1p3 of the CPU. ”h]”j£)”}”(hŒŽ``ERRATA_A57_859972``: This applies errata 859972 workaround to Cortex-A57 CPU. This needs to be enabled only for revision <= r1p3 of the CPU.”h]”(já)”}”(hŒ``ERRATA_A57_859972``”h]”hŒERRATA_A57_859972”…””}”(hhh!j¼ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j¸ubhŒy: This applies errata 859972 workaround to Cortex-A57 CPU. This needs to be enabled only for revision <= r1p3 of the CPU.”…””}”(hŒy: This applies errata 859972 workaround to Cortex-A57 CPU. This needs to be enabled only for revision <= r1p3 of the CPU.”h!j¸ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCK¼h!j´ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!j+hhhAj¡hCNubj×)”}”(hŒc``ERRATA_A57_1319537``: This applies errata 1319537 workaround to all revisions of Cortex-A57 CPU. ”h]”j£)”}”(hŒb``ERRATA_A57_1319537``: This applies errata 1319537 workaround to all revisions of Cortex-A57 CPU.”h]”(já)”}”(hŒ``ERRATA_A57_1319537``”h]”hŒERRATA_A57_1319537”…””}”(hhh!jãubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jßubhŒL: This applies errata 1319537 workaround to all revisions of Cortex-A57 CPU.”…””}”(hŒL: This applies errata 1319537 workaround to all revisions of Cortex-A57 CPU.”h!jßubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCK¿h!jÛubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!j+hhhAj¡hCNubeh"}”(h$]”h&]”h+]”h-]”h/]”jšj›uh1jÑhAj¡hCKžh!j²hhubj£)”}”(hŒ>For Cortex-A72, the following errata build flags are defined :”h]”hŒ>For Cortex-A72, the following errata build flags are defined :”…””}”(hj h!jhhhANhCNubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKÂh!j²hhubjÒ)”}”(hhh]”(j×)”}”(hŒ``ERRATA_A72_859971``: This applies errata 859971 workaround to Cortex-A72 CPU. This needs to be enabled only for revision <= r0p3 of the CPU. ”h]”j£)”}”(hŒŽ``ERRATA_A72_859971``: This applies errata 859971 workaround to Cortex-A72 CPU. This needs to be enabled only for revision <= r0p3 of the CPU.”h]”(já)”}”(hŒ``ERRATA_A72_859971``”h]”hŒERRATA_A72_859971”…””}”(hhh!j!ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jubhŒy: This applies errata 859971 workaround to Cortex-A72 CPU. This needs to be enabled only for revision <= r0p3 of the CPU.”…””}”(hŒy: This applies errata 859971 workaround to Cortex-A72 CPU. This needs to be enabled only for revision <= r0p3 of the CPU.”h!jubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKÄh!jubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jhhhAj¡hCNubj×)”}”(hŒc``ERRATA_A72_1319367``: This applies errata 1319367 workaround to all revisions of Cortex-A72 CPU. ”h]”j£)”}”(hŒb``ERRATA_A72_1319367``: This applies errata 1319367 workaround to all revisions of Cortex-A72 CPU.”h]”(já)”}”(hŒ``ERRATA_A72_1319367``”h]”hŒERRATA_A72_1319367”…””}”(hhh!jHubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jDubhŒL: This applies errata 1319367 workaround to all revisions of Cortex-A72 CPU.”…””}”(hŒL: This applies errata 1319367 workaround to all revisions of Cortex-A72 CPU.”h!jDubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKÇh!j@ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jhhhAj¡hCNubeh"}”(h$]”h&]”h+]”h-]”h/]”jšj›uh1jÑhAj¡hCKÄh!j²hhubj£)”}”(hŒ>For Cortex-A73, the following errata build flags are defined :”h]”hŒ>For Cortex-A73, the following errata build flags are defined :”…””}”(hjoh!jmhhhANhCNubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKÊh!j²hhubjÒ)”}”(hhh]”(j×)”}”(hŒŒ``ERRATA_A73_852427``: This applies errata 852427 workaround to Cortex-A73 CPU. This needs to be enabled only for revision r0p0 of the CPU. ”h]”j£)”}”(hŒ‹``ERRATA_A73_852427``: This applies errata 852427 workaround to Cortex-A73 CPU. This needs to be enabled only for revision r0p0 of the CPU.”h]”(já)”}”(hŒ``ERRATA_A73_852427``”h]”hŒERRATA_A73_852427”…””}”(hhh!j†ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j‚ubhŒv: This applies errata 852427 workaround to Cortex-A73 CPU. This needs to be enabled only for revision r0p0 of the CPU.”…””}”(hŒv: This applies errata 852427 workaround to Cortex-A73 CPU. This needs to be enabled only for revision r0p0 of the CPU.”h!j‚ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKÌh!j~ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!j{hhhAj¡hCNubj×)”}”(hŒ``ERRATA_A73_855423``: This applies errata 855423 workaround to Cortex-A73 CPU. This needs to be enabled only for revision <= r0p1 of the CPU. ”h]”j£)”}”(hŒŽ``ERRATA_A73_855423``: This applies errata 855423 workaround to Cortex-A73 CPU. This needs to be enabled only for revision <= r0p1 of the CPU.”h]”(já)”}”(hŒ``ERRATA_A73_855423``”h]”hŒERRATA_A73_855423”…””}”(hhh!jubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j©ubhŒy: This applies errata 855423 workaround to Cortex-A73 CPU. This needs to be enabled only for revision <= r0p1 of the CPU.”…””}”(hŒy: This applies errata 855423 workaround to Cortex-A73 CPU. This needs to be enabled only for revision <= r0p1 of the CPU.”h!j©ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKÏh!j¥ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!j{hhhAj¡hCNubeh"}”(h$]”h&]”h+]”h-]”h/]”jšj›uh1jÑhAj¡hCKÌh!j²hhubj£)”}”(hŒ>For Cortex-A75, the following errata build flags are defined :”h]”hŒ>For Cortex-A75, the following errata build flags are defined :”…””}”(hjÔh!jÒhhhANhCNubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKÒh!j²hhubjÒ)”}”(hhh]”(j×)”}”(hŒŒ``ERRATA_A75_764081``: This applies errata 764081 workaround to Cortex-A75 CPU. This needs to be enabled only for revision r0p0 of the CPU. ”h]”j£)”}”(hŒ‹``ERRATA_A75_764081``: This applies errata 764081 workaround to Cortex-A75 CPU. This needs to be enabled only for revision r0p0 of the CPU.”h]”(já)”}”(hŒ``ERRATA_A75_764081``”h]”hŒERRATA_A75_764081”…””}”(hhh!jëubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jçubhŒv: This applies errata 764081 workaround to Cortex-A75 CPU. This needs to be enabled only for revision r0p0 of the CPU.”…””}”(hŒv: This applies errata 764081 workaround to Cortex-A75 CPU. This needs to be enabled only for revision r0p0 of the CPU.”h!jçubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKÔh!jãubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jàhhhAj¡hCNubj×)”}”(hŒ``ERRATA_A75_790748``: This applies errata 790748 workaround to Cortex-A75 CPU. This needs to be enabled only for revision r0p0 of the CPU. ”h]”h Œdefinition_list”“”)”}”(hhh]”h Œdefinition_list_item”“”)”}”(hŒŒ``ERRATA_A75_790748``: This applies errata 790748 workaround to Cortex-A75 CPU. This needs to be enabled only for revision r0p0 of the CPU. ”h]”(h Œterm”“”)”}”(hŒJ``ERRATA_A75_790748``: This applies errata 790748 workaround to Cortex-A75”h]”(já)”}”(hŒ``ERRATA_A75_790748``”h]”hŒERRATA_A75_790748”…””}”(hhh!jubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jubhŒ5: This applies errata 790748 workaround to Cortex-A75”…””}”(hŒ5: This applies errata 790748 workaround to Cortex-A75”h!jubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1jhAj¡hCKØh!jubh Œ definition”“”)”}”(hhh]”j£)”}”(hŒ@CPU. This needs to be enabled only for revision r0p0 of the CPU.”h]”hŒ@CPU. This needs to be enabled only for revision r0p0 of the CPU.”…””}”(hj?h!j=ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKØh!j:ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j8h!jubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1jhAj¡hCKØh!jubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!j ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jàhhhANhCNubeh"}”(h$]”h&]”h+]”h-]”h/]”jšj›uh1jÑhAj¡hCKÔh!j²hhubj£)”}”(hŒ>For Cortex-A76, the following errata build flags are defined :”h]”hŒ>For Cortex-A76, the following errata build flags are defined :”…””}”(hjkh!jihhhANhCNubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKÚh!j²hhubjÒ)”}”(hhh]”(j×)”}”(hŒ‘``ERRATA_A76_1073348``: This applies errata 1073348 workaround to Cortex-A76 CPU. This needs to be enabled only for revision <= r1p0 of the CPU. ”h]”j£)”}”(hŒ``ERRATA_A76_1073348``: This applies errata 1073348 workaround to Cortex-A76 CPU. This needs to be enabled only for revision <= r1p0 of the CPU.”h]”(já)”}”(hŒ``ERRATA_A76_1073348``”h]”hŒERRATA_A76_1073348”…””}”(hhh!j‚ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j~ubhŒz: This applies errata 1073348 workaround to Cortex-A76 CPU. This needs to be enabled only for revision <= r1p0 of the CPU.”…””}”(hŒz: This applies errata 1073348 workaround to Cortex-A76 CPU. This needs to be enabled only for revision <= r1p0 of the CPU.”h!j~ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKÜh!jzubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jwhhhAj¡hCNubj×)”}”(hŒ‘``ERRATA_A76_1130799``: This applies errata 1130799 workaround to Cortex-A76 CPU. This needs to be enabled only for revision <= r2p0 of the CPU. ”h]”j£)”}”(hŒ``ERRATA_A76_1130799``: This applies errata 1130799 workaround to Cortex-A76 CPU. This needs to be enabled only for revision <= r2p0 of the CPU.”h]”(já)”}”(hŒ``ERRATA_A76_1130799``”h]”hŒERRATA_A76_1130799”…””}”(hhh!j©ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j¥ubhŒz: This applies errata 1130799 workaround to Cortex-A76 CPU. This needs to be enabled only for revision <= r2p0 of the CPU.”…””}”(hŒz: This applies errata 1130799 workaround to Cortex-A76 CPU. This needs to be enabled only for revision <= r2p0 of the CPU.”h!j¥ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKßh!j¡ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jwhhhAj¡hCNubj×)”}”(hŒ‘``ERRATA_A76_1220197``: This applies errata 1220197 workaround to Cortex-A76 CPU. This needs to be enabled only for revision <= r2p0 of the CPU. ”h]”j£)”}”(hŒ``ERRATA_A76_1220197``: This applies errata 1220197 workaround to Cortex-A76 CPU. This needs to be enabled only for revision <= r2p0 of the CPU.”h]”(já)”}”(hŒ``ERRATA_A76_1220197``”h]”hŒERRATA_A76_1220197”…””}”(hhh!jÐubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jÌubhŒz: This applies errata 1220197 workaround to Cortex-A76 CPU. This needs to be enabled only for revision <= r2p0 of the CPU.”…””}”(hŒz: This applies errata 1220197 workaround to Cortex-A76 CPU. This needs to be enabled only for revision <= r2p0 of the CPU.”h!jÌubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKâh!jÈubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jwhhhAj¡hCNubj×)”}”(hŒ‘``ERRATA_A76_1257314``: This applies errata 1257314 workaround to Cortex-A76 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. ”h]”j£)”}”(hŒ``ERRATA_A76_1257314``: This applies errata 1257314 workaround to Cortex-A76 CPU. This needs to be enabled only for revision <= r3p0 of the CPU.”h]”(já)”}”(hŒ``ERRATA_A76_1257314``”h]”hŒERRATA_A76_1257314”…””}”(hhh!j÷ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jóubhŒz: This applies errata 1257314 workaround to Cortex-A76 CPU. This needs to be enabled only for revision <= r3p0 of the CPU.”…””}”(hŒz: This applies errata 1257314 workaround to Cortex-A76 CPU. This needs to be enabled only for revision <= r3p0 of the CPU.”h!jóubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKåh!jïubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jwhhhAj¡hCNubj×)”}”(hŒ‘``ERRATA_A76_1262606``: This applies errata 1262606 workaround to Cortex-A76 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. ”h]”j£)”}”(hŒ``ERRATA_A76_1262606``: This applies errata 1262606 workaround to Cortex-A76 CPU. This needs to be enabled only for revision <= r3p0 of the CPU.”h]”(já)”}”(hŒ``ERRATA_A76_1262606``”h]”hŒERRATA_A76_1262606”…””}”(hhh!jubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jubhŒz: This applies errata 1262606 workaround to Cortex-A76 CPU. This needs to be enabled only for revision <= r3p0 of the CPU.”…””}”(hŒz: This applies errata 1262606 workaround to Cortex-A76 CPU. This needs to be enabled only for revision <= r3p0 of the CPU.”h!jubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKèh!jubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jwhhhAj¡hCNubj×)”}”(hŒ‘``ERRATA_A76_1262888``: This applies errata 1262888 workaround to Cortex-A76 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. ”h]”j£)”}”(hŒ``ERRATA_A76_1262888``: This applies errata 1262888 workaround to Cortex-A76 CPU. This needs to be enabled only for revision <= r3p0 of the CPU.”h]”(já)”}”(hŒ``ERRATA_A76_1262888``”h]”hŒERRATA_A76_1262888”…””}”(hhh!jEubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jAubhŒz: This applies errata 1262888 workaround to Cortex-A76 CPU. This needs to be enabled only for revision <= r3p0 of the CPU.”…””}”(hŒz: This applies errata 1262888 workaround to Cortex-A76 CPU. This needs to be enabled only for revision <= r3p0 of the CPU.”h!jAubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKëh!j=ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jwhhhAj¡hCNubj×)”}”(hŒ‘``ERRATA_A76_1275112``: This applies errata 1275112 workaround to Cortex-A76 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. ”h]”j£)”}”(hŒ``ERRATA_A76_1275112``: This applies errata 1275112 workaround to Cortex-A76 CPU. This needs to be enabled only for revision <= r3p0 of the CPU.”h]”(já)”}”(hŒ``ERRATA_A76_1275112``”h]”hŒERRATA_A76_1275112”…””}”(hhh!jlubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jhubhŒz: This applies errata 1275112 workaround to Cortex-A76 CPU. This needs to be enabled only for revision <= r3p0 of the CPU.”…””}”(hŒz: This applies errata 1275112 workaround to Cortex-A76 CPU. This needs to be enabled only for revision <= r3p0 of the CPU.”h!jhubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKîh!jdubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jwhhhAj¡hCNubj×)”}”(hŒ‘``ERRATA_A76_1791580``: This applies errata 1791580 workaround to Cortex-A76 CPU. This needs to be enabled only for revision <= r4p0 of the CPU. ”h]”j£)”}”(hŒ``ERRATA_A76_1791580``: This applies errata 1791580 workaround to Cortex-A76 CPU. This needs to be enabled only for revision <= r4p0 of the CPU.”h]”(já)”}”(hŒ``ERRATA_A76_1791580``”h]”hŒERRATA_A76_1791580”…””}”(hhh!j“ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jubhŒz: This applies errata 1791580 workaround to Cortex-A76 CPU. This needs to be enabled only for revision <= r4p0 of the CPU.”…””}”(hŒz: This applies errata 1791580 workaround to Cortex-A76 CPU. This needs to be enabled only for revision <= r4p0 of the CPU.”h!jubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKñh!j‹ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jwhhhAj¡hCNubj×)”}”(hŒå``ERRATA_A76_1165522``: This applies errata 1165522 workaround to all revisions of Cortex-A76 CPU. This errata is fixed in r3p0 but due to limitation of errata framework this errata is applied to all revisions of Cortex-A76 CPU. ”h]”j£)”}”(hŒä``ERRATA_A76_1165522``: This applies errata 1165522 workaround to all revisions of Cortex-A76 CPU. This errata is fixed in r3p0 but due to limitation of errata framework this errata is applied to all revisions of Cortex-A76 CPU.”h]”(já)”}”(hŒ``ERRATA_A76_1165522``”h]”hŒERRATA_A76_1165522”…””}”(hhh!jºubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j¶ubhŒÎ: This applies errata 1165522 workaround to all revisions of Cortex-A76 CPU. This errata is fixed in r3p0 but due to limitation of errata framework this errata is applied to all revisions of Cortex-A76 CPU.”…””}”(hŒÎ: This applies errata 1165522 workaround to all revisions of Cortex-A76 CPU. This errata is fixed in r3p0 but due to limitation of errata framework this errata is applied to all revisions of Cortex-A76 CPU.”h!j¶ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKôh!j²ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jwhhhAj¡hCNubj×)”}”(hŒ‘``ERRATA_A76_1868343``: This applies errata 1868343 workaround to Cortex-A76 CPU. This needs to be enabled only for revision <= r4p0 of the CPU. ”h]”j£)”}”(hŒ``ERRATA_A76_1868343``: This applies errata 1868343 workaround to Cortex-A76 CPU. This needs to be enabled only for revision <= r4p0 of the CPU.”h]”(já)”}”(hŒ``ERRATA_A76_1868343``”h]”hŒERRATA_A76_1868343”…””}”(hhh!jáubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jÝubhŒz: This applies errata 1868343 workaround to Cortex-A76 CPU. This needs to be enabled only for revision <= r4p0 of the CPU.”…””}”(hŒz: This applies errata 1868343 workaround to Cortex-A76 CPU. This needs to be enabled only for revision <= r4p0 of the CPU.”h!jÝubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKùh!jÙubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jwhhhAj¡hCNubj×)”}”(hŒ–``ERRATA_A76_1946160``: This applies errata 1946160 workaround to Cortex-A76 CPU. This needs to be enabled only for revisions r3p0 - r4p1 of the CPU. ”h]”j£)”}”(hŒ•``ERRATA_A76_1946160``: This applies errata 1946160 workaround to Cortex-A76 CPU. This needs to be enabled only for revisions r3p0 - r4p1 of the CPU.”h]”(já)”}”(hŒ``ERRATA_A76_1946160``”h]”hŒERRATA_A76_1946160”…””}”(hhh!jubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jubhŒ: This applies errata 1946160 workaround to Cortex-A76 CPU. This needs to be enabled only for revisions r3p0 - r4p1 of the CPU.”…””}”(hŒ: This applies errata 1946160 workaround to Cortex-A76 CPU. This needs to be enabled only for revisions r3p0 - r4p1 of the CPU.”h!jubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKüh!jubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jwhhhAj¡hCNubeh"}”(h$]”h&]”h+]”h-]”h/]”jšj›uh1jÑhAj¡hCKÜh!j²hhubj£)”}”(hŒ>For Cortex-A77, the following errata build flags are defined :”h]”hŒ>For Cortex-A77, the following errata build flags are defined :”…””}”(hj/h!j-hhhANhCNubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKÿh!j²hhubjÒ)”}”(hhh]”(j×)”}”(hŒ‘``ERRATA_A77_1508412``: This applies errata 1508412 workaround to Cortex-A77 CPU. This needs to be enabled only for revision <= r1p0 of the CPU. ”h]”j£)”}”(hŒ``ERRATA_A77_1508412``: This applies errata 1508412 workaround to Cortex-A77 CPU. This needs to be enabled only for revision <= r1p0 of the CPU.”h]”(já)”}”(hŒ``ERRATA_A77_1508412``”h]”hŒERRATA_A77_1508412”…””}”(hhh!jFubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jBubhŒz: This applies errata 1508412 workaround to Cortex-A77 CPU. This needs to be enabled only for revision <= r1p0 of the CPU.”…””}”(hŒz: This applies errata 1508412 workaround to Cortex-A77 CPU. This needs to be enabled only for revision <= r1p0 of the CPU.”h!jBubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMh!j>ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!j;hhhAj¡hCNubj×)”}”(hŒ‘``ERRATA_A77_1925769``: This applies errata 1925769 workaround to Cortex-A77 CPU. This needs to be enabled only for revision <= r1p1 of the CPU. ”h]”j£)”}”(hŒ``ERRATA_A77_1925769``: This applies errata 1925769 workaround to Cortex-A77 CPU. This needs to be enabled only for revision <= r1p1 of the CPU.”h]”(já)”}”(hŒ``ERRATA_A77_1925769``”h]”hŒERRATA_A77_1925769”…””}”(hhh!jmubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jiubhŒz: This applies errata 1925769 workaround to Cortex-A77 CPU. This needs to be enabled only for revision <= r1p1 of the CPU.”…””}”(hŒz: This applies errata 1925769 workaround to Cortex-A77 CPU. This needs to be enabled only for revision <= r1p1 of the CPU.”h!jiubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMh!jeubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!j;hhhAj¡hCNubj×)”}”(hŒ‘``ERRATA_A77_1946167``: This applies errata 1946167 workaround to Cortex-A77 CPU. This needs to be enabled only for revision <= r1p1 of the CPU. ”h]”j£)”}”(hŒ``ERRATA_A77_1946167``: This applies errata 1946167 workaround to Cortex-A77 CPU. This needs to be enabled only for revision <= r1p1 of the CPU.”h]”(já)”}”(hŒ``ERRATA_A77_1946167``”h]”hŒERRATA_A77_1946167”…””}”(hhh!j”ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jubhŒz: This applies errata 1946167 workaround to Cortex-A77 CPU. This needs to be enabled only for revision <= r1p1 of the CPU.”…””}”(hŒz: This applies errata 1946167 workaround to Cortex-A77 CPU. This needs to be enabled only for revision <= r1p1 of the CPU.”h!jubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMh!jŒubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!j;hhhAj¡hCNubj×)”}”(hŒ—``ERRATA_A77_1791578``: This applies errata 1791578 workaround to Cortex-A77 CPU. This needs to be enabled for r0p0, r1p0, and r1p1, it is still open. ”h]”j£)”}”(hŒ–``ERRATA_A77_1791578``: This applies errata 1791578 workaround to Cortex-A77 CPU. This needs to be enabled for r0p0, r1p0, and r1p1, it is still open.”h]”(já)”}”(hŒ``ERRATA_A77_1791578``”h]”hŒERRATA_A77_1791578”…””}”(hhh!j»ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j·ubhŒ€: This applies errata 1791578 workaround to Cortex-A77 CPU. This needs to be enabled for r0p0, r1p0, and r1p1, it is still open.”…””}”(hŒ€: This applies errata 1791578 workaround to Cortex-A77 CPU. This needs to be enabled for r0p0, r1p0, and r1p1, it is still open.”h!j·ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCM h!j³ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!j;hhhAj¡hCNubeh"}”(h$]”h&]”h+]”h-]”h/]”jšj›uh1jÑhAj¡hCMh!j²hhubj£)”}”(hŒ>For Cortex-A78, the following errata build flags are defined :”h]”hŒ>For Cortex-A78, the following errata build flags are defined :”…””}”(hjâh!jàhhhANhCNubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCM h!j²hhubjÒ)”}”(hhh]”(j×)”}”(hŒ•``ERRATA_A78_1688305``: This applies errata 1688305 workaround to Cortex-A78 CPU. This needs to be enabled only for revision r0p0 - r1p0 of the CPU. ”h]”j£)”}”(hŒ”``ERRATA_A78_1688305``: This applies errata 1688305 workaround to Cortex-A78 CPU. This needs to be enabled only for revision r0p0 - r1p0 of the CPU.”h]”(já)”}”(hŒ``ERRATA_A78_1688305``”h]”hŒERRATA_A78_1688305”…””}”(hhh!jùubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jõubhŒ~: This applies errata 1688305 workaround to Cortex-A78 CPU. This needs to be enabled only for revision r0p0 - r1p0 of the CPU.”…””}”(hŒ~: This applies errata 1688305 workaround to Cortex-A78 CPU. This needs to be enabled only for revision r0p0 - r1p0 of the CPU.”h!jõubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMh!jñubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jîhhhAj¡hCNubj×)”}”(hŒš``ERRATA_A78_1941498``: This applies errata 1941498 workaround to Cortex-A78 CPU. This needs to be enabled for revisions r0p0, r1p0, and r1p1 of the CPU. ”h]”j£)”}”(hŒ™``ERRATA_A78_1941498``: This applies errata 1941498 workaround to Cortex-A78 CPU. This needs to be enabled for revisions r0p0, r1p0, and r1p1 of the CPU.”h]”(já)”}”(hŒ``ERRATA_A78_1941498``”h]”hŒERRATA_A78_1941498”…””}”(hhh!j ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jubhŒƒ: This applies errata 1941498 workaround to Cortex-A78 CPU. This needs to be enabled for revisions r0p0, r1p0, and r1p1 of the CPU.”…””}”(hŒƒ: This applies errata 1941498 workaround to Cortex-A78 CPU. This needs to be enabled for revisions r0p0, r1p0, and r1p1 of the CPU.”h!jubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMh!jubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jîhhhAj¡hCNubj×)”}”(hŒÎ``ERRATA_A78_1951500``: This applies errata 1951500 workaround to Cortex-A78 CPU. This needs to be enabled for revisions r1p0 and r1p1, r0p0 has the same issue but there is no workaround for that revision. ”h]”j£)”}”(hŒÍ``ERRATA_A78_1951500``: This applies errata 1951500 workaround to Cortex-A78 CPU. This needs to be enabled for revisions r1p0 and r1p1, r0p0 has the same issue but there is no workaround for that revision.”h]”(já)”}”(hŒ``ERRATA_A78_1951500``”h]”hŒERRATA_A78_1951500”…””}”(hhh!jGubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jCubhŒ·: This applies errata 1951500 workaround to Cortex-A78 CPU. This needs to be enabled for revisions r1p0 and r1p1, r0p0 has the same issue but there is no workaround for that revision.”…””}”(hŒ·: This applies errata 1951500 workaround to Cortex-A78 CPU. This needs to be enabled for revisions r1p0 and r1p1, r0p0 has the same issue but there is no workaround for that revision.”h!jCubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMh!j?ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jîhhhAj¡hCNubj×)”}”(hŒˆ``ERRATA_A78_1821534``: This applies errata 1821534 workaround to Cortex-A78 CPU. This needs to be enabled for revisions r0p0 and r1p0. ”h]”j£)”}”(hŒ‡``ERRATA_A78_1821534``: This applies errata 1821534 workaround to Cortex-A78 CPU. This needs to be enabled for revisions r0p0 and r1p0.”h]”(já)”}”(hŒ``ERRATA_A78_1821534``”h]”hŒERRATA_A78_1821534”…””}”(hhh!jnubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jjubhŒq: This applies errata 1821534 workaround to Cortex-A78 CPU. This needs to be enabled for revisions r0p0 and r1p0.”…””}”(hŒq: This applies errata 1821534 workaround to Cortex-A78 CPU. This needs to be enabled for revisions r0p0 and r1p0.”h!jjubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMh!jfubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jîhhhAj¡hCNubj×)”}”(hŒ“``ERRATA_A78_1952683``: This applies errata 1952683 workaround to Cortex-A78 CPU. This needs to be enabled for revision r0p0, it is fixed in r1p0. ”h]”j£)”}”(hŒ’``ERRATA_A78_1952683``: This applies errata 1952683 workaround to Cortex-A78 CPU. This needs to be enabled for revision r0p0, it is fixed in r1p0.”h]”(já)”}”(hŒ``ERRATA_A78_1952683``”h]”hŒERRATA_A78_1952683”…””}”(hhh!j•ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j‘ubhŒ|: This applies errata 1952683 workaround to Cortex-A78 CPU. This needs to be enabled for revision r0p0, it is fixed in r1p0.”…””}”(hŒ|: This applies errata 1952683 workaround to Cortex-A78 CPU. This needs to be enabled for revision r0p0, it is fixed in r1p0.”h!j‘ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMh!jubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jîhhhAj¡hCNubj×)”}”(hŒ§``ERRATA_A78_2132060``: This applies errata 2132060 workaround to Cortex-A78 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, and r1p2. It is still open. ”h]”j£)”}”(hŒ¦``ERRATA_A78_2132060``: This applies errata 2132060 workaround to Cortex-A78 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, and r1p2. It is still open.”h]”(já)”}”(hŒ``ERRATA_A78_2132060``”h]”hŒERRATA_A78_2132060”…””}”(hhh!j¼ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j¸ubhŒ: This applies errata 2132060 workaround to Cortex-A78 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, and r1p2. It is still open.”…””}”(hŒ: This applies errata 2132060 workaround to Cortex-A78 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, and r1p2. It is still open.”h!j¸ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMh!j´ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jîhhhAj¡hCNubj×)”}”(hŒÚ``ERRATA_A78_2242635``: This applies errata 2242635 workaround to Cortex-A78 CPU. This needs to be enabled for revisions r1p0, r1p1, and r1p2. The issue is present in r0p0 but there is no workaround. It is still open. ”h]”j£)”}”(hŒÙ``ERRATA_A78_2242635``: This applies errata 2242635 workaround to Cortex-A78 CPU. This needs to be enabled for revisions r1p0, r1p1, and r1p2. The issue is present in r0p0 but there is no workaround. It is still open.”h]”(já)”}”(hŒ``ERRATA_A78_2242635``”h]”hŒERRATA_A78_2242635”…””}”(hhh!jãubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jßubhŒÃ: This applies errata 2242635 workaround to Cortex-A78 CPU. This needs to be enabled for revisions r1p0, r1p1, and r1p2. The issue is present in r0p0 but there is no workaround. It is still open.”…””}”(hŒÃ: This applies errata 2242635 workaround to Cortex-A78 CPU. This needs to be enabled for revisions r1p0, r1p1, and r1p2. The issue is present in r0p0 but there is no workaround. It is still open.”h!jßubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCM#h!jÛubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jîhhhAj¡hCNubeh"}”(h$]”h&]”h+]”h-]”h/]”jšj›uh1jÑhAj¡hCMh!j²hhubj£)”}”(hŒAFor Cortex-A78 AE, the following errata build flags are defined :”h]”hŒAFor Cortex-A78 AE, the following errata build flags are defined :”…””}”(hj h!jhhhANhCNubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCM'h!j²hhubjÒ)”}”(hhh]”(j×)”}”(hŒ``ERRATA_A78_AE_1941500`` : This applies errata 1941500 workaround to Cortex-A78 AE CPU. This needs to be enabled for revisions r0p0 and r0p1. This erratum is still open. ”h]”j)”}”(hhh]”j)”}”(hŒ«``ERRATA_A78_AE_1941500`` : This applies errata 1941500 workaround to Cortex-A78 AE CPU. This needs to be enabled for revisions r0p0 and r0p1. This erratum is still open. ”h]”(j)”}”(hŒ``ERRATA_A78_AE_1941500``”h]”(já)”}”(hŒ``ERRATA_A78_AE_1941500``”h]”hŒERRATA_A78_AE_1941500”…””}”(hhh!j(ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j$ubhh…””}”(hhh!j$ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1jhAj¡hCM+h!j ubh Œ classifier”“”)”}”(hŒ4This applies errata 1941500 workaround to Cortex-A78”h]”hŒ4This applies errata 1941500 workaround to Cortex-A78”…””}”(hhh!jAubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j?h!j hAj¡ubj9)”}”(hhh]”j£)”}”(hŒYAE CPU. This needs to be enabled for revisions r0p0 and r0p1. This erratum is still open.”h]”hŒYAE CPU. This needs to be enabled for revisions r0p0 and r0p1. This erratum is still open.”…””}”(hjTh!jRubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCM*h!jOubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j8h!j ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1jhAj¡hCM+h!jubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jhhhANhCNubj×)”}”(hŒ«``ERRATA_A78_AE_1951502`` : This applies errata 1951502 workaround to Cortex-A78 AE CPU. This needs to be enabled for revisions r0p0 and r0p1. This erratum is still open. ”h]”j£)”}”(hŒª``ERRATA_A78_AE_1951502`` : This applies errata 1951502 workaround to Cortex-A78 AE CPU. This needs to be enabled for revisions r0p0 and r0p1. This erratum is still open.”h]”(já)”}”(hŒ``ERRATA_A78_AE_1951502``”h]”hŒERRATA_A78_AE_1951502”…””}”(hhh!j€ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j|ubhŒ‘ : This applies errata 1951502 workaround to Cortex-A78 AE CPU. This needs to be enabled for revisions r0p0 and r0p1. This erratum is still open.”…””}”(hŒ‘ : This applies errata 1951502 workaround to Cortex-A78 AE CPU. This needs to be enabled for revisions r0p0 and r0p1. This erratum is still open.”h!j|ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCM-h!jxubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jhhhAj¡hCNubeh"}”(h$]”h&]”h+]”h-]”h/]”jšj›uh1jÑhAj¡hCM)h!j²hhubj£)”}”(hŒ?For Neoverse N1, the following errata build flags are defined :”h]”hŒ?For Neoverse N1, the following errata build flags are defined :”…””}”(hj§h!j¥hhhANhCNubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCM1h!j²hhubjÒ)”}”(hhh]”(j×)”}”(hŒ—``ERRATA_N1_1073348``: This applies errata 1073348 workaround to Neoverse-N1 CPU. This needs to be enabled only for revision r0p0 and r1p0 of the CPU. ”h]”j£)”}”(hŒ–``ERRATA_N1_1073348``: This applies errata 1073348 workaround to Neoverse-N1 CPU. This needs to be enabled only for revision r0p0 and r1p0 of the CPU.”h]”(já)”}”(hŒ``ERRATA_N1_1073348``”h]”hŒERRATA_N1_1073348”…””}”(hhh!j¾ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jºubhŒ: This applies errata 1073348 workaround to Neoverse-N1 CPU. This needs to be enabled only for revision r0p0 and r1p0 of the CPU.”…””}”(hŒ: This applies errata 1073348 workaround to Neoverse-N1 CPU. This needs to be enabled only for revision r0p0 and r1p0 of the CPU.”h!jºubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCM3h!j¶ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!j³hhhAj¡hCNubj×)”}”(hŒ‘``ERRATA_N1_1130799``: This applies errata 1130799 workaround to Neoverse-N1 CPU. This needs to be enabled only for revision <= r2p0 of the CPU. ”h]”j£)”}”(hŒ``ERRATA_N1_1130799``: This applies errata 1130799 workaround to Neoverse-N1 CPU. This needs to be enabled only for revision <= r2p0 of the CPU.”h]”(já)”}”(hŒ``ERRATA_N1_1130799``”h]”hŒERRATA_N1_1130799”…””}”(hhh!jåubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jáubhŒ{: This applies errata 1130799 workaround to Neoverse-N1 CPU. This needs to be enabled only for revision <= r2p0 of the CPU.”…””}”(hŒ{: This applies errata 1130799 workaround to Neoverse-N1 CPU. This needs to be enabled only for revision <= r2p0 of the CPU.”h!jáubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCM6h!jÝubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!j³hhhAj¡hCNubj×)”}”(hŒ‘``ERRATA_N1_1165347``: This applies errata 1165347 workaround to Neoverse-N1 CPU. This needs to be enabled only for revision <= r2p0 of the CPU. ”h]”j£)”}”(hŒ``ERRATA_N1_1165347``: This applies errata 1165347 workaround to Neoverse-N1 CPU. This needs to be enabled only for revision <= r2p0 of the CPU.”h]”(já)”}”(hŒ``ERRATA_N1_1165347``”h]”hŒERRATA_N1_1165347”…””}”(hhh!jubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jubhŒ{: This applies errata 1165347 workaround to Neoverse-N1 CPU. This needs to be enabled only for revision <= r2p0 of the CPU.”…””}”(hŒ{: This applies errata 1165347 workaround to Neoverse-N1 CPU. This needs to be enabled only for revision <= r2p0 of the CPU.”h!jubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCM9h!jubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!j³hhhAj¡hCNubj×)”}”(hŒ‘``ERRATA_N1_1207823``: This applies errata 1207823 workaround to Neoverse-N1 CPU. This needs to be enabled only for revision <= r2p0 of the CPU. ”h]”j£)”}”(hŒ``ERRATA_N1_1207823``: This applies errata 1207823 workaround to Neoverse-N1 CPU. This needs to be enabled only for revision <= r2p0 of the CPU.”h]”(já)”}”(hŒ``ERRATA_N1_1207823``”h]”hŒERRATA_N1_1207823”…””}”(hhh!j3ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j/ubhŒ{: This applies errata 1207823 workaround to Neoverse-N1 CPU. This needs to be enabled only for revision <= r2p0 of the CPU.”…””}”(hŒ{: This applies errata 1207823 workaround to Neoverse-N1 CPU. This needs to be enabled only for revision <= r2p0 of the CPU.”h!j/ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!j;hhhAj¡hCNubj×)”}”(hŒ²``ERRATA_A710_2081180``: This applies errata 2081180 workaround to Cortex-A710 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r2p0 of the CPU. It is still open. ”h]”j£)”}”(hŒ±``ERRATA_A710_2081180``: This applies errata 2081180 workaround to Cortex-A710 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r2p0 of the CPU. It is still open.”h]”(já)”}”(hŒ``ERRATA_A710_2081180``”h]”hŒERRATA_A710_2081180”…””}”(hhh!jmubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jiubhŒš: This applies errata 2081180 workaround to Cortex-A710 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r2p0 of the CPU. It is still open.”…””}”(hŒš: This applies errata 2081180 workaround to Cortex-A710 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r2p0 of the CPU. It is still open.”h!jiubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMˆh!jeubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!j;hhhAj¡hCNubj×)”}”(hŒ¤``ERRATA_A710_2055002``: This applies errata 2055002 workaround to Cortex-A710 CPU. This needs to be enabled for revisions r1p0, r2p0 of the CPU and is still open. ”h]”j£)”}”(hŒ£``ERRATA_A710_2055002``: This applies errata 2055002 workaround to Cortex-A710 CPU. This needs to be enabled for revisions r1p0, r2p0 of the CPU and is still open.”h]”(já)”}”(hŒ``ERRATA_A710_2055002``”h]”hŒERRATA_A710_2055002”…””}”(hhh!j”ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jubhŒŒ: This applies errata 2055002 workaround to Cortex-A710 CPU. This needs to be enabled for revisions r1p0, r2p0 of the CPU and is still open.”…””}”(hŒŒ: This applies errata 2055002 workaround to Cortex-A710 CPU. This needs to be enabled for revisions r1p0, r2p0 of the CPU and is still open.”h!jubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMŒh!jŒubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!j;hhhAj¡hCNubj×)”}”(hŒ``ERRATA_A710_2017096``: This applies errata 2017096 workaround to Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 of the CPU and is still open. ”h]”j£)”}”(hŒ¬``ERRATA_A710_2017096``: This applies errata 2017096 workaround to Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 of the CPU and is still open.”h]”(já)”}”(hŒ``ERRATA_A710_2017096``”h]”hŒERRATA_A710_2017096”…””}”(hhh!j»ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j·ubhŒ•: This applies errata 2017096 workaround to Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 of the CPU and is still open.”…””}”(hŒ•: This applies errata 2017096 workaround to Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 of the CPU and is still open.”h!j·ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMh!j³ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!j;hhhAj¡hCNubj×)”}”(hŒ``ERRATA_A710_2083908``: This applies errata 2083908 workaround to Cortex-A710 CPU. This needs to be enabled for revision r2p0 of the CPU and is still open. ”h]”j£)”}”(hŒœ``ERRATA_A710_2083908``: This applies errata 2083908 workaround to Cortex-A710 CPU. This needs to be enabled for revision r2p0 of the CPU and is still open.”h]”(já)”}”(hŒ``ERRATA_A710_2083908``”h]”hŒERRATA_A710_2083908”…””}”(hhh!jâubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jÞubhŒ…: This applies errata 2083908 workaround to Cortex-A710 CPU. This needs to be enabled for revision r2p0 of the CPU and is still open.”…””}”(hŒ…: This applies errata 2083908 workaround to Cortex-A710 CPU. This needs to be enabled for revision r2p0 of the CPU and is still open.”h!jÞubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCM”h!jÚubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!j;hhhAj¡hCNubj×)”}”(hŒ``ERRATA_A710_2058056``: This applies errata 2058056 workaround to Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 of the CPU and is still open. ”h]”j£)”}”(hŒ¬``ERRATA_A710_2058056``: This applies errata 2058056 workaround to Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 of the CPU and is still open.”h]”(já)”}”(hŒ``ERRATA_A710_2058056``”h]”hŒERRATA_A710_2058056”…””}”(hhh!j ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jubhŒ•: This applies errata 2058056 workaround to Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 of the CPU and is still open.”…””}”(hŒ•: This applies errata 2058056 workaround to Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 of the CPU and is still open.”h!jubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCM˜h!jubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!j;hhhAj¡hCNubeh"}”(h$]”h&]”h+]”h-]”h/]”jšj›uh1jÑhAj¡hCM„h!j²hhubj£)”}”(hŒ?For Neoverse N2, the following errata build flags are defined :”h]”hŒ?For Neoverse N2, the following errata build flags are defined :”…””}”(hj0h!j.hhhANhCNubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMœh!j²hhubjÒ)”}”(hhh]”(j×)”}”(hŒ›``ERRATA_N2_2002655``: This applies errata 2002655 workaround to Neoverse-N2 CPU. This needs to be enabled for revision r0p0 of the CPU, it is still open. ”h]”j£)”}”(hŒš``ERRATA_N2_2002655``: This applies errata 2002655 workaround to Neoverse-N2 CPU. This needs to be enabled for revision r0p0 of the CPU, it is still open.”h]”(já)”}”(hŒ``ERRATA_N2_2002655``”h]”hŒERRATA_N2_2002655”…””}”(hhh!jGubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jCubhŒ…: This applies errata 2002655 workaround to Neoverse-N2 CPU. This needs to be enabled for revision r0p0 of the CPU, it is still open.”…””}”(hŒ…: This applies errata 2002655 workaround to Neoverse-N2 CPU. This needs to be enabled for revision r0p0 of the CPU, it is still open.”h!jCubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMžh!j?ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!j<hhhAj¡hCNubj×)”}”(hŒ›``ERRATA_N2_2067956``: This applies errata 2067956 workaround to Neoverse-N2 CPU. This needs to be enabled for revision r0p0 of the CPU and is still open. ”h]”j£)”}”(hŒš``ERRATA_N2_2067956``: This applies errata 2067956 workaround to Neoverse-N2 CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.”h]”(já)”}”(hŒ``ERRATA_N2_2067956``”h]”hŒERRATA_N2_2067956”…””}”(hhh!jnubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jjubhŒ…: This applies errata 2067956 workaround to Neoverse-N2 CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.”…””}”(hŒ…: This applies errata 2067956 workaround to Neoverse-N2 CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.”h!jjubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCM¡h!jfubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!j<hhhAj¡hCNubj×)”}”(hŒ›``ERRATA_N2_2025414``: This applies errata 2025414 workaround to Neoverse-N2 CPU. This needs to be enabled for revision r0p0 of the CPU and is still open. ”h]”j£)”}”(hŒš``ERRATA_N2_2025414``: This applies errata 2025414 workaround to Neoverse-N2 CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.”h]”(já)”}”(hŒ``ERRATA_N2_2025414``”h]”hŒERRATA_N2_2025414”…””}”(hhh!j•ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j‘ubhŒ…: This applies errata 2025414 workaround to Neoverse-N2 CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.”…””}”(hŒ…: This applies errata 2025414 workaround to Neoverse-N2 CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.”h!j‘ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCM¤h!jubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!j<hhhAj¡hCNubj×)”}”(hŒ›``ERRATA_N2_2189731``: This applies errata 2189731 workaround to Neoverse-N2 CPU. This needs to be enabled for revision r0p0 of the CPU and is still open. ”h]”j£)”}”(hŒš``ERRATA_N2_2189731``: This applies errata 2189731 workaround to Neoverse-N2 CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.”h]”(já)”}”(hŒ``ERRATA_N2_2189731``”h]”hŒERRATA_N2_2189731”…””}”(hhh!j¼ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j¸ubhŒ…: This applies errata 2189731 workaround to Neoverse-N2 CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.”…””}”(hŒ…: This applies errata 2189731 workaround to Neoverse-N2 CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.”h!j¸ube•—th"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCM§h!j´ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!j<hhhAj¡hCNubj×)”}”(hŒ›``ERRATA_N2_2138956``: This applies errata 2138956 workaround to Neoverse-N2 CPU. This needs to be enabled for revision r0p0 of the CPU and is still open. ”h]”j£)”}”(hŒš``ERRATA_N2_2138956``: This applies errata 2138956 workaround to Neoverse-N2 CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.”h]”(já)”}”(hŒ``ERRATA_N2_2138956``”h]”hŒERRATA_N2_2138956”…””}”(hhh!jãubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jßubhŒ…: This applies errata 2138956 workaround to Neoverse-N2 CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.”…””}”(hŒ…: This applies errata 2138956 workaround to Neoverse-N2 CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.”h!jßubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMªh!jÛubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!j<hhhAj¡hCNubj×)”}”(hŒ›``ERRATA_N2_2138953``: This applies errata 2138953 workaround to Neoverse-N2 CPU. This needs to be enabled for revision r0p0 of the CPU and is still open. ”h]”j£)”}”(hŒš``ERRATA_N2_2138953``: This applies errata 2138953 workaround to Neoverse-N2 CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.”h]”(já)”}”(hŒ``ERRATA_N2_2138953``”h]”hŒERRATA_N2_2138953”…””}”(hhh!j ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jubhŒ…: This applies errata 2138953 workaround to Neoverse-N2 CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.”…””}”(hŒ…: This applies errata 2138953 workaround to Neoverse-N2 CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.”h!jubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMh!jubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!j<hhhAj¡hCNubj×)”}”(hŒ›``ERRATA_N2_2242415``: This applies errata 2242415 workaround to Neoverse-N2 CPU. This needs to be enabled for revision r0p0 of the CPU and is still open. ”h]”j£)”}”(hŒš``ERRATA_N2_2242415``: This applies errata 2242415 workaround to Neoverse-N2 CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.”h]”(já)”}”(hŒ``ERRATA_N2_2242415``”h]”hŒERRATA_N2_2242415”…””}”(hhh!j1ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j-ubhŒ…: This applies errata 2242415 workaround to Neoverse-N2 CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.”…””}”(hŒ…: This applies errata 2242415 workaround to Neoverse-N2 CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.”h!j-ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCM°h!j)ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!j<hhhAj¡hCNubj×)”}”(hŒ›``ERRATA_N2_2138958``: This applies errata 2138958 workaround to Neoverse-N2 CPU. This needs to be enabled for revision r0p0 of the CPU and is still open. ”h]”j£)”}”(hŒš``ERRATA_N2_2138958``: This applies errata 2138958 workaround to Neoverse-N2 CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.”h]”(já)”}”(hŒ``ERRATA_N2_2138958``”h]”hŒERRATA_N2_2138958”…””}”(hhh!jXubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jTubhŒ…: This applies errata 2138958 workaround to Neoverse-N2 CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.”…””}”(hŒ…: This applies errata 2138958 workaround to Neoverse-N2 CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.”h!jTubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCM³h!jPubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!j<hhhAj¡hCNubj×)”}”(hŒ›``ERRATA_N2_2242400``: This applies errata 2242400 workaround to Neoverse-N2 CPU. This needs to be enabled for revision r0p0 of the CPU and is still open. ”h]”j£)”}”(hŒš``ERRATA_N2_2242400``: This applies errata 2242400 workaround to Neoverse-N2 CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.”h]”(já)”}”(hŒ``ERRATA_N2_2242400``”h]”hŒERRATA_N2_2242400”…””}”(hhh!jubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j{ubhŒ…: This applies errata 2242400 workaround to Neoverse-N2 CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.”…””}”(hŒ…: This applies errata 2242400 workaround to Neoverse-N2 CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.”h!j{ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCM¶h!jwubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!j<hhhAj¡hCNubj×)”}”(hŒ›``ERRATA_N2_2280757``: This applies errata 2280757 workaround to Neoverse-N2 CPU. This needs to be enabled for revision r0p0 of the CPU and is still open. ”h]”j£)”}”(hŒš``ERRATA_N2_2280757``: This applies errata 2280757 workaround to Neoverse-N2 CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.”h]”(já)”}”(hŒ``ERRATA_N2_2280757``”h]”hŒERRATA_N2_2280757”…””}”(hhh!j¦ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j¢ubhŒ…: This applies errata 2280757 workaround to Neoverse-N2 CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.”…””}”(hŒ…: This applies errata 2280757 workaround to Neoverse-N2 CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.”h!j¢ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCM¹h!jžubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!j<hhhAj¡hCNubeh"}”(h$]”h&]”h+]”h-]”h/]”jšj›uh1jÑhAj¡hCMžh!j²hhubeh"}”(h$]”(Œcpu-errata-workarounds”j©eh&]”h+]”(Œcpu errata workarounds”Œ!arm_cpu_macros_errata_workarounds”eh-]”h/]”uh1jŒh!jŽhhhAj¡hCK#Œexpect_referenced_by_name”}”jÑjžsŒexpect_referenced_by_id”}”j©jžsŒ referenced”Kubj)”}”(hhh]”(j’)”}”(hŒDSU Errata Workarounds”h]”hŒDSU Errata Workarounds”…””}”(hjÞh!jÜhhhANhCNubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j‘h!jÙhhhAj¡hCM½ubj£)”}”(hŒ¦Similar to CPU errata, TF-A also implements workarounds for DSU (DynamIQ Shared Unit) errata. The DSU errata details can be found in the respective Arm documentation:”h]”hŒ¦Similar to CPU errata, TF-A also implements workarounds for DSU (DynamIQ Shared Unit) errata. The DSU errata details can be found in the respective Arm documentation:”…””}”(hjìh!jêhhhANhCNubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCM¿h!jÙhhubjÒ)”}”(hhh]”j×)”}”(hŒ.`Arm DSU Software Developers Errata Notice`_. ”h]”j£)”}”(hŒ-`Arm DSU Software Developers Errata Notice`_.”h]”(jö)”}”(hŒ,`Arm DSU Software Developers Errata Notice`_”h]”hŒ)Arm DSU Software Developers Errata Notice”…””}”(hŒ)Arm DSU Software Developers Errata Notice”h!j ubah"}”(h$]”h&]”h+]”h-]”h/]”Œname”Œ)Arm DSU Software Developers Errata Notice”jŒEhttp://infocenter.arm.com/help/topic/com.arm.doc.epm138168/index.html”uh1jõh!jÿj KubhŒ.”…””}”(hŒ.”h!jÿubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMÃh!jûubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jøhhhAj¡hCNubah"}”(h$]”h&]”h+]”h-]”h/]”jšj›uh1jÑhAj¡hCMÃh!jÙhhubj£)”}”(hX*Each erratum is identified by an ``ID``, as defined in the DSU errata notice document. Thus, the build flags which enable/disable the errata workarounds have the format ``ERRATA_DSU_``. The implementation and application logic of DSU errata workarounds are similar to `CPU errata workarounds`_.”h]”(hŒ!Each erratum is identified by an ”…””}”(hŒ!Each erratum is identified by an ”h!j, hhhANhCNubjá)”}”(hŒ``ID``”h]”hŒID”…””}”(hhh!j5 ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j, ubhŒ‚, as defined in the DSU errata notice document. Thus, the build flags which enable/disable the errata workarounds have the format ”…””}”(hŒ‚, as defined in the DSU errata notice document. Thus, the build flags which enable/disable the errata workarounds have the format ”h!j, hhhANhCNubjá)”}”(hŒ``ERRATA_DSU_``”h]”hŒERRATA_DSU_”…””}”(hhh!jH ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j, ubhŒT. The implementation and application logic of DSU errata workarounds are similar to ”…””}”(hŒT. The implementation and application logic of DSU errata workarounds are similar to ”h!j, hhhANhCNubjö)”}”(hŒ`CPU errata workarounds`_”h]”hŒCPU errata workarounds”…””}”(hŒCPU errata workarounds”h!j[ ubah"}”(h$]”h&]”h+]”h-]”h/]”Œname”ŒCPU errata workarounds”j¨jÍuh1jõh!j, j KubhŒ.”…””}”(hj h!j, hhhANhCNubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMÅh!jÙhhubj£)”}”(hŒ6For DSU errata, the following build flags are defined:”h]”hŒ6For DSU errata, the following build flags are defined:”…””}”(hjx h!jv hhhANhCNubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMÊh!jÙhhubjÒ)”}”(hhh]”(j×)”}”(hX``ERRATA_DSU_798953``: This applies errata 798953 workaround for the affected DSU configurations. This errata applies only for those DSUs that revision is r0p0 (on r0p1 it is fixed). However, please note that this workaround results in increased DSU power consumption on idle. ”h]”j£)”}”(hX``ERRATA_DSU_798953``: This applies errata 798953 workaround for the affected DSU configurations. This errata applies only for those DSUs that revision is r0p0 (on r0p1 it is fixed). However, please note that this workaround results in increased DSU power consumption on idle.”h]”(já)”}”(hŒ``ERRATA_DSU_798953``”h]”hŒERRATA_DSU_798953”…””}”(hhh!j ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j‹ ubhŒÿ: This applies errata 798953 workaround for the affected DSU configurations. This errata applies only for those DSUs that revision is r0p0 (on r0p1 it is fixed). However, please note that this workaround results in increased DSU power consumption on idle.”…””}”(hŒÿ: This applies errata 798953 workaround for the affected DSU configurations. This errata applies only for those DSUs that revision is r0p0 (on r0p1 it is fixed). However, please note that this workaround results in increased DSU power consumption on idle.”h!j‹ ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMÌh!j‡ ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!j„ hhhAj¡hCNubj×)”}”(hXJ``ERRATA_DSU_936184``: This applies errata 936184 workaround for the affected DSU configurations. This errata applies only for those DSUs that contain the ACP interface **and** the DSU revision is older than r2p0 (on r2p0 it is fixed). However, please note that this workaround results in increased DSU power consumption on idle. ”h]”j£)”}”(hXI``ERRATA_DSU_936184``: This applies errata 936184 workaround for the affected DSU configurations. This errata applies only for those DSUs that contain the ACP interface **and** the DSU revision is older than r2p0 (on r2p0 it is fixed). However, please note that this workaround results in increased DSU power consumption on idle.”h]”(já)”}”(hŒ``ERRATA_DSU_936184``”h]”hŒERRATA_DSU_936184”…””}”(hhh!j¶ ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j² ubhŒ”: This applies errata 936184 workaround for the affected DSU configurations. This errata applies only for those DSUs that contain the ACP interface ”…””}”(hŒ”: This applies errata 936184 workaround for the affected DSU configurations. This errata applies only for those DSUs that contain the ACP interface ”h!j² ubh Œstrong”“”)”}”(hŒ**and**”h]”hŒand”…””}”(hhh!jË ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÉ h!j² ubhŒ™ the DSU revision is older than r2p0 (on r2p0 it is fixed). However, please note that this workaround results in increased DSU power consumption on idle.”…””}”(hŒ™ the DSU revision is older than r2p0 (on r2p0 it is fixed). However, please note that this workaround results in increased DSU power consumption on idle.”h!j² ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMÑh!j® ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!j„ hhhAj¡hCNubeh"}”(h$]”h&]”h+]”h-]”h/]”jšj›uh1jÑhAj¡hCMÌh!jÙhhubeh"}”(h$]”Œdsu-errata-workarounds”ah&]”h+]”Œdsu errata workarounds”ah-]”h/]”uh1jŒh!jŽhhhAj¡hCM½ubj)”}”(hhh]”(j’)”}”(hŒCPU Specific optimizations”h]”hŒCPU Specific optimizations”…””}”(hjý h!jû hhhANhCNubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j‘h!jø hhhAj¡hCMØubj£)”}”(hŒ†This section describes some of the optimizations allowed by the CPU micro architecture that can be enabled by the platform as desired.”h]”hŒ†This section describes some of the optimizations allowed by the CPU micro architecture that can be enabled by the platform as desired.”…””}”(hj!h!j !hhhANhCNubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMÚh!jø hhubjÒ)”}”(hhh]”(j×)”}”(hXÍ``SKIP_A57_L1_FLUSH_PWR_DWN``: This flag enables an optimization in the Cortex-A57 cluster power down sequence by not flushing the Level 1 data cache. The L1 data cache and the L2 unified cache are inclusive. A flush of the L2 by set/way flushes any dirty lines from the L1 as well. This is a known safe deviation from the Cortex-A57 TRM defined power down sequence. Each Cortex-A57 based platform must make its own decision on whether to use the optimization. ”h]”j£)”}”(hXÌ``SKIP_A57_L1_FLUSH_PWR_DWN``: This flag enables an optimization in the Cortex-A57 cluster power down sequence by not flushing the Level 1 data cache. The L1 data cache and the L2 unified cache are inclusive. A flush of the L2 by set/way flushes any dirty lines from the L1 as well. This is a known safe deviation from the Cortex-A57 TRM defined power down sequence. Each Cortex-A57 based platform must make its own decision on whether to use the optimization.”h]”(já)”}”(hŒ``SKIP_A57_L1_FLUSH_PWR_DWN``”h]”hŒSKIP_A57_L1_FLUSH_PWR_DWN”…””}”(hhh!j"!ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j!ubhX¯: This flag enables an optimization in the Cortex-A57 cluster power down sequence by not flushing the Level 1 data cache. The L1 data cache and the L2 unified cache are inclusive. A flush of the L2 by set/way flushes any dirty lines from the L1 as well. This is a known safe deviation from the Cortex-A57 TRM defined power down sequence. Each Cortex-A57 based platform must make its own decision on whether to use the optimization.”…””}”(hX¯: This flag enables an optimization in the Cortex-A57 cluster power down sequence by not flushing the Level 1 data cache. The L1 data cache and the L2 unified cache are inclusive. A flush of the L2 by set/way flushes any dirty lines from the L1 as well. This is a known safe deviation from the Cortex-A57 TRM defined power down sequence. Each Cortex-A57 based platform must make its own decision on whether to use the optimization.”h!j!ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMÝh!j!ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!j!hhhAj¡hCNubj×)”}”(hX5``A53_DISABLE_NON_TEMPORAL_HINT``: This flag disables the cache non-temporal hint. The LDNP/STNP instructions as implemented on Cortex-A53 do not behave in a way most programmers expect, and will most probably result in a significant speed degradation to any code that employs them. The Armv8-A architecture (see Arm DDI 0487A.h, section D3.4.3) allows cores to ignore the non-temporal hint and treat LDNP/STNP as LDP/STP instead. Enabling this flag enforces this behaviour. This needs to be enabled only for revisions <= r0p3 of the CPU and is enabled by default. ”h]”j£)”}”(hX4``A53_DISABLE_NON_TEMPORAL_HINT``: This flag disables the cache non-temporal hint. The LDNP/STNP instructions as implemented on Cortex-A53 do not behave in a way most programmers expect, and will most probably result in a significant speed degradation to any code that employs them. The Armv8-A architecture (see Arm DDI 0487A.h, section D3.4.3) allows cores to ignore the non-temporal hint and treat LDNP/STNP as LDP/STP instead. Enabling this flag enforces this behaviour. This needs to be enabled only for revisions <= r0p3 of the CPU and is enabled by default.”h]”(já)”}”(hŒ!``A53_DISABLE_NON_TEMPORAL_HINT``”h]”hŒA53_DISABLE_NON_TEMPORAL_HINT”…””}”(hhh!jI!ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jE!ubhX: This flag disables the cache non-temporal hint. The LDNP/STNP instructions as implemented on Cortex-A53 do not behave in a way most programmers expect, and will most probably result in a significant speed degradation to any code that employs them. The Armv8-A architecture (see Arm DDI 0487A.h, section D3.4.3) allows cores to ignore the non-temporal hint and treat LDNP/STNP as LDP/STP instead. Enabling this flag enforces this behaviour. This needs to be enabled only for revisions <= r0p3 of the CPU and is enabled by default.”…””}”(hX: This flag disables the cache non-temporal hint. The LDNP/STNP instructions as implemented on Cortex-A53 do not behave in a way most programmers expect, and will most probably result in a significant speed degradation to any code that employs them. The Armv8-A architecture (see Arm DDI 0487A.h, section D3.4.3) allows cores to ignore the non-temporal hint and treat LDNP/STNP as LDP/STP instead. Enabling this flag enforces this behaviour. This needs to be enabled only for revisions <= r0p3 of the CPU and is enabled by default.”h!jE!ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMåh!jA!ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!j!hhhAj¡hCNubj×)”}”(hXC``A57_DISABLE_NON_TEMPORAL_HINT``: This flag has the same behaviour as ``A53_DISABLE_NON_TEMPORAL_HINT`` but for Cortex-A57. This needs to be enabled only for revisions <= r1p2 of the CPU and is enabled by default, as recommended in section "4.7 Non-Temporal Loads/Stores" of the `Cortex-A57 Software Optimization Guide`_. ”h]”j£)”}”(hXB``A57_DISABLE_NON_TEMPORAL_HINT``: This flag has the same behaviour as ``A53_DISABLE_NON_TEMPORAL_HINT`` but for Cortex-A57. This needs to be enabled only for revisions <= r1p2 of the CPU and is enabled by default, as recommended in section "4.7 Non-Temporal Loads/Stores" of the `Cortex-A57 Software Optimization Guide`_.”h]”(já)”}”(hŒ!``A57_DISABLE_NON_TEMPORAL_HINT``”h]”hŒA57_DISABLE_NON_TEMPORAL_HINT”…””}”(hhh!jp!ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jl!ubhŒ&: This flag has the same behaviour as ”…””}”(hŒ&: This flag has the same behaviour as ”h!jl!ubjá)”}”(hŒ!``A53_DISABLE_NON_TEMPORAL_HINT``”h]”hŒA53_DISABLE_NON_TEMPORAL_HINT”…””}”(hhh!jƒ!ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jl!ubhŒ´ but for Cortex-A57. This needs to be enabled only for revisions <= r1p2 of the CPU and is enabled by default, as recommended in section â€œ4.7 Non-Temporal Loads/Storesâ€ of the ”…””}”(hŒ° but for Cortex-A57. This needs to be enabled only for revisions <= r1p2 of the CPU and is enabled by default, as recommended in section "4.7 Non-Temporal Loads/Stores" of the ”h!jl!ubjö)”}”(hŒ)`Cortex-A57 Software Optimization Guide`_”h]”hŒ&Cortex-A57 Software Optimization Guide”…””}”(hŒ&Cortex-A57 Software Optimization Guide”h!j–!ubah"}”(h$]”h&]”h+]”h-]”h/]”Œname”Œ&Cortex-A57 Software Optimization Guide”jŒmhttp://infocenter.arm.com/help/topic/com.arm.doc.uan0015b/Cortex_A57_Software_Optimization_Guide_external.pdf”uh1jõh!jl!j KubhŒ.”…””}”(hj h!jl!ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMîh!jh!ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!j!hhhAj¡hCNubj×)”}”(hX”''A57_ENABLE_NON_CACHEABLE_LOAD_FWD'': This flag enables non-cacheable streaming enhancement feature for Cortex-A57 CPUs. Platforms can set this bit only if their memory system meets the requirement that cache line fill requests from the Cortex-A57 processor are atomic. Each Cortex-A57 based platform must make its own decision on whether to use the optimization. This flag is disabled by default. ”h]”j)”}”(hhh]”j)”}”(hX''A57_ENABLE_NON_CACHEABLE_LOAD_FWD'': This flag enables non-cacheable streaming enhancement feature for Cortex-A57 CPUs. Platforms can set this bit only if their memory system meets the requirement that cache line fill requests from the Cortex-A57 processor are atomic. Each Cortex-A57 based platform must make its own decision on whether to use the optimization. This flag is disabled by default. ”h]”(j)”}”(hŒF''A57_ENABLE_NON_CACHEABLE_LOAD_FWD'': This flag enables non-cacheable”h]”hŒNâ€˜â€™A57_ENABLE_NON_CACHEABLE_LOAD_FWDâ€™â€™: This flag enables non-cacheable”…””}”(hjÅ!h!jÃ!ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jhAj¡hCMùh!j¿!ubj9)”}”(hhh]”j£)”}”(hXGstreaming enhancement feature for Cortex-A57 CPUs. Platforms can set this bit only if their memory system meets the requirement that cache line fill requests from the Cortex-A57 processor are atomic. Each Cortex-A57 based platform must make its own decision on whether to use the optimization. This flag is disabled by default.”h]”hXGstreaming enhancement feature for Cortex-A57 CPUs. Platforms can set this bit only if their memory system meets the requirement that cache line fill requests from the Cortex-A57 processor are atomic. Each Cortex-A57 based platform must make its own decision on whether to use the optimization. This flag is disabled by default.”…””}”(hjÖ!h!jÔ!ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMõh!jÑ!ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j8h!j¿!ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1jhAj¡hCMùh!j¼!ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!j¸!ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!j!hhhANhCNubj×)”}”(hX6``NEOVERSE_Nx_EXTERNAL_LLC``: This flag indicates that an external last level cache(LLC) is present in the system, and that the DataSource field on the master CHI interface indicates when data is returned from the LLC. This is used to control how the LL_CACHE* PMU events count. Default value is 0 (Disabled). ”h]”j£)”}”(hX5``NEOVERSE_Nx_EXTERNAL_LLC``: This flag indicates that an external last level cache(LLC) is present in the system, and that the DataSource field on the master CHI interface indicates when data is returned from the LLC. This is used to control how the LL_CACHE* PMU events count. Default value is 0 (Disabled).”h]”(já)”}”(hŒ``NEOVERSE_Nx_EXTERNAL_LLC``”h]”hŒNEOVERSE_Nx_EXTERNAL_LLC”…””}”(hhh!j"ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jþ!ubhX: This flag indicates that an external last level cache(LLC) is present in the system, and that the DataSource field on the master CHI interface indicates when data is returned from the LLC. This is used to control how the LL_CACHE* PMU events count. Default value is 0 (Disabled).”…””}”(hX: This flag indicates that an external last level cache(LLC) is present in the system, and that the DataSource field on the master CHI interface indicates when data is returned from the LLC. This is used to control how the LL_CACHE* PMU events count. Default value is 0 (Disabled).”h!jþ!ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMûh!jú!ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!j!hhhAj¡hCNubeh"}”(h$]”h&]”h+]”h-]”h/]”jšj›uh1jÑhAj¡hCMÝh!jø hhubh Œ transition”“”)”}”(hŒ--------------”h]”h"}”(h$]”h&]”h+]”h-]”h/]”uh1j'"hAj¡hCMh!jø hhubj£)”}”(hŒM*Copyright (c) 2014-2021, Arm Limited and Contributors. All rights reserved.*”h]”h Œemphasis”“”)”}”(hj5"h]”hŒKCopyright (c) 2014-2021, Arm Limited and Contributors. All rights reserved.”…””}”(hhh!j9"ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j7"h!j3"ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMh!jø hhubj)”}”(hŒN.. _CVE-2017-5715: http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2017-5715”h]”h"}”(h$]”Œ cve-2017-5715”ah&]”h+]”Œ cve-2017-5715”ah-]”h/]”jjuh1jœhCMJh!jø hhhAj¡jØKubj)”}”(hŒN.. _CVE-2018-3639: http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2018-3639”h]”h"}”(h$]”Œ cve-2018-3639”ah&]”h+]”Œ cve-2018-3639”ah-]”h/]”jjFuh1jœhCMKh!jø hhhAj¡jØKubj)”}”(hŒ~.. _Cortex-A53 MPCore Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm048406/index.html”h]”h"}”(h$]”Œ3cortex-a53-mpcore-software-developers-errata-notice”ah&]”h+]”Œ3cortex-a53 mpcore software developers errata notice”ah-]”h/]”jjëuh1jœhCMLh!jø hhhAj¡jØKubj)”}”(hŒ~.. _Cortex-A57 MPCore Software Developers Errata Notice: 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