€•Œsphinx.addnodes”Œdocument”“”)”}”(Œ rawsource”Œ”Œchildren”]”(Œdocutils.nodes”Œsubstitution_definition”“”)”}”(hŒ&.. |AArch32| replace:: :term:`AArch32`”h]”hŒpending_xref”“”)”}”(hŒ:term:`AArch32`”h]”h Œinline”“”)”}”(hhh]”h ŒText”“”ŒAArch32”…””}”(hhŒparent”hubaŒ attributes”}”(Œids”]”Œclasses”]”(Œxref”Œstd”Œstd-term”eŒnames”]”Œdupnames”]”Œbackrefs”]”uŒtagname”hh!hubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”Œgetting_started/build-options”Œ refdomain”h)Œreftype”Œterm”Œrefexplicit”‰Œrefwarn”ˆŒ reftarget”ŒAArch32”uh1hŒsource”Œ”Œline”Kh!hubah"}”(h$]”h&]”h+]”ŒAArch32”ah-]”h/]”uh1h hAhBhCKh!hhhubh)”}”(hŒ&.. |AArch64| replace:: :term:`AArch64`”h]”h)”}”(hŒ:term:`AArch64`”h]”h)”}”(hhQh]”hŒAArch64”…””}”(hhh!hSubah"}”(h$]”h&]”(h(Œstd”Œstd-term”eh+]”h-]”h/]”uh1hh!hOubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”h]Œreftype”Œterm”Œrefexplicit”‰Œrefwarn”ˆh?ŒAArch64”uh1hhAhBhCKh!hKubah"}”(h$]”h&]”h+]”ŒAArch64”ah-]”h/]”uh1h hAhBhCKh!hhhubh)”}”(hŒ.. |AMU| replace:: :term:`AMU`”h]”h)”}”(hŒ:term:`AMU`”h]”h)”}”(hh|h]”hŒAMU”…””}”(hhh!h~ubah"}”(h$]”h&]”(h(Œstd”Œstd-term”eh+]”h-]”h/]”uh1hh!hzubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”hˆŒreftype”Œterm”Œrefexplicit”‰Œrefwarn”ˆh?ŒAMU”uh1hhAhBhCKh!hvubah"}”(h$]”h&]”h+]”ŒAMU”ah-]”h/]”uh1h hAhBhCKh!hhhubh)”}”(hŒ&.. |AMUs| replace:: :term:`AMUs `”h]”h)”}”(hŒ:term:`AMUs `”h]”h)”}”(hh§h]”hŒAMUs”…””}”(hhh!h©ubah"}”(h$]”h&]”(h(Œstd”Œstd-term”eh+]”h-]”h/]”uh1hh!h¥ubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”h³Œreftype”Œterm”Œrefexplicit”ˆŒrefwarn”ˆh?ŒAMU”uh1hhAhBhCKh!h¡ubah"}”(h$]”h&]”h+]”ŒAMUs”ah-]”h/]”uh1h hAhBhCKh!hhhubh)”}”(hŒ.. |API| replace:: :term:`API`”h]”h)”}”(hŒ:term:`API`”h]”h)”}”(hhÒh]”hŒAPI”…””}”(hhh!hÔubah"}”(h$]”h&]”(h(Œstd”Œstd-term”eh+]”h-]”h/]”uh1hh!hÐubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”hÞŒreftype”Œterm”Œrefexplicit”‰Œrefwarn”ˆh?ŒAPI”uh1hhAhBhCKh!hÌubah"}”(h$]”h&]”h+]”ŒAPI”ah-]”h/]”uh1h hAhBhCKh!hhhubh)”}”(hŒ.. |BTI| replace:: :term:`BTI`”h]”h)”}”(hŒ:term:`BTI`”h]”h)”}”(hhýh]”hŒBTI”…””}”(hhh!hÿubah"}”(h$]”h&]”(h(Œstd”Œstd-term”eh+]”h-]”h/]”uh1hh!hûubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”j Œreftype”Œterm”Œrefexplicit”‰Œrefwarn”ˆh?ŒBTI”uh1hhAhBhCKh!h÷ubah"}”(h$]”h&]”h+]”ŒBTI”ah-]”h/]”uh1h hAhBhCKh!hhhubh)”}”(hŒ.. |CoT| replace:: :term:`CoT`”h]”h)”}”(hŒ:term:`CoT`”h]”h)”}”(hj(h]”hŒCoT”…””}”(hhh!j*ubah"}”(h$]”h&]”(h(Œstd”Œstd-term”eh+]”h-]”h/]”uh1hh!j&ubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”j4Œreftype”Œterm”Œrefexplicit”‰Œrefwarn”ˆh?ŒCoT”uh1hhAhBhCKh!j"ubah"}”(h$]”h&]”h+]”ŒCoT”ah-]”h/]”uh1h hAhBhCKh!hhhubh)”}”(hŒ.. |COT| replace:: :term:`COT`”h]”h)”}”(hŒ:term:`COT`”h]”h)”}”(hjSh]”hŒCOT”…””}”(hhh!jUubah"}”(h$]”h&]”(h(Œstd”Œstd-term”eh+]”h-]”h/]”uh1hh!jQubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”j_Œreftype”Œterm”Œrefexplicit”‰Œrefwarn”ˆh?ŒCOT”uh1hhAhBhCKh!jMubah"}”(h$]”h&]”h+]”ŒCOT”ah-]”h/]”uh1h hAhBhCKh!hhhubh)”}”(hŒ.. |CSS| replace:: :term:`CSS`”h]”h)”}”(hŒ:term:`CSS`”h]”h)”}”(hj~h]”hŒCSS”…””}”(hhh!j€ubah"}”(h$]”h&]”(h(Œstd”Œstd-term”eh+]”h-]”h/]”uh1hh!j|ubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”jŠŒreftype”Œterm”Œrefexplicit”‰Œrefwarn”ˆh?ŒCSS”uh1hhAhBhCK h!jxubah"}”(h$]”h&]”h+]”ŒCSS”ah-]”h/]”uh1h hAhBhCK h!hhhubh)”}”(hŒ.. |CVE| replace:: :term:`CVE`”h]”h)”}”(hŒ:term:`CVE`”h]”h)”}”(hj©h]”hŒCVE”…””}”(hhh!j«ubah"}”(h$]”h&]”(h(Œstd”Œstd-term”eh+]”h-]”h/]”uh1hh!j§ubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”jµŒreftype”Œterm”Œrefexplicit”‰Œrefwarn”ˆh?ŒCVE”uh1hhAhBhCK h!j£ubah"}”(h$]”h&]”h+]”ŒCVE”ah-]”h/]”uh1h hAhBhCK h!hhhubh)”}”(hŒ.. |DTB| replace:: :term:`DTB`”h]”h)”}”(hŒ:term:`DTB`”h]”h)”}”(hjÔh]”hŒDTB”…””}”(hhh!jÖubah"}”(h$]”h&]”(h(Œstd”Œstd-term”eh+]”h-]”h/]”uh1hh!jÒubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”jàŒreftype”Œterm”Œrefexplicit”‰Œrefwarn”ˆh?ŒDTB”uh1hhAhBhCKh!jÎubah"}”(h$]”h&]”h+]”ŒDTB”ah-]”h/]”uh1h hAhBhCKh!hhhubh)”}”(hŒ .. |DS-5| replace:: :term:`DS-5`”h]”h)”}”(hŒ:term:`DS-5`”h]”h)”}”(hjÿh]”hŒDS-5”…””}”(hhh!jubah"}”(h$]”h&]”(h(Œstd”Œstd-term”eh+]”h-]”h/]”uh1hh!jýubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”jŒreftype”Œterm”Œrefexplicit”‰Œrefwarn”ˆh?ŒDS-5”uh1hhAhBhCKh!jùubah"}”(h$]”h&]”h+]”ŒDS-5”ah-]”h/]”uh1h hAhBhCKh!hhhubh)”}”(hŒ.. |DSU| replace:: :term:`DSU`”h]”h)”}”(hŒ:term:`DSU`”h]”h)”}”(hj*h]”hŒDSU”…””}”(hhh!j,ubah"}”(h$]”h&]”(h(Œstd”Œstd-term”eh+]”h-]”h/]”uh1hh!j(ubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”j6Œreftype”Œterm”Œrefexplicit”‰Œrefwarn”ˆh?ŒDSU”uh1hhAhBhCK h!j$ubah"}”(h$]”h&]”h+]”ŒDSU”ah-]”h/]”uh1h hAhBhCK h!hhhubh)”}”(hŒ.. |DT| replace:: :term:`DT`”h]”h)”}”(hŒ :term:`DT`”h]”h)”}”(hjUh]”hŒDT”…””}”(hhh!jWubah"}”(h$]”h&]”(h(Œstd”Œstd-term”eh+]”h-]”h/]”uh1hh!jSubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”jaŒreftype”Œterm”Œrefexplicit”‰Œrefwarn”ˆh?ŒDT”uh1hhAhBhCKh!jOubah"}”(h$]”h&]”h+]”ŒDT”ah-]”h/]”uh1h hAhBhCKh!hhhubh)”}”(hŒ.. |EL| replace:: :term:`EL`”h]”h)”}”(hŒ :term:`EL`”h]”h)”}”(hj€h]”hŒEL”…””}”(hhh!j‚ubah"}”(h$]”h&]”(h(Œstd”Œstd-term”eh+]”h-]”h/]”uh1hh!j~ubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”jŒŒreftype”Œterm”Œrefexplicit”‰Œrefwarn”ˆh?ŒEL”uh1hhAhBhCKh!jzubah"}”(h$]”h&]”h+]”ŒEL”ah-]”h/]”uh1h hAhBhCKh!hhhubh)”}”(hŒ.. |EHF| replace:: :term:`EHF`”h]”h)”}”(hŒ:term:`EHF`”h]”h)”}”(hj«h]”hŒEHF”…””}”(hhh!jubah"}”(h$]”h&]”(h(Œstd”Œstd-term”eh+]”h-]”h/]”uh1hh!j©ubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”j·Œreftype”Œterm”Œrefexplicit”‰Œrefwarn”ˆh?ŒEHF”uh1hhAhBhCKh!j¥ubah"}”(h$]”h&]”h+]”ŒEHF”ah-]”h/]”uh1h hAhBhCKh!hhhubh)”}”(hŒ".. |FCONF| replace:: :term:`FCONF`”h]”h)”}”(hŒ :term:`FCONF`”h]”h)”}”(hjÖh]”hŒFCONF”…””}”(hhh!jØubah"}”(h$]”h&]”(h(Œstd”Œstd-term”eh+]”h-]”h/]”uh1hh!jÔubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”jâŒreftype”Œterm”Œrefexplicit”‰Œrefwarn”ˆh?ŒFCONF”uh1hhAhBhCKh!jÐubah"}”(h$]”h&]”h+]”ŒFCONF”ah-]”h/]”uh1h hAhBhCKh!hhhubh)”}”(hŒ.. |FDT| replace:: :term:`FDT`”h]”h)”}”(hŒ:term:`FDT`”h]”h)”}”(hjh]”hŒFDT”…””}”(hhh!jubah"}”(h$]”h&]”(h(Œstd”Œstd-term”eh+]”h-]”h/]”uh1hh!jÿubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”j Œreftype”Œterm”Œrefexplicit”‰Œrefwarn”ˆh?ŒFDT”uh1hhAhBhCKh!jûubah"}”(h$]”h&]”h+]”ŒFDT”ah-]”h/]”uh1h hAhBhCKh!hhhubh)”}”(hŒ .. |FF-A| replace:: :term:`FF-A`”h]”h)”}”(hŒ:term:`FF-A`”h]”h)”}”(hj,h]”hŒFF-A”…””}”(hhh!j.ubah"}”(h$]”h&]”(h(Œstd”Œstd-term”eh+]”h-]”h/]”uh1hh!j*ubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”j8Œreftype”Œterm”Œrefexplicit”‰Œrefwarn”ˆh?ŒFF-A”uh1hhAhBhCKh!j&ubah"}”(h$]”h&]”h+]”ŒFF-A”ah-]”h/]”uh1h hAhBhCKh!hhhubh)”}”(hŒ.. |FIP| replace:: :term:`FIP`”h]”h)”}”(hŒ:term:`FIP`”h]”h)”}”(hjWh]”hŒFIP”…””}”(hhh!jYubah"}”(h$]”h&]”(h(Œstd”Œstd-term”eh+]”h-]”h/]”uh1hh!jUubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”jcŒreftype”Œterm”Œrefexplicit”‰Œrefwarn”ˆh?ŒFIP”uh1hhAhBhCKh!jQubah"}”(h$]”h&]”h+]”ŒFIP”ah-]”h/]”uh1h hAhBhCKh!hhhubh)”}”(hŒ.. |FVP| replace:: :term:`FVP`”h]”h)”}”(hŒ:term:`FVP`”h]”h)”}”(hj‚h]”hŒFVP”…””}”(hhh!j„ubah"}”(h$]”h&]”(h(Œstd”Œstd-term”eh+]”h-]”h/]”uh1hh!j€ubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”jŽŒreftype”Œterm”Œrefexplicit”‰Œrefwarn”ˆh?ŒFVP”uh1hhAhBhCKh!j|ubah"}”(h$]”h&]”h+]”ŒFVP”ah-]”h/]”uh1h hAhBhCKh!hhhubh)”}”(hŒ.. |FWU| replace:: :term:`FWU`”h]”h)”}”(hŒ:term:`FWU`”h]”h)”}”(hjh]”hŒFWU”…””}”(hhh!j¯ubah"}”(h$]”h&]”(h(Œstd”Œstd-term”eh+]”h-]”h/]”uh1hh!j«ubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”j¹Œreftype”Œterm”Œrefexplicit”‰Œrefwarn”ˆh?ŒFWU”uh1hhAhBhCKh!j§ubah"}”(h$]”h&]”h+]”ŒFWU”ah-]”h/]”uh1h hAhBhCKh!hhhubh)”}”(hŒ.. |GIC| replace:: :term:`GIC`”h]”h)”}”(hŒ:term:`GIC`”h]”h)”}”(hjØh]”hŒGIC”…””}”(hhh!jÚubah"}”(h$]”h&]”(h(Œstd”Œstd-term”eh+]”h-]”h/]”uh1hh!jÖubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”jäŒreftype”Œterm”Œrefexplicit”‰Œrefwarn”ˆh?ŒGIC”uh1hhAhBhCKh!jÒubah"}”(h$]”h&]”h+]”ŒGIC”ah-]”h/]”uh1h hAhBhCKh!hhhubh)”}”(hŒ.. |ISA| replace:: :term:`ISA`”h]”h)”}”(hŒ:term:`ISA`”h]”h)”}”(hjh]”hŒISA”…””}”(hhh!jubah"}”(h$]”h&]”(h(Œstd”Œstd-term”eh+]”h-]”h/]”uh1hh!jubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”jŒreftype”Œterm”Œrefexplicit”‰Œrefwarn”ˆh?ŒISA”uh1hhAhBhCKh!jýubah"}”(h$]”h&]”h+]”ŒISA”ah-]”h/]”uh1h hAhBhCKh!hhhubh)”}”(hŒ$.. |Linaro| replace:: :term:`Linaro`”h]”h)”}”(hŒ:term:`Linaro`”h]”h)”}”(hj.h]”hŒLinaro”…””}”(hhh!j0ubah"}”(h$]”h&]”(h(Œstd”Œstd-term”eh+]”h-]”h/]”uh1hh!j,ubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”j:Œreftype”Œterm”Œrefexplicit”‰Œrefwarn”ˆh?ŒLinaro”uh1hhAhBhCKh!j(ubah"}”(h$]”h&]”h+]”ŒLinaro”ah-]”h/]”uh1h hAhBhCKh!hhhubh)”}”(hŒ.. |MMU| replace:: :term:`MMU`”h]”h)”}”(hŒ:term:`MMU`”h]”h)”}”(hjYh]”hŒMMU”…””}”(hhh!j[ubah"}”(h$]”h&]”(h(Œstd”Œstd-term”eh+]”h-]”h/]”uh1hh!jWubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”jeŒreftype”Œterm”Œrefexplicit”‰Œrefwarn”ˆh?ŒMMU”uh1hhAhBhCKh!jSubah"}”(h$]”h&]”h+]”ŒMMU”ah-]”h/]”uh1h hAhBhCKh!hhhubh)”}”(hŒ .. |MPAM| replace:: :term:`MPAM`”h]”h)”}”(hŒ:term:`MPAM`”h]”h)”}”(hj„h]”hŒMPAM”…””}”(hhh!j†ubah"}”(h$]”h&]”(h(Œstd”Œstd-term”eh+]”h-]”h/]”uh1hh!j‚ubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”jŒreftype”Œterm”Œrefexplicit”‰Œrefwarn”ˆh?ŒMPAM”uh1hhAhBhCKh!j~ubah"}”(h$]”h&]”h+]”ŒMPAM”ah-]”h/]”uh1h hAhBhCKh!hhhubh)”}”(hŒ .. |MPMM| replace:: :term:`MPMM`”h]”h)”}”(hŒ:term:`MPMM`”h]”h)”}”(hj¯h]”hŒMPMM”…””}”(hhh!j±ubah"}”(h$]”h&]”(h(Œstd”Œstd-term”eh+]”h-]”h/]”uh1hh!jubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”j»Œreftype”Œterm”Œrefexplicit”‰Œrefwarn”ˆh?ŒMPMM”uh1hhAhBhCKh!j©ubah"}”(h$]”h&]”h+]”ŒMPMM”ah-]”h/]”uh1h hAhBhCKh!hhhubh)”}”(hŒ".. |MPIDR| replace:: :term:`MPIDR`”h]”h)”}”(hŒ :term:`MPIDR`”h]”h)”}”(hjÚh]”hŒMPIDR”…””}”(hhh!jÜubah"}”(h$]”h&]”(h(Œstd”Œstd-term”eh+]”h-]”h/]”uh1hh!jØubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”jæŒreftype”Œterm”Œrefexplicit”‰Œrefwarn”ˆh?ŒMPIDR”uh1hhAhBhCKh!jÔubah"}”(h$]”h&]”h+]”ŒMPIDR”ah-]”h/]”uh1h hAhBhCKh!hhhubh)”}”(hŒ.. |MTE| replace:: :term:`MTE`”h]”h)”}”(hŒ:term:`MTE`”h]”h)”}”(hjh]”hŒMTE”…””}”(hhh!jubah"}”(h$]”h&]”(h(Œstd”Œstd-term”eh+]”h-]”h/]”uh1hh!jubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”jŒreftype”Œterm”Œrefexplicit”‰Œrefwarn”ˆh?ŒMTE”uh1hhAhBhCKh!jÿubah"}”(h$]”h&]”h+]”ŒMTE”ah-]”h/]”uh1h hAhBhCKh!hhhubh)”}”(hŒ.. |OEN| replace:: :term:`OEN`”h]”h)”}”(hŒ:term:`OEN`”h]”h)”}”(hj0h]”hŒOEN”…””}”(hhh!j2ubah"}”(h$]”h&]”(h(Œstd”Œstd-term”eh+]”h-]”h/]”uh1hh!j.ubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”j<Œreftype”Œterm”Œrefexplicit”‰Œrefwarn”ˆh?ŒOEN”uh1hhAhBhCKh!j*ubah"}”(h$]”h&]”h+]”ŒOEN”ah-]”h/]”uh1h hAhBhCKh!hhhubh)”}”(hŒ$.. |OP-TEE| replace:: :term:`OP-TEE`”h]”h)”}”(hŒ:term:`OP-TEE`”h]”h)”}”(hj[h]”hŒOP-TEE”…””}”(hhh!j]ubah"}”(h$]”h&]”(h(Œstd”Œstd-term”eh+]”h-]”h/]”uh1hh!jYubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”jgŒreftype”Œterm”Œrefexplicit”‰Œrefwarn”ˆh?ŒOP-TEE”uh1hhAhBhCK h!jUubah"}”(h$]”h&]”h+]”ŒOP-TEE”ah-]”h/]”uh1h hAhBhCK h!hhhubh)”}”(hŒ.. |OTE| replace:: :term:`OTE`”h]”h)”}”(hŒ:term:`OTE`”h]”h)”}”(hj†h]”hŒOTE”…””}”(hhh!jˆubah"}”(h$]”h&]”(h(Œstd”Œstd-term”eh+]”h-]”h/]”uh1hh!j„ubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”j’Œreftype”Œterm”Œrefexplicit”‰Œrefwarn”ˆh?ŒOTE”uh1hhAhBhCK!h!j€ubah"}”(h$]”h&]”h+]”ŒOTE”ah-]”h/]”uh1h hAhBhCK!h!hhhubh)”}”(hŒ.. |PDD| replace:: :term:`PDD`”h]”h)”}”(hŒ:term:`PDD`”h]”h)”}”(hj±h]”hŒPDD”…””}”(hhh!j³ubah"}”(h$]”h&]”(h(Œstd”Œstd-term”eh+]”h-]”h/]”uh1hh!j¯ubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”j½Œreftype”Œterm”Œrefexplicit”‰Œrefwarn”ˆh?ŒPDD”uh1hhAhBhCK"h!j«ubah"}”(h$]”h&]”h+]”ŒPDD”ah-]”h/]”uh1h hAhBhCK"h!hhhubh)”}”(hŒ".. |PAUTH| replace:: :term:`PAUTH`”h]”h)”}”(hŒ :term:`PAUTH`”h]”h)”}”(hjÜh]”hŒPAUTH”…””}”(hhh!jÞubah"}”(h$]”h&]”(h(Œstd”Œstd-term”eh+]”h-]”h/]”uh1hh!jÚubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”jèŒreftype”Œterm”Œrefexplicit”‰Œrefwarn”ˆh?ŒPAUTH”uh1hhAhBhCK#h!jÖubah"}”(h$]”h&]”h+]”ŒPAUTH”ah-]”h/]”uh1h hAhBhCK#h!hhhubh)”}”(hŒ.. |PMF| replace:: :term:`PMF`”h]”h)”}”(hŒ:term:`PMF`”h]”h)”}”(hjh]”hŒPMF”…””}”(hhh!j ubah"}”(h$]”h&]”(h(Œstd”Œstd-term”eh+]”h-]”h/]”uh1hh!jubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”jŒreftype”Œterm”Œrefexplicit”‰Œrefwarn”ˆh?ŒPMF”uh1hhAhBhCK$h!jubah"}”(h$]”h&]”h+]”ŒPMF”ah-]”h/]”uh1h hAhBhCK$h!hhhubh)”}”(hŒ .. |PSCI| replace:: :term:`PSCI`”h]”h)”}”(hŒ:term:`PSCI`”h]”h)”}”(hj2h]”hŒPSCI”…””}”(hhh!j4ubah"}”(h$]”h&]”(h(Œstd”Œstd-term”eh+]”h-]”h/]”uh1hh!j0ubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”j>Œreftype”Œterm”Œrefexplicit”‰Œrefwarn”ˆh?ŒPSCI”uh1hhAhBhCK%h!j,ubah"}”(h$]”h&]”h+]”ŒPSCI”ah-]”h/]”uh1h hAhBhCK%h!hhhubh)”}”(hŒ.. |RAS| replace:: :term:`RAS`”h]”h)”}”(hŒ:term:`RAS`”h]”h)”}”(hj]h]”hŒRAS”…””}”(hhh!j_ubah"}”(h$]”h&]”(h(Œstd”Œstd-term”eh+]”h-]”h/]”uh1hh!j[ubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”jiŒreftype”Œterm”Œrefexplicit”‰Œrefwarn”ˆh?ŒRAS”uh1hhAhBhCK&h!jWubah"}”(h$]”h&]”h+]”ŒRAS”ah-]”h/]”uh1h hAhBhCK&h!hhhubh)”}”(hŒ.. |ROT| replace:: :term:`ROT`”h]”h)”}”(hŒ:term:`ROT`”h]”h)”}”(hjˆh]”hŒROT”…””}”(hhh!jŠubah"}”(h$]”h&]”(h(Œstd”Œstd-term”eh+]”h-]”h/]”uh1hh!j†ubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”j”Œreftype”Œterm”Œrefexplicit”‰Œrefwarn”ˆh?ŒROT”uh1hhAhBhCK'h!j‚ubah"}”(h$]”h&]”h+]”ŒROT”ah-]”h/]”uh1h hAhBhCK'h!hhhubh)”}”(hŒ .. |SCMI| replace:: :term:`SCMI`”h]”h)”}”(hŒ:term:`SCMI`”h]”h)”}”(hj³h]”hŒSCMI”…””}”(hhh!jµubah"}”(h$]”h&]”(h(Œstd”Œstd-term”eh+]”h-]”h/]”uh1hh!j±ubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”j¿Œreftype”Œterm”Œrefexplicit”‰Œrefwarn”ˆh?ŒSCMI”uh1hhAhBhCK(h!jubah"}”(h$]”h&]”h+]”ŒSCMI”ah-]”h/]”uh1h hAhBhCK(h!hhhubh)”}”(hŒ.. |SCP| replace:: :term:`SCP`”h]”h)”}”(hŒ:term:`SCP`”h]”h)”}”(hjÞh]”hŒSCP”…””}”(hhh!jàubah"}”(h$]”h&]”(h(Œstd”Œstd-term”eh+]”h-]”h/]”uh1hh!jÜubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”jêŒreftype”Œterm”Œrefexplicit”‰Œrefwarn”ˆh?ŒSCP”uh1hhAhBhCK)h!jØubah"}”(h$]”h&]”h+]”ŒSCP”ah-]”h/]”uh1h hAhBhCK)h!hhhubh)”}”(hŒ .. |SDEI| replace:: :term:`SDEI`”h]”h)”}”(hŒ:term:`SDEI`”h]”h)”}”(hj h]”hŒSDEI”…””}”(hhh!jubah"}”(h$]”h&]”(h(Œstd”Œstd-term”eh+]”h-]”h/]”uh1hh!jubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”jŒreftype”Œterm”Œrefexplicit”‰Œrefwarn”ˆh?ŒSDEI”uh1hhAhBhCK*h!jubah"}”(h$]”h&]”h+]”ŒSDEI”ah-]”h/]”uh1h hAhBhCK*h!hhhubh)”}”(hŒ.. |SDS| replace:: :term:`SDS`”h]”h)”}”(hŒ:term:`SDS`”h]”h)”}”(hj4h]”hŒSDS”…””}”(hhh!j6ubah"}”(h$]”h&]”(h(Œstd”Œstd-term”eh+]”h-]”h/]”uh1hh!j2ubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”j@Œreftype”Œterm”Œrefexplicit”‰Œrefwarn”ˆh?ŒSDS”uh1hhAhBhCK+h!j.ubah"}”(h$]”h&]”h+]”ŒSDS”ah-]”h/]”uh1h hAhBhCK+h!hhhubh)”}”(hŒ.. |SEA| replace:: :term:`SEA`”h]”h)”}”(hŒ:term:`SEA`”h]”h)”}”(hj_h]”hŒSEA”…””}”(hhh!jaubah"}”(h$]”h&]”(h(Œstd”Œstd-term”eh+]”h-]”h/]”uh1hh!j]ubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”jkŒreftype”Œterm”Œrefexplicit”‰Œrefwarn”ˆh?ŒSEA”uh1hhAhBhCK,h!jYubah"}”(h$]”h&]”h+]”ŒSEA”ah-]”h/]”uh1h hAhBhCK,h!hhhubh)”}”(hŒ.. |SiP| replace:: :term:`SiP`”h]”h)”}”(hŒ:term:`SiP`”h]”h)”}”(hjŠh]”hŒSiP”…””}”(hhh!jŒubah"}”(h$]”h&]”(h(Œstd”Œstd-term”eh+]”h-]”h/]”uh1hh!jˆubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”j–Œreftype”Œterm”Œrefexplicit”‰Œrefwarn”ˆh?ŒSiP”uh1hhAhBhCK-h!j„ubah"}”(h$]”h&]”h+]”ŒSiP”ah-]”h/]”uh1h hAhBhCK-h!hhhubh)”}”(hŒ.. |SIP| replace:: :term:`SIP`”h]”h)”}”(hŒ:term:`SIP`”h]”h)”}”(hjµh]”hŒSIP”…””}”(hhh!j·ubah"}”(h$]”h&]”(h(Œstd”Œstd-term”eh+]”h-]”h/]”uh1hh!j³ubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”jÁŒreftype”Œterm”Œrefexplicit”‰Œrefwarn”ˆh?ŒSIP”uh1hhAhBhCK.h!j¯ubah"}”(h$]”h&]”h+]”ŒSIP”ah-]”h/]”uh1h hAhBhCK.h!hhhubh)”}”(hŒ.. |SMC| replace:: :term:`SMC`”h]”h)”}”(hŒ:term:`SMC`”h]”h)”}”(hjàh]”hŒSMC”…””}”(hhh!jâubah"}”(h$]”h&]”(h(Œstd”Œstd-term”eh+]”h-]”h/]”uh1hh!jÞubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”jìŒreftype”Œterm”Œrefexplicit”‰Œrefwarn”ˆh?ŒSMC”uh1hhAhBhCK/h!jÚubah"}”(h$]”h&]”h+]”ŒSMC”ah-]”h/]”uh1h hAhBhCK/h!hhhubh)”}”(hŒ".. |SMCCC| replace:: :term:`SMCCC`”h]”h)”}”(hŒ :term:`SMCCC`”h]”h)”}”(hjh]”hŒSMCCC”…””}”(hhh!j ubah"}”(h$]”h&]”(h(Œstd”Œstd-term”eh+]”h-]”h/]”uh1hh!j ubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”jŒreftype”Œterm”Œrefexplicit”‰Œrefwarn”ˆh?ŒSMCCC”uh1hhAhBhCK0h!jubah"}”(h$]”h&]”h+]”ŒSMCCC”ah-]”h/]”uh1h hAhBhCK0h!hhhubh)”}”(hŒ.. |SoC| replace:: :term:`SoC`”h]”h)”}”(hŒ:term:`SoC`”h]”h)”}”(hj6h]”hŒSoC”…””}”(hhh!j8ubah"}”(h$]”h&]”(h(Œstd”Œstd-term”eh+]”h-]”h/]”uh1hh!j4ubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”jBŒreftype”Œterm”Œrefexplicit”‰Œrefwarn”ˆh?ŒSoC”uh1hhAhBhCK1h!j0ubah"}”(h$]”h&]”h+]”ŒSoC”ah-]”h/]”uh1h hAhBhCK1h!hhhubh)”}”(hŒ.. |SP| replace:: :term:`SP`”h]”h)”}”(hŒ :term:`SP`”h]”h)”}”(hjah]”hŒSP”…””}”(hhh!jcubah"}”(h$]”h&]”(h(Œstd”Œstd-term”eh+]”h-]”h/]”uh1hh!j_ubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”jmŒreftype”Œterm”Œrefexplicit”‰Œrefwarn”ˆh?ŒSP”uh1hhAhBhCK2h!j[ubah"}”(h$]”h&]”h+]”ŒSP”ah-]”h/]”uh1h hAhBhCK2h!hhhubh)”}”(hŒ.. |SPD| replace:: :term:`SPD`”h]”h)”}”(hŒ:term:`SPD`”h]”h)”}”(hjŒh]”hŒSPD”…””}”(hhh!jŽubah"}”(h$]”h&]”(h(Œstd”Œstd-term”eh+]”h-]”h/]”uh1hh!jŠubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”j˜Œreftype”Œterm”Œrefexplicit”‰Œrefwarn”ˆh?ŒSPD”uh1hhAhBhCK3h!j†ubah"}”(h$]”h&]”h+]”ŒSPD”ah-]”h/]”uh1h hAhBhCK3h!hhhubh)”}”(hŒ.. |SPM| replace:: :term:`SPM`”h]”h)”}”(hŒ:term:`SPM`”h]”h)”}”(hj·h]”hŒSPM”…””}”(hhh!j¹ubah"}”(h$]”h&]”(h(Œstd”Œstd-term”eh+]”h-]”h/]”uh1hh!jµubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”jÃŒreftype”Œterm”Œrefexplicit”‰Œrefwarn”ˆh?ŒSPM”uh1hhAhBhCK4h!j±ubah"}”(h$]”h&]”h+]”ŒSPM”ah-]”h/]”uh1h hAhBhCK4h!hhhubh)”}”(hŒ .. |SSBS| replace:: :term:`SSBS`”h]”h)”}”(hŒ:term:`SSBS`”h]”h)”}”(hjâh]”hŒSSBS”…””}”(hhh!jäubah"}”(h$]”h&]”(h(Œstd”Œstd-term”eh+]”h-]”h/]”uh1hh!jàubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”jîŒreftype”Œterm”Œrefexplicit”‰Œrefwarn”ˆh?ŒSSBS”uh1hhAhBhCK5h!jÜubah"}”(h$]”h&]”h+]”ŒSSBS”ah-]”h/]”uh1h hAhBhCK5h!hhhubh)”}”(hŒ.. |SVE| replace:: :term:`SVE`”h]”h)”}”(hŒ:term:`SVE`”h]”h)”}”(hj h]”hŒSVE”…””}”(hhh!j ubah"}”(h$]”h&]”(h(Œstd”Œstd-term”eh+]”h-]”h/]”uh1hh!j ubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”j Œreftype”Œterm”Œrefexplicit”‰Œrefwarn”ˆh?ŒSVE”uh1hhAhBhCK6h!j ubah"}”(h$]”h&]”h+]”ŒSVE”ah-]”h/]”uh1h hAhBhCK6h!hhhubh)”}”(hŒ.. |TBB| replace:: :term:`TBB`”h]”h)”}”(hŒ:term:`TBB`”h]”h)”}”(hj8 h]”hŒTBB”…””}”(hhh!j: ubah"}”(h$]”h&]”(h(Œstd”Œstd-term”eh+]”h-]”h/]”uh1hh!j6 ubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”jD Œreftype”Œterm”Œrefexplicit”‰Œrefwarn”ˆh?ŒTBB”uh1hhAhBhCK7h!j2 ubah"}”(h$]”h&]”h+]”ŒTBB”ah-]”h/]”uh1h hAhBhCK7h!hhhubh)”}”(hŒ .. |TBBR| replace:: :term:`TBBR`”h]”h)”}”(hŒ:term:`TBBR`”h]”h)”}”(hjc h]”hŒTBBR”…””}”(hhh!je ubah"}”(h$]”h&]”(h(Œstd”Œstd-term”eh+]”h-]”h/]”uh1hh!ja ubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”jo Œreftype”Œterm”Œrefexplicit”‰Œrefwarn”ˆh?ŒTBBR”uh1hhAhBhCK8h!j] ubah"}”(h$]”h&]”h+]”ŒTBBR”ah-]”h/]”uh1h hAhBhCK8h!hhhubh)”}”(hŒ.. |TEE| replace:: :term:`TEE`”h]”h)”}”(hŒ:term:`TEE`”h]”h)”}”(hjŽ h]”hŒTEE”…””}”(hhh!j ubah"}”(h$]”h&]”(h(Œstd”Œstd-term”eh+]”h-]”h/]”uh1hh!jŒ ubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”jš Œreftype”Œterm”Œrefexplicit”‰Œrefwarn”ˆh?ŒTEE”uh1hhAhBhCK9h!jˆ ubah"}”(h$]”h&]”h+]”ŒTEE”ah-]”h/]”uh1h hAhBhCK9h!hhhubh)”}”(hŒ .. |TF-A| replace:: :term:`TF-A`”h]”h)”}”(hŒ:term:`TF-A`”h]”h)”}”(hj¹ h]”hŒTF-A”…””}”(hhh!j» ubah"}”(h$]”h&]”(h(Œstd”Œstd-term”eh+]”h-]”h/]”uh1hh!j· ubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”jÅ Œreftype”Œterm”Œrefexplicit”‰Œrefwarn”ˆh?ŒTF-A”uh1hhAhBhCK:h!j³ ubah"}”(h$]”h&]”h+]”ŒTF-A”ah-]”h/]”uh1h hAhBhCK:h!hhhubh)”}”(hŒ .. |TF-M| replace:: :term:`TF-M`”h]”h)”}”(hŒ:term:`TF-M`”h]”h)”}”(hjä h]”hŒTF-M”…””}”(hhh!jæ ubah"}”(h$]”h&]”(h(Œstd”Œstd-term”eh+]”h-]”h/]”uh1hh!jâ ubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”jð Œreftype”Œterm”Œrefexplicit”‰Œrefwarn”ˆh?ŒTF-M”uh1hhAhBhCK;h!jÞ ubah"}”(h$]”h&]”h+]”ŒTF-M”ah-]”h/]”uh1h hAhBhCK;h!hhhubh)”}”(hŒ.. |TLB| replace:: :term:`TLB`”h]”h)”}”(hŒ:term:`TLB`”h]”h)”}”(hj h]”hŒTLB”…””}”(hhh!j ubah"}”(h$]”h&]”(h(Œstd”Œstd-term”eh+]”h-]”h/]”uh1hh!j ubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”j Œreftype”Œterm”Œrefexplicit”‰Œrefwarn”ˆh?ŒTLB”uh1hhAhBhCKh!j_ ubah"}”(h$]”h&]”h+]”ŒTRNG”ah-]”h/]”uh1h hAhBhCK>h!hhhubh)”}”(hŒ.. |TSP| replace:: :term:`TSP`”h]”h)”}”(hŒ:term:`TSP`”h]”h)”}”(hj h]”hŒTSP”…””}”(hhh!j’ ubah"}”(h$]”h&]”(h(Œstd”Œstd-term”eh+]”h-]”h/]”uh1hh!jŽ ubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”jœ Œreftype”Œterm”Œrefexplicit”‰Œrefwarn”ˆh?ŒTSP”uh1hhAhBhCK?h!jŠ ubah"}”(h$]”h&]”h+]”ŒTSP”ah-]”h/]”uh1h hAhBhCK?h!hhhubh)”}”(hŒ.. |TZC| replace:: :term:`TZC`”h]”h)”}”(hŒ:term:`TZC`”h]”h)”}”(hj» h]”hŒTZC”…””}”(hhh!j½ ubah"}”(h$]”h&]”(h(Œstd”Œstd-term”eh+]”h-]”h/]”uh1hh!j¹ ubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”jÇ Œreftype”Œterm”Œrefexplicit”‰Œrefwarn”ˆh?ŒTZC”uh1hhAhBhCK@h!jµ ubah"}”(h$]”h&]”h+]”ŒTZC”ah-]”h/]”uh1h hAhBhCK@h!hhhubh)”}”(hŒ".. |UBSAN| replace:: :term:`UBSAN`”h]”h)”}”(hŒ :term:`UBSAN`”h]”h)”}”(hjæ h]”hŒUBSAN”…””}”(hhh!jè ubah"}”(h$]”h&]”(h(Œstd”Œstd-term”eh+]”h-]”h/]”uh1hh!jä ubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”jò Œreftype”Œterm”Œrefexplicit”‰Œrefwarn”ˆh?ŒUBSAN”uh1hhAhBhCKAh!jà ubah"}”(h$]”h&]”h+]”ŒUBSAN”ah-]”h/]”uh1h hAhBhCKAh!hhhubh)”}”(hŒ .. |UEFI| replace:: :term:`UEFI`”h]”h)”}”(hŒ:term:`UEFI`”h]”h)”}”(hjh]”hŒUEFI”…””}”(hhh!jubah"}”(h$]”h&]”(h(Œstd”Œstd-term”eh+]”h-]”h/]”uh1hh!jubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”jŒreftype”Œterm”Œrefexplicit”‰Œrefwarn”ˆh?ŒUEFI”uh1hhAhBhCKBh!jubah"}”(h$]”h&]”h+]”ŒUEFI”ah-]”h/]”uh1h hAhBhCKBh!hhhubh)”}”(hŒ .. |WDOG| replace:: :term:`WDOG`”h]”h)”}”(hŒ:term:`WDOG`”h]”h)”}”(hj<h]”hŒWDOG”…””}”(hhh!j>ubah"}”(h$]”h&]”(h(Œstd”Œstd-term”eh+]”h-]”h/]”uh1hh!j:ubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”jHŒreftype”Œterm”Œrefexplicit”‰Œrefwarn”ˆh?ŒWDOG”uh1hhAhBhCKCh!j6ubah"}”(h$]”h&]”h+]”ŒWDOG”ah-]”h/]”uh1h hAhBhCKCh!hhhubh)”}”(hŒ!.. |XLAT| replace:: :term:`XLAT` ”h]”h)”}”(hŒ:term:`XLAT`”h]”h)”}”(hjgh]”hŒXLAT”…””}”(hhh!jiubah"}”(h$]”h&]”(h(Œstd”Œstd-term”eh+]”h-]”h/]”uh1hh!jeubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”jsŒreftype”Œterm”Œrefexplicit”‰Œrefwarn”ˆh?ŒXLAT”uh1hhAhBhCKDh!jaubah"}”(h$]”h&]”h+]”ŒXLAT”ah-]”h/]”uh1h hAhBhCKDh!hhhubh Œsection”“”)”}”(hhh]”(h Œtitle”“”)”}”(hŒ Build Options”h]”hŒ Build Options”…””}”(hj•h!j“hhhANhCNubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j‘h!jŽhhhAŒ^/home/test/workspace/code/optee_3.16/trusted-firmware-a/docs/getting_started/build-options.rst”hCKubh Œ paragraph”“”)”}”(hX…The TF-A build system supports the following build options. Unless mentioned otherwise, these options are expected to be specified at the build command line and are not to be modified in any component makefiles. Note that the build system doesn't track dependency for build options. Therefore, if any of the build options are changed from a previous build, a clean build must be performed.”h]”hX‡The TF-A build system supports the following build options. Unless mentioned otherwise, these options are expected to be specified at the build command line and are not to be modified in any component makefiles. Note that the build system doesnâ€™t track dependency for build options. Therefore, if any of the build options are changed from a previous build, a clean build must be performed.”…””}”(hj¦h!j¤hhhANhCNubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKh!jŽhhubh Œtarget”“”)”}”(hŒ.. _build_options_common:”h]”h"}”(h$]”h&]”h+]”h-]”h/]”Œrefid”Œbuild-options-common”uh1j²hCKPh!jŽhhhAj¡ubj)”}”(hhh]”(j’)”}”(hŒCommon build options”h]”hŒCommon build options”…””}”(hjÅh!jÃhhhANhCNubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j‘h!jÀhhhAj¡hCKubh Œbullet_list”“”)”}”(hhh]”(h Œ list_item”“”)”}”(hŒ¼``AARCH32_INSTRUCTION_SET``: Choose the AArch32 instruction set that the compiler should use. Valid values are T32 and A32. It defaults to T32 due to code having a smaller resulting size. ”h]”j£)”}”(hŒ»``AARCH32_INSTRUCTION_SET``: Choose the AArch32 instruction set that the compiler should use. Valid values are T32 and A32. It defaults to T32 due to code having a smaller resulting size.”h]”(h Œliteral”“”)”}”(hŒ``AARCH32_INSTRUCTION_SET``”h]”hŒAARCH32_INSTRUCTION_SET”…””}”(hhh!jâubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jÜubhŒ : Choose the AArch32 instruction set that the compiler should use. Valid values are T32 and A32. It defaults to T32 due to code having a smaller resulting size.”…””}”(hŒ : Choose the AArch32 instruction set that the compiler should use. Valid values are T32 and A32. It defaults to T32 due to code having a smaller resulting size.”h!jÜubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKh!jØubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hX*``AARCH32_SP`` : Choose the AArch32 Secure Payload component to be built as as the BL32 image when ``ARCH=aarch32``. The value should be the path to the directory containing the SP source, relative to the ``bl32/``; the directory is expected to contain a makefile called ``.mk``. ”h]”j£)”}”(hX)``AARCH32_SP`` : Choose the AArch32 Secure Payload component to be built as as the BL32 image when ``ARCH=aarch32``. The value should be the path to the directory containing the SP source, relative to the ``bl32/``; the directory is expected to contain a makefile called ``.mk``.”h]”(já)”}”(hŒ``AARCH32_SP``”h]”hŒ AARCH32_SP”…””}”(hhh!j ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jubhŒU : Choose the AArch32 Secure Payload component to be built as as the BL32 image when ”…””}”(hŒU : Choose the AArch32 Secure Payload component to be built as as the BL32 image when ”h!jubjá)”}”(hŒ``ARCH=aarch32``”h]”hŒARCH=aarch32”…””}”(hhh!jubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jubhŒZ. The value should be the path to the directory containing the SP source, relative to the ”…””}”(hŒZ. The value should be the path to the directory containing the SP source, relative to the ”h!jubjá)”}”(hŒ ``bl32/``”h]”hŒbl32/”…””}”(hhh!j/ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jubhŒ9; the directory is expected to contain a makefile called ”…””}”(hŒ9; the directory is expected to contain a makefile called ”h!jubjá)”}”(hŒ``.mk``”h]”hŒ.mk”…””}”(hhh!jBubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jubhŒ.”…””}”(hŒ.”h!jubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKh!jubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hŒÊ``AMU_RESTRICT_COUNTERS``: Register reads to the group 1 counters will return zero at all but the highest implemented exception level. Reads from the memory mapped view are unaffected by this control. ”h]”j£)”}”(hŒÉ``AMU_RESTRICT_COUNTERS``: Register reads to the group 1 counters will return zero at all but the highest implemented exception level. Reads from the memory mapped view are unaffected by this control.”h]”(já)”}”(hŒ``AMU_RESTRICT_COUNTERS``”h]”hŒAMU_RESTRICT_COUNTERS”…””}”(hhh!jiubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jeubhŒ°: Register reads to the group 1 counters will return zero at all but the highest implemented exception level. Reads from the memory mapped view are unaffected by this control.”…””}”(hŒ°: Register reads to the group 1 counters will return zero at all but the highest implemented exception level. Reads from the memory mapped view are unaffected by this control.”h!jeubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKh!jaubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hŒ``ARCH`` : Choose the target build architecture for TF-A. It can take either ``aarch64`` or ``aarch32`` as values. By default, it is defined to ``aarch64``. ”h]”j£)”}”(hŒœ``ARCH`` : Choose the target build architecture for TF-A. It can take either ``aarch64`` or ``aarch32`` as values. By default, it is defined to ``aarch64``.”h]”(já)”}”(hŒ``ARCH``”h]”hŒARCH”…””}”(hhh!jubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jŒubhŒE : Choose the target build architecture for TF-A. It can take either ”…””}”(hŒE : Choose the target build architecture for TF-A. It can take either ”h!jŒubjá)”}”(hŒ``aarch64``”h]”hŒaarch64”…””}”(hhh!j£ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jŒubhŒ or ”…””}”(hŒ or ”h!jŒubjá)”}”(hŒ``aarch32``”h]”hŒaarch32”…””}”(hhh!j¶ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jŒubhŒ) as values. By default, it is defined to ”…””}”(hŒ) as values. By default, it is defined to ”h!jŒubjá)”}”(hŒ``aarch64``”h]”hŒaarch64”…””}”(hhh!jÉubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jŒubhŒ.”…””}”(hjTh!jŒubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKh!jˆubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hXH``ARM_ARCH_FEATURE``: Optional Arm Architecture build option which specifies one or more feature modifiers. This option has the form ``[no]feature+...`` and defaults to ``none``. It translates into compiler option ``-march=armvX[.Y]-a+[no]feature+...``. See compiler's documentation for the list of supported feature modifiers. ”h]”j£)”}”(hXG``ARM_ARCH_FEATURE``: Optional Arm Architecture build option which specifies one or more feature modifiers. This option has the form ``[no]feature+...`` and defaults to ``none``. It translates into compiler option ``-march=armvX[.Y]-a+[no]feature+...``. See compiler's documentation for the list of supported feature modifiers.”h]”(já)”}”(hŒ``ARM_ARCH_FEATURE``”h]”hŒARM_ARCH_FEATURE”…””}”(hhh!jïubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jëubhŒq: Optional Arm Architecture build option which specifies one or more feature modifiers. This option has the form ”…””}”(hŒq: Optional Arm Architecture build option which specifies one or more feature modifiers. This option has the form ”h!jëubjá)”}”(hŒ``[no]feature+...``”h]”hŒ[no]feature+...”…””}”(hhh!j ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jëubhŒ and defaults to ”…””}”(hŒ and defaults to ”h!jëubjá)”}”(hŒ``none``”h]”hŒnone”…””}”(hhh!j ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jëubhŒ%. It translates into compiler option ”…””}”(hŒ%. It translates into compiler option ”h!jëubjá)”}”(hŒ&``-march=armvX[.Y]-a+[no]feature+...``”h]”hŒ"-march=armvX[.Y]-a+[no]feature+...”…””}”(hhh!j( ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jëubhŒM. See compilerâ€™s documentation for the list of supported feature modifiers.”…””}”(hŒK. See compiler's documentation for the list of supported feature modifiers.”h!jëubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCK!h!jçubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hŒñ``ARM_ARCH_MAJOR``: The major version of Arm Architecture to target when compiling TF-A. Its value must be numeric, and defaults to 8 . See also, *Armv8 Architecture Extensions* and *Armv7 Architecture Extensions* in :ref:`Firmware Design`. ”h]”j£)”}”(hŒð``ARM_ARCH_MAJOR``: The major version of Arm Architecture to target when compiling TF-A. Its value must be numeric, and defaults to 8 . See also, *Armv8 Architecture Extensions* and *Armv7 Architecture Extensions* in :ref:`Firmware Design`.”h]”(já)”}”(hŒ``ARM_ARCH_MAJOR``”h]”hŒARM_ARCH_MAJOR”…””}”(hhh!jO ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jK ubhŒ€: The major version of Arm Architecture to target when compiling TF-A. Its value must be numeric, and defaults to 8 . See also, ”…””}”(hŒ€: The major version of Arm Architecture to target when compiling TF-A. Its value must be numeric, and defaults to 8 . See also, ”h!jK ubh Œemphasis”“”)”}”(hŒ*Armv8 Architecture Extensions*”h]”hŒArmv8 Architecture Extensions”…””}”(hhh!jd ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jb h!jK ubhŒ and ”…””}”(hŒ and ”h!jK ubjc )”}”(hŒ*Armv7 Architecture Extensions*”h]”hŒArmv7 Architecture Extensions”…””}”(hhh!jw ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jb h!jK ubhŒ in ”…””}”(hŒ in ”h!jK ubh)”}”(hŒ:ref:`Firmware Design`”h]”h)”}”(hjŒ h]”hŒFirmware Design”…””}”(hhh!jŽ ubah"}”(h$]”h&]”(h(Œstd”Œstd-ref”eh+]”h-]”h/]”uh1hh!jŠ ubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”j˜ Œreftype”Œref”Œrefexplicit”‰Œrefwarn”ˆh?Œfirmware design”uh1hhAj¡hCK'h!jK ubhŒ.”…””}”(hjTh!jK ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCK'h!jG ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hŒÎ``ARM_ARCH_MINOR``: The minor version of Arm Architecture to target when compiling TF-A. Its value must be a numeric, and defaults to 0. See also, *Armv8 Architecture Extensions* in :ref:`Firmware Design`. ”h]”j£)”}”(hŒÍ``ARM_ARCH_MINOR``: The minor version of Arm Architecture to target when compiling TF-A. Its value must be a numeric, and defaults to 0. See also, *Armv8 Architecture Extensions* in :ref:`Firmware Design`.”h]”(já)”}”(hŒ``ARM_ARCH_MINOR``”h]”hŒARM_ARCH_MINOR”…””}”(hhh!jÂ ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j¾ ubhŒ: The minor version of Arm Architecture to target when compiling TF-A. Its value must be a numeric, and defaults to 0. See also, ”…””}”(hŒ: The minor version of Arm Architecture to target when compiling TF-A. Its value must be a numeric, and defaults to 0. See also, ”h!j¾ ubjc )”}”(hŒ*Armv8 Architecture Extensions*”h]”hŒArmv8 Architecture Extensions”…””}”(hhh!jÕ ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jb h!j¾ ubhŒ in ”…””}”(hŒ in ”h!j¾ ubh)”}”(hŒ:ref:`Firmware Design`”h]”h)”}”(hjê h]”hŒFirmware Design”…””}”(hhh!jì ubah"}”(h$]”h&]”(h(Œstd”Œstd-ref”eh+]”h-]”h/]”uh1hh!jè ubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”jö Œreftype”Œref”Œrefexplicit”‰Œrefwarn”ˆh?Œfirmware design”uh1hhAj¡hCK,h!j¾ ubhŒ.”…””}”(hjTh!j¾ ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCK,h!jº ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hŒ``BL2``: This is an optional build option which specifies the path to BL2 image for the ``fip`` target. In this case, the BL2 in the TF-A will not be built. ”h]”j£)”}”(hŒœ``BL2``: This is an optional build option which specifies the path to BL2 image for the ``fip`` target. In this case, the BL2 in the TF-A will not be built.”h]”(já)”}”(hŒ``BL2``”h]”hŒBL2”…””}”(hhh!j ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jubhŒQ: This is an optional build option which specifies the path to BL2 image for the ”…””}”(hŒQ: This is an optional build option which specifies the path to BL2 image for the ”h!jubjá)”}”(hŒ``fip``”h]”hŒfip”…””}”(hhh!j3ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jubhŒ= target. In this case, the BL2 in the TF-A will not be built.”…””}”(hŒ= target. In this case, the BL2 in the TF-A will not be built.”h!jubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCK0h!jubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hŒ…``BL2U``: This is an optional build option which specifies the path to BL2U image. In this case, the BL2U in TF-A will not be built. ”h]”j£)”}”(hŒ„``BL2U``: This is an optional build option which specifies the path to BL2U image. In this case, the BL2U in TF-A will not be built.”h]”(já)”}”(hŒ``BL2U``”h]”hŒBL2U”…””}”(hhh!jZubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jVubhŒ|: This is an optional build option which specifies the path to BL2U image. In this case, the BL2U in TF-A will not be built.”…””}”(hŒ|: This is an optional build option which specifies the path to BL2U image. In this case, the BL2U in TF-A will not be built.”h!jVubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCK4h!jRubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hŒe``BL2_AT_EL3``: This is an optional build option that enables the use of BL2 at EL3 execution level. ”h]”j£)”}”(hŒd``BL2_AT_EL3``: This is an optional build option that enables the use of BL2 at EL3 execution level.”h]”(já)”}”(hŒ``BL2_AT_EL3``”h]”hŒ BL2_AT_EL3”…””}”(hhh!jubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j}ubhŒV: This is an optional build option that enables the use of BL2 at EL3 execution level.”…””}”(hŒV: This is an optional build option that enables the use of BL2 at EL3 execution level.”h!j}ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCK7h!jyubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hŒŒ``BL2_ENABLE_SP_LOAD``: Boolean option to enable loading SP packages from the FIP. Automatically enabled if ``SP_LAYOUT_FILE`` is provided. ”h]”j£)”}”(hŒ‹``BL2_ENABLE_SP_LOAD``: Boolean option to enable loading SP packages from the FIP. Automatically enabled if ``SP_LAYOUT_FILE`` is provided.”h]”(já)”}”(hŒ``BL2_ENABLE_SP_LOAD``”h]”hŒBL2_ENABLE_SP_LOAD”…””}”(hhh!j¨ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j¤ubhŒV: Boolean option to enable loading SP packages from the FIP. Automatically enabled if ”…””}”(hŒV: Boolean option to enable loading SP packages from the FIP. Automatically enabled if ”h!j¤ubjá)”}”(hŒ``SP_LAYOUT_FILE``”h]”hŒSP_LAYOUT_FILE”…””}”(hhh!j»ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j¤ubhŒ is provided.”…””}”(hŒ is provided.”h!j¤ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCK:h!j ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hX?``BL2_IN_XIP_MEM``: In some use-cases BL2 will be stored in eXecute In Place (XIP) memory, like BL1. In these use-cases, it is necessary to initialize the RW sections in RAM, while leaving the RO sections in place. This option enable this use-case. For now, this option is only supported when BL2_AT_EL3 is set to '1'. ”h]”j£)”}”(hX>``BL2_IN_XIP_MEM``: In some use-cases BL2 will be stored in eXecute In Place (XIP) memory, like BL1. In these use-cases, it is necessary to initialize the RW sections in RAM, while leaving the RO sections in place. This option enable this use-case. For now, this option is only supported when BL2_AT_EL3 is set to '1'.”h]”(já)”}”(hŒ``BL2_IN_XIP_MEM``”h]”hŒBL2_IN_XIP_MEM”…””}”(hhh!jâubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jÞubhX0: In some use-cases BL2 will be stored in eXecute In Place (XIP) memory, like BL1. In these use-cases, it is necessary to initialize the RW sections in RAM, while leaving the RO sections in place. This option enable this use-case. For now, this option is only supported when BL2_AT_EL3 is set to â€˜1â€™.”…””}”(hX,: In some use-cases BL2 will be stored in eXecute In Place (XIP) memory, like BL1. In these use-cases, it is necessary to initialize the RW sections in RAM, while leaving the RO sections in place. This option enable this use-case. For now, this option is only supported when BL2_AT_EL3 is set to '1'.”h!jÞubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCK=h!jÚubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hŒœ``BL31``: This is an optional build option which specifies the path to BL31 image for the ``fip`` target. In this case, the BL31 in TF-A will not be built. ”h]”j£)”}”(hŒ›``BL31``: This is an optional build option which specifies the path to BL31 image for the ``fip`` target. In this case, the BL31 in TF-A will not be built.”h]”(já)”}”(hŒ``BL31``”h]”hŒBL31”…””}”(hhh!j ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jubhŒR: This is an optional build option which specifies the path to BL31 image for the ”…””}”(hŒR: This is an optional build option which specifies the path to BL31 image for the ”h!jubjá)”}”(hŒ``fip``”h]”hŒfip”…””}”(hhh!jubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jubhŒ: target. In this case, the BL31 in TF-A will not be built.”…””}”(hŒ: target. In this case, the BL31 in TF-A will not be built.”h!jubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKCh!jubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hŒÄ``BL31_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the file that contains the BL31 private key in PEM format. If ``SAVE_KEYS=1``, this file name will be used to save the key. ”h]”j£)”}”(hŒÃ``BL31_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the file that contains the BL31 private key in PEM format. If ``SAVE_KEYS=1``, this file name will be used to save the key.”h]”(já)”}”(hŒ``BL31_KEY``”h]”hŒBL31_KEY”…””}”(hhh!jCubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j?ubhŒ: This option is used when ”…””}”(hŒ: This option is used when ”h!j?ubjá)”}”(hŒ``GENERATE_COT=1``”h]”hŒGENERATE_COT=1”…””}”(hhh!jVubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j?ubhŒM. It specifies the file that contains the BL31 private key in PEM format. If ”…””}”(hŒM. It specifies the file that contains the BL31 private key in PEM format. If ”h!j?ubjá)”}”(hŒ``SAVE_KEYS=1``”h]”hŒSAVE_KEYS=1”…””}”(hhh!jiubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j?ubhŒ., this file name will be used to save the key.”…””}”(hŒ., this file name will be used to save the key.”h!j?ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKGh!j;ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hŒœ``BL32``: This is an optional build option which specifies the path to BL32 image for the ``fip`` target. In this case, the BL32 in TF-A will not be built. ”h]”j£)”}”(hŒ›``BL32``: This is an optional build option which specifies the path to BL32 image for the ``fip`` target. In this case, the BL32 in TF-A will not be built.”h]”(já)”}”(hŒ``BL32``”h]”hŒBL32”…””}”(hhh!jubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jŒubhŒR: This is an optional build option which specifies the path to BL32 image for the ”…””}”(hŒR: This is an optional build option which specifies the path to BL32 image for the ”h!jŒubjá)”}”(hŒ``fip``”h]”hŒfip”…””}”(hhh!j£ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jŒubhŒ: target. In this case, the BL32 in TF-A will not be built.”…””}”(hŒ: target. In this case, the BL32 in TF-A will not be built.”h!jŒubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKKh!jˆubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hŒ``BL32_EXTRA1``: This is an optional build option which specifies the path to Trusted OS Extra1 image for the ``fip`` target. ”h]”j£)”}”(hŒ~``BL32_EXTRA1``: This is an optional build option which specifies the path to Trusted OS Extra1 image for the ``fip`` target.”h]”(já)”}”(hŒ``BL32_EXTRA1``”h]”hŒBL32_EXTRA1”…””}”(hhh!jÊubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jÆubhŒ`: This is an optional build option which specifies the path to Trusted OS Extra1 image for the ”…””}”(hŒ`: This is an optional build option which specifies the path to Trusted OS Extra1 image for the ”h!jÆubjá)”}”(hŒ``fip``”h]”hŒfip”…””}”(hhh!jÝubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jÆubhŒ target.”…””}”(hŒ target.”h!jÆubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKOh!jÂubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hŒ~``BL32_EXTRA2``: This is an optional build option which specifies the path to Trusted OS Extra2 image for the ``fip`` target. ”h]”j£)”}”(hŒ}``BL32_EXTRA2``: This is an optional build option which specifies the path to Trusted OS Extra2 image for the ``fip`` target.”h]”(já)”}”(hŒ``BL32_EXTRA2``”h]”hŒBL32_EXTRA2”…””}”(hhh!jubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jubhŒ_: This is an optional build option which specifies the path to Trusted OS Extra2 image for the ”…””}”(hŒ_: This is an optional build option which specifies the path to Trusted OS Extra2 image for the ”h!jubjá)”}”(hŒ``fip``”h]”hŒfip”…””}”(hhh!jubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jubhŒ target.”…””}”(hŒ target.”h!jubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKRh!jüubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hŒÄ``BL32_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the file that contains the BL32 private key in PEM format. If ``SAVE_KEYS=1``, this file name will be used to save the key. ”h]”j£)”}”(hŒÃ``BL32_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the file that contains the BL32 private key in PEM format. If ``SAVE_KEYS=1``, this file name will be used to save the key.”h]”(já)”}”(hŒ``BL32_KEY``”h]”hŒBL32_KEY”…””}”(hhh!j>ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j:ubhŒ: This option is used when ”…””}”(hŒ: This option is used when ”h!j:ubjá)”}”(hŒ``GENERATE_COT=1``”h]”hŒGENERATE_COT=1”…””}”(hhh!jQubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j:ubhŒM. It specifies the file that contains the BL32 private key in PEM format. If ”…””}”(hŒM. It specifies the file that contains the BL32 private key in PEM format. If ”h!j:ubjá)”}”(hŒ``SAVE_KEYS=1``”h]”hŒSAVE_KEYS=1”…””}”(hhh!jdubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j:ubhŒ., this file name will be used to save the key.”…””}”(hŒ., this file name will be used to save the key.”h!j:ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKUh!j6ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hŒu``BL33``: Path to BL33 image in the host file system. This is mandatory for ``fip`` target in case TF-A BL2 is used. ”h]”j£)”}”(hŒt``BL33``: Path to BL33 image in the host file system. This is mandatory for ``fip`` target in case TF-A BL2 is used.”h]”(já)”}”(hŒ``BL33``”h]”hŒBL33”…””}”(hhh!j‹ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j‡ubhŒD: Path to BL33 image in the host file system. This is mandatory for ”…””}”(hŒD: Path to BL33 image in the host file system. This is mandatory for ”h!j‡ubjá)”}”(hŒ``fip``”h]”hŒfip”…””}”(hhh!jžubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j‡ubhŒ! target in case TF-A BL2 is used.”…””}”(hŒ! target in case TF-A BL2 is used.”h!j‡ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKYh!jƒubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hŒÄ``BL33_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the file that contains the BL33 private key in PEM format. If ``SAVE_KEYS=1``, this file name will be used to save the key. ”h]”j£)”}”(hŒÃ``BL33_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the file that contains the BL33 private key in PEM format. If ``SAVE_KEYS=1``, this file name will be used to save the key.”h]”(já)”}”(hŒ``BL33_KEY``”h]”hŒBL33_KEY”…””}”(hhh!jÅubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jÁubhŒ: This option is used when ”…””}”(hŒ: This option is used when ”h!jÁubjá)”}”(hŒ``GENERATE_COT=1``”h]”hŒGENERATE_COT=1”…””}”(hhh!jØubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jÁubhŒM. It specifies the file that contains the BL33 private key in PEM format. If ”…””}”(hŒM. It specifies the file that contains the BL33 private key in PEM format. If ”h!jÁubjá)”}”(hŒ``SAVE_KEYS=1``”h]”hŒSAVE_KEYS=1”…””}”(hhh!jëubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jÁubhŒ., this file name will be used to save the key.”…””}”(hŒ., this file name will be used to save the key.”h!jÁubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCK\h!j½ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hX)``BRANCH_PROTECTION``: Numeric value to enable ARMv8.3 Pointer Authentication and ARMv8.5 Branch Target Identification support for TF-A BL images themselves. If enabled, it is needed to use a compiler that supports the option ``-mbranch-protection``. Selects the branch protection features to use:”h]”j£)”}”(hX)``BRANCH_PROTECTION``: Numeric value to enable ARMv8.3 Pointer Authentication and ARMv8.5 Branch Target Identification support for TF-A BL images themselves. If enabled, it is needed to use a compiler that supports the option ``-mbranch-protection``. Selects the branch protection features to use:”h]”(já)”}”(hŒ``BRANCH_PROTECTION``”h]”hŒBRANCH_PROTECTION”…””}”(hhh!jubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jubhŒÍ: Numeric value to enable ARMv8.3 Pointer Authentication and ARMv8.5 Branch Target Identification support for TF-A BL images themselves. If enabled, it is needed to use a compiler that supports the option ”…””}”(hŒÍ: Numeric value to enable ARMv8.3 Pointer Authentication and ARMv8.5 Branch Target Identification support for TF-A BL images themselves. If enabled, it is needed to use a compiler that supports the option ”h!jubjá)”}”(hŒ``-mbranch-protection``”h]”hŒ-mbranch-protection”…””}”(hhh!j%ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jubhŒ0. Selects the branch protection features to use:”…””}”(hŒ0. Selects the branch protection features to use:”h!jubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCK`h!j ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hŒ90: Default value turns off all types of branch protection”h]”j£)”}”(hjFh]”hŒ90: Default value turns off all types of branch protection”…””}”(hjFh!jHubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKdh!jDubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hŒ21: Enables all types of branch protection features”h]”j£)”}”(hj]h]”hŒ21: Enables all types of branch protection features”…””}”(hj]h!j_ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKeh!j[ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hŒ/2: Return address signing to its standard level”h]”j£)”}”(hjth]”hŒ/2: Return address signing to its standard level”…””}”(hjth!jvubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKfh!jrubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hŒ/3: Extend the signing to include leaf functions”h]”j£)”}”(hj‹h]”hŒ/3: Extend the signing to include leaf functions”…””}”(hj‹h!jubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKgh!j‰ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hX@4: Turn on branch target identification mechanism The table below summarizes ``BRANCH_PROTECTION`` values, GCC compilation options and resulting PAuth/BTI features. +-------+--------------+-------+-----+ | Value | GCC option | PAuth | BTI | +=======+==============+=======+=====+ | 0 | none | N | N | +-------+--------------+-------+-----+ | 1 | standard | Y | Y | +-------+--------------+-------+-----+ | 2 | pac-ret | Y | N | +-------+--------------+-------+-----+ | 3 | pac-ret+leaf | Y | N | +-------+--------------+-------+-----+ | 4 | bti | N | Y | +-------+--------------+-------+-----+ This option defaults to 0. Note that Pointer Authentication is enabled for Non-secure world irrespective of the value of this option if the CPU supports it. ”h]”(j£)”}”(hŒ14: Turn on branch target identification mechanism”h]”hŒ14: Turn on branch target identification mechanism”…””}”(hj¦h!j¤ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKhh!j ubj£)”}”(hŒrThe table below summarizes ``BRANCH_PROTECTION`` values, GCC compilation options and resulting PAuth/BTI features.”h]”(hŒThe table below summarizes ”…””}”(hŒThe table below summarizes ”h!j²ubjá)”}”(hŒ``BRANCH_PROTECTION``”h]”hŒBRANCH_PROTECTION”…””}”(hhh!j»ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j²ubhŒB values, GCC compilation options and resulting PAuth/BTI features.”…””}”(hŒB values, GCC compilation options and resulting PAuth/BTI features.”h!j²ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKjh!j ubh Œtable”“”)”}”(hhh]”h Œtgroup”“”)”}”(hhh]”(h Œcolspec”“”)”}”(hhh]”h"}”(h$]”h&]”h+]”h-]”h/]”Œcolwidth”Kuh1jÞh!jÛubjß)”}”(hhh]”h"}”(h$]”h&]”h+]”h-]”h/]”Œcolwidth”Kuh1jÞh!jÛubjß)”}”(hhh]”h"}”(h$]”h&]”h+]”h-]”h/]”Œcolwidth”Kuh1jÞh!jÛubjß)”}”(hhh]”h"}”(h$]”h&]”h+]”h-]”h/]”Œcolwidth”Kuh1jÞh!jÛubh Œthead”“”)”}”(hhh]”h Œrow”“”)”}”(hhh]”(h Œentry”“”)”}”(hhh]”j£)”}”(hŒValue”h]”hŒValue”…””}”(hjh!jubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKnh!jubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jubj)”}”(hhh]”j£)”}”(hŒ GCC option”h]”hŒ GCC option”…””}”(hj0h!j.ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKnh!j+ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jubj)”}”(hhh]”j£)”}”(hŒPAuth”h]”hŒPAuth”…””}”(hjGh!jEubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKnh!jBubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jubj)”}”(hhh]”j£)”}”(hŒBTI”h]”hŒBTI”…””}”(hj^h!j\ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKnh!jYubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j h!j ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jÛubh Œtbody”“”)”}”(hhh]”(j)”}”(hhh]”(j)”}”(hhh]”j£)”}”(hŒ0”h]”hŒ0”…””}”(hj‰h!j‡ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKph!j„ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jubj)”}”(hhh]”j£)”}”(hŒnone”h]”hŒnone”…””}”(hj h!jžubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKph!j›ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jubj)”}”(hhh]”j£)”}”(hŒN”h]”hŒN”…””}”(hj·h!jµubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKph!j²ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jubj)”}”(hhh]”j£)”}”(hj·h]”hŒN”…””}”(hj·h!jÌubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKph!jÉubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j h!j~ubj)”}”(hhh]”(j)”}”(hhh]”j£)”}”(hŒ1”h]”hŒ1”…””}”(hjíh!jëubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKrh!jèubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jåubj)”}”(hhh]”j£)”}”(hŒstandard”h]”hŒstandard”…””}”(hjh!jubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKrh!jÿubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jåubj)”}”(hhh]”j£)”}”(hŒY”h]”hŒY”…””}”(hjh!jubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKrh!jubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jåubj)”}”(hhh]”j£)”}”(hjh]”hŒY”…””}”(hjh!j0ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKrh!j-ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jåubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j h!j~ubj)”}”(hhh]”(j)”}”(hhh]”j£)”}”(hŒ2”h]”hŒ2”…””}”(hjQh!jOubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKth!jLubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jIubj)”}”(hhh]”j£)”}”(hŒpac-ret”h]”hŒpac-ret”…””}”(hjhh!jfubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKth!jcubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jIubj)”}”(hhh]”j£)”}”(hjh]”hŒY”…””}”(hjh!j}ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKth!jzubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jIubj)”}”(hhh]”j£)”}”(hj·h]”hŒN”…””}”(hj·h!j“ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKth!jubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jIubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j h!j~ubj)”}”(hhh]”(j)”}”(hhh]”j£)”}”(hŒ3”h]”hŒ3”…””}”(hj´h!j²ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKvh!j¯ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!j¬ubj)”}”(hhh]”j£)”}”(hŒpac-ret+leaf”h]”hŒpac-ret+leaf”…””}”(hjËh!jÉubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKvh!jÆubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!j¬ubj)”}”(hhh]”j£)”}”(hjh]”hŒY”…””}”(hjh!jàubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKvh!jÝubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!j¬ubj)”}”(hhh]”j£)”}”(hj·h]”hŒN”…””}”(hj·h!jöubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKvh!jóubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!j¬ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j h!j~ubj)”}”(hhh]”(j)”}”(hhh]”j£)”}”(hŒ4”h]”hŒ4”…””}”(hjh!jubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKxh!jubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jubj)”}”(hhh]”j£)”}”(hŒbti”h]”hŒbti”…””}”(hj.h!j,ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKxh!j)ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jubj)”}”(hhh]”j£)”}”(hj·h]”hŒN”…””}”(hj·h!jCubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKxh!j@ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jubj)”}”(hhh]”j£)”}”(hjh]”hŒY”…””}”(hjh!jYubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKxh!jVubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j h!j~ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j|h!jÛubeh"}”(h$]”h&]”h+]”h-]”h/]”Œcols”Kuh1jÙh!jÖubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÔh!j ubj£)”}”(hŒœThis option defaults to 0. Note that Pointer Authentication is enabled for Non-secure world irrespective of the value of this option if the CPU supports it.”h]”hŒœThis option defaults to 0. Note that Pointer Authentication is enabled for Non-secure world irrespective of the value of this option if the CPU supports it.”…””}”(hj‡h!j…ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCK{h!j ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hŒô``BUILD_MESSAGE_TIMESTAMP``: String used to identify the time and date of the compilation of each build. It must be set to a C string (including quotes where applicable). Defaults to a string that contains the time and date of the compilation. ”h]”j£)”}”(hŒó``BUILD_MESSAGE_TIMESTAMP``: String used to identify the time and date of the compilation of each build. It must be set to a C string (including quotes where applicable). Defaults to a string that contains the time and date of the compilation.”h]”(já)”}”(hŒ``BUILD_MESSAGE_TIMESTAMP``”h]”hŒBUILD_MESSAGE_TIMESTAMP”…””}”(hhh!j¡ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jubhŒØ: String used to identify the time and date of the compilation of each build. It must be set to a C string (including quotes where applicable). Defaults to a string that contains the time and date of the compilation.”…””}”(hŒØ: String used to identify the time and date of the compilation of each build. It must be set to a C string (including quotes where applicable). Defaults to a string that contains the time and date of the compilation.”h!jubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKh!j™ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hŒ‘``BUILD_STRING``: Input string for VERSION_STRING, which allows the TF-A build to be uniquely identified. Defaults to the current git commit id. ”h]”j£)”}”(hŒ``BUILD_STRING``: Input string for VERSION_STRING, which allows the TF-A build to be uniquely identified. Defaults to the current git commit id.”h]”(já)”}”(hŒ``BUILD_STRING``”h]”hŒBUILD_STRING”…””}”(hhh!jÈubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jÄubhŒ€: Input string for VERSION_STRING, which allows the TF-A build to be uniquely identified. Defaults to the current git commit id.”…””}”(hŒ€: Input string for VERSION_STRING, which allows the TF-A build to be uniquely identified. Defaults to the current git commit id.”h!jÄubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCK„h!jÀubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hŒH``BUILD_BASE``: Output directory for the build. Defaults to ``./build`` ”h]”j£)”}”(hŒG``BUILD_BASE``: Output directory for the build. Defaults to ``./build``”h]”(já)”}”(hŒ``BUILD_BASE``”h]”hŒ BUILD_BASE”…””}”(hhh!jïubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jëubhŒ.: Output directory for the build. Defaults to ”…””}”(hŒ.: Output directory for the build. Defaults to ”h!jëubjá)”}”(hŒ``./build``”h]”hŒ./build”…””}”(hhh!jubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jëubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCK‡h!jçubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hŒ{``CFLAGS``: Extra user options appended on the compiler's command line in addition to the options set by the build system. ”h]”j£)”}”(hŒz``CFLAGS``: Extra user options appended on the compiler's command line in addition to the options set by the build system.”h]”(já)”}”(hŒ ``CFLAGS``”h]”hŒCFLAGS”…””}”(hhh!j$ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j ubhŒr: Extra user options appended on the compilerâ€™s command line in addition to the options set by the build system.”…””}”(hŒp: Extra user options appended on the compiler's command line in addition to the options set by the build system.”h!j ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCK‰h!jubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hX``COLD_BOOT_SINGLE_CPU``: This option indicates whether the platform may release several CPUs out of reset. It can take either 0 (several CPUs may be brought up) or 1 (only one CPU will ever be brought up during cold reset). Default is 0. If the platform always brings up a single CPU, there is no need to distinguish between primary and secondary CPUs and the boot path can be optimised. The ``plat_is_my_cpu_primary()`` and ``plat_secondary_cold_boot_setup()`` platform porting interfaces do not need to be implemented in this case. ”h]”j£)”}”(hX``COLD_BOOT_SINGLE_CPU``: This option indicates whether the platform may release several CPUs out of reset. It can take either 0 (several CPUs may be brought up) or 1 (only one CPU will ever be brought up during cold reset). Default is 0. If the platform always brings up a single CPU, there is no need to distinguish between primary and secondary CPUs and the boot path can be optimised. The ``plat_is_my_cpu_primary()`` and ``plat_secondary_cold_boot_setup()`` platform porting interfaces do not need to be implemented in this case.”h]”(já)”}”(hŒ``COLD_BOOT_SINGLE_CPU``”h]”hŒCOLD_BOOT_SINGLE_CPU”…””}”(hhh!jKubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jGubhXq: This option indicates whether the platform may release several CPUs out of reset. It can take either 0 (several CPUs may be brought up) or 1 (only one CPU will ever be brought up during cold reset). Default is 0. If the platform always brings up a single CPU, there is no need to distinguish between primary and secondary CPUs and the boot path can be optimised. The ”…””}”(hXq: This option indicates whether the platform may release several CPUs out of reset. It can take either 0 (several CPUs may be brought up) or 1 (only one CPU will ever be brought up during cold reset). Default is 0. If the platform always brings up a single CPU, there is no need to distinguish between primary and secondary CPUs and the boot path can be optimised. The ”•zh!jGubjá)”}”(hŒ``plat_is_my_cpu_primary()``”h]”hŒplat_is_my_cpu_primary()”…””}”(hhh!j^ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jGubhŒ and ”…””}”(hŒ and ”h!jGubjá)”}”(hŒ$``plat_secondary_cold_boot_setup()``”h]”hŒ plat_secondary_cold_boot_setup()”…””}”(hhh!jqubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jGubhŒH platform porting interfaces do not need to be implemented in this case.”…””}”(hŒH platform porting interfaces do not need to be implemented in this case.”h!jGubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKŒh!jCubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hŒa``COT``: When Trusted Boot is enabled, selects the desired chain of trust. Defaults to ``tbbr``. ”h]”j£)”}”(hŒ```COT``: When Trusted Boot is enabled, selects the desired chain of trust. Defaults to ``tbbr``.”h]”(já)”}”(hŒ``COT``”h]”hŒCOT”…””}”(hhh!j˜ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j”ubhŒP: When Trusted Boot is enabled, selects the desired chain of trust. Defaults to ”…””}”(hŒP: When Trusted Boot is enabled, selects the desired chain of trust. Defaults to ”h!j”ubjá)”}”(hŒ``tbbr``”h]”hŒtbbr”…””}”(hhh!j«ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j”ubhŒ.”…””}”(hjTh!j”ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCK•h!jubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hX``CRASH_REPORTING``: A non-zero value enables a console dump of processor register state when an unexpected exception occurs during execution of BL31. This option defaults to the value of ``DEBUG`` - i.e. by default this is only enabled for a debug build of the firmware. ”h]”j£)”}”(hX``CRASH_REPORTING``: A non-zero value enables a console dump of processor register state when an unexpected exception occurs during execution of BL31. This option defaults to the value of ``DEBUG`` - i.e. by default this is only enabled for a debug build of the firmware.”h]”(já)”}”(hŒ``CRASH_REPORTING``”h]”hŒCRASH_REPORTING”…””}”(hhh!jÑubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jÍubhŒ©: A non-zero value enables a console dump of processor register state when an unexpected exception occurs during execution of BL31. This option defaults to the value of ”…””}”(hŒ©: A non-zero value enables a console dump of processor register state when an unexpected exception occurs during execution of BL31. This option defaults to the value of ”h!jÍubjá)”}”(hŒ ``DEBUG``”h]”hŒDEBUG”…””}”(hhh!jäubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jÍubhŒJ - i.e. by default this is only enabled for a debug build of the firmware.”…””}”(hŒJ - i.e. by default this is only enabled for a debug build of the firmware.”h!jÍubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCK˜h!jÉubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hŒÚ``CREATE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the certificate generation tool to create new keys in case no valid keys are present or specified. Allowed options are '0' or '1'. Default is '1'. ”h]”j£)”}”(hŒÙ``CREATE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the certificate generation tool to create new keys in case no valid keys are present or specified. Allowed options are '0' or '1'. Default is '1'.”h]”(já)”}”(hŒ``CREATE_KEYS``”h]”hŒCREATE_KEYS”…””}”(hhh!jubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jubhŒ: This option is used when ”…””}”(hŒ: This option is used when ”h!jubjá)”}”(hŒ``GENERATE_COT=1``”h]”hŒGENERATE_COT=1”…””}”(hhh!jubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jubhŒ©. It tells the certificate generation tool to create new keys in case no valid keys are present or specified. Allowed options are â€˜0â€™ or â€˜1â€™. Default is â€˜1â€™.”…””}”(hŒ. It tells the certificate generation tool to create new keys in case no valid keys are present or specified. Allowed options are '0' or '1'. Default is '1'.”h!jubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKh!jubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hXN``CTX_INCLUDE_AARCH32_REGS`` : Boolean option that, when set to 1, will cause the AArch32 system registers to be included when saving and restoring the CPU context. The option must be set to 0 for AArch64-only platforms (that is on hardware that does not implement AArch32, or at least not at EL1 and higher ELs). Default value is 1. ”h]”j£)”}”(hXM``CTX_INCLUDE_AARCH32_REGS`` : Boolean option that, when set to 1, will cause the AArch32 system registers to be included when saving and restoring the CPU context. The option must be set to 0 for AArch64-only platforms (that is on hardware that does not implement AArch32, or at least not at EL1 and higher ELs). Default value is 1.”h]”(já)”}”(hŒ``CTX_INCLUDE_AARCH32_REGS``”h]”hŒCTX_INCLUDE_AARCH32_REGS”…””}”(hhh!jEubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jAubhX1 : Boolean option that, when set to 1, will cause the AArch32 system registers to be included when saving and restoring the CPU context. The option must be set to 0 for AArch64-only platforms (that is on hardware that does not implement AArch32, or at least not at EL1 and higher ELs). Default value is 1.”…””}”(hX1 : Boolean option that, when set to 1, will cause the AArch32 system registers to be included when saving and restoring the CPU context. The option must be set to 0 for AArch64-only platforms (that is on hardware that does not implement AArch32, or at least not at EL1 and higher ELs). Default value is 1.”h!jAubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCK¡h!j=ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hXG``CTX_INCLUDE_EL2_REGS`` : This boolean option provides context save/restore operations when entering/exiting an EL2 execution context. This is of primary interest when Armv8.4-SecEL2 extension is implemented. Default is 0 (disabled). This option must be equal to 1 (enabled) when ``SPD=spmd`` and ``SPMD_SPM_AT_SEL2`` is set. ”h]”j£)”}”(hXF``CTX_INCLUDE_EL2_REGS`` : This boolean option provides context save/restore operations when entering/exiting an EL2 execution context. This is of primary interest when Armv8.4-SecEL2 extension is implemented. Default is 0 (disabled). This option must be equal to 1 (enabled) when ``SPD=spmd`` and ``SPMD_SPM_AT_SEL2`` is set.”h]”(já)”}”(hŒ``CTX_INCLUDE_EL2_REGS``”h]”hŒCTX_INCLUDE_EL2_REGS”…””}”(hhh!jlubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jhubhX : This boolean option provides context save/restore operations when entering/exiting an EL2 execution context. This is of primary interest when Armv8.4-SecEL2 extension is implemented. Default is 0 (disabled). This option must be equal to 1 (enabled) when ”…””}”(hX : This boolean option provides context save/restore operations when entering/exiting an EL2 execution context. This is of primary interest when Armv8.4-SecEL2 extension is implemented. Default is 0 (disabled). This option must be equal to 1 (enabled) when ”h!jhubjá)”}”(hŒ``SPD=spmd``”h]”hŒSPD=spmd”…””}”(hhh!jubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jhubhŒ and ”…””}”(hŒ and ”h!jhubjá)”}”(hŒ``SPMD_SPM_AT_SEL2``”h]”hŒSPMD_SPM_AT_SEL2”…””}”(hhh!j’ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jhubhŒ is set.”…””}”(hŒ is set.”h!jhubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCK§h!jdubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hŒ ``CTX_INCLUDE_FPREGS``: Boolean option that, when set to 1, will cause the FP registers to be included when saving and restoring the CPU context. Default is 0. ”h]”j£)”}”(hŒŸ``CTX_INCLUDE_FPREGS``: Boolean option that, when set to 1, will cause the FP registers to be included when saving and restoring the CPU context. Default is 0.”h]”(já)”}”(hŒ``CTX_INCLUDE_FPREGS``”h]”hŒCTX_INCLUDE_FPREGS”…””}”(hhh!j¹ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jµubhŒ‰: Boolean option that, when set to 1, will cause the FP registers to be included when saving and restoring the CPU context. Default is 0.”…””}”(hŒ‰: Boolean option that, when set to 1, will cause the FP registers to be included when saving and restoring the CPU context. Default is 0.”h!jµubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKh!j±ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hŒ¼``CTX_INCLUDE_NEVE_REGS``: Boolean option that, when set to 1, will cause the Armv8.4-NV registers to be saved/restored when entering/exiting an EL2 execution context. Default value is 0. ”h]”j£)”}”(hŒ»``CTX_INCLUDE_NEVE_REGS``: Boolean option that, when set to 1, will cause the Armv8.4-NV registers to be saved/restored when entering/exiting an EL2 execution context. Default value is 0.”h]”(já)”}”(hŒ``CTX_INCLUDE_NEVE_REGS``”h]”hŒCTX_INCLUDE_NEVE_REGS”…””}”(hhh!jàubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jÜubhŒ¢: Boolean option that, when set to 1, will cause the Armv8.4-NV registers to be saved/restored when entering/exiting an EL2 execution context. Default value is 0.”…””}”(hŒ¢: Boolean option that, when set to 1, will cause the Armv8.4-NV registers to be saved/restored when entering/exiting an EL2 execution context. Default value is 0.”h!jÜubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCK±h!jØubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hXƒ``CTX_INCLUDE_PAUTH_REGS``: Boolean option that, when set to 1, enables Pointer Authentication for Secure world. This will cause the ARMv8.3-PAuth registers to be included when saving and restoring the CPU context as part of world switch. Default value is 0. Note that Pointer Authentication is enabled for Non-secure world irrespective of the value of this flag if the CPU supports it. ”h]”j£)”}”(hX‚``CTX_INCLUDE_PAUTH_REGS``: Boolean option that, when set to 1, enables Pointer Authentication for Secure world. This will cause the ARMv8.3-PAuth registers to be included when saving and restoring the CPU context as part of world switch. Default value is 0. Note that Pointer Authentication is enabled for Non-secure world irrespective of the value of this flag if the CPU supports it.”h]”(já)”}”(hŒ``CTX_INCLUDE_PAUTH_REGS``”h]”hŒCTX_INCLUDE_PAUTH_REGS”…””}”(hhh!jubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jubhXh: Boolean option that, when set to 1, enables Pointer Authentication for Secure world. This will cause the ARMv8.3-PAuth registers to be included when saving and restoring the CPU context as part of world switch. Default value is 0. Note that Pointer Authentication is enabled for Non-secure world irrespective of the value of this flag if the CPU supports it.”…””}”(hXh: Boolean option that, when set to 1, enables Pointer Authentication for Secure world. This will cause the ARMv8.3-PAuth registers to be included when saving and restoring the CPU context as part of world switch. Default value is 0. Note that Pointer Authentication is enabled for Non-secure world irrespective of the value of this flag if the CPU supports it.”h!jubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKµh!jÿubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hŒ``DEBUG``: Chooses between a debug and release build. It can take either 0 (release) or 1 (debug) as values. 0 is the default. ”h]”j£)”}”(hŒ~``DEBUG``: Chooses between a debug and release build. It can take either 0 (release) or 1 (debug) as values. 0 is the default.”h]”(já)”}”(hŒ ``DEBUG``”h]”hŒDEBUG”…””}”(hhh!j.ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j*ubhŒu: Chooses between a debug and release build. It can take either 0 (release) or 1 (debug) as values. 0 is the default.”…””}”(hŒu: Chooses between a debug and release build. It can take either 0 (release) or 1 (debug) as values. 0 is the default.”h!j*ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCK¼h!j&ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hX;``DECRYPTION_SUPPORT``: This build flag enables the user to select the authenticated decryption algorithm to be used to decrypt firmware/s during boot. It accepts 2 values: ``aes_gcm`` and ``none``. The default value of this flag is ``none`` to disable firmware decryption which is an optional feature as per TBBR. ”h]”j£)”}”(hX:``DECRYPTION_SUPPORT``: This build flag enables the user to select the authenticated decryption algorithm to be used to decrypt firmware/s during boot. It accepts 2 values: ``aes_gcm`` and ``none``. The default value of this flag is ``none`` to disable firmware decryption which is an optional feature as per TBBR.”h]”(já)”}”(hŒ``DECRYPTION_SUPPORT``”h]”hŒDECRYPTION_SUPPORT”…””}”(hhh!jUubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jQubhŒ—: This build flag enables the user to select the authenticated decryption algorithm to be used to decrypt firmware/s during boot. It accepts 2 values: ”…””}”(hŒ—: This build flag enables the user to select the authenticated decryption algorithm to be used to decrypt firmware/s during boot. It accepts 2 values: ”h!jQubjá)”}”(hŒ``aes_gcm``”h]”hŒaes_gcm”…””}”(hhh!jhubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jQubhŒ and ”…””}”(hŒ and ”h!jQubjá)”}”(hŒ``none``”h]”hŒnone”…””}”(hhh!j{ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jQubhŒ$. The default value of this flag is ”…””}”(hŒ$. The default value of this flag is ”h!jQubjá)”}”(hŒ``none``”h]”hŒnone”…””}”(hhh!jŽubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jQubhŒI to disable firmware decryption which is an optional feature as per TBBR.”…””}”(hŒI to disable firmware decryption which is an optional feature as per TBBR.”h!jQubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCK¿h!jMubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hŒ›``DISABLE_BIN_GENERATION``: Boolean option to disable the generation of the binary image. If set to 1, then only the ELF image is built. 0 is the default. ”h]”j£)”}”(hŒš``DISABLE_BIN_GENERATION``: Boolean option to disable the generation of the binary image. If set to 1, then only the ELF image is built. 0 is the default.”h]”(já)”}”(hŒ``DISABLE_BIN_GENERATION``”h]”hŒDISABLE_BIN_GENERATION”…””}”(hhh!jµubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j±ubhŒ€: Boolean option to disable the generation of the binary image. If set to 1, then only the ELF image is built. 0 is the default.”…””}”(hŒ€: Boolean option to disable the generation of the binary image. If set to 1, then only the ELF image is built. 0 is the default.”h!j±ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKÅh!jubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hŒô``DISABLE_MTPMU``: Boolean option to disable FEAT_MTPMU if implemented (Armv8.6 onwards). Its default value is 0 to keep consistency with platforms that do not implement FEAT_MTPMU. For more information on FEAT_MTPMU, check the latest Arm ARM. ”h]”j£)”}”(hŒó``DISABLE_MTPMU``: Boolean option to disable FEAT_MTPMU if implemented (Armv8.6 onwards). Its default value is 0 to keep consistency with platforms that do not implement FEAT_MTPMU. For more information on FEAT_MTPMU, check the latest Arm ARM.”h]”(já)”}”(hŒ``DISABLE_MTPMU``”h]”hŒ DISABLE_MTPMU”…””}”(hhh!jÜubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jØubhŒâ: Boolean option to disable FEAT_MTPMU if implemented (Armv8.6 onwards). Its default value is 0 to keep consistency with platforms that do not implement FEAT_MTPMU. For more information on FEAT_MTPMU, check the latest Arm ARM.”…””}”(hŒâ: Boolean option to disable FEAT_MTPMU if implemented (Armv8.6 onwards). Its default value is 0 to keep consistency with platforms that do not implement FEAT_MTPMU. For more information on FEAT_MTPMU, check the latest Arm ARM.”h!jØubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKÉh!jÔubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hX``DYN_DISABLE_AUTH``: Provides the capability to dynamically disable Trusted Board Boot authentication at runtime. This option is meant to be enabled only for development platforms. ``TRUSTED_BOARD_BOOT`` flag must be set if this flag has to be enabled. 0 is the default. ”h]”j£)”}”(hX``DYN_DISABLE_AUTH``: Provides the capability to dynamically disable Trusted Board Boot authentication at runtime. This option is meant to be enabled only for development platforms. ``TRUSTED_BOARD_BOOT`` flag must be set if this flag has to be enabled. 0 is the default.”h]”(já)”}”(hŒ``DYN_DISABLE_AUTH``”h]”hŒDYN_DISABLE_AUTH”…””}”(hhh!jubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jÿubhŒ¢: Provides the capability to dynamically disable Trusted Board Boot authentication at runtime. This option is meant to be enabled only for development platforms. ”…””}”(hŒ¢: Provides the capability to dynamically disable Trusted Board Boot authentication at runtime. This option is meant to be enabled only for development platforms. ”h!jÿubjá)”}”(hŒ``TRUSTED_BOARD_BOOT``”h]”hŒTRUSTED_BOARD_BOOT”…””}”(hhh!jubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jÿubhŒC flag must be set if this flag has to be enabled. 0 is the default.”…””}”(hŒC flag must be set if this flag has to be enabled. 0 is the default.”h!jÿubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKÎh!jûubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hŒB``E``: Boolean option to make warnings into errors. Default is 1. ”h]”j£)”}”(hŒA``E``: Boolean option to make warnings into errors. Default is 1.”h]”(já)”}”(hŒ``E``”h]”hŒE”…””}”(hhh!j=ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j9ubhŒ<: Boolean option to make warnings into errors. Default is 1.”…””}”(hŒ<: Boolean option to make warnings into errors. Default is 1.”h!j9ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKÓh!j5ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hŒå``EL3_PAYLOAD_BASE``: This option enables booting an EL3 payload instead of the normal boot flow. It must specify the entry point address of the EL3 payload. Please refer to the "Booting an EL3 payload" section for more details. ”h]”j£)”}”(hŒä``EL3_PAYLOAD_BASE``: This option enables booting an EL3 payload instead of the normal boot flow. It must specify the entry point address of the EL3 payload. Please refer to the "Booting an EL3 payload" section for more details.”h]”(já)”}”(hŒ``EL3_PAYLOAD_BASE``”h]”hŒEL3_PAYLOAD_BASE”…””}”(hhh!jdubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j`ubhŒÔ: This option enables booting an EL3 payload instead of the normal boot flow. It must specify the entry point address of the EL3 payload. Please refer to the â€œBooting an EL3 payloadâ€ section for more details.”…””}”(hŒÐ: This option enables booting an EL3 payload instead of the normal boot flow. It must specify the entry point address of the EL3 payload. Please refer to the "Booting an EL3 payload" section for more details.”h!j`ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKÕh!j\ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hX``ENABLE_AMU``: Boolean option to enable Activity Monitor Unit extensions. This is an optional architectural feature available on v8.4 onwards. Some v8.2 implementations also implement an AMU and this option can be used to enable this feature on those systems as well. Default is 0. ”h]”j£)”}”(hX``ENABLE_AMU``: Boolean option to enable Activity Monitor Unit extensions. This is an optional architectural feature available on v8.4 onwards. Some v8.2 implementations also implement an AMU and this option can be used to enable this feature on those systems as well. Default is 0.”h]”(já)”}”(hŒ``ENABLE_AMU``”h]”hŒ ENABLE_AMU”…””}”(hhh!j‹ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j‡ubhX: Boolean option to enable Activity Monitor Unit extensions. This is an optional architectural feature available on v8.4 onwards. Some v8.2 implementations also implement an AMU and this option can be used to enable this feature on those systems as well. Default is 0.”…””}”(hX: Boolean option to enable Activity Monitor Unit extensions. This is an optional architectural feature available on v8.4 onwards. Some v8.2 implementations also implement an AMU and this option can be used to enable this feature on those systems as well. Default is 0.”h!j‡ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKÚh!jƒubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hŒà``ENABLE_AMU_AUXILIARY_COUNTERS``: Enables support for AMU auxiliary counters (also known as group 1 counters). These are implementation-defined counters, and as such require additional platform configuration. Default is 0. ”h]”j£)”}”(hŒß``ENABLE_AMU_AUXILIARY_COUNTERS``: Enables support for AMU auxiliary counters (also known as group 1 counters). These are implementation-defined counters, and as such require additional platform configuration. Default is 0.”h]”(já)”}”(hŒ!``ENABLE_AMU_AUXILIARY_COUNTERS``”h]”hŒENABLE_AMU_AUXILIARY_COUNTERS”…””}”(hhh!j²ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j®ubhŒ¾: Enables support for AMU auxiliary counters (also known as group 1 counters). These are implementation-defined counters, and as such require additional platform configuration. Default is 0.”…””}”(hŒ¾: Enables support for AMU auxiliary counters (also known as group 1 counters). These are implementation-defined counters, and as such require additional platform configuration. Default is 0.”h!j®ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKßh!jªubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hŒ¼``ENABLE_AMU_FCONF``: Enables configuration of the AMU through FCONF, which allows platforms with auxiliary counters to describe them via the ``HW_CONFIG`` device tree blob. Default is 0. ”h]”j£)”}”(hŒ»``ENABLE_AMU_FCONF``: Enables configuration of the AMU through FCONF, which allows platforms with auxiliary counters to describe them via the ``HW_CONFIG`` device tree blob. Default is 0.”h]”(já)”}”(hŒ``ENABLE_AMU_FCONF``”h]”hŒENABLE_AMU_FCONF”…””}”(hhh!jÙubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jÕubhŒz: Enables configuration of the AMU through FCONF, which allows platforms with auxiliary counters to describe them via the ”…””}”(hŒz: Enables configuration of the AMU through FCONF, which allows platforms with auxiliary counters to describe them via the ”h!jÕubjá)”}”(hŒ ``HW_CONFIG``”h]”hŒ HW_CONFIG”…””}”(hhh!jìubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jÕubhŒ device tree blob. Default is 0.”…””}”(hŒ device tree blob. Default is 0.”h!jÕubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKãh!jÑubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hXÔ``ENABLE_ASSERTIONS``: This option controls whether or not calls to ``assert()`` are compiled out. For debug builds, this option defaults to 1, and calls to ``assert()`` are left in place. For release builds, this option defaults to 0 and calls to ``assert()`` function are compiled out. This option can be set independently of ``DEBUG``. It can also be used to hide any auxiliary code that is only required for the assertion and does not fit in the assertion itself. ”h]”j£)”}”(hXÓ``ENABLE_ASSERTIONS``: This option controls whether or not calls to ``assert()`` are compiled out. For debug builds, this option defaults to 1, and calls to ``assert()`` are left in place. For release builds, this option defaults to 0 and calls to ``assert()`` function are compiled out. This option can be set independently of ``DEBUG``. It can also be used to hide any auxiliary code that is only required for the assertion and does not fit in the assertion itself.”h]”(já)”}”(hŒ``ENABLE_ASSERTIONS``”h]”hŒENABLE_ASSERTIONS”…””}”(hhh!jubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jubhŒ/: This option controls whether or not calls to ”…””}”(hŒ/: This option controls whether or not calls to ”h!jubjá)”}”(hŒ``assert()``”h]”hŒassert()”…””}”(hhh!j&ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jubhŒM are compiled out. For debug builds, this option defaults to 1, and calls to ”…””}”(hŒM are compiled out. For debug builds, this option defaults to 1, and calls to ”h!jubjá)”}”(hŒ``assert()``”h]”hŒassert()”…””}”(hhh!j9ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jubhŒO are left in place. For release builds, this option defaults to 0 and calls to ”…””}”(hŒO are left in place. For release builds, this option defaults to 0 and calls to ”h!jubjá)”}”(hŒ``assert()``”h]”hŒassert()”…””}”(hhh!jLubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jubhŒD function are compiled out. This option can be set independently of ”…””}”(hŒD function are compiled out. This option can be set independently of ”h!jubjá)”}”(hŒ ``DEBUG``”h]”hŒDEBUG”…””}”(hhh!j_ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jubhŒ‚. It can also be used to hide any auxiliary code that is only required for the assertion and does not fit in the assertion itself.”…””}”(hŒ‚. It can also be used to hide any auxiliary code that is only required for the assertion and does not fit in the assertion itself.”h!jubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKçh!jubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hXj``ENABLE_BACKTRACE``: This option controls whether to enable backtrace dumps or not. It is supported in both AArch64 and AArch32. However, in AArch32 the format of the frame records are not defined in the AAPCS and they are defined by the implementation. This implementation of backtrace only supports the format used by GCC when T32 interworking is disabled. For this reason enabling this option in AArch32 will force the compiler to only generate A32 code. This option is enabled by default only in AArch64 debug builds, but this behaviour can be overridden in each platform's Makefile or in the build command line. ”h]”j£)”}”(hXi``ENABLE_BACKTRACE``: This option controls whether to enable backtrace dumps or not. It is supported in both AArch64 and AArch32. However, in AArch32 the format of the frame records are not defined in the AAPCS and they are defined by the implementation. This implementation of backtrace only supports the format used by GCC when T32 interworking is disabled. For this reason enabling this option in AArch32 will force the compiler to only generate A32 code. This option is enabled by default only in AArch64 debug builds, but this behaviour can be overridden in each platform's Makefile or in the build command line.”h]”(já)”}”(hŒ``ENABLE_BACKTRACE``”h]”hŒENABLE_BACKTRACE”…””}”(hhh!j†ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j‚ubhXW: This option controls whether to enable backtrace dumps or not. It is supported in both AArch64 and AArch32. However, in AArch32 the format of the frame records are not defined in the AAPCS and they are defined by the implementation. This implementation of backtrace only supports the format used by GCC when T32 interworking is disabled. For this reason enabling this option in AArch32 will force the compiler to only generate A32 code. This option is enabled by default only in AArch64 debug builds, but this behaviour can be overridden in each platformâ€™s Makefile or in the build command line.”…””}”(hXU: This option controls whether to enable backtrace dumps or not. It is supported in both AArch64 and AArch32. However, in AArch32 the format of the frame records are not defined in the AAPCS and they are defined by the implementation. This implementation of backtrace only supports the format used by GCC when T32 interworking is disabled. For this reason enabling this option in AArch32 will force the compiler to only generate A32 code. This option is enabled by default only in AArch64 debug builds, but this behaviour can be overridden in each platform's Makefile or in the build command line.”h!j‚ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKïh!j~ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hŒÕ``ENABLE_FEAT_HCX``: This option sets the bit SCR_EL3.HXEn in EL3 to allow access to HCRX_EL2 (extended hypervisor control register) from EL2 as well as adding HCRX_EL2 to the EL2 context save/restore operations. ”h]”j£)”}”(hŒÔ``ENABLE_FEAT_HCX``: This option sets the bit SCR_EL3.HXEn in EL3 to allow access to HCRX_EL2 (extended hypervisor control register) from EL2 as well as adding HCRX_EL2 to the EL2 context save/restore operations.”h]”(já)”}”(hŒ``ENABLE_FEAT_HCX``”h]”hŒENABLE_FEAT_HCX”…””}”(hhh!jubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j©ubhŒÁ: This option sets the bit SCR_EL3.HXEn in EL3 to allow access to HCRX_EL2 (extended hypervisor control register) from EL2 as well as adding HCRX_EL2 to the EL2 context save/restore operations.”…””}”(hŒÁ: This option sets the bit SCR_EL3.HXEn in EL3 to allow access to HCRX_EL2 (extended hypervisor control register) from EL2 as well as adding HCRX_EL2 to the EL2 context save/restore operations.”h!j©ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKùh!j¥ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hŒ¢``ENABLE_LTO``: Boolean option to enable Link Time Optimization (LTO) support in GCC for TF-A. This option is currently only supported for AArch64. Default is 0. ”h]”j£)”}”(hŒ¡``ENABLE_LTO``: Boolean option to enable Link Time Optimization (LTO) support in GCC for TF-A. This option is currently only supported for AArch64. Default is 0.”h]”(já)”}”(hŒ``ENABLE_LTO``”h]”hŒ ENABLE_LTO”…””}”(hhh!jÔubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jÐubhŒ“: Boolean option to enable Link Time Optimization (LTO) support in GCC for TF-A. This option is currently only supported for AArch64. Default is 0.”…””}”(hŒ“: Boolean option to enable Link Time Optimization (LTO) support in GCC for TF-A. This option is currently only supported for AArch64. Default is 0.”h!jÐubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCKýh!jÌubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hXh``ENABLE_MPAM_FOR_LOWER_ELS``: Boolean option to enable lower ELs to use MPAM feature. MPAM is an optional Armv8.4 extension that enables various memory system components and resources to define partitions; software running at various ELs can assign themselves to desired partition to control their performance aspects. When this option is set to ``1``, EL3 allows lower ELs to access their own MPAM registers without trapping into EL3. This option doesn't make use of partitioning in EL3, however. Platform initialisation code should configure and use partitions in EL3 as required. This option defaults to ``0``. ”h]”(j£)”}”(hX?``ENABLE_MPAM_FOR_LOWER_ELS``: Boolean option to enable lower ELs to use MPAM feature. MPAM is an optional Armv8.4 extension that enables various memory system components and resources to define partitions; software running at various ELs can assign themselves to desired partition to control their performance aspects.”h]”(já)”}”(hŒ``ENABLE_MPAM_FOR_LOWER_ELS``”h]”hŒENABLE_MPAM_FOR_LOWER_ELS”…””}”(hhh!jûubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j÷ubhX": Boolean option to enable lower ELs to use MPAM feature. MPAM is an optional Armv8.4 extension that enables various memory system components and resources to define partitions; software running at various ELs can assign themselves to desired partition to control their performance aspects.”…””}”(hX": Boolean option to enable lower ELs to use MPAM feature. MPAM is an optional Armv8.4 extension that enables various memory system components and resources to define partitions; software running at various ELs can assign themselves to desired partition to control their performance aspects.”h!j÷ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMh!jóubj£)”}”(hX&When this option is set to ``1``, EL3 allows lower ELs to access their own MPAM registers without trapping into EL3. This option doesn't make use of partitioning in EL3, however. Platform initialisation code should configure and use partitions in EL3 as required. This option defaults to ``0``.”h]”(hŒWhen this option is set to ”…””}”(hŒWhen this option is set to ”h!jubjá)”}”(hŒ``1``”h]”hŒ1”…””}”(hhh!jubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jubhX, EL3 allows lower ELs to access their own MPAM registers without trapping into EL3. This option doesnâ€™t make use of partitioning in EL3, however. Platform initialisation code should configure and use partitions in EL3 as required. This option defaults to ”…””}”(hX, EL3 allows lower ELs to access their own MPAM registers without trapping into EL3. This option doesn't make use of partitioning in EL3, however. Platform initialisation code should configure and use partitions in EL3 as required. This option defaults to ”h!jubjá)”}”(hŒ``0``”h]”hŒ0”…””}”(hhh!j0ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jubhŒ.”…””}”(hjTh!jubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMh!jóubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hXy``ENABLE_MPMM``: Boolean option to enable support for the Maximum Power Mitigation Mechanism supported by certain Arm cores, which allows the SoC firmware to detect and limit high activity events to assist in SoC processor power domain dynamic power budgeting and limit the triggering of whole-rail (i.e. clock chopping) responses to overcurrent conditions. Defaults to ``0``. ”h]”j£)”}”(hXx``ENABLE_MPMM``: Boolean option to enable support for the Maximum Power Mitigation Mechanism supported by certain Arm cores, which allows the SoC firmware to detect and limit high activity events to assist in SoC processor power domain dynamic power budgeting and limit the triggering of whole-rail (i.e. clock chopping) responses to overcurrent conditions. Defaults to ``0``.”h]”(já)”}”(hŒ``ENABLE_MPMM``”h]”hŒENABLE_MPMM”…””}”(hhh!jVubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jRubhXc: Boolean option to enable support for the Maximum Power Mitigation Mechanism supported by certain Arm cores, which allows the SoC firmware to detect and limit high activity events to assist in SoC processor power domain dynamic power budgeting and limit the triggering of whole-rail (i.e. clock chopping) responses to overcurrent conditions. Defaults to ”…””}”(hXc: Boolean option to enable support for the Maximum Power Mitigation Mechanism supported by certain Arm cores, which allows the SoC firmware to detect and limit high activity events to assist in SoC processor power domain dynamic power budgeting and limit the triggering of whole-rail (i.e. clock chopping) responses to overcurrent conditions. Defaults to ”h!jRubjá)”}”(hŒ``0``”h]”hŒ0”…””}”(hhh!jiubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jRubhŒ.”…””}”(hjTh!jRubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMh!jNubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hŒ½``ENABLE_MPMM_FCONF``: Enables configuration of MPMM through FCONF, which allows platforms with cores supporting MPMM to describe them via the ``HW_CONFIG`` device tree blob. Default is 0. ”h]”j£)”}”(hŒ¼``ENABLE_MPMM_FCONF``: Enables configuration of MPMM through FCONF, which allows platforms with cores supporting MPMM to describe them via the ``HW_CONFIG`` device tree blob. Default is 0.”h]”(já)”}”(hŒ``ENABLE_MPMM_FCONF``”h]”hŒENABLE_MPMM_FCONF”…””}”(hhh!jubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j‹ubhŒz: Enables configuration of MPMM through FCONF, which allows platforms with cores supporting MPMM to describe them via the ”…””}”(hŒz: Enables configuration of MPMM through FCONF, which allows platforms with cores supporting MPMM to describe them via the ”h!j‹ubjá)”}”(hŒ ``HW_CONFIG``”h]”hŒ HW_CONFIG”…””}”(hhh!j¢ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j‹ubhŒ device tree blob. Default is 0.”…””}”(hŒ device tree blob. Default is 0.”h!j‹ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMh!j‡ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hX``ENABLE_PIE``: Boolean option to enable Position Independent Executable(PIE) support within generic code in TF-A. This option is currently only supported in BL2_AT_EL3, BL31, and BL32 (TSP) for AARCH64 binaries, and in BL32 (SP_min) for AARCH32. Default is 0. ”h]”j£)”}”(hX``ENABLE_PIE``: Boolean option to enable Position Independent Executable(PIE) support within generic code in TF-A. This option is currently only supported in BL2_AT_EL3, BL31, and BL32 (TSP) for AARCH64 binaries, and in BL32 (SP_min) for AARCH32. Default is 0.”h]”(já)”}”(hŒ``ENABLE_PIE``”h]”hŒ ENABLE_PIE”…””}”(hhh!jÉubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jÅubhŒö: Boolean option to enable Position Independent Executable(PIE) support within generic code in TF-A. This option is currently only supported in BL2_AT_EL3, BL31, and BL32 (TSP) for AARCH64 binaries, and in BL32 (SP_min) for AARCH32. Default is 0.”…””}”(hŒö: Boolean option to enable Position Independent Executable(PIE) support within generic code in TF-A. This option is currently only supported in BL2_AT_EL3, BL31, and BL32 (TSP) for AARCH64 binaries, and in BL32 (SP_min) for AARCH32. Default is 0.”h!jÅubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMh!jÁubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hŒt``ENABLE_PMF``: Boolean option to enable support for optional Performance Measurement Framework(PMF). Default is 0. ”h]”j£)”}”(hŒs``ENABLE_PMF``: Boolean option to enable support for optional Performance Measurement Framework(PMF). Default is 0.”h]”(já)”}”(hŒ``ENABLE_PMF``”h]”hŒ ENABLE_PMF”…””}”(hhh!jðubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jìubhŒe: Boolean option to enable support for optional Performance Measurement Framework(PMF). Default is 0.”…””}”(hŒe: Boolean option to enable support for optional Performance Measurement Framework(PMF). Default is 0.”h!jìubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMh!jèubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hX6``ENABLE_PSCI_STAT``: Boolean option to enable support for optional PSCI functions ``PSCI_STAT_RESIDENCY`` and ``PSCI_STAT_COUNT``. Default is 0. In the absence of an alternate stat collection backend, ``ENABLE_PMF`` must be enabled. If ``ENABLE_PMF`` is set, the residency statistics are tracked in software. ”h]”j£)”}”(hX5``ENABLE_PSCI_STAT``: Boolean option to enable support for optional PSCI functions ``PSCI_STAT_RESIDENCY`` and ``PSCI_STAT_COUNT``. Default is 0. In the absence of an alternate stat collection backend, ``ENABLE_PMF`` must be enabled. If ``ENABLE_PMF`` is set, the residency statistics are tracked in software.”h]”(já)”}”(hŒ``ENABLE_PSCI_STAT``”h]”hŒENABLE_PSCI_STAT”…””}”(hhh!jubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jubhŒ?: Boolean option to enable support for optional PSCI functions ”…””}”(hŒ?: Boolean option to enable support for optional PSCI functions ”h!jubjá)”}”(hŒ``PSCI_STAT_RESIDENCY``”h]”hŒPSCI_STAT_RESIDENCY”…””}”(hhh!j*ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jubhŒ and ”…””}”(hŒ and ”h!jubjá)”}”(hŒ``PSCI_STAT_COUNT``”h]”hŒPSCI_STAT_COUNT”…””}”(hhh!j=ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jubhŒH. Default is 0. In the absence of an alternate stat collection backend, ”…””}”(hŒH. Default is 0. In the absence of an alternate stat collection backend, ”h!jubjá)”}”(hŒ``ENABLE_PMF``”h]”hŒ ENABLE_PMF”…””}”(hhh!jPubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jubhŒ must be enabled. If ”…””}”(hŒ must be enabled. If ”h!jubjá)”}”(hŒ``ENABLE_PMF``”h]”hŒ ENABLE_PMF”…””}”(hhh!jcubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jubhŒ: is set, the residency statistics are tracked in software.”…””}”(hŒ: is set, the residency statistics are tracked in software.”h!jubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMh!jubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hŒœ``ENABLE_RME``: Boolean option to enable support for the ARMv9 Realm Management Extension. Default value is 0. This is currently an experimental feature. ”h]”h Œdefinition_list”“”)”}”(hhh]”h Œdefinition_list_item”“”)”}”(hŒš``ENABLE_RME``: Boolean option to enable support for the ARMv9 Realm Management Extension. Default value is 0. This is currently an experimental feature. ”h]”(h Œterm”“”)”}”(hŒD``ENABLE_RME``: Boolean option to enable support for the ARMv9 Realm”h]”(já)”}”(hŒ``ENABLE_RME``”h]”hŒ ENABLE_RME”…””}”(hhh!j—ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j“ubhŒ6: Boolean option to enable support for the ARMv9 Realm”…””}”(hŒ6: Boolean option to enable support for the ARMv9 Realm”h!j“ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j‘hAj¡hCM&h!jubh Œ definition”“”)”}”(hhh]”j£)”}”(hŒTManagement Extension. Default value is 0. This is currently an experimental feature.”h]”hŒTManagement Extension. Default value is 0. This is currently an experimental feature.”…””}”(hj·h!jµubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCM%h!j²ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j°h!jubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j‹hAj¡hCM&h!jˆubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j†h!j‚ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhANhCNubj×)”}”(hX0``ENABLE_RUNTIME_INSTRUMENTATION``: Boolean option to enable runtime instrumentation which injects timestamp collection points into TF-A to allow runtime performance to be measured. Currently, only PSCI is instrumented. Enabling this option enables the ``ENABLE_PMF`` build option as well. Default is 0. ”h]”j£)”}”(hX/``ENABLE_RUNTIME_INSTRUMENTATION``: Boolean option to enable runtime instrumentation which injects timestamp collection points into TF-A to allow runtime performance to be measured. Currently, only PSCI is instrumented. Enabling this option enables the ``ENABLE_PMF`` build option as well. Default is 0.”h]”(já)”}”(hŒ"``ENABLE_RUNTIME_INSTRUMENTATION``”h]”hŒENABLE_RUNTIME_INSTRUMENTATION”…””}”(hhh!jãubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jßubhŒÛ: Boolean option to enable runtime instrumentation which injects timestamp collection points into TF-A to allow runtime performance to be measured. Currently, only PSCI is instrumented. Enabling this option enables the ”…””}”(hŒÛ: Boolean option to enable runtime instrumentation which injects timestamp collection points into TF-A to allow runtime performance to be measured. Currently, only PSCI is instrumented. Enabling this option enables the ”h!jßubjá)”}”(hŒ``ENABLE_PMF``”h]”hŒ ENABLE_PMF”…””}”(hhh!jöubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jßubhŒ$ build option as well. Default is 0.”…””}”(hŒ$ build option as well. Default is 0.”h!jßubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCM(h!jÛubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hX6``ENABLE_SME_FOR_NS``: Boolean option to enable Scalable Matrix Extension (SME), SVE, and FPU/SIMD for the non-secure world only. These features share registers so are enabled together. Using this option without ENABLE_SME_FOR_SWD=1 will cause SME, SVE, and FPU/SIMD instructions in secure world to trap to EL3. SME is an optional architectural feature for AArch64 and TF-A support is experimental. At this time, this build option cannot be used on systems that have SPD=spmd/SPM_MM or ENABLE_RME, and attempting to build with these options will fail. Default is 0. ”h]”j£)”}”(hX5``ENABLE_SME_FOR_NS``: Boolean option to enable Scalable Matrix Extension (SME), SVE, and FPU/SIMD for the non-secure world only. These features share registers so are enabled together. Using this option without ENABLE_SME_FOR_SWD=1 will cause SME, SVE, and FPU/SIMD instructions in secure world to trap to EL3. SME is an optional architectural feature for AArch64 and TF-A support is experimental. At this time, this build option cannot be used on systems that have SPD=spmd/SPM_MM or ENABLE_RME, and attempting to build with these options will fail. Default is 0.”h]”(já)”}”(hŒ``ENABLE_SME_FOR_NS``”h]”hŒENABLE_SME_FOR_NS”…””}”(hhh!jubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jubhX : Boolean option to enable Scalable Matrix Extension (SME), SVE, and FPU/SIMD for the non-secure world only. These features share registers so are enabled together. Using this option without ENABLE_SME_FOR_SWD=1 will cause SME, SVE, and FPU/SIMD instructions in secure world to trap to EL3. SME is an optional architectural feature for AArch64 and TF-A support is experimental. At this time, this build option cannot be used on systems that have SPD=spmd/SPM_MM or ENABLE_RME, and attempting to build with these options will fail. Default is 0.”…””}”(hX : Boolean option to enable Scalable Matrix Extension (SME), SVE, and FPU/SIMD for the non-secure world only. These features share registers so are enabled together. Using this option without ENABLE_SME_FOR_SWD=1 will cause SME, SVE, and FPU/SIMD instructions in secure world to trap to EL3. SME is an optional architectural feature for AArch64 and TF-A support is experimental. At this time, this build option cannot be used on systems that have SPD=spmd/SPM_MM or ENABLE_RME, and attempting to build with these options will fail. Default is 0.”h!jubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCM.h!jubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hXq``ENABLE_SME_FOR_SWD``: Boolean option to enable the Scalable Matrix Extension for secure world use along with SVE and FPU/SIMD, ENABLE_SME_FOR_NS must also be set to use this. If enabling this, the secure world MUST handle context switching for SME, SVE, and FPU/SIMD registers to ensure that no data is leaked to non-secure world. This is experimental. Default is 0. ”h]”j£)”}”(hXp``ENABLE_SME_FOR_SWD``: Boolean option to enable the Scalable Matrix Extension for secure world use along with SVE and FPU/SIMD, ENABLE_SME_FOR_NS must also be set to use this. If enabling this, the secure world MUST handle context switching for SME, SVE, and FPU/SIMD registers to ensure that no data is leaked to non-secure world. This is experimental. Default is 0.”h]”(já)”}”(hŒ``ENABLE_SME_FOR_SWD``”h]”hŒENABLE_SME_FOR_SWD”…””}”(hhh!jDubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j@ubhXZ: Boolean option to enable the Scalable Matrix Extension for secure world use along with SVE and FPU/SIMD, ENABLE_SME_FOR_NS must also be set to use this. If enabling this, the secure world MUST handle context switching for SME, SVE, and FPU/SIMD registers to ensure that no data is leaked to non-secure world. This is experimental. Default is 0.”…””}”(hXZ: Boolean option to enable the Scalable Matrix Extension for secure world use along with SVE and FPU/SIMD, ENABLE_SME_FOR_NS must also be set to use this. If enabling this, the secure world MUST handle context switching for SME, SVE, and FPU/SIMD registers to ensure that no data is leaked to non-secure world. This is experimental. Default is 0.”h!j@ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCM7h!j<ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hŒé``ENABLE_SPE_FOR_LOWER_ELS`` : Boolean option to enable Statistical Profiling extensions. This is an optional architectural feature for AArch64. The default is 1 but is automatically disabled when the target architecture is AArch32. ”h]”j£)”}”(hŒè``ENABLE_SPE_FOR_LOWER_ELS`` : Boolean option to enable Statistical Profiling extensions. This is an optional architectural feature for AArch64. The default is 1 but is automatically disabled when the target architecture is AArch32.”h]”(já)”}”(hŒ``ENABLE_SPE_FOR_LOWER_ELS``”h]”hŒENABLE_SPE_FOR_LOWER_ELS”…””}”(hhh!jkubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jgubhŒÌ : Boolean option to enable Statistical Profiling extensions. This is an optional architectural feature for AArch64. The default is 1 but is automatically disabled when the target architecture is AArch32.”…””}”(hŒÌ : Boolean option to enable Statistical Profiling extensions. This is an optional architectural feature for AArch64. The default is 1 but is automatically disabled when the target architecture is AArch32.”h!jgubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCM=h!jcubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hXI``ENABLE_SVE_FOR_NS``: Boolean option to enable Scalable Vector Extension (SVE) for the Non-secure world only. SVE is an optional architectural feature for AArch64. Note that when SVE is enabled for the Non-secure world, access to SIMD and floating-point functionality from the Secure world is disabled by default and controlled with ENABLE_SVE_FOR_SWD. This is to avoid corruption of the Non-secure world data in the Z-registers which are aliased by the SIMD and FP registers. The build option is not compatible with the ``CTX_INCLUDE_FPREGS`` build option, and will raise an assert on platforms where SVE is implemented and ``ENABLE_SVE_FOR_NS`` set to 1. The default is 1 but is automatically disabled when ENABLE_SME_FOR_NS=1 since SME encompasses SVE. At this time, this build option cannot be used on systems that have SPM_MM enabled. ”h]”j£)”}”(hXH``ENABLE_SVE_FOR_NS``: Boolean option to enable Scalable Vector Extension (SVE) for the Non-secure world only. SVE is an optional architectural feature for AArch64. Note that when SVE is enabled for the Non-secure world, access to SIMD and floating-point functionality from the Secure world is disabled by default and controlled with ENABLE_SVE_FOR_SWD. This is to avoid corruption of the Non-secure world data in the Z-registers which are aliased by the SIMD and FP registers. The build option is not compatible with the ``CTX_INCLUDE_FPREGS`` build option, and will raise an assert on platforms where SVE is implemented and ``ENABLE_SVE_FOR_NS`` set to 1. The default is 1 but is automatically disabled when ENABLE_SME_FOR_NS=1 since SME encompasses SVE. At this time, this build option cannot be used on systems that have SPM_MM enabled.”h]”(já)”}”(hŒ``ENABLE_SVE_FOR_NS``”h]”hŒENABLE_SVE_FOR_NS”…””}”(hhh!j’ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jŽubhXõ: Boolean option to enable Scalable Vector Extension (SVE) for the Non-secure world only. SVE is an optional architectural feature for AArch64. Note that when SVE is enabled for the Non-secure world, access to SIMD and floating-point functionality from the Secure world is disabled by default and controlled with ENABLE_SVE_FOR_SWD. This is to avoid corruption of the Non-secure world data in the Z-registers which are aliased by the SIMD and FP registers. The build option is not compatible with the ”…””}”(hXõ: Boolean option to enable Scalable Vector Extension (SVE) for the Non-secure world only. SVE is an optional architectural feature for AArch64. Note that when SVE is enabled for the Non-secure world, access to SIMD and floating-point functionality from the Secure world is disabled by default and controlled with ENABLE_SVE_FOR_SWD. This is to avoid corruption of the Non-secure world data in the Z-registers which are aliased by the SIMD and FP registers. The build option is not compatible with the ”h!jŽubjá)”}”(hŒ``CTX_INCLUDE_FPREGS``”h]”hŒCTX_INCLUDE_FPREGS”…””}”(hhh!j¥ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jŽubhŒR build option, and will raise an assert on platforms where SVE is implemented and ”…””}”(hŒR build option, and will raise an assert on platforms where SVE is implemented and ”h!jŽubjá)”}”(hŒ``ENABLE_SVE_FOR_NS``”h]”hŒENABLE_SVE_FOR_NS”…””}”(hhh!j¸ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jŽubhŒÁ set to 1. The default is 1 but is automatically disabled when ENABLE_SME_FOR_NS=1 since SME encompasses SVE. At this time, this build option cannot be used on systems that have SPM_MM enabled.”…””}”(hŒÁ set to 1. The default is 1 but is automatically disabled when ENABLE_SME_FOR_NS=1 since SME encompasses SVE. At this time, this build option cannot be used on systems that have SPM_MM enabled.”h!jŽubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMBh!jŠubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hX``ENABLE_SVE_FOR_SWD``: Boolean option to enable SVE for the Secure world. SVE is an optional architectural feature for AArch64. Note that this option requires ENABLE_SVE_FOR_NS to be enabled. The default is 0 and it is automatically disabled when the target architecture is AArch32. ”h]”j£)”}”(hX``ENABLE_SVE_FOR_SWD``: Boolean option to enable SVE for the Secure world. SVE is an optional architectural feature for AArch64. Note that this option requires ENABLE_SVE_FOR_NS to be enabled. The default is 0 and it is automatically disabled when the target architecture is AArch32.”h]”(já)”}”(hŒ``ENABLE_SVE_FOR_SWD``”h]”hŒENABLE_SVE_FOR_SWD”…””}”(hhh!jßubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jÛubhX: Boolean option to enable SVE for the Secure world. SVE is an optional architectural feature for AArch64. Note that this option requires ENABLE_SVE_FOR_NS to be enabled. The default is 0 and it is automatically disabled when the target architecture is AArch32.”…””}”(hX: Boolean option to enable SVE for the Secure world. SVE is an optional architectural feature for AArch64. Note that this option requires ENABLE_SVE_FOR_NS to be enabled. The default is 0 and it is automatically disabled when the target architecture is AArch32.”h!jÛubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMOh!j×ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hX``ENABLE_STACK_PROTECTOR``: String option to enable the stack protection checks in GCC. Allowed values are "all", "strong", "default" and "none". The default value is set to "none". "strong" is the recommended stack protection level if this feature is desired. "none" disables the stack protection. For all values other than "none", the ``plat_get_stack_protector_canary()`` platform hook needs to be implemented. The value is passed as the last component of the option ``-fstack-protector-$ENABLE_STACK_PROTECTOR``. ”h]”j£)”}”(hX``ENABLE_STACK_PROTECTOR``: String option to enable the stack protection checks in GCC. Allowed values are "all", "strong", "default" and "none". The default value is set to "none". "strong" is the recommended stack protection level if this feature is desired. "none" disables the stack protection. For all values other than "none", the ``plat_get_stack_protector_canary()`` platform hook needs to be implemented. The value is passed as the last component of the option ``-fstack-protector-$ENABLE_STACK_PROTECTOR``.”h]”(já)”}”(hŒ``ENABLE_STACK_PROTECTOR``”h]”hŒENABLE_STACK_PROTECTOR”…””}”(hhh!jubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jubhXW: String option to enable the stack protection checks in GCC. Allowed values are â€œallâ€, â€œstrongâ€, â€œdefaultâ€ and â€œnoneâ€. The default value is set to â€œnoneâ€. â€œstrongâ€ is the recommended stack protection level if this feature is desired. â€œnoneâ€ disables the stack protection. For all values other than â€œnoneâ€, the ”…””}”(hX7: String option to enable the stack protection checks in GCC. Allowed values are "all", "strong", "default" and "none". The default value is set to "none". "strong" is the recommended stack protection level if this feature is desired. "none" disables the stack protection. For all values other than "none", the ”h!jubjá)”}”(hŒ%``plat_get_stack_protector_canary()``”h]”hŒ!plat_get_stack_protector_canary()”…””}”(hhh!jubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jubhŒ` platform hook needs to be implemented. The value is passed as the last component of the option ”…””}”(hŒ` platform hook needs to be implemented. The value is passed as the last component of the option ”h!jubjá)”}”(hŒ-``-fstack-protector-$ENABLE_STACK_PROTECTOR``”h]”hŒ)-fstack-protector-$ENABLE_STACK_PROTECTOR”…””}”(hhh!j,ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jubhŒ.”…””}”(hjTh!jubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMTh!jþubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hŒ}``ENCRYPT_BL31``: Binary flag to enable encryption of BL31 firmware. This flag depends on ``DECRYPTION_SUPPORT`` build flag. ”h]”j£)”}”(hŒ|``ENCRYPT_BL31``: Binary flag to enable encryption of BL31 firmware. This flag depends on ``DECRYPTION_SUPPORT`` build flag.”h]”(já)”}”(hŒ``ENCRYPT_BL31``”h]”hŒENCRYPT_BL31”…””}”(hhh!jRubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jNubhŒJ: Binary flag to enable encryption of BL31 firmware. This flag depends on ”…””}”(hŒJ: Binary flag to enable encryption of BL31 firmware. This flag depends on ”h!jNubjá)”}”(hŒ``DECRYPTION_SUPPORT``”h]”hŒDECRYPTION_SUPPORT”…””}”(hhh!jeubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jNubhŒ build flag.”…””}”(hŒ build flag.”h!jNubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCM\h!jJubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hŒƒ``ENCRYPT_BL32``: Binary flag to enable encryption of Secure BL32 payload. This flag depends on ``DECRYPTION_SUPPORT`` build flag. ”h]”j£)”}”(hŒ‚``ENCRYPT_BL32``: Binary flag to enable encryption of Secure BL32 payload. This flag depends on ``DECRYPTION_SUPPORT`` build flag.”h]”(já)”}”(hŒ``ENCRYPT_BL32``”h]”hŒENCRYPT_BL32”…””}”(hhh!jŒubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jˆubhŒP: Binary flag to enable encryption of Secure BL32 payload. This flag depends on ”…””}”(hŒP: Binary flag to enable encryption of Secure BL32 payload. This flag depends on ”h!jˆubjá)”}”(hŒ``DECRYPTION_SUPPORT``”h]”hŒDECRYPTION_SUPPORT”…””}”(hhh!jŸubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jˆubhŒ build flag.”…””}”(hŒ build flag.”h!jˆubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCM_h!j„ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hŒÂ``ENC_KEY``: A 32-byte (256-bit) symmetric key in hex string format. It could either be SSK or BSSK depending on ``FW_ENC_STATUS`` flag. This value depends on ``DECRYPTION_SUPPORT`` build flag. ”h]”j£)”}”(hŒÁ``ENC_KEY``: A 32-byte (256-bit) symmetric key in hex string format. It could either be SSK or BSSK depending on ``FW_ENC_STATUS`` flag. This value depends on ``DECRYPTION_SUPPORT`` build flag.”h]”(já)”}”(hŒ``ENC_KEY``”h]”hŒENC_KEY”…””}”(hhh!jÆubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jÂubhŒf: A 32-byte (256-bit) symmetric key in hex string format. It could either be SSK or BSSK depending on ”…””}”(hŒf: A 32-byte (256-bit) symmetric key in hex string format. It could either be SSK or BSSK depending on ”h!jÂubjá)”}”(hŒ``FW_ENC_STATUS``”h]”hŒ FW_ENC_STATUS”…””}”(hhh!jÙubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jÂubhŒ flag. This value depends on ”…””}”(hŒ flag. This value depends on ”h!jÂubjá)”}”(hŒ``DECRYPTION_SUPPORT``”h]”hŒDECRYPTION_SUPPORT”…””}”(hhh!jìubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jÂubhŒ build flag.”…””}”(hŒ build flag.”h!jÂubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMbh!j¾ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hŒ ``ENC_NONCE``: A 12-byte (96-bit) encryption nonce or Initialization Vector (IV) in hex string format. This value depends on ``DECRYPTION_SUPPORT`` build flag. ”h]”j£)”}”(hŒŸ``ENC_NONCE``: A 12-byte (96-bit) encryption nonce or Initialization Vector (IV) in hex string format. This value depends on ``DECRYPTION_SUPPORT`` build flag.”h]”(já)”}”(hŒ ``ENC_NONCE``”h]”hŒ ENC_NONCE”…””}”(hhh!jubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jubhŒp: A 12-byte (96-bit) encryption nonce or Initialization Vector (IV) in hex string format. This value depends on ”…””}”(hŒp: A 12-byte (96-bit) encryption nonce or Initialization Vector (IV) in hex string format. This value depends on ”h!jubjá)”}”(hŒ``DECRYPTION_SUPPORT``”h]”hŒDECRYPTION_SUPPORT”…””}”(hhh!j&ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jubhŒ build flag.”…””}”(hŒ build flag.”h!jubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMfh!jubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hŒû``ERROR_DEPRECATED``: This option decides whether to treat the usage of deprecated platform APIs, helper functions or drivers within Trusted Firmware as error. It can take the value 1 (flag the use of deprecated APIs as error) or 0. The default is 0. ”h]”j£)”}”(hŒú``ERROR_DEPRECATED``: This option decides whether to treat the usage of deprecated platform APIs, helper functions or drivers within Trusted Firmware as error. It can take the value 1 (flag the use of deprecated APIs as error) or 0. The default is 0.”h]”(já)”}”(hŒ``ERROR_DEPRECATED``”h]”hŒERROR_DEPRECATED”…””}”(hhh!jMubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jIubhŒæ: This option decides whether to treat the usage of deprecated platform APIs, helper functions or drivers within Trusted Firmware as error. It can take the value 1 (flag the use of deprecated APIs as error) or 0. The default is 0.”…””}”(hŒæ: This option decides whether to treat the usage of deprecated platform APIs, helper functions or drivers within Trusted Firmware as error. It can take the value 1 (flag the use of deprecated APIs as error) or 0. The default is 0.”h!jIubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMjh!jEubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hŒê``EL3_EXCEPTION_HANDLING``: When set to ``1``, enable handling of exceptions targeted at EL3. When set ``0`` (default), no exceptions are expected or handled at EL3, and a panic will result. This is supported only for AArch64 builds. ”h]”j£)”}”(hŒé``EL3_EXCEPTION_HANDLING``: When set to ``1``, enable handling of exceptions targeted at EL3. When set ``0`` (default), no exceptions are expected or handled at EL3, and a panic will result. This is supported only for AArch64 builds.”h]”(já)”}”(hŒ``EL3_EXCEPTION_HANDLING``”h]”hŒEL3_EXCEPTION_HANDLING”…””}”(hhh!jtubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jpubhŒ: When set to ”…””}”(hŒ: When set to ”h!jpubjá)”}”(hŒ``1``”h]”hŒ1”…””}”(hhh!j‡ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jpubhŒ:, enable handling of exceptions targeted at EL3. When set ”…””}”(hŒ:, enable handling of exceptions targeted at EL3. When set ”h!jpubjá)”}”(hŒ``0``”h]”hŒ0”…””}”(hhh!jšubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jpubhŒ} (default), no exceptions are expected or handled at EL3, and a panic will result. This is supported only for AArch64 builds.”…””}”(hŒ} (default), no exceptions are expected or handled at EL3, and a panic will result. This is supported only for AArch64 builds.”h!jpubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMoh!jlubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hŒ¼``EVENT_LOG_LEVEL``: Chooses the log level to use for Measured Boot when ``MEASURED_BOOT`` is enabled. For a list of valid values, see ``LOG_LEVEL``. Default value is 40 (LOG_LEVEL_INFO). ”h]”j£)”}”(hŒ»``EVENT_LOG_LEVEL``: Chooses the log level to use for Measured Boot when ``MEASURED_BOOT`` is enabled. For a list of valid values, see ``LOG_LEVEL``. Default value is 40 (LOG_LEVEL_INFO).”h]”(já)”}”(hŒ``EVENT_LOG_LEVEL``”h]”hŒEVENT_LOG_LEVEL”…””}”(hhh!jÁubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j½ubhŒ6: Chooses the log level to use for Measured Boot when ”…””}”(hŒ6: Chooses the log level to use for Measured Boot when ”h!j½ubjá)”}”(hŒ``MEASURED_BOOT``”h]”hŒ MEASURED_BOOT”…””}”(hhh!jÔubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j½ubhŒ- is enabled. For a list of valid values, see ”…””}”(hŒ- is enabled. For a list of valid values, see ”h!j½ubjá)”}”(hŒ ``LOG_LEVEL``”h]”hŒ LOG_LEVEL”…””}”(hhh!jçubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j½ubhŒ'. Default value is 40 (LOG_LEVEL_INFO).”…””}”(hŒ'. Default value is 40 (LOG_LEVEL_INFO).”h!j½ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMth!j¹ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hXm``FAULT_INJECTION_SUPPORT``: ARMv8.4 extensions introduced support for fault injection from lower ELs, and this build option enables lower ELs to use Error Records accessed via System Registers to inject faults. This is applicable only to AArch64 builds. This feature is intended for testing purposes only, and is advisable to keep disabled for production images. ”h]”(j£)”}”(hŒþ``FAULT_INJECTION_SUPPORT``: ARMv8.4 extensions introduced support for fault injection from lower ELs, and this build option enables lower ELs to use Error Records accessed via System Registers to inject faults. This is applicable only to AArch64 builds.”h]”(já)”}”(hŒ``FAULT_INJECTION_SUPPORT``”h]”hŒFAULT_INJECTION_SUPPORT”…””}”(hhh!jubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j ubhŒã: ARMv8.4 extensions introduced support for fault injection from lower ELs, and this build option enables lower ELs to use Error Records accessed via System Registers to inject faults. This is applicable only to AArch64 builds.”…””}”(hŒã: ARMv8.4 extensions introduced support for fault injection from lower ELs, and this build option enables lower ELs to use Error Records accessed via System Registers to inject faults. This is applicable only to AArch64 builds.”•ûh!j ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMxh!jubj£)”}”(hŒlThis feature is intended for testing purposes only, and is advisable to keep disabled for production images.”h]”hŒlThis feature is intended for testing purposes only, and is advisable to keep disabled for production images.”…””}”(hj)h!j'ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCM}h!jubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hŒ€``FIP_NAME``: This is an optional build option which specifies the FIP filename for the ``fip`` target. Default is ``fip.bin``. ”h]”j£)”}”(hŒ``FIP_NAME``: This is an optional build option which specifies the FIP filename for the ``fip`` target. Default is ``fip.bin``.”h]”(já)”}”(hŒ``FIP_NAME``”h]”hŒFIP_NAME”…””}”(hhh!jCubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j?ubhŒL: This is an optional build option which specifies the FIP filename for the ”…””}”(hŒL: This is an optional build option which specifies the FIP filename for the ”h!j?ubjá)”}”(hŒ``fip``”h]”hŒfip”…””}”(hhh!jVubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j?ubhŒ target. Default is ”…””}”(hŒ target. Default is ”h!j?ubjá)”}”(hŒ``fip.bin``”h]”hŒfip.bin”…””}”(hhh!jiubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j?ubhŒ.”…””}”(hjTh!j?ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCM€h!j;ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hŒ``FWU_FIP_NAME``: This is an optional build option which specifies the FWU FIP filename for the ``fwu_fip`` target. Default is ``fwu_fip.bin``. ”h]”j£)”}”(hŒ``FWU_FIP_NAME``: This is an optional build option which specifies the FWU FIP filename for the ``fwu_fip`` target. Default is ``fwu_fip.bin``.”h]”(já)”}”(hŒ``FWU_FIP_NAME``”h]”hŒFWU_FIP_NAME”…””}”(hhh!jubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j‹ubhŒP: This is an optional build option which specifies the FWU FIP filename for the ”…””}”(hŒP: This is an optional build option which specifies the FWU FIP filename for the ”h!j‹ubjá)”}”(hŒ``fwu_fip``”h]”hŒfwu_fip”…””}”(hhh!j¢ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j‹ubhŒ target. Default is ”…””}”(hŒ target. Default is ”h!j‹ubjá)”}”(hŒ``fwu_fip.bin``”h]”hŒfwu_fip.bin”…””}”(hhh!jµubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j‹ubhŒ.”…””}”(hjTh!j‹ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMƒh!j‡ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hXN``FW_ENC_STATUS``: Top level firmware's encryption numeric flag, values: :: 0: Encryption is done with Secret Symmetric Key (SSK) which is common for a class of devices. 1: Encryption is done with Binding Secret Symmetric Key (BSSK) which is unique per device. This flag depends on ``DECRYPTION_SUPPORT`` build flag. ”h]”(j£)”}”(hŒH``FW_ENC_STATUS``: Top level firmware's encryption numeric flag, values:”h]”(já)”}”(hŒ``FW_ENC_STATUS``”h]”hŒ FW_ENC_STATUS”…””}”(hhh!jÛubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j×ubhŒ9: Top level firmwareâ€™s encryption numeric flag, values:”…””}”(hŒ7: Top level firmware's encryption numeric flag, values:”h!j×ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCM†h!jÓubh Œ literal_block”“”)”}”(hŒ¾0: Encryption is done with Secret Symmetric Key (SSK) which is common for a class of devices. 1: Encryption is done with Binding Secret Symmetric Key (BSSK) which is unique per device.”h]”hŒ¾0: Encryption is done with Secret Symmetric Key (SSK) which is common for a class of devices. 1: Encryption is done with Binding Secret Symmetric Key (BSSK) which is unique per device.”…””}”(hhh!jöubah"}”(h$]”h&]”h+]”h-]”h/]”Œ xml:space”Œpreserve”uh1jôhAj¡hCMŠh!jÓubj£)”}”(hŒ7This flag depends on ``DECRYPTION_SUPPORT`` build flag.”h]”(hŒThis flag depends on ”…””}”(hŒThis flag depends on ”h!j ubjá)”}”(hŒ``DECRYPTION_SUPPORT``”h]”hŒDECRYPTION_SUPPORT”…””}”(hhh!j ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j ubhŒ build flag.”…””}”(hŒ build flag.”h!j ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMh!jÓubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hX``GENERATE_COT``: Boolean flag used to build and execute the ``cert_create`` tool to create certificates as per the Chain of Trust described in :ref:`Trusted Board Boot`. The build system then calls ``fiptool`` to include the certificates in the FIP and FWU_FIP. Default value is '0'. Specify both ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=1`` to include support for the Trusted Board Boot feature in the BL1 and BL2 images, to generate the corresponding certificates, and to include those certificates in the FIP and FWU_FIP. Note that if ``TRUSTED_BOARD_BOOT=0`` and ``GENERATE_COT=1``, the BL1 and BL2 images will not include support for Trusted Board Boot. The FIP will still include the corresponding certificates. This FIP can be used to verify the Chain of Trust on the host machine through other mechanisms. Note that if ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=0``, the BL1 and BL2 images will include support for Trusted Board Boot, but the FIP and FWU_FIP will not include the corresponding certificates, causing a boot failure. ”h]”(j£)”}”(hX``GENERATE_COT``: Boolean flag used to build and execute the ``cert_create`` tool to create certificates as per the Chain of Trust described in :ref:`Trusted Board Boot`. The build system then calls ``fiptool`` to include the certificates in the FIP and FWU_FIP. Default value is '0'.”h]”(já)”}”(hŒ``GENERATE_COT``”h]”hŒGENERATE_COT”…””}”(hhh!j6 ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j2 ubhŒ-: Boolean flag used to build and execute the ”…””}”(hŒ-: Boolean flag used to build and execute the ”h!j2 ubjá)”}”(hŒ``cert_create``”h]”hŒcert_create”…””}”(hhh!jI ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j2 ubhŒD tool to create certificates as per the Chain of Trust described in ”…””}”(hŒD tool to create certificates as per the Chain of Trust described in ”h!j2 ubh)”}”(hŒ:ref:`Trusted Board Boot`”h]”h)”}”(hj^ h]”hŒTrusted Board Boot”…””}”(hhh!j` ubah"}”(h$]”h&]”(h(Œstd”Œstd-ref”eh+]”h-]”h/]”uh1hh!j\ ubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”jj Œreftype”Œref”Œrefexplicit”‰Œrefwarn”ˆh?Œtrusted board boot”uh1hhAj¡hCM‘h!j2 ubhŒ. The build system then calls ”…””}”(hŒ. The build system then calls ”h!j2 ubjá)”}”(hŒ``fiptool``”h]”hŒfiptool”…””}”(hhh!j ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j2 ubhŒN to include the certificates in the FIP and FWU_FIP. Default value is â€˜0â€™.”…””}”(hŒJ to include the certificates in the FIP and FWU_FIP. Default value is '0'.”h!j2 ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCM‘h!j. ubj£)”}”(hŒóSpecify both ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=1`` to include support for the Trusted Board Boot feature in the BL1 and BL2 images, to generate the corresponding certificates, and to include those certificates in the FIP and FWU_FIP.”h]”(hŒ Specify both ”…””}”(hŒ Specify both ”h!jš ubjá)”}”(hŒ``TRUSTED_BOARD_BOOT=1``”h]”hŒTRUSTED_BOARD_BOOT=1”…””}”(hhh!j£ ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jš ubhŒ and ”…””}”(hŒ and ”h!jš ubjá)”}”(hŒ``GENERATE_COT=1``”h]”hŒGENERATE_COT=1”…””}”(hhh!j¶ ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jš ubhŒ· to include support for the Trusted Board Boot feature in the BL1 and BL2 images, to generate the corresponding certificates, and to include those certificates in the FIP and FWU_FIP.”…””}”(hŒ· to include support for the Trusted Board Boot feature in the BL1 and BL2 images, to generate the corresponding certificates, and to include those certificates in the FIP and FWU_FIP.”h!jš ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCM–h!j. ubj£)”}”(hX Note that if ``TRUSTED_BOARD_BOOT=0`` and ``GENERATE_COT=1``, the BL1 and BL2 images will not include support for Trusted Board Boot. The FIP will still include the corresponding certificates. This FIP can be used to verify the Chain of Trust on the host machine through other mechanisms.”h]”(hŒ Note that if ”…””}”(hŒ Note that if ”h!jÏ ubjá)”}”(hŒ``TRUSTED_BOARD_BOOT=0``”h]”hŒTRUSTED_BOARD_BOOT=0”…””}”(hhh!jØ ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jÏ ubhŒ and ”…””}”(hŒ and ”h!jÏ ubjá)”}”(hŒ``GENERATE_COT=1``”h]”hŒGENERATE_COT=1”…””}”(hhh!jë ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jÏ ubhŒä, the BL1 and BL2 images will not include support for Trusted Board Boot. The FIP will still include the corresponding certificates. This FIP can be used to verify the Chain of Trust on the host machine through other mechanisms.”…””}”(hŒä, the BL1 and BL2 images will not include support for Trusted Board Boot. The FIP will still include the corresponding certificates. This FIP can be used to verify the Chain of Trust on the host machine through other mechanisms.”h!jÏ ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCM›h!j. ubj£)”}”(hŒâNote that if ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=0``, the BL1 and BL2 images will include support for Trusted Board Boot, but the FIP and FWU_FIP will not include the corresponding certificates, causing a boot failure.”h]”(hŒ Note that if ”…””}”(hŒ Note that if ”h!j!ubjá)”}”(hŒ``TRUSTED_BOARD_BOOT=1``”h]”hŒTRUSTED_BOARD_BOOT=1”…””}”(hhh!j !ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j!ubhŒ and ”…””}”(hŒ and ”h!j!ubjá)”}”(hŒ``GENERATE_COT=0``”h]”hŒGENERATE_COT=0”…””}”(hhh!j !ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j!ubhŒ¦, the BL1 and BL2 images will include support for Trusted Board Boot, but the FIP and FWU_FIP will not include the corresponding certificates, causing a boot failure.”…””}”(hŒ¦, the BL1 and BL2 images will include support for Trusted Board Boot, but the FIP and FWU_FIP will not include the corresponding certificates, causing a boot failure.”h!j!ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCM h!j. ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hXå``GICV2_G0_FOR_EL3``: Unlike GICv3, the GICv2 architecture doesn't have inherent support for specific EL3 type interrupts. Setting this build option to ``1`` assumes GICv2 *Group 0* interrupts are expected to target EL3, both by :ref:`platform abstraction layer` and :ref:`Interrupt Management Framework`. This allows GICv2 platforms to enable features requiring EL3 interrupt type. This also means that all GICv2 Group 0 interrupts are delivered to EL3, and the Secure Payload interrupts needs to be synchronously handed over to Secure EL1 for handling. The default value of this option is ``0``, which means the Group 0 interrupts are assumed to be handled by Secure EL1. ”h]”j£)”}”(hXä``GICV2_G0_FOR_EL3``: Unlike GICv3, the GICv2 architecture doesn't have inherent support for specific EL3 type interrupts. Setting this build option to ``1`` assumes GICv2 *Group 0* interrupts are expected to target EL3, both by :ref:`platform abstraction layer` and :ref:`Interrupt Management Framework`. This allows GICv2 platforms to enable features requiring EL3 interrupt type. This also means that all GICv2 Group 0 interrupts are delivered to EL3, and the Secure Payload interrupts needs to be synchronously handed over to Secure EL1 for handling. The default value of this option is ``0``, which means the Group 0 interrupts are assumed to be handled by Secure EL1.”h]”(já)”}”(hŒ``GICV2_G0_FOR_EL3``”h]”hŒGICV2_G0_FOR_EL3”…””}”(hhh!jG!ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jC!ubhŒ†: Unlike GICv3, the GICv2 architecture doesnâ€™t have inherent support for specific EL3 type interrupts. Setting this build option to ”…””}”(hŒ„: Unlike GICv3, the GICv2 architecture doesn't have inherent support for specific EL3 type interrupts. Setting this build option to ”h!jC!ubjá)”}”(hŒ``1``”h]”hŒ1”…””}”(hhh!jZ!ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jC!ubhŒ assumes GICv2 ”…””}”(hŒ assumes GICv2 ”h!jC!ubjc )”}”(hŒ *Group 0*”h]”hŒGroup 0”…””}”(hhh!jm!ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jb h!jC!ubhŒ0 interrupts are expected to target EL3, both by ”…””}”(hŒ0 interrupts are expected to target EL3, both by ”h!jC!ubh)”}”(hŒD:ref:`platform abstraction layer`”h]”h)”}”(hj‚!h]”hŒplatform abstraction layer”…””}”(hhh!j„!ubah"}”(h$]”h&]”(h(Œstd”Œstd-ref”eh+]”h-]”h/]”uh1hh!j€!ubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”jŽ!Œreftype”Œref”Œrefexplicit”ˆŒrefwarn”ˆh?Œ!platform interrupt controller api”uh1hhAj¡hCM¤h!jC!ubhŒ and ”…””}”(hŒ and ”h!jC!ubh)”}”(hŒE:ref:`Interrupt Management Framework`”h]”h)”}”(hj§!h]”hŒInterrupt Management Framework”…””}”(hhh!j©!ubah"}”(h$]”h&]”(h(Œstd”Œstd-ref”eh+]”h-]”h/]”uh1hh!j¥!ubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”j³!Œreftype”Œref”Œrefexplicit”ˆŒrefwarn”ˆh?Œinterrupt management framework”uh1hhAj¡hCM¤h!jC!ubhX. This allows GICv2 platforms to enable features requiring EL3 interrupt type. This also means that all GICv2 Group 0 interrupts are delivered to EL3, and the Secure Payload interrupts needs to be synchronously handed over to Secure EL1 for handling. The default value of this option is ”…””}”(hX. This allows GICv2 platforms to enable features requiring EL3 interrupt type. This also means that all GICv2 Group 0 interrupts are delivered to EL3, and the Secure Payload interrupts needs to be synchronously handed over to Secure EL1 for handling. The default value of this option is ”h!jC!ubjá)”}”(hŒ``0``”h]”hŒ0”…””}”(hhh!jÊ!ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jC!ubhŒM, which means the Group 0 interrupts are assumed to be handled by Secure EL1.”…””}”(hŒM, which means the Group 0 interrupts are assumed to be handled by Secure EL1.”h!jC!ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCM¤h!j?!ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hX``HANDLE_EA_EL3_FIRST``: When set to ``1``, External Aborts and SError Interrupts will be always trapped in EL3 i.e. in BL31 at runtime. When set to ``0`` (default), these exceptions will be trapped in the current exception level (or in EL1 if the current exception level is EL0). ”h]”j£)”}”(hX``HANDLE_EA_EL3_FIRST``: When set to ``1``, External Aborts and SError Interrupts will be always trapped in EL3 i.e. in BL31 at runtime. When set to ``0`` (default), these exceptions will be trapped in the current exception level (or in EL1 if the current exception level is EL0).”h]”(já)”}”(hŒ``HANDLE_EA_EL3_FIRST``”h]”hŒHANDLE_EA_EL3_FIRST”…””}”(hhh!jñ!ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jí!ubhŒ: When set to ”…””}”(hŒ: When set to ”h!jí!ubjá)”}”(hŒ``1``”h]”hŒ1”…””}”(hhh!j"ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jí!ubhŒk, External Aborts and SError Interrupts will be always trapped in EL3 i.e. in BL31 at runtime. When set to ”…””}”(hŒk, External Aborts and SError Interrupts will be always trapped in EL3 i.e. in BL31 at runtime. When set to ”h!jí!ubjá)”}”(hŒ``0``”h]”hŒ0”…””}”(hhh!j"ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jí!ubhŒ~ (default), these exceptions will be trapped in the current exception level (or in EL1 if the current exception level is EL0).”…””}”(hŒ~ (default), these exceptions will be trapped in the current exception level (or in EL1 if the current exception level is EL0).”h!jí!ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCM¯h!jé!ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hXì``HW_ASSISTED_COHERENCY``: On most Arm systems to-date, platform-specific software operations are required for CPUs to enter and exit coherency. However, newer systems exist where CPUs' entry to and exit from coherency is managed in hardware. Such systems require software to only initiate these operations, and the rest is managed in hardware, minimizing active software management. In such systems, this boolean option enables TF-A to carry out build and run-time optimizations during boot and power management operations. This option defaults to 0 and if it is enabled, then it implies ``WARMBOOT_ENABLE_DCACHE_EARLY`` is also enabled. If this flag is disabled while the platform which TF-A is compiled for includes cores that manage coherency in hardware, then a compilation error is generated. This is based on the fact that a system cannot have, at the same time, cores that manage coherency in hardware and cores that don't. In other words, a platform cannot have, at the same time, cores that require ``HW_ASSISTED_COHERENCY=1`` and cores that require ``HW_ASSISTED_COHERENCY=0``. Note that, when ``HW_ASSISTED_COHERENCY`` is enabled, version 2 of translation library (xlat tables v2) must be used; version 1 of translation library is not supported. ”h]”(j£)”}”(hX~``HW_ASSISTED_COHERENCY``: On most Arm systems to-date, platform-specific software operations are required for CPUs to enter and exit coherency. However, newer systems exist where CPUs' entry to and exit from coherency is managed in hardware. Such systems require software to only initiate these operations, and the rest is managed in hardware, minimizing active software management. In such systems, this boolean option enables TF-A to carry out build and run-time optimizations during boot and power management operations. This option defaults to 0 and if it is enabled, then it implies ``WARMBOOT_ENABLE_DCACHE_EARLY`` is also enabled.”h]”(já)”}”(hŒ``HW_ASSISTED_COHERENCY``”h]”hŒHW_ASSISTED_COHERENCY”…””}”(hhh!j>"ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j:"ubhX6: On most Arm systems to-date, platform-specific software operations are required for CPUs to enter and exit coherency. However, newer systems exist where CPUsâ€™ entry to and exit from coherency is managed in hardware. Such systems require software to only initiate these operations, and the rest is managed in hardware, minimizing active software management. In such systems, this boolean option enables TF-A to carry out build and run-time optimizations during boot and power management operations. This option defaults to 0 and if it is enabled, then it implies ”…””}”(hX4: On most Arm systems to-date, platform-specific software operations are required for CPUs to enter and exit coherency. However, newer systems exist where CPUs' entry to and exit from coherency is managed in hardware. Such systems require software to only initiate these operations, and the rest is managed in hardware, minimizing active software management. In such systems, this boolean option enables TF-A to carry out build and run-time optimizations during boot and power management operations. This option defaults to 0 and if it is enabled, then it implies ”h!j:"ubjá)”}”(hŒ ``WARMBOOT_ENABLE_DCACHE_EARLY``”h]”hŒWARMBOOT_ENABLE_DCACHE_EARLY”…””}”(hhh!jQ"ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j:"ubhŒ is also enabled.”…””}”(hŒ is also enabled.”h!j:"ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCM´h!j6"ubj£)”}”(hXÁIf this flag is disabled while the platform which TF-A is compiled for includes cores that manage coherency in hardware, then a compilation error is generated. This is based on the fact that a system cannot have, at the same time, cores that manage coherency in hardware and cores that don't. In other words, a platform cannot have, at the same time, cores that require ``HW_ASSISTED_COHERENCY=1`` and cores that require ``HW_ASSISTED_COHERENCY=0``.”h]”(hXtIf this flag is disabled while the platform which TF-A is compiled for includes cores that manage coherency in hardware, then a compilation error is generated. This is based on the fact that a system cannot have, at the same time, cores that manage coherency in hardware and cores that donâ€™t. In other words, a platform cannot have, at the same time, cores that require ”…””}”(hXrIf this flag is disabled while the platform which TF-A is compiled for includes cores that manage coherency in hardware, then a compilation error is generated. This is based on the fact that a system cannot have, at the same time, cores that manage coherency in hardware and cores that don't. In other words, a platform cannot have, at the same time, cores that require ”h!jj"ubjá)”}”(hŒ``HW_ASSISTED_COHERENCY=1``”h]”hŒHW_ASSISTED_COHERENCY=1”…””}”(hhh!js"ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jj"ubhŒ and cores that require ”…””}”(hŒ and cores that require ”h!jj"ubjá)”}”(hŒ``HW_ASSISTED_COHERENCY=0``”h]”hŒHW_ASSISTED_COHERENCY=0”…””}”(hhh!j†"ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jj"ubhŒ.”…””}”(hjTh!jj"ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCM¾h!j6"ubj£)”}”(hŒ¨Note that, when ``HW_ASSISTED_COHERENCY`` is enabled, version 2 of translation library (xlat tables v2) must be used; version 1 of translation library is not supported.”h]”(hŒNote that, when ”…””}”(hŒNote that, when ”h!jž"ubjá)”}”(hŒ``HW_ASSISTED_COHERENCY``”h]”hŒHW_ASSISTED_COHERENCY”…””}”(hhh!j§"ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jž"ubhŒ is enabled, version 2 of translation library (xlat tables v2) must be used; version 1 of translation library is not supported.”…””}”(hŒ is enabled, version 2 of translation library (xlat tables v2) must be used; version 1 of translation library is not supported.”h!jž"ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMÆh!j6"ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hŒø``INVERTED_MEMMAP``: memmap tool print by default lower addresses at the bottom, higher addresses at the top. This build flag can be set to '1' to invert this behavior. Lower addresses will be printed at the top and higher addresses at the bottom. ”h]”j£)”}”(hŒ÷``INVERTED_MEMMAP``: memmap tool print by default lower addresses at the bottom, higher addresses at the top. This build flag can be set to '1' to invert this behavior. Lower addresses will be printed at the top and higher addresses at the bottom.”h]”(já)”}”(hŒ``INVERTED_MEMMAP``”h]”hŒINVERTED_MEMMAP”…””}”(hhh!jÎ"ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jÊ"ubhŒè: memmap tool print by default lower addresses at the bottom, higher addresses at the top. This build flag can be set to â€˜1â€™ to invert this behavior. Lower addresses will be printed at the top and higher addresses at the bottom.”…””}”(hŒä: memmap tool print by default lower addresses at the bottom, higher addresses at the top. This build flag can be set to '1' to invert this behavior. Lower addresses will be printed at the top and higher addresses at the bottom.”h!jÊ"ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMÊh!jÆ"ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hX;``JUNO_AARCH32_EL3_RUNTIME``: This build flag enables you to execute EL3 runtime software in AArch32 mode, which is required to run AArch32 on Juno. By default this flag is set to '0'. Enabling this flag builds BL1 and BL2 in AArch64 and facilitates the loading of ``SP_MIN`` and BL33 as AArch32 executable images. ”h]”j£)”}”(hX:``JUNO_AARCH32_EL3_RUNTIME``: This build flag enables you to execute EL3 runtime software in AArch32 mode, which is required to run AArch32 on Juno. By default this flag is set to '0'. Enabling this flag builds BL1 and BL2 in AArch64 and facilitates the loading of ``SP_MIN`` and BL33 as AArch32 executable images.”h]”(já)”}”(hŒ``JUNO_AARCH32_EL3_RUNTIME``”h]”hŒJUNO_AARCH32_EL3_RUNTIME”…””}”(hhh!jõ"ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jñ"ubhŒñ: This build flag enables you to execute EL3 runtime software in AArch32 mode, which is required to run AArch32 on Juno. By default this flag is set to â€˜0â€™. Enabling this flag builds BL1 and BL2 in AArch64 and facilitates the loading of ”…””}”(hŒí: This build flag enables you to execute EL3 runtime software in AArch32 mode, which is required to run AArch32 on Juno. By default this flag is set to '0'. Enabling this flag builds BL1 and BL2 in AArch64 and facilitates the loading of ”h!jñ"ubjá)”}”(hŒ ``SP_MIN``”h]”hŒSP_MIN”…””}”(hhh!j#ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jñ"ubhŒ' and BL33 as AArch32 executable images.”…””}”(hŒ' and BL33 as AArch32 executable images.”h!jñ"ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMÏh!jí"ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hX±``KEY_ALG``: This build flag enables the user to select the algorithm to be used for generating the PKCS keys and subsequent signing of the certificate. It accepts 3 values: ``rsa``, ``rsa_1_5`` and ``ecdsa``. The option ``rsa_1_5`` is the legacy PKCS#1 RSA 1.5 algorithm which is not TBBR compliant and is retained only for compatibility. The default value of this flag is ``rsa`` which is the TBBR compliant PKCS#1 RSA 2.1 scheme. ”h]”j£)”}”(hX°``KEY_ALG``: This build flag enables the user to select the algorithm to be used for generating the PKCS keys and subsequent signing of the certificate. It accepts 3 values: ``rsa``, ``rsa_1_5`` and ``ecdsa``. The option ``rsa_1_5`` is the legacy PKCS#1 RSA 1.5 algorithm which is not TBBR compliant and is retained only for compatibility. The default value of this flag is ``rsa`` which is the TBBR compliant PKCS#1 RSA 2.1 scheme.”h]”(já)”}”(hŒ``KEY_ALG``”h]”hŒKEY_ALG”…””}”(hhh!j/#ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j+#ubhŒ£: This build flag enables the user to select the algorithm to be used for generating the PKCS keys and subsequent signing of the certificate. It accepts 3 values: ”…””}”(hŒ£: This build flag enables the user to select the algorithm to be used for generating the PKCS keys and subsequent signing of the certificate. It accepts 3 values: ”h!j+#ubjá)”}”(hŒ``rsa``”h]”hŒrsa”…””}”(hhh!jB#ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j+#ubhŒ, ”…””}”(hŒ, ”h!j+#ubjá)”}”(hŒ``rsa_1_5``”h]”hŒrsa_1_5”…””}”(hhh!jU#ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j+#ubhŒ and ”…””}”(hŒ and ”h!j+#ubjá)”}”(hŒ ``ecdsa``”h]”hŒecdsa”…””}”(hhh!jh#ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j+#ubhŒ . The option ”…””}”(hŒ . The option ”h!j+#ubjá)”}”(hŒ``rsa_1_5``”h]”hŒrsa_1_5”…””}”(hhh!j{#ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j+#ubhŒŽ is the legacy PKCS#1 RSA 1.5 algorithm which is not TBBR compliant and is retained only for compatibility. The default value of this flag is ”…””}”(hŒŽ is the legacy PKCS#1 RSA 1.5 algorithm which is not TBBR compliant and is retained only for compatibility. The default value of this flag is ”h!j+#ubjá)”}”(hŒ``rsa``”h]”hŒrsa”…””}”(hhh!jŽ#ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j+#ubhŒ3 which is the TBBR compliant PKCS#1 RSA 2.1 scheme.”…””}”(hŒ3 which is the TBBR compliant PKCS#1 RSA 2.1 scheme.”h!j+#ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMÕh!j'#ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hXÈ``KEY_SIZE``: This build flag enables the user to select the key size for the algorithm specified by ``KEY_ALG``. The valid values for ``KEY_SIZE`` depend on the chosen algorithm and the cryptographic module. +-----------+------------------------------------+ | KEY_ALG | Possible key sizes | +===========+====================================+ | rsa | 1024 , 2048 (default), 3072, 4096* | +-----------+------------------------------------+ | ecdsa | unavailable | +-----------+------------------------------------+ * Only 2048 bits size is available with CryptoCell 712 SBROM release 1. Only 3072 bits size is available with CryptoCell 712 SBROM release 2. ”h]”(j£)”}”(hŒÐ``KEY_SIZE``: This build flag enables the user to select the key size for the algorithm specified by ``KEY_ALG``. The valid values for ``KEY_SIZE`` depend on the chosen algorithm and the cryptographic module.”h]”(já)”}”(hŒ``KEY_SIZE``”h]”hŒKEY_SIZE”…””}”(hhh!jµ#ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j±#ubhŒY: This build flag enables the user to select the key size for the algorithm specified by ”…””}”(hŒY: This build flag enables the user to select the key size for the algorithm specified by ”h!j±#ubjá)”}”(hŒ``KEY_ALG``”h]”hŒKEY_ALG”…””}”(hhh!jÈ#ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j±#ubhŒ. The valid values for ”…””}”(hŒ. The valid values for ”h!j±#ubjá)”}”(hŒ``KEY_SIZE``”h]”hŒKEY_SIZE”…””}”(hhh!jÛ#ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j±#ubhŒ= depend on the chosen algorithm and the cryptographic module.”…””}”(hŒ= depend on the chosen algorithm and the cryptographic module.”h!j±#ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMÜh!j#ubjÕ)”}”(hhh]”jÚ)”}”(hhh]”(jß)”}”(hhh]”h"}”(h$]”h&]”h+]”h-]”h/]”Œcolwidth”Kuh1jÞh!j÷#ubjß)”}”(hhh]”h"}”(h$]”h&]”h+]”h-]”h/]”Œcolwidth”K$uh1jÞh!j÷#ubj )”}”(hhh]”j)”}”(hhh]”(j)”}”(hhh]”j£)”}”(hŒKEY_ALG”h]”hŒKEY_ALG”…””}”(hj$h!j$ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMáh!j$ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!j$ubj)”}”(hhh]”j£)”}”(hŒPossible key sizes”h]”hŒPossible key sizes”…””}”(hj0$h!j.$ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMáh!j+$ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!j$ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j h!j$ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!j÷#ubj})”}”(hhh]”(j)”}”(hhh]”(j)”}”(hhh]”j£)”}”(hŒrsa”h]”hŒrsa”…””}”(hjY$h!jW$ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMãh!jT$ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jQ$ubj)”}”(hhh]”j£)”}”(hŒ"1024 , 2048 (default), 3072, 4096*”h]”hŒ"1024 , 2048 (default), 3072, 4096*”…””}”(hjp$h!jn$ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMãh!jk$ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jQ$ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j h!jN$ubj)”}”(hhh]”(j)”}”(hhh]”j£)”}”(hŒecdsa”h]”hŒecdsa”…””}”(hj$h!jŽ$ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMåh!j‹$ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jˆ$ubj)”}”(hhh]”j£)”}”(hŒunavailable”h]”hŒunavailable”…””}”(hj§$h!j¥$ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMåh!j¢$ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jˆ$ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j h!jN$ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j|h!j÷#ubeh"}”(h$]”h&]”h+]”h-]”h/]”Œcols”Kuh1jÙh!jô#ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÔh!j#ubjÒ)”}”(hhh]”j×)”}”(hŒŒOnly 2048 bits size is available with CryptoCell 712 SBROM release 1. Only 3072 bits size is available with CryptoCell 712 SBROM release 2. ”h]”j£)”}”(hŒ‹Only 2048 bits size is available with CryptoCell 712 SBROM release 1. Only 3072 bits size is available with CryptoCell 712 SBROM release 2.”h]”hŒ‹Only 2048 bits size is available with CryptoCell 712 SBROM release 1. Only 3072 bits size is available with CryptoCell 712 SBROM release 2.”…””}”(hjÛ$h!jÙ$ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMèh!jÕ$ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÒ$ubah"}”(h$]”h&]”h+]”h-]”h/]”Œbullet”Œ*”uh1jÑhAj¡hCMèh!j#ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhANhCNubj×)”}”(hŒ¾``HASH_ALG``: This build flag enables the user to select the secure hash algorithm. It accepts 3 values: ``sha256``, ``sha384`` and ``sha512``. The default value of this flag is ``sha256``. ”h]”j£)”}”(hŒ½``HASH_ALG``: This build flag enables the user to select the secure hash algorithm. It accepts 3 values: ``sha256``, ``sha384`` and ``sha512``. The default value of this flag is ``sha256``.”h]”(já)”}”(hŒ``HASH_ALG``”h]”hŒHASH_ALG”…””}”(hhh!j%ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jÿ$ubhŒ]: This build flag enables the user to select the secure hash algorithm. It accepts 3 values: ”…””}”(hŒ]: This build flag enables the user to select the secure hash algorithm. It accepts 3 values: ”h!jÿ$ubjá)”}”(hŒ ``sha256``”h]”hŒsha256”…””}”(hhh!j%ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jÿ$ubhŒ, ”…””}”(hŒ, ”h!jÿ$ubjá)”}”(hŒ ``sha384``”h]”hŒsha384”…””}”(hhh!j)%ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jÿ$ubhŒ and ”…””}”(hŒ and ”h!jÿ$ubjá)”}”(hŒ ``sha512``”h]”hŒsha512”…””}”(hhh!j<%ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jÿ$ubhŒ$. The default value of this flag is ”…””}”(hŒ$. The default value of this flag is ”h!jÿ$ubjá)”}”(hŒ ``sha256``”h]”hŒsha256”…””}”(hhh!jO%ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jÿ$ubhŒ.”…””}”(hjTh!jÿ$ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMëh!jû$ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hŒv``LDFLAGS``: Extra user options appended to the linkers' command line in addition to the one set by the build system. ”h]”j£)”}”(hŒu``LDFLAGS``: Extra user options appended to the linkers' command line in addition to the one set by the build system.”h]”(já)”}”(hŒ``LDFLAGS``”h]”hŒLDFLAGS”…””}”(hhh!ju%ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jq%ubhŒl: Extra user options appended to the linkersâ€™ command line in addition to the one set by the build system.”…””}”(hŒj: Extra user options appended to the linkers' command line in addition to the one set by the build system.”h!jq%ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMïh!jm%ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hXË``LOG_LEVEL``: Chooses the log level, which controls the amount of console log output compiled into the build. This should be one of the following: :: 0 (LOG_LEVEL_NONE) 10 (LOG_LEVEL_ERROR) 20 (LOG_LEVEL_NOTICE) 30 (LOG_LEVEL_WARNING) 40 (LOG_LEVEL_INFO) 50 (LOG_LEVEL_VERBOSE) All log output up to and including the selected log level is compiled into the build. The default value is 40 in debug builds and 20 in release builds. ”h]”(j£)”}”(hŒ“``LOG_LEVEL``: Chooses the log level, which controls the amount of console log output compiled into the build. This should be one of the following:”h]”(já)”}”(hŒ ``LOG_LEVEL``”h]”hŒ LOG_LEVEL”…””}”(hhh!jœ%ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j˜%ubhŒ†: Chooses the log level, which controls the amount of console log output compiled into the build. This should be one of the following:”…””}”(hŒ†: Chooses the log level, which controls the amount of console log output compiled into the build. This should be one of the following:”h!j˜%ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMòh!j”%ubjõ)”}”(hŒ€0 (LOG_LEVEL_NONE) 10 (LOG_LEVEL_ERROR) 20 (LOG_LEVEL_NOTICE) 30 (LOG_LEVEL_WARNING) 40 (LOG_LEVEL_INFO) 50 (LOG_LEVEL_VERBOSE)”h]”hŒ€0 (LOG_LEVEL_NONE) 10 (LOG_LEVEL_ERROR) 20 (LOG_LEVEL_NOTICE) 30 (LOG_LEVEL_WARNING) 40 (LOG_LEVEL_INFO) 50 (LOG_LEVEL_VERBOSE)”…””}”(hhh!jµ%ubah"}”(h$]”h&]”h+]”h-]”h/]”j j uh1jôhAj¡hCM÷h!j”%ubj£)”}”(hŒ—All log output up to and including the selected log level is compiled into the build. The default value is 40 in debug builds and 20 in release builds.”h]”hŒ—All log output up to and including the selected log level is compiled into the build. The default value is 40 in debug builds and 20 in release builds.”…””}”(hjÅ%h!jÃ%ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMþh!j”%ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hX ``MEASURED_BOOT``: Boolean flag to include support for the Measured Boot feature. If this flag is enabled ``TRUSTED_BOARD_BOOT`` must be set as well in order to provide trust that the code taking the measurements and recording them has not been tampered with. This option defaults to 0. ”h]”(j£)”}”(hX``MEASURED_BOOT``: Boolean flag to include support for the Measured Boot feature. If this flag is enabled ``TRUSTED_BOARD_BOOT`` must be set as well in order to provide trust that the code taking the measurements and recording them has not been tampered with.”h]”(já)”}”(hŒ``MEASURED_BOOT``”h]”hŒ MEASURED_BOOT”…””}”(hhh!jß%ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jÛ%ubhŒY: Boolean flag to include support for the Measured Boot feature. If this flag is enabled ”…””}”(hŒY: Boolean flag to include support for the Measured Boot feature. If this flag is enabled ”h!jÛ%ubjá)”}”(hŒ``TRUSTED_BOARD_BOOT``”h]”hŒTRUSTED_BOARD_BOOT”…””}”(hhh!jò%ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jÛ%ubhŒƒ must be set as well in order to provide trust that the code taking the measurements and recording them has not been tampered with.”…””}”(hŒƒ must be set as well in order to provide trust that the code taking the measurements and recording them has not been tampered with.”h!jÛ%ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMh!j×%ubj£)”}”(hŒThis option defaults to 0.”h]”hŒThis option defaults to 0.”…””}”(hj &h!j&ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMh!j×%ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hŒÞ``NON_TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the file that contains the Non-Trusted World private key in PEM format. If ``SAVE_KEYS=1``, this file name will be used to save the key. ”h]”j£)”}”(hŒÝ``NON_TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the file that contains the Non-Trusted World private key in PEM format. If ``SAVE_KEYS=1``, this file name will be used to save the key.”h]”(já)”}”(hŒ``NON_TRUSTED_WORLD_KEY``”h]”hŒNON_TRUSTED_WORLD_KEY”…””}”(hhh!j'&ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j#&ubhŒ: This option is used when ”…””}”(hŒ: This option is used when ”h!j#&ubjá)”}”(hŒ``GENERATE_COT=1``”h]”hŒGENERATE_COT=1”…””}”(hhh!j:&ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j#&ubhŒZ. It specifies the file that contains the Non-Trusted World private key in PEM format. If ”…””}”(hŒZ. It specifies the file that contains the Non-Trusted World private key in PEM format. If ”h!j#&ubjá)”}”(hŒ``SAVE_KEYS=1``”h]”hŒSAVE_KEYS=1”…””}”(hhh!jM&ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j#&ubhŒ., this file name will be used to save the key.”…””}”(hŒ., this file name will be used to save the key.”h!j#&ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMh!j&ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hŒÇ``NS_BL2U``: Path to NS_BL2U image in the host file system. This image is optional. It is only needed if the platform makefile specifies that it is required in order to build the ``fwu_fip`` target. ”h]”j£)”}”(hŒÆ``NS_BL2U``: Path to NS_BL2U image in the host file system. This image is optional. It is only needed if the platform makefile specifies that it is required in order to build the ``fwu_fip`` target.”h]”(já)”}”(hŒ``NS_BL2U``”h]”hŒNS_BL2U”…””}”(hhh!jt&ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jp&ubhŒ¨: Path to NS_BL2U image in the host file system. This image is optional. It is only needed if the platform makefile specifies that it is required in order to build the ”…””}”(hŒ¨: Path to NS_BL2U image in the host file system. This image is optional. It is only needed if the platform makefile specifies that it is required in order to build the ”h!jp&ubjá)”}”(hŒ``fwu_fip``”h]”hŒfwu_fip”…””}”(hhh!j‡&ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jp&ubhŒ target.”…””}”(hŒ target.”h!jp&ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMh!jl&ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hX``NS_TIMER_SWITCH``: Enable save and restore for non-secure timer register contents upon world switch. It can take either 0 (don't save and restore) or 1 (do save and restore). 0 is the default. An SPD may set this to 1 if it wants the timer registers to be saved and restored. ”h]”j£)”}”(hX``NS_TIMER_SWITCH``: Enable save and restore for non-secure timer register contents upon world switch. It can take either 0 (don't save and restore) or 1 (do save and restore). 0 is the default. An SPD may set this to 1 if it wants the timer registers to be saved and restored.”h]”(já)”}”(hŒ``NS_TIMER_SWITCH``”h]”hŒNS_TIMER_SWITCH”…””}”(hhh!j®&ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jª&ubhX: Enable save and restore for non-secure timer register contents upon world switch. It can take either 0 (donâ€™t save and restore) or 1 (do save and restore). 0 is the default. An SPD may set this to 1 if it wants the timer registers to be saved and restored.”…””}”(hX: Enable save and restore for non-secure timer register contents upon world switch. It can take either 0 (don't save and restore) or 1 (do save and restore). 0 is the default. An SPD may set this to 1 if it wants the timer registers to be saved and restored.”h!jª&ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMh!j¦&ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hŒ£``OVERRIDE_LIBC``: This option allows platforms to override the default libc for the BL image. It can be either 0 (include) or 1 (remove). The default value is 0. ”h]”j£)”}”(hŒ¢``OVERRIDE_LIBC``: This option allows platforms to override the default libc for the BL image. It can be either 0 (include) or 1 (remove). The default value is 0.”h]”(já)”}”(hŒ``OVERRIDE_LIBC``”h]”hŒ OVERRIDE_LIBC”…””}”(hhh!jÕ&ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jÑ&ubhŒ‘: This option allows platforms to override the default libc for the BL image. It can be either 0 (include) or 1 (remove). The default value is 0.”…””}”(hŒ‘: This option allows platforms to override the default libc for the BL image. It can be either 0 (include) or 1 (remove). The default value is 0.”h!jÑ&ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMh!jÍ&ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hX```PL011_GENERIC_UART``: Boolean option to indicate the PL011 driver that the underlying hardware is not a full PL011 UART but a minimally compliant generic UART, which is a subset of the PL011. The driver will not access any register that is not part of the SBSA generic UART specification. Default value is 0 (a full PL011 compliant UART is present). ”h]”j£)”}”(hX_``PL011_GENERIC_UART``: Boolean option to indicate the PL011 driver that the underlying hardware is not a full PL011 UART but a minimally compliant generic UART, which is a subset of the PL011. The driver will not access any register that is not part of the SBSA generic UART specification. Default value is 0 (a full PL011 compliant UART is present).”h]”(já)”}”(hŒ``PL011_GENERIC_UART``”h]”hŒPL011_GENERIC_UART”…””}”(hhh!jü&ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jø&ubhXI: Boolean option to indicate the PL011 driver that the underlying hardware is not a full PL011 UART but a minimally compliant generic UART, which is a subset of the PL011. The driver will not access any register that is not part of the SBSA generic UART specification. Default value is 0 (a full PL011 compliant UART is present).”…””}”(hXI: Boolean option to indicate the PL011 driver that the underlying hardware is not a full PL011 UART but a minimally compliant generic UART, which is a subset of the PL011. The driver will not access any register that is not part of the SBSA generic UART specification. Default value is 0 (a full PL011 compliant UART is present).”h!jø&ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMh!jô&ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hŒü``PLAT``: Choose a platform to build TF-A for. The chosen platform name must be subdirectory of any depth under ``plat/``, and must contain a platform makefile named ``platform.mk``. For example, to build TF-A for the Arm Juno board, select PLAT=juno. ”h]”j£)”}”(hŒû``PLAT``: Choose a platform to build TF-A for. The chosen platform name must be subdirectory of any depth under ``plat/``, and must contain a platform makefile named ``platform.mk``. For example, to build TF-A for the Arm Juno board, select PLAT=juno.”h]”(já)”}”(hŒ``PLAT``”h]”hŒPLAT”…””}”(hhh!j#'ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j'ubhŒh: Choose a platform to build TF-A for. The chosen platform name must be subdirectory of any depth under ”…””}”(hŒh: Choose a platform to build TF-A for. The chosen platform name must be subdirectory of any depth under ”h!j'ubjá)”}”(hŒ ``plat/``”h]”hŒplat/”…””}”(hhh!j6'ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j'ubhŒ-, and must contain a platform makefile named ”…””}”(hŒ-, and must contain a platform makefile named ”h!j'ubjá)”}”(hŒ``platform.mk``”h]”hŒplatform.mk”…””}”(hhh!jI'ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j'ubhŒF. For example, to build TF-A for the Arm Juno board, select PLAT=juno.”…””}”(hŒF. For example, to build TF-A for the Arm Juno board, select PLAT=juno.”h!j'ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMh!j'ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hXM``PRELOADED_BL33_BASE``: This option enables booting a preloaded BL33 image instead of the normal boot flow. When defined, it must specify the entry point address for the preloaded BL33 image. This option is incompatible with ``EL3_PAYLOAD_BASE``. If both are defined, ``EL3_PAYLOAD_BASE`` has priority over ``PRELOADED_BL33_BASE``. ”h]”j£)”}”(hXL``PRELOADED_BL33_BASE``: This option enables booting a preloaded BL33 image instead of the normal boot flow. When defined, it must specify the entry point address for the preloaded BL33 image. This option is incompatible with ``EL3_PAYLOAD_BASE``. If both are defined, ``EL3_PAYLOAD_BASE`` has priority over ``PRELOADED_BL33_BASE``.”h]”(já)”}”(hŒ``PRELOADED_BL33_BASE``”h]”hŒPRELOADED_BL33_BASE”…””}”(hhh!jp'ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jl'ubhŒË: This option enables booting a preloaded BL33 image instead of the normal boot flow. When defined, it must specify the entry point address for the preloaded BL33 image. This option is incompatible with ”…””}”(hŒË: This option enables booting a preloaded BL33 image instead of the normal boot flow. When defined, it must specify the entry point address for the preloaded BL33 image. This option is incompatible with ”h!jl'ubjá)”}”(hŒ``EL3_PAYLOAD_BASE``”h]”hŒEL3_PAYLOAD_BASE”…””}”(hhh!jƒ'ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jl'ubhŒ. If both are defined, ”…””}”(hŒ. If both are defined, ”h!jl'ubjá)”}”(hŒ``EL3_PAYLOAD_BASE``”h]”hŒEL3_PAYLOAD_BASE”…””}”(hhh!j–'ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jl'ubhŒ has priority over ”…””}”(hŒ has priority over ”h!jl'ubjá)”}”(hŒ``PRELOADED_BL33_BASE``”h]”hŒPRELOADED_BL33_BASE”…””}”(hhh!j©'ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jl'ubhŒ.”…””}”(hjTh!jl'ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCM$h!jh'ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hX:``PROGRAMMABLE_RESET_ADDRESS``: This option indicates whether the reset vector address can be programmed or is fixed on the platform. It can take either 0 (fixed) or 1 (programmable). Default is 0. If the platform has a programmable reset address, it is expected that a CPU will start executing code directly at the right address, both on a cold and warm reset. In this case, there is no need to identify the entrypoint on boot and the boot path can be optimised. The ``plat_get_my_entrypoint()`` platform porting interface does not need to be implemented in this case. ”h]”j£)”}”(hX9``PROGRAMMABLE_RESET_ADDRESS``: This option indicates whether the reset vector address can be programmed or is fixed on the platform. It can take either 0 (fixed) or 1 (programmable). Default is 0. If the platform has a programmable reset address, it is expected that a CPU will start executing code directly at the right address, both on a cold and warm reset. In this case, there is no need to identify the entrypoint on boot and the boot path can be optimised. The ``plat_get_my_entrypoint()`` platform porting interface does not need to be implemented in this case.”h]”(já)”}”(hŒ``PROGRAMMABLE_RESET_ADDRESS``”h]”hŒPROGRAMMABLE_RESET_ADDRESS”…””}”(hhh!jÏ'ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jË'ubhX¶: This option indicates whether the reset vector address can be programmed or is fixed on the platform. It can take either 0 (fixed) or 1 (programmable). Default is 0. If the platform has a programmable reset address, it is expected that a CPU will start executing code directly at the right address, both on a cold and warm reset. In this case, there is no need to identify the entrypoint on boot and the boot path can be optimised. The ”…””}”(hX¶: This option indicates whether the reset vector address can be programmed or is fixed on the platform. It can take either 0 (fixed) or 1 (programmable). Default is 0. If the platform has a programmable reset address, it is expected that a CPU will start executing code directly at the right address, both on a cold and warm reset. In this case, there is no need to identify the entrypoint on boot and the boot path can be optimised. The ”h!jË'ubjá)”}”(hŒ``plat_get_my_entrypoint()``”h]”hŒplat_get_my_entrypoint()”…””}”(hhh!jâ'ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jË'ubhŒI platform porting interface does not need to be implemented in this case.”…””}”(hŒI platform porting interface does not need to be implemented in this case.”h!jË'ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCM*h!jÇ'ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hXw``PSCI_EXTENDED_STATE_ID``: As per PSCI1.0 Specification, there are 2 formats possible for the PSCI power-state parameter: original and extended State-ID formats. This flag if set to 1, configures the generic PSCI layer to use the extended format. The default value of this flag is 0, which means by default the original power-state format is used by the PSCI implementation. This flag should be specified by the platform makefile and it governs the return value of PSCI_FEATURES API for CPU_SUSPEND smc function id. When this option is enabled on Arm platforms, the option ``ARM_RECOM_STATE_ID_ENC`` needs to be set to 1 as well. ”h]”j£)”}”(hXv``PSCI_EXTENDED_STATE_ID``: As per PSCI1.0 Specification, there are 2 formats possible for the PSCI power-state parameter: original and extended State-ID formats. This flag if set to 1, configures the generic PSCI layer to use the extended format. The default value of this flag is 0, which means by default the original power-state format is used by the PSCI implementation. This flag should be specified by the platform makefile and it governs the return value of PSCI_FEATURES API for CPU_SUSPEND smc function id. When this option is enabled on Arm platforms, the option ``ARM_RECOM_STATE_ID_ENC`` needs to be set to 1 as well.”h]”(já)”}”(hŒ``PSCI_EXTENDED_STATE_ID``”h]”hŒPSCI_EXTENDED_STATE_ID”…””}”(hhh!j (ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j(ubhX$: As per PSCI1.0 Specification, there are 2 formats possible for the PSCI power-state parameter: original and extended State-ID formats. This flag if set to 1, configures the generic PSCI layer to use the extended format. The default value of this flag is 0, which means by default the original power-state format is used by the PSCI implementation. This flag should be specified by the platform makefile and it governs the return value of PSCI_FEATURES API for CPU_SUSPEND smc function id. When this option is enabled on Arm platforms, the option ”…””}”(hX$: As per PSCI1.0 Specification, there are 2 formats possible for the PSCI power-state parameter: original and extended State-ID formats. This flag if set to 1, configures the generic PSCI layer to use the extended format. The default value of this flag is 0, which means by default the original power-state format is used by the PSCI implementation. This flag should be specified by the platform makefile and it governs the return value of PSCI_FEATURES API for CPU_SUSPEND smc function id. When this option is enabled on Arm platforms, the option ”h!j(ubjá)”}”(hŒ``ARM_RECOM_STATE_ID_ENC``”h]”hŒARM_RECOM_STATE_ID_ENC”…””}”(hhh!j(ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j(ubhŒ needs to be set to 1 as well.”…””}”(hŒ needs to be set to 1 as well.”h!j(ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCM3h!j(ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hX.``RAS_EXTENSION``: When set to ``1``, enable Armv8.2 RAS features. RAS features are an optional extension for pre-Armv8.2 CPUs, but are mandatory for Armv8.2 or later CPUs. When ``RAS_EXTENSION`` is set to ``1``, ``HANDLE_EA_EL3_FIRST`` must also be set to ``1``. This option is disabled by default. ”h]”(j£)”}”(hŒ¬``RAS_EXTENSION``: When set to ``1``, enable Armv8.2 RAS features. RAS features are an optional extension for pre-Armv8.2 CPUs, but are mandatory for Armv8.2 or later CPUs.”h]”(já)”}”(hŒ``RAS_EXTENSION``”h]”hŒ RAS_EXTENSION”…””}”(hhh!jC(ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j?(ubhŒ: When set to ”…””}”(hŒ: When set to ”h!j?(ubjá)”}”(hŒ``1``”h]”hŒ1”…””}”(hhh!jV(ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j?(ubhŒˆ, enable Armv8.2 RAS features. RAS features are an optional extension for pre-Armv8.2 CPUs, but are mandatory for Armv8.2 or later CPUs.”…””}”(hŒˆ, enable Armv8.2 RAS features. RAS features are an optional extension for pre-Armv8.2 CPUs, but are mandatory for Armv8.2 or later CPUs.”h!j?(ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCM=h!j;(ubj£)”}”(hŒZWhen ``RAS_EXTENSION`` is set to ``1``, ``HANDLE_EA_EL3_FIRST`` must also be set to ``1``.”h]”(hŒWhen ”…””}”(hŒWhen ”h!jo(ubjá)”}”(hŒ``RAS_EXTENSION``”h]”hŒ RAS_EXTENSION”…””}”(hhh!jx(ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jo(ubhŒ is set to ”…””}”(hŒ is set to ”h!jo(ubjá)”}”(hŒ``1``”h]”hŒ1”…””}”(hhh!j‹(ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jo(ubhŒ, ”…””}”(hŒ, ”h!jo(ubjá)”}”(hŒ``HANDLE_EA_EL3_FIRST``”h]”hŒHANDLE_EA_EL3_FIRST”…””}”(hhh!jž(ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jo(ubhŒ must also be set to ”…””}”(hŒ must also be set to ”h!jo(ubjá)”}”(hŒ``1``”h]”hŒ1”…””}”(hhh!j±(ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jo(ubhŒ.”…””}”(hjTh!jo(ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMAh!j;(ubj£)”}”(hŒ#This option is disabled by default.”h]”hŒ#This option is disabled by default.”…””}”(hjË(h!jÉ(ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMDh!j;(ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hŒÔ``RESET_TO_BL31``: Enable BL31 entrypoint as the CPU reset vector instead of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1 entrypoint) or 1 (CPU reset to BL31 entrypoint). The default value is 0. ”h]”j£)”}”(hŒÓ``RESET_TO_BL31``: Enable BL31 entrypoint as the CPU reset vector instead of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1 entrypoint) or 1 (CPU reset to BL31 entrypoint). The default value is 0.”h]”(já)”}”(hŒ``RESET_TO_BL31``”h]”hŒ RESET_TO_BL31”…””}”(hhh!jå(ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!já(ubhŒÂ: Enable BL31 entrypoint as the CPU reset vector instead of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1 entrypoint) or 1 (CPU reset to BL31 entrypoint). The default value is 0.”…””}”(hŒÂ: Enable BL31 entrypoint as the CPU reset vector instead of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1 entrypoint) or 1 (CPU reset to BL31 entrypoint). The default value is 0.”h!já(ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMFh!jÝ(ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hX'``RESET_TO_SP_MIN``: SP_MIN is the minimal AArch32 Secure Payload provided in TF-A. This flag configures SP_MIN entrypoint as the CPU reset vector instead of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1 entrypoint) or 1 (CPU reset to SP_MIN entrypoint). The default value is 0. ”h]”j£)”}”(hX&``RESET_TO_SP_MIN``: SP_MIN is the minimal AArch32 Secure Payload provided in TF-A. This flag configures SP_MIN entrypoint as the CPU reset vector instead of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1 entrypoint) or 1 (CPU reset to SP_MIN entrypoint). The default value is 0.”h]”(já)”}”(hŒ``RESET_TO_SP_MIN``”h]”hŒRESET_TO_SP_MIN”…””}”(hhh!j)ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j)ubhX: SP_MIN is the minimal AArch32 Secure Payload provided in TF-A. This flag configures SP_MIN entrypoint as the CPU reset vector instead of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1 entrypoint) or 1 (CPU reset to SP_MIN entrypoint). The default value is 0.”…””}”(hX: SP_MIN is the minimal AArch32 Secure Payload provided in TF-A. This flag configures SP_MIN entrypoint as the CPU reset vector instead of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1 entrypoint) or 1 (CPU reset to SP_MIN entrypoint). The default value is 0.”h!j)ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMKh!j)ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hŒê``ROT_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the file that contains the ROT private key in PEM format and enforces public key hash generation. If ``SAVE_KEYS=1``, this file name will be used to save the key. ”h]”j£)”}”(hŒé``ROT_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the file that contains the ROT private key in PEM format and enforces public key hash generation. If ``SAVE_KEYS=1``, this file name will be used to save the key.”h]”(já)”}”(hŒ``ROT_KEY``”h]”hŒROT_KEY”…””}”(hhh!j3)ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j/)ubhŒ: This option is used when ”…””}”(hŒ: This option is used when ”h!j/)ubjá)”}”(hŒ``GENERATE_COT=1``”h]”hŒGENERATE_COT=1”…””}”(hhh!jF)ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j/)ubhŒt. It specifies the file that contains the ROT private key in PEM format and enforces public key hash generation. If ”…””}”(hŒt. It specifies the file that contains the ROT private key in PEM format and enforces public key hash generation. If ”h!j/)ubjá)”}”(hŒ``SAVE_KEYS=1``”h]”hŒSAVE_KEYS=1”…””}”(hhh!jY)ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j/)ubhŒ., this file name will be used to save the key.”…””}”(hŒ., this file name will be used to save the key.”h!j/)ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMPh!j+)ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hŒÚ``SAVE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the certificate generation tool to save the keys used to establish the Chain of Trust. Allowed options are '0' or '1'. Default is '0' (do not save). ”h]”j£)”}”(hŒÙ``SAVE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the certificate generation tool to save the keys used to establish the Chain of Trust. Allowed options are '0' or '1'. Default is '0' (do not save).”h]”(já)”}”(hŒ ``SAVE_KEYS``”h]”hŒ SAVE_KEYS”…””}”(hhh!j€)ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j|)ubhŒ: This option is used when ”…””}”(hŒ: This option is used when ”h!j|)ubjá)”}”(hŒ``GENERATE_COT=1``”h]”hŒGENERATE_COT=1”…””}”(hhh!j“)ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j|)ubhŒ«. It tells the certificate generation tool to save the keys used to establish the Chain of Trust. Allowed options are â€˜0â€™ or â€˜1â€™. Default is â€˜0â€™ (do not save).”…””}”(hŒŸ. It tells the certificate generation tool to save the keys used to establish the Chain of Trust. Allowed options are '0' or '1'. Default is '0' (do not save).”h!j|)ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMUh!jx)ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hŒª``SCP_BL2``: Path to SCP_BL2 image in the host file system. This image is optional. If a SCP_BL2 image is present then this option must be passed for the ``fip`` target. ”h]”j£)”}”(hŒ©``SCP_BL2``: Path to SCP_BL2 image in the host file system. This image is optional. If a SCP_BL2 image is present then this option must be passed for the ``fip`` target.”h]”(já)”}”(hŒ``SCP_BL2``”h]”hŒSCP_BL2”…””}”(hhh!jº)ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j¶)ubhŒ: Path to SCP_BL2 image in the host file system. This image is optional. If a SCP_BL2 image is present then this option must be passed for the ”…””}”(hŒ: Path to SCP_BL2 image in the host file system. This image is optional. If a SCP_BL2 image is present then this option must be passed for the ”h!j¶)ubjá)”}”(hŒ``fip``”h]”hŒfip”…””}”(hhh!jÍ)ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j¶)ubhŒ target.”…””}”(hŒ target.”h!j¶)ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMYh!j²)ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hŒÊ``SCP_BL2_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the file that contains the SCP_BL2 private key in PEM format. If ``SAVE_KEYS=1``, this file name will be used to save the key. ”h]”j£)”}”(hŒÉ``SCP_BL2_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the file that contains the SCP_BL2 private key in PEM format. If ``SAVE_KEYS=1``, this file name will be used to save the key.”h]”(já)”}”(hŒ``SCP_BL2_KEY``”h]”hŒSCP_BL2_KEY”…””}”(hhh!jô)ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jð)ubhŒ: This option is used when ”…””}”(hŒ: This option is used when ”h!jð)ubjá)”}”(hŒ``GENERATE_COT=1``”h]”hŒGENERATE_COT=1”…””}”(hhh!j*ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jð)ubhŒP. It specifies the file that contains the SCP_BL2 private key in PEM format. If ”…””}”(hŒP. It specifies the file that contains the SCP_BL2 private key in PEM format. If ”h!jð)ubjá)”}”(hŒ``SAVE_KEYS=1``”h]”hŒSAVE_KEYS=1”…””}”(hhh!j*ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jð)ubhŒ., this file name will be used to save the key.”…””}”(hŒ., this file name will be used to save the key.”h!jð)ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCM]h!jì)ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hŒÉ``SCP_BL2U``: Path to SCP_BL2U image in the host file system. This image is optional. It is only needed if the platform makefile specifies that it is required in order to build the ``fwu_fip`` target. ”h]”j£)”}”(hŒÈ``SCP_BL2U``: Path to SCP_BL2U image in the host file system. This image is optional. It is only needed if the platform makefile specifies that it is required in order to build the ``fwu_fip`` target.”h]”(já)”}”(hŒ``SCP_BL2U``”h]”hŒSCP_BL2U”…””}”(hhh!jA*ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j=*ubhŒ©: Path to SCP_BL2U image in the host file system. This image is optional. It is only needed if the platform makefile specifies that it is required in order to build the ”…””}”(hŒ©: Path to SCP_BL2U image in the host file system. This image is optional. It is only needed if the platform makefile specifies that it is required in order to build the ”h!j=*ubjá)”}”(hŒ``fwu_fip``”h]”hŒfwu_fip”…””}”(hhh!jT*ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j=*ubhŒ target.”…””}”(hŒ target.”h!j=*ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMah!j9*ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hŒå``SDEI_SUPPORT``: Setting this to ``1`` enables support for Software Delegated Exception Interface to BL31 image. This defaults to ``0``. When set to ``1``, the build option ``EL3_EXCEPTION_HANDLING`` must also be set to ``1``. ”h]”(j£)”}”(hŒ‰``SDEI_SUPPORT``: Setting this to ``1`` enables support for Software Delegated Exception Interface to BL31 image. This defaults to ``0``.”h]”(já)”}”(hŒ``SDEI_SUPPORT``”h]”hŒSDEI_SUPPORT”…””}”(hhh!j{*ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jw*ubhŒ: Setting this to ”…””}”(hŒ: Setting this to ”h!jw*ubjá)”}”(hŒ``1``”h]”hŒ1”…””}”(hhh!jŽ*ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jw*ubhŒ\ enables support for Software Delegated Exception Interface to BL31 image. This defaults to ”…””}”(hŒ\ enables support for Software Delegated Exception Interface to BL31 image. This defaults to ”h!jw*ubjá)”}”(hŒ``0``”h]”hŒ0”…””}”(hhh!j¡*ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jw*ubhŒ.”…””}”(hjTh!jw*ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMeh!js*ubj£)”}”(hŒYWhen set to ``1``, the build option ``EL3_EXCEPTION_HANDLING`` must also be set to ``1``.”h]”(hŒWhen set to ”…””}”(hŒWhen set to ”h!j¹*ubjá)”}”(hŒ``1``”h]”hŒ1”…””}”(hhh!jÂ*ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j¹*ubhŒ, the build option ”…””}”(hŒ, the build option ”h!j¹*ubjá)”}”(hŒ``EL3_EXCEPTION_HANDLING``”h]”hŒEL3_EXCEPTION_HANDLING”…””}”(hhh!jÕ*ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j¹*ubhŒ must also be set to ”…””}”(hŒ must also be set to ”h!j¹*ubjá)”}”(hŒ``1``”h]”hŒ1”…””}”(hhh!jè*ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j¹*ubhŒ.”…””}”(hjTh!j¹*ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMhh!js*ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hXB``SEPARATE_CODE_AND_RODATA``: Whether code and read-only data should be isolated on separate memory pages. This is a trade-off between security and memory usage. See "Isolating code and read-only data on separate memory pages" section in :ref:`Firmware Design`. This flag is disabled by default and affects all BL images. ”•h]”j£)”}”(hXA``SEPARATE_CODE_AND_RODATA``: Whether code and read-only data should be isolated on separate memory pages. This is a trade-off between security and memory usage. See "Isolating code and read-only data on separate memory pages" section in :ref:`Firmware Design`. This flag is disabled by default and affects all BL images.”h]”(já)”}”(hŒ``SEPARATE_CODE_AND_RODATA``”h]”hŒSEPARATE_CODE_AND_RODATA”…””}”(hhh!j+ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j +ubhŒÖ: Whether code and read-only data should be isolated on separate memory pages. This is a trade-off between security and memory usage. See â€œIsolating code and read-only data on separate memory pagesâ€ section in ”…””}”(hŒÒ: Whether code and read-only data should be isolated on separate memory pages. This is a trade-off between security and memory usage. See "Isolating code and read-only data on separate memory pages" section in ”h!j +ubh)”}”(hŒ:ref:`Firmware Design`”h]”h)”}”(hj#+h]”hŒFirmware Design”…””}”(hhh!j%+ubah"}”(h$]”h&]”(h(Œstd”Œstd-ref”eh+]”h-]”h/]”uh1hh!j!+ubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”j/+Œreftype”Œref”Œrefexplicit”‰Œrefwarn”ˆh?Œfirmware design”uh1hhAj¡hCMkh!j +ubhŒ=. This flag is disabled by default and affects all BL images.”…””}”(hŒ=. This flag is disabled by default and affects all BL images.”h!j +ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMkh!j+ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hX»``SEPARATE_NOBITS_REGION``: Setting this option to ``1`` allows the NOBITS sections of BL31 (.bss, stacks, page tables, and coherent memory) to be allocated in RAM discontiguous from the loaded firmware image. When set, the platform is expected to provide definitions for ``BL31_NOBITS_BASE`` and ``BL31_NOBITS_LIMIT``. When the option is ``0`` (the default), NOBITS sections are placed in RAM immediately following the loaded firmware image. ”h]”j£)”}”(hXº``SEPARATE_NOBITS_REGION``: Setting this option to ``1`` allows the NOBITS sections of BL31 (.bss, stacks, page tables, and coherent memory) to be allocated in RAM discontiguous from the loaded firmware image. When set, the platform is expected to provide definitions for ``BL31_NOBITS_BASE`` and ``BL31_NOBITS_LIMIT``. When the option is ``0`` (the default), NOBITS sections are placed in RAM immediately following the loaded firmware image.”h]”(já)”}”(hŒ``SEPARATE_NOBITS_REGION``”h]”hŒSEPARATE_NOBITS_REGION”…””}”(hhh!jZ+ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jV+ubhŒ: Setting this option to ”…””}”(hŒ: Setting this option to ”h!jV+ubjá)”}”(hŒ``1``”h]”hŒ1”…””}”(hhh!jm+ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jV+ubhŒØ allows the NOBITS sections of BL31 (.bss, stacks, page tables, and coherent memory) to be allocated in RAM discontiguous from the loaded firmware image. When set, the platform is expected to provide definitions for ”…””}”(hŒØ allows the NOBITS sections of BL31 (.bss, stacks, page tables, and coherent memory) to be allocated in RAM discontiguous from the loaded firmware image. When set, the platform is expected to provide definitions for ”h!jV+ubjá)”}”(hŒ``BL31_NOBITS_BASE``”h]”hŒBL31_NOBITS_BASE”…””}”(hhh!j€+ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jV+ubhŒ and ”…””}”(hŒ and ”h!jV+ubjá)”}”(hŒ``BL31_NOBITS_LIMIT``”h]”hŒBL31_NOBITS_LIMIT”…””}”(hhh!j“+ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jV+ubhŒ. When the option is ”…””}”(hŒ. When the option is ”h!jV+ubjá)”}”(hŒ``0``”h]”hŒ0”…””}”(hhh!j¦+ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jV+ubhŒb (the default), NOBITS sections are placed in RAM immediately following the loaded firmware image.”…””}”(hŒb (the default), NOBITS sections are placed in RAM immediately following the loaded firmware image.”h!jV+ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMqh!jR+ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hX``SMC_PCI_SUPPORT``: This option allows platforms to handle PCI configuration access requests via a standard SMCCC defined in `DEN0115`_. When combined with UEFI+ACPI this can provide a certain amount of OS forward compatibility with newer platforms that aren't ECAM compliant. ”h]”j£)”}”(hX``SMC_PCI_SUPPORT``: This option allows platforms to handle PCI configuration access requests via a standard SMCCC defined in `DEN0115`_. When combined with UEFI+ACPI this can provide a certain amount of OS forward compatibility with newer platforms that aren't ECAM compliant.”h]”(já)”}”(hŒ``SMC_PCI_SUPPORT``”h]”hŒSMC_PCI_SUPPORT”…””}”(hhh!jÍ+ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jÉ+ubhŒk: This option allows platforms to handle PCI configuration access requests via a standard SMCCC defined in ”…””}”(hŒk: This option allows platforms to handle PCI configuration access requests via a standard SMCCC defined in ”h!jÉ+ubh Œ reference”“”)”}”(hŒ `DEN0115`_”h]”hŒDEN0115”…””}”(hŒDEN0115”h!jâ+ubah"}”(h$]”h&]”h+]”h-]”h/]”Œname”jê+Œrefuri”Œ-https://developer.arm.com/docs/den0115/latest”uh1jà+h!jÉ+Œresolved”KubhŒ. When combined with UEFI+ACPI this can provide a certain amount of OS forward compatibility with newer platforms that arenâ€™t ECAM compliant.”…””}”(hŒ. When combined with UEFI+ACPI this can provide a certain amount of OS forward compatibility with newer platforms that aren't ECAM compliant.”h!jÉ+ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMxh!jÅ+ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hXæ``SPD``: Choose a Secure Payload Dispatcher component to be built into TF-A. This build option is only valid if ``ARCH=aarch64``. The value should be the path to the directory containing the SPD source, relative to ``services/spd/``; the directory is expected to contain a makefile called ``.mk``. The SPM Dispatcher standard service is located in services/std_svc/spmd and enabled by ``SPD=spmd``. The SPM Dispatcher cannot be enabled when the ``SPM_MM`` option is enabled. ”h]”j£)”}”(hXå``SPD``: Choose a Secure Payload Dispatcher component to be built into TF-A. This build option is only valid if ``ARCH=aarch64``. The value should be the path to the directory containing the SPD source, relative to ``services/spd/``; the directory is expected to contain a makefile called ``.mk``. The SPM Dispatcher standard service is located in services/std_svc/spmd and enabled by ``SPD=spmd``. The SPM Dispatcher cannot be enabled when the ``SPM_MM`` option is enabled.”h]”(já)”}”(hŒ``SPD``”h]”hŒSPD”…””}”(hhh!j,ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j ,ubhŒi: Choose a Secure Payload Dispatcher component to be built into TF-A. This build option is only valid if ”…””}”(hŒi: Choose a Secure Payload Dispatcher component to be built into TF-A. This build option is only valid if ”h!j ,ubjá)”}”(hŒ``ARCH=aarch64``”h]”hŒARCH=aarch64”…””}”(hhh!j!,ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j ,ubhŒW. The value should be the path to the directory containing the SPD source, relative to ”…””}”(hŒW. The value should be the path to the directory containing the SPD source, relative to ”h!j ,ubjá)”}”(hŒ``services/spd/``”h]”hŒ services/spd/”…””}”(hhh!j4,ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j ,ubhŒ9; the directory is expected to contain a makefile called ”…””}”(hŒ9; the directory is expected to contain a makefile called ”h!j ,ubjá)”}”(hŒ``.mk``”h]”hŒ.mk”…””}”(hhh!jG,ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j ,ubhŒY. The SPM Dispatcher standard service is located in services/std_svc/spmd and enabled by ”…””}”(hŒY. The SPM Dispatcher standard service is located in services/std_svc/spmd and enabled by ”h!j ,ubjá)”}”(hŒ``SPD=spmd``”h]”hŒSPD=spmd”…””}”(hhh!jZ,ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j ,ubhŒ0. The SPM Dispatcher cannot be enabled when the ”…””}”(hŒ0. The SPM Dispatcher cannot be enabled when the ”h!j ,ubjá)”}”(hŒ ``SPM_MM``”h]”hŒSPM_MM”…””}”(hhh!jm,ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j ,ubhŒ option is enabled.”…””}”(hŒ option is enabled.”h!j ,ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCM}h!j,ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hXn``SPIN_ON_BL1_EXIT``: This option introduces an infinite loop in BL1. It can take either 0 (no loop) or 1 (add a loop). 0 is the default. This loop stops execution in BL1 just before handing over to BL31. At this point, all firmware images have been loaded in memory, and the MMU and caches are turned off. Refer to the "Debugging options" section for more details. ”h]”j£)”}”(hXm``SPIN_ON_BL1_EXIT``: This option introduces an infinite loop in BL1. It can take either 0 (no loop) or 1 (add a loop). 0 is the default. This loop stops execution in BL1 just before handing over to BL31. At this point, all firmware images have been loaded in memory, and the MMU and caches are turned off. Refer to the "Debugging options" section for more details.”h]”(já)”}”(hŒ``SPIN_ON_BL1_EXIT``”h]”hŒSPIN_ON_BL1_EXIT”…””}”(hhh!j”,ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j,ubhX]: This option introduces an infinite loop in BL1. It can take either 0 (no loop) or 1 (add a loop). 0 is the default. This loop stops execution in BL1 just before handing over to BL31. At this point, all firmware images have been loaded in memory, and the MMU and caches are turned off. Refer to the â€œDebugging optionsâ€ section for more details.”…””}”(hXY: This option introduces an infinite loop in BL1. It can take either 0 (no loop) or 1 (add a loop). 0 is the default. This loop stops execution in BL1 just before handing over to BL31. At this point, all firmware images have been loaded in memory, and the MMU and caches are turned off. Refer to the "Debugging options" section for more details.”h!j,ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCM…h!jŒ,ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hXà``SPMD_SPM_AT_SEL2`` : this boolean option is used jointly with the SPM Dispatcher option (``SPD=spmd``). When enabled (1) it indicates the SPMC component runs at the S-EL2 execution state provided by the Armv8.4-SecEL2 extension. This is the default when enabling the SPM Dispatcher. When disabled (0) it indicates the SPMC component runs at the S-EL1 execution state. This latter configuration supports pre-Armv8.4 platforms (aka not implementing the Armv8.4-SecEL2 extension). ”h]”j£)”}”(hXß``SPMD_SPM_AT_SEL2`` : this boolean option is used jointly with the SPM Dispatcher option (``SPD=spmd``). When enabled (1) it indicates the SPMC component runs at the S-EL2 execution state provided by the Armv8.4-SecEL2 extension. This is the default when enabling the SPM Dispatcher. When disabled (0) it indicates the SPMC component runs at the S-EL1 execution state. This latter configuration supports pre-Armv8.4 platforms (aka not implementing the Armv8.4-SecEL2 extension).”h]”(já)”}”(hŒ``SPMD_SPM_AT_SEL2``”h]”hŒSPMD_SPM_AT_SEL2”…””}”(hhh!j»,ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j·,ubhŒG : this boolean option is used jointly with the SPM Dispatcher option (”…””}”(hŒG : this boolean option is used jointly with the SPM Dispatcher option (”h!j·,ubjá)”}”(hŒ``SPD=spmd``”h]”hŒSPD=spmd”…””}”(hhh!jÎ,ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j·,ubhXx). When enabled (1) it indicates the SPMC component runs at the S-EL2 execution state provided by the Armv8.4-SecEL2 extension. This is the default when enabling the SPM Dispatcher. When disabled (0) it indicates the SPMC component runs at the S-EL1 execution state. This latter configuration supports pre-Armv8.4 platforms (aka not implementing the Armv8.4-SecEL2 extension).”…””}”(hXx). When enabled (1) it indicates the SPMC component runs at the S-EL2 execution state provided by the Armv8.4-SecEL2 extension. This is the default when enabling the SPM Dispatcher. When disabled (0) it indicates the SPMC component runs at the S-EL1 execution state. This latter configuration supports pre-Armv8.4 platforms (aka not implementing the Armv8.4-SecEL2 extension).”h!j·,ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCM‹h!j³,ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hŒð``SPM_MM`` : Boolean option to enable the Management Mode (MM)-based Secure Partition Manager (SPM) implementation. The default value is ``0`` (disabled). This option cannot be enabled (``1``) when SPM Dispatcher is enabled (``SPD=spmd``). ”h]”j£)”}”(hŒï``SPM_MM`` : Boolean option to enable the Management Mode (MM)-based Secure Partition Manager (SPM) implementation. The default value is ``0`` (disabled). This option cannot be enabled (``1``) when SPM Dispatcher is enabled (``SPD=spmd``).”h]”(já)”}”(hŒ ``SPM_MM``”h]”hŒSPM_MM”…””}”(hhh!jõ,ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jñ,ubhŒ : Boolean option to enable the Management Mode (MM)-based Secure Partition Manager (SPM) implementation. The default value is ”…””}”(hŒ : Boolean option to enable the Management Mode (MM)-based Secure Partition Manager (SPM) implementation. The default value is ”h!jñ,ubjá)”}”(hŒ``0``”h]”hŒ0”…””}”(hhh!j-ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jñ,ubhŒ, (disabled). This option cannot be enabled (”…””}”(hŒ, (disabled). This option cannot be enabled (”h!jñ,ubjá)”}”(hŒ``1``”h]”hŒ1”…””}”(hhh!j-ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jñ,ubhŒ") when SPM Dispatcher is enabled (”…””}”(hŒ") when SPM Dispatcher is enabled (”h!jñ,ubjá)”}”(hŒ``SPD=spmd``”h]”hŒSPD=spmd”…””}”(hhh!j.-ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jñ,ubhŒ).”…””}”(hŒ).”h!jñ,ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCM“h!jí,ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hX``SP_LAYOUT_FILE``: Platform provided path to JSON file containing the description of secure partitions. The build system will parse this file and package all secure partition blobs into the FIP. This file is not necessarily part of TF-A tree. Only available when ``SPD=spmd``. ”h]”j£)”}”(hX``SP_LAYOUT_FILE``: Platform provided path to JSON file containing the description of secure partitions. The build system will parse this file and package all secure partition blobs into the FIP. This file is not necessarily part of TF-A tree. Only available when ``SPD=spmd``.”h]”(já)”}”(hŒ``SP_LAYOUT_FILE``”h]”hŒSP_LAYOUT_FILE”…””}”(hhh!jU-ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jQ-ubhŒö: Platform provided path to JSON file containing the description of secure partitions. The build system will parse this file and package all secure partition blobs into the FIP. This file is not necessarily part of TF-A tree. Only available when ”…””}”(hŒö: Platform provided path to JSON file containing the description of secure partitions. The build system will parse this file and package all secure partition blobs into the FIP. This file is not necessarily part of TF-A tree. Only available when ”h!jQ-ubjá)”}”(hŒ``SPD=spmd``”h]”hŒSPD=spmd”…””}”(hhh!jh-ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jQ-ubhŒ.”…””}”(hjTh!jQ-ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCM˜h!jM-ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hX¯``SP_MIN_WITH_SECURE_FIQ``: Boolean flag to indicate the SP_MIN handles secure interrupts (caught through the FIQ line). Platforms can enable this directive if they need to handle such interruption. When enabled, the FIQ are handled in monitor mode and non secure world is not allowed to mask these events. Platforms that enable FIQ handling in SP_MIN shall implement the api ``sp_min_plat_fiq_handler()``. The default value is 0. ”h]”j£)”}”(hX®``SP_MIN_WITH_SECURE_FIQ``: Boolean flag to indicate the SP_MIN handles secure interrupts (caught through the FIQ line). Platforms can enable this directive if they need to handle such interruption. When enabled, the FIQ are handled in monitor mode and non secure world is not allowed to mask these events. Platforms that enable FIQ handling in SP_MIN shall implement the api ``sp_min_plat_fiq_handler()``. The default value is 0.”h]”(já)”}”(hŒ``SP_MIN_WITH_SECURE_FIQ``”h]”hŒSP_MIN_WITH_SECURE_FIQ”…””}”(hhh!jŽ-ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jŠ-ubhX^: Boolean flag to indicate the SP_MIN handles secure interrupts (caught through the FIQ line). Platforms can enable this directive if they need to handle such interruption. When enabled, the FIQ are handled in monitor mode and non secure world is not allowed to mask these events. Platforms that enable FIQ handling in SP_MIN shall implement the api ”…””}”(hX^: Boolean flag to indicate the SP_MIN handles secure interrupts (caught through the FIQ line). Platforms can enable this directive if they need to handle such interruption. When enabled, the FIQ are handled in monitor mode and non secure world is not allowed to mask these events. Platforms that enable FIQ handling in SP_MIN shall implement the api ”h!jŠ-ubjá)”}”(hŒ``sp_min_plat_fiq_handler()``”h]”hŒsp_min_plat_fiq_handler()”…””}”(hhh!j¡-ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jŠ-ubhŒ. The default value is 0.”…””}”(hŒ. The default value is 0.”h!jŠ-ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMh!j†-ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hX*``TRUSTED_BOARD_BOOT``: Boolean flag to include support for the Trusted Board Boot feature. When set to '1', BL1 and BL2 images include support to load and verify the certificates and images in a FIP, and BL1 includes support for the Firmware Update. The default value is '0'. Generation and inclusion of certificates in the FIP and FWU_FIP depends upon the value of the ``GENERATE_COT`` option. .. warning:: This option depends on ``CREATE_KEYS`` to be enabled. If the keys already exist in disk, they will be overwritten without further notice. ”h]”(j£)”}”(hX‹``TRUSTED_BOARD_BOOT``: Boolean flag to include support for the Trusted Board Boot feature. When set to '1', BL1 and BL2 images include support to load and verify the certificates and images in a FIP, and BL1 includes support for the Firmware Update. The default value is '0'. Generation and inclusion of certificates in the FIP and FWU_FIP depends upon the value of the ``GENERATE_COT`` option.”h]”(já)”}”(hŒ``TRUSTED_BOARD_BOOT``”h]”hŒTRUSTED_BOARD_BOOT”…””}”(hhh!jÈ-ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jÄ-ubhXe: Boolean flag to include support for the Trusted Board Boot feature. When set to â€˜1â€™, BL1 and BL2 images include support to load and verify the certificates and images in a FIP, and BL1 includes support for the Firmware Update. The default value is â€˜0â€™. Generation and inclusion of certificates in the FIP and FWU_FIP depends upon the value of the ”…””}”(hX]: Boolean flag to include support for the Trusted Board Boot feature. When set to '1', BL1 and BL2 images include support to load and verify the certificates and images in a FIP, and BL1 includes support for the Firmware Update. The default value is '0'. Generation and inclusion of certificates in the FIP and FWU_FIP depends upon the value of the ”h!jÄ-ubjá)”}”(hŒ``GENERATE_COT``”h]”hŒGENERATE_COT”…””}”(hhh!jÛ-ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jÄ-ubhŒ option.”…””}”(hŒ option.”h!jÄ-ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCM¤h!jÀ-ubh Œwarning”“”)”}”(hŒ‰This option depends on ``CREATE_KEYS`` to be enabled. If the keys already exist in disk, they will be overwritten without further notice.”h]”j£)”}”(hŒ‰This option depends on ``CREATE_KEYS`` to be enabled. If the keys already exist in disk, they will be overwritten without further notice.”h]”(hŒThis option depends on ”…””}”(hŒThis option depends on ”h!jú-ubjá)”}”(hŒ``CREATE_KEYS``”h]”hŒCREATE_KEYS”…””}”(hhh!j.ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jú-ubhŒc to be enabled. If the keys already exist in disk, they will be overwritten without further notice.”…””}”(hŒc to be enabled. If the keys already exist in disk, they will be overwritten without further notice.”h!jú-ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCM¬h!jö-ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jô-h!jÀ-ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhANhCNubj×)”}”(hŒÖ``TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the file that contains the Trusted World private key in PEM format. If ``SAVE_KEYS=1``, this file name will be used to save the key. ”h]”j£)”}”(hŒÕ``TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the file that contains the Trusted World private key in PEM format. If ``SAVE_KEYS=1``, this file name will be used to save the key.”h]”(já)”}”(hŒ``TRUSTED_WORLD_KEY``”h]”hŒTRUSTED_WORLD_KEY”…””}”(hhh!j0.ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j,.ubhŒ: This option is used when ”…””}”(hŒ: This option is used when ”h!j,.ubjá)”}”(hŒ``GENERATE_COT=1``”h]”hŒGENERATE_COT=1”…””}”(hhh!jC.ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j,.ubhŒV. It specifies the file that contains the Trusted World private key in PEM format. If ”…””}”(hŒV. It specifies the file that contains the Trusted World private key in PEM format. If ”h!j,.ubjá)”}”(hŒ``SAVE_KEYS=1``”h]”hŒSAVE_KEYS=1”…””}”(hhh!jV.ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j,.ubhŒ., this file name will be used to save the key.”…””}”(hŒ., this file name will be used to save the key.”h!j,.ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCM¯h!j(.ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hX&``TSP_INIT_ASYNC``: Choose BL32 initialization method as asynchronous or synchronous, (see "Initializing a BL32 Image" section in :ref:`Firmware Design`). It can take the value 0 (BL32 is initialized using synchronous method) or 1 (BL32 is initialized using asynchronous method). Default is 0. ”h]”j£)”}”(hX%``TSP_INIT_ASYNC``: Choose BL32 initialization method as asynchronous or synchronous, (see "Initializing a BL32 Image" section in :ref:`Firmware Design`). It can take the value 0 (BL32 is initialized using synchronous method) or 1 (BL32 is initialized using asynchronous method). Default is 0.”h]”(já)”}”(hŒ``TSP_INIT_ASYNC``”h]”hŒTSP_INIT_ASYNC”…””}”(hhh!j}.ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jy.ubhŒt: Choose BL32 initialization method as asynchronous or synchronous, (see â€œInitializing a BL32 Imageâ€ section in ”…””}”(hŒp: Choose BL32 initialization method as asynchronous or synchronous, (see "Initializing a BL32 Image" section in ”h!jy.ubh)”}”(hŒ:ref:`Firmware Design`”h]”h)”}”(hj’.h]”hŒFirmware Design”…””}”(hhh!j”.ubah"}”(h$]”h&]”(h(Œstd”Œstd-ref”eh+]”h-]”h/]”uh1hh!j.ubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”jž.Œreftype”Œref”Œrefexplicit”‰Œrefwarn”ˆh?Œfirmware design”uh1hhAj¡hCM³h!jy.ubhŒ). It can take the value 0 (BL32 is initialized using synchronous method) or 1 (BL32 is initialized using asynchronous method). Default is 0.”…””}”(hŒ). It can take the value 0 (BL32 is initialized using synchronous method) or 1 (BL32 is initialized using asynchronous method). Default is 0.”h!jy.ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCM³h!ju.ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hX.``TSP_NS_INTR_ASYNC_PREEMPT``: A non zero value enables the interrupt routing model which routes non-secure interrupts asynchronously from TSP to EL3 causing immediate preemption of TSP. The EL3 is responsible for saving and restoring the TSP context in this routing model. The default routing model (when the value is 0) is to route non-secure interrupts to TSP allowing it to save its context and hand over synchronously to EL3 via an SMC. .. note:: When ``EL3_EXCEPTION_HANDLING`` is ``1``, ``TSP_NS_INTR_ASYNC_PREEMPT`` must also be set to ``1``. ”h]”(j£)”}”(hX¹``TSP_NS_INTR_ASYNC_PREEMPT``: A non zero value enables the interrupt routing model which routes non-secure interrupts asynchronously from TSP to EL3 causing immediate preemption of TSP. The EL3 is responsible for saving and restoring the TSP context in this routing model. The default routing model (when the value is 0) is to route non-secure interrupts to TSP allowing it to save its context and hand over synchronously to EL3 via an SMC.”h]”(já)”}”(hŒ``TSP_NS_INTR_ASYNC_PREEMPT``”h]”hŒTSP_NS_INTR_ASYNC_PREEMPT”…””}”(hhh!jÉ.ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jÅ.ubhXœ: A non zero value enables the interrupt routing model which routes non-secure interrupts asynchronously from TSP to EL3 causing immediate preemption of TSP. The EL3 is responsible for saving and restoring the TSP context in this routing model. The default routing model (when the value is 0) is to route non-secure interrupts to TSP allowing it to save its context and hand over synchronously to EL3 via an SMC.”…””}”(hXœ: A non zero value enables the interrupt routing model which routes non-secure interrupts asynchronously from TSP to EL3 causing immediate preemption of TSP. The EL3 is responsible for saving and restoring the TSP context in this routing model. The default routing model (when the value is 0) is to route non-secure interrupts to TSP allowing it to save its context and hand over synchronously to EL3 via an SMC.”h!jÅ.ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCM¹h!jÁ.ubh Œnote”“”)”}”(hŒbWhen ``EL3_EXCEPTION_HANDLING`` is ``1``, ``TSP_NS_INTR_ASYNC_PREEMPT`` must also be set to ``1``.”h]”j£)”}”(hŒbWhen ``EL3_EXCEPTION_HANDLING`` is ``1``, ``TSP_NS_INTR_ASYNC_PREEMPT`` must also be set to ``1``.”h]”(hŒWhen ”…””}”(hŒWhen ”h!jè.ubjá)”}”(hŒ``EL3_EXCEPTION_HANDLING``”h]”hŒEL3_EXCEPTION_HANDLING”…””}”(hhh!jñ.ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jè.ubhŒ is ”…””}”(hŒ is ”h!jè.ubjá)”}”(hŒ``1``”h]”hŒ1”…””}”(hhh!j/ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jè.ubhŒ, ”…””}”(hŒ, ”h!jè.ubjá)”}”(hŒ``TSP_NS_INTR_ASYNC_PREEMPT``”h]”hŒTSP_NS_INTR_ASYNC_PREEMPT”…””}”(hhh!j/ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jè.ubhŒ must also be set to ”…””}”(hŒ must also be set to ”h!jè.ubjá)”}”(hŒ``1``”h]”hŒ1”…””}”(hhh!j*/ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jè.ubhŒ.”…””}”(hjTh!jè.ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMÂh!jä.ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jâ.h!jÁ.ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhANhCNubj×)”}”(hXa``USE_ARM_LINK``: This flag determines whether to enable support for ARM linker. When the ``LINKER`` build variable points to the armlink linker, this flag is enabled automatically. To enable support for armlink, platforms will have to provide a scatter file for the BL image. Currently, Tegra platforms use the armlink support to compile BL3-1 images. ”h]”j£)”}”(hX```USE_ARM_LINK``: This flag determines whether to enable support for ARM linker. When the ``LINKER`` build variable points to the armlink linker, this flag is enabled automatically. To enable support for armlink, platforms will have to provide a scatter file for the BL image. Currently, Tegra platforms use the armlink support to compile BL3-1 images.”h]”(já)”}”(hŒ``USE_ARM_LINK``”h]”hŒUSE_ARM_LINK”…””}”(hhh!jV/ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jR/ubhŒJ: This flag determines whether to enable support for ARM linker. When the ”…””}”(hŒJ: This flag determines whether to enable support for ARM linker. When the ”h!jR/ubjá)”}”(hŒ ``LINKER``”h]”hŒLINKER”…””}”(hhh!ji/ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jR/ubhŒü build variable points to the armlink linker, this flag is enabled automatically. To enable support for armlink, platforms will have to provide a scatter file for the BL image. Currently, Tegra platforms use the armlink support to compile BL3-1 images.”…””}”(hŒü build variable points to the armlink linker, this flag is enabled automatically. To enable support for armlink, platforms will have to provide a scatter file for the BL image. Currently, Tegra platforms use the armlink support to compile BL3-1 images.”h!jR/ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMÅh!jN/ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hX5``USE_COHERENT_MEM``: This flag determines whether to include the coherent memory region in the BL memory map or not (see "Use of Coherent memory in TF-A" section in :ref:`Firmware Design`). It can take the value 1 (Coherent memory region is included) or 0 (Coherent memory region is excluded). Default is 1. ”h]”j£)”}”(hX4``USE_COHERENT_MEM``: This flag determines whether to include the coherent memory region in the BL memory map or not (see "Use of Coherent memory in TF-A" section in :ref:`Firmware Design`). It can take the value 1 (Coherent memory region is included) or 0 (Coherent memory region is excluded). Default is 1.”h]”(já)”}”(hŒ``USE_COHERENT_MEM``”h]”hŒUSE_COHERENT_MEM”…””}”(hhh!j/ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jŒ/ubhŒ–: This flag determines whether to include the coherent memory region in the BL memory map or not (see â€œUse of Coherent memory in TF-Aâ€ section in ”…””}”(hŒ’: This flag determines whether to include the coherent memory region in the BL memory map or not (see "Use of Coherent memory in TF-A" section in ”h!jŒ/ubh)”}”(hŒ:ref:`Firmware Design`”h]”h)”}”(hj¥/h]”hŒFirmware Design”…””}”(hhh!j§/ubah"}”(h$]”h&]”(h(Œstd”Œstd-ref”eh+]”h-]”h/]”uh1hh!j£/ubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”j±/Œreftype”Œref”Œrefexplicit”‰Œrefwarn”ˆh?Œfirmware design”uh1hhAj¡hCMËh!jŒ/ubhŒx). It can take the value 1 (Coherent memory region is included) or 0 (Coherent memory region is excluded). Default is 1.”…””}”(hŒx). It can take the value 1 (Coherent memory region is included) or 0 (Coherent memory region is excluded). Default is 1.”h!jŒ/ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMËh!jˆ/ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hŒ§``USE_DEBUGFS``: When set to 1 this option activates an EXPERIMENTAL feature exposing a virtual filesystem interface through BL31 as a SiP SMC function. Default is 0. ”h]”j£)”}”(hŒ¦``USE_DEBUGFS``: When set to 1 this option activates an EXPERIMENTAL feature exposing a virtual filesystem interface through BL31 as a SiP SMC function. Default is 0.”h]”(já)”}”(hŒ``USE_DEBUGFS``”h]”hŒUSE_DEBUGFS”…””}”(hhh!jÜ/ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jØ/ubhŒ—: When set to 1 this option activates an EXPERIMENTAL feature exposing a virtual filesystem interface through BL31 as a SiP SMC function. Default is 0.”…””}”(hŒ—: When set to 1 this option activates an EXPERIMENTAL feature exposing a virtual filesystem interface through BL31 as a SiP SMC function. Default is 0.”h!jØ/ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMÑh!jÔ/ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hŒØ``ARM_IO_IN_DTB``: This flag determines whether to use IO based on the firmware configuration framework. This will move the io_policies into a configuration device tree, instead of static structure in the code base. ”h]”j£)”}”(hŒ×``ARM_IO_IN_DTB``: This flag determines whether to use IO based on the firmware configuration framework. This will move the io_policies into a configuration device tree, instead of static structure in the code base.”h]”(já)”}”(hŒ``ARM_IO_IN_DTB``”h]”hŒ ARM_IO_IN_DTB”…””}”(hhh!j0ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jÿ/ubhŒÆ: This flag determines whether to use IO based on the firmware configuration framework. This will move the io_policies into a configuration device tree, instead of static structure in the code base.”…””}”(hŒÆ: This flag determines whether to use IO based on the firmware configuration framework. This will move the io_policies into a configuration device tree, instead of static structure in the code base.”h!jÿ/ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMÕh!jû/ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hXy``COT_DESC_IN_DTB``: This flag determines whether to create COT descriptors at runtime using fconf. If this flag is enabled, COT descriptors are statically captured in tb_fw_config file in the form of device tree nodes and properties. Currently, COT descriptors used by BL2 are moved to the device tree and COT descriptors used by BL1 are retained in the code base statically. ”h]”j£)”}”(hXx``COT_DESC_IN_DTB``: This flag determines whether to create COT descriptors at runtime using fconf. If this flag is enabled, COT descriptors are statically captured in tb_fw_config file in the form of device tree nodes and properties. Currently, COT descriptors used by BL2 are moved to the device tree and COT descriptors used by BL1 are retained in the code base statically.”h]”(já)”}”(hŒ``COT_DESC_IN_DTB``”h]”hŒCOT_DESC_IN_DTB”…””}”(hhh!j*0ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j&0ubhXe: This flag determines whether to create COT descriptors at runtime using fconf. If this flag is enabled, COT descriptors are statically captured in tb_fw_config file in the form of device tree nodes and properties. Currently, COT descriptors used by BL2 are moved to the device tree and COT descriptors used by BL1 are retained in the code base statically.”…””}”(hXe: This flag determines whether to create COT descriptors at runtime using fconf. If this flag is enabled, COT descriptors are statically captured in tb_fw_config file in the form of device tree nodes and properties. Currently, COT descriptors used by BL2 are moved to the device tree and COT descriptors used by BL1 are retained in the code base statically.”h!j&0ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMÙh!j"0ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hXK``SDEI_IN_FCONF``: This flag determines whether to configure SDEI setup in runtime using firmware configuration framework. The platform specific SDEI shared and private events configuration is retrieved from device tree rather than static C structures at compile time. This is only supported if SDEI_SUPPORT build flag is enabled. ”h]”j£)”}”(hXJ``SDEI_IN_FCONF``: This flag determines whether to configure SDEI setup in runtime using firmware configuration framework. The platform specific SDEI shared and private events configuration is retrieved from device tree rather than static C structures at compile time. This is only supported if SDEI_SUPPORT build flag is enabled.”h]”(já)”}”(hŒ``SDEI_IN_FCONF``”h]”hŒ SDEI_IN_FCONF”…””}”(hhh!jQ0ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jM0ubhX9: This flag determines whether to configure SDEI setup in runtime using firmware configuration framework. The platform specific SDEI shared and private events configuration is retrieved from device tree rather than static C structures at compile time. This is only supported if SDEI_SUPPORT build flag is enabled.”…””}”(hX9: This flag determines whether to configure SDEI setup in runtime using firmware configuration framework. The platform specific SDEI shared and private events configuration is retrieved from device tree rather than static C structures at compile time. This is only supported if SDEI_SUPPORT build flag is enabled.”h!jM0ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMàh!jI0ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hX7``SEC_INT_DESC_IN_FCONF``: This flag determines whether to configure Group 0 and Group1 secure interrupts using the firmware configuration framework. The platform specific secure interrupt property descriptor is retrieved from device tree in runtime rather than depending on static C structure at compile time. ”h]”j£)”}”(hX6``SEC_INT_DESC_IN_FCONF``: This flag determines whether to configure Group 0 and Group1 secure interrupts using the firmware configuration framework. The platform specific secure interrupt property descriptor is retrieved from device tree in runtime rather than depending on static C structure at compile time.”h]”(já)”}”(hŒ``SEC_INT_DESC_IN_FCONF``”h]”hŒSEC_INT_DESC_IN_FCONF”…””}”(hhh!jx0ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jt0ubhX: This flag determines whether to configure Group 0 and Group1 secure interrupts using the firmware configuration framework. The platform specific secure interrupt property descriptor is retrieved from device tree in runtime rather than depending on static C structure at compile time.”…””}”(hX: This flag determines whether to configure Group 0 and Group1 secure interrupts using the firmware configuration framework. The platform specific secure interrupt property descriptor is retrieved from device tree in runtime rather than depending on static C structure at compile time.”h!jt0ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMæh!jp0ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hŒé``USE_ROMLIB``: This flag determines whether library at ROM will be used. This feature creates a library of functions to be placed in ROM and thus reduces SRAM usage. Refer to :ref:`Library at ROM` for further details. Default is 0. ”h]”j£)”}”(hŒè``USE_ROMLIB``: This flag determines whether library at ROM will be used. This feature creates a library of functions to be placed in ROM and thus reduces SRAM usage. Refer to :ref:`Library at ROM` for further details. Default is 0.”h]”(já)”}”(hŒ``USE_ROMLIB``”h]”hŒ USE_ROMLIB”…””}”(hhh!jŸ0ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j›0ubhŒ¢: This flag determines whether library at ROM will be used. This feature creates a library of functions to be placed in ROM and thus reduces SRAM usage. Refer to ”…””}”(hŒ¢: This flag determines whether library at ROM will be used. This feature creates a library of functions to be placed in ROM and thus reduces SRAM usage. Refer to ”h!j›0ubh)”}”(hŒ:ref:`Library at ROM`”h]”h)”}”(hj´0h]”hŒLibrary at ROM”…””}”(hhh!j¶0ubah"}”(h$]”h&]”(h(Œstd”Œstd-ref”eh+]”h-]”h/]”uh1hh!j²0ubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”jÀ0Œreftype”Œref”Œrefexplicit”‰Œrefwarn”ˆh?Œlibrary at rom”uh1hhAj¡hCMìh!j›0ubhŒ# for further details. Default is 0.”…””}”(hŒ# for further details. Default is 0.”h!j›0ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMìh!j—0ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hŒg``V``: Verbose build. If assigned anything other than 0, the build commands are printed. Default is 0. ”h]”j£)”}”(hŒf``V``: Verbose build. If assigned anything other than 0, the build commands are printed. Default is 0.”h]”(já)”}”(hŒ``V``”h]”hŒV”…””}”(hhh!jë0ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jç0ubhŒa: Verbose build. If assigned anything other than 0, the build commands are printed. Default is 0.”…””}”(hŒa: Verbose build. If assigned anything other than 0, the build commands are printed. Default is 0.”h!jç0ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMñh!jã0ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hŒ¥``VERSION_STRING``: String used in the log output for each TF-A image. Defaults to a string formed by concatenating the version number, build type and build string. ”h]”j£)”}”(hŒ¤``VERSION_STRING``: String used in the log output for each TF-A image. Defaults to a string formed by concatenating the version number, build type and build string.”h]”(já)”}”(hŒ``VERSION_STRING``”h]”hŒVERSION_STRING”…””}”(hhh!j1ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j1ubhŒ’: String used in the log output for each TF-A image. Defaults to a string formed by concatenating the version number, build type and build string.”…””}”(hŒ’: String used in the log output for each TF-A image. Defaults to a string formed by concatenating the version number, build type and build string.”h!j1ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMôh!j 1ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hŒÐ``W``: Warning level. Some compiler warning options of interest have been regrouped and put in the root Makefile. This flag can take the values 0 to 3, each level enabling more warning options. Default is 0. ”h]”j£)”}”(hŒÏ``W``: Warning level. Some compiler warning options of interest have been regrouped and put in the root Makefile. This flag can take the values 0 to 3, each level enabling more warning options. Default is 0.”h]”(já)”}”(hŒ``W``”h]”hŒW”…””}”(hhh!j91ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j51ubhŒÊ: Warning level. Some compiler warning options of interest have been regrouped and put in the root Makefile. This flag can take the values 0 to 3, each level enabling more warning options. Default is 0.”…””}”(hŒÊ: Warning level. Some compiler warning options of interest have been regrouped and put in the root Makefile. This flag can take the values 0 to 3, each level enabling more warning options. Default is 0.”h!j51ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMøh!j11ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hXj``WARMBOOT_ENABLE_DCACHE_EARLY`` : Boolean option to enable D-cache early on the CPU after warm boot. This is applicable for platforms which do not require interconnect programming to enable cache coherency (eg: single cluster platforms). If this option is enabled, then warm boot path enables D-caches immediately after enabling MMU. This option defaults to 0. ”h]”j£)”}”(hXi``WARMBOOT_ENABLE_DCACHE_EARLY`` : Boolean option to enable D-cache early on the CPU after warm boot. This is applicable for platforms which do not require interconnect programming to enable cache coherency (eg: single cluster platforms). If this option is enabled, then warm boot path enables D-caches immediately after enabling MMU. This option defaults to 0.”h]”(já)”}”(hŒ ``WARMBOOT_ENABLE_DCACHE_EARLY``”h]”hŒWARMBOOT_ENABLE_DCACHE_EARLY”…””}”(hhh!j`1ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j\1ubhXI : Boolean option to enable D-cache early on the CPU after warm boot. This is applicable for platforms which do not require interconnect programming to enable cache coherency (eg: single cluster platforms). If this option is enabled, then warm boot path enables D-caches immediately after enabling MMU. This option defaults to 0.”…””}”(hXI : Boolean option to enable D-cache early on the CPU after warm boot. This is applicable for platforms which do not require interconnect programming to enable cache coherency (eg: single cluster platforms). If this option is enabled, then warm boot path enables D-caches immediately after enabling MMU. This option defaults to 0.”h!j\1ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMüh!jX1ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hX``SUPPORT_STACK_MEMTAG``: This flag determines whether to enable memory tagging for stack or not. It accepts 2 values: ``yes`` and ``no``. The default value of this flag is ``no``. Note this option must be enabled only for ARM architecture greater than Armv8.5-A. ”h]”j£)”}”(hX``SUPPORT_STACK_MEMTAG``: This flag determines whether to enable memory tagging for stack or not. It accepts 2 values: ``yes`` and ``no``. The default value of this flag is ``no``. Note this option must be enabled only for ARM architecture greater than Armv8.5-A.”h]”(já)”}”(hŒ``SUPPORT_STACK_MEMTAG``”h]”hŒSUPPORT_STACK_MEMTAG”…””}”(hhh!j‡1ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jƒ1ubhŒ_: This flag determines whether to enable memory tagging for stack or not. It accepts 2 values: ”…””}”(hŒ_: This flag determines whether to enable memory tagging for stack or not. It accepts 2 values: ”h!jƒ1ubjá)”}”(hŒ``yes``”h]”hŒyes”…””}”(hhh!jš1ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jƒ1ubhŒ and ”…””}”(hŒ and ”h!jƒ1ubjá)”}”(hŒ``no``”h]”hŒno”…””}”(hhh!j1ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jƒ1ubhŒ$. The default value of this flag is ”…””}”(hŒ$. The default value of this flag is ”h!jƒ1ubjá)”}”(hŒ``no``”h]”hŒno”…””}”(hhh!jÀ1ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jƒ1ubhŒT. Note this option must be enabled only for ARM architecture greater than Armv8.5-A.”…””}”(hŒT. Note this option must be enabled only for ARM architecture greater than Armv8.5-A.”h!jƒ1ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMh!j1ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hXè``ERRATA_SPECULATIVE_AT``: This flag determines whether to enable ``AT`` speculative errata workaround or not. It accepts 2 values: ``1`` and ``0``. The default value of this flag is ``0``. ``AT`` speculative errata workaround disables stage1 page table walk for lower ELs (EL1 and EL0) in EL3 so that ``AT`` speculative fetch at any point produces either the correct result or failure without TLB allocation. This boolean option enables errata for all below CPUs. +---------+--------------+-------------------------+ | Errata | CPU | Workaround Define | +=========+==============+=========================+ | 1165522 | Cortex-A76 | ``ERRATA_A76_1165522`` | +---------+--------------+-------------------------+ | 1319367 | Cortex-A72 | ``ERRATA_A72_1319367`` | +---------+--------------+-------------------------+ | 1319537 | Cortex-A57 | ``ERRATA_A57_1319537`` | +---------+--------------+-------------------------+ | 1530923 | Cortex-A55 | ``ERRATA_A55_1530923`` | +---------+--------------+-------------------------+ | 1530924 | Cortex-A53 | ``ERRATA_A53_1530924`` | +---------+--------------+-------------------------+ .. note:: This option is enabled by build only if platform sets any of above defines mentioned in â€™Workaround Define' column in the table. If this option is enabled for the EL3 software then EL2 software also must implement this workaround due to the behaviour of the errata mentioned in new SDEN document which will get published soon. ”h]”(j£)”}”(hŒ½``ERRATA_SPECULATIVE_AT``: This flag determines whether to enable ``AT`` speculative errata workaround or not. It accepts 2 values: ``1`` and ``0``. The default value of this flag is ``0``.”h]”(já)”}”(hŒ``ERRATA_SPECULATIVE_AT``”h]”hŒERRATA_SPECULATIVE_AT”…””}”(hhh!jç1ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jã1ubhŒ): This flag determines whether to enable ”…””}”(hŒ): This flag determines whether to enable ”h!jã1ubjá)”}”(hŒ``AT``”h]”hŒAT”…””}”(hhh!jú1ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jã1ubhŒ< speculative errata workaround or not. It accepts 2 values: ”…””}”(hŒ< speculative errata workaround or not. It accepts 2 values: ”h!jã1ubjá)”}”(hŒ``1``”h]”hŒ1”…””}”(hhh!j 2ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jã1ubhŒ and ”…””}”(hŒ and ”h!jã1ubjá)”}”(hŒ``0``”h]”hŒ0”…””}”(hhh!j 2ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jã1ubhŒ$. The default value of this flag is ”…””}”(hŒ$. The default value of this flag is ”h!jã1ubjá)”}”(hŒ``0``”h]”hŒ0”…””}”(hhh!j32ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jã1ubhŒ.”…””}”(hjTh!jã1ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMh!jß1ubj£)”}”(hŒÛ``AT`` speculative errata workaround disables stage1 page table walk for lower ELs (EL1 and EL0) in EL3 so that ``AT`` speculative fetch at any point produces either the correct result or failure without TLB allocation.”h]”(já)”}”(hŒ``AT``”h]”hŒAT”…””}”(hhh!jO2ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jK2ubhŒj speculative errata workaround disables stage1 page table walk for lower ELs (EL1 and EL0) in EL3 so that ”…””}”(hŒj speculative errata workaround disables stage1 page table walk for lower ELs (EL1 and EL0) in EL3 so that ”h!jK2ubjá)”}”(hŒ``AT``”h]”hŒAT”…””}”(hhh!jb2ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jK2ubhŒe speculative fetch at any point produces either the correct result or failure without TLB allocation.”…””}”(hŒe speculative fetch at any point produces either the correct result or failure without TLB allocation.”h!jK2ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMh!jß1ubj£)”}”(hŒ6This boolean option enables errata for all below CPUs.”h]”hŒ6This boolean option enables errata for all below CPUs.”…””}”(hj}2h!j{2ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMh!jß1ubjÕ)”}”(hhh]”jÚ)”}”(hhh]”(jß)”}”(hhh]”h"}”(h$]”h&]”h+]”h-]”h/]”Œcolwidth”K uh1jÞh!jŒ2ubjß)”}”(hhh]”h"}”(h$]”h&]”h+]”h-]”h/]”Œcolwidth”Kuh1jÞh!jŒ2ubjß)”}”(hhh]”h"}”(h$]”h&]”h+]”h-]”h/]”Œcolwidth”Kuh1jÞh!jŒ2ubj )”}”(hhh]”j)”}”(hhh]”(j)”}”(hhh]”j£)”}”(hŒErrata”h]”hŒErrata”…””}”(hj¸2h!j¶2ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMh!j³2ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!j°2ubj)”}”(hhh]”j£)”}”(hŒCPU”h]”hŒCPU”…””}”(hjÏ2h!jÍ2ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMh!jÊ2ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!j°2ubj)”}”(hhh]”j£)”}”(hŒWorkaround Define”h]”hŒWorkaround Define”…””}”(hjæ2h!jä2ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMh!já2ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!j°2ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j h!j2ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jŒ2ubj})”}”(hhh]”(j)”}”(hhh]”(j)”}”(hhh]”j£)”}”(hŒ1165522”h]”hŒ1165522”…””}”(hj3h!j 3ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMh!j 3ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!j3ubj)”}”(hhh]”j£)”}”(hŒ Cortex-A76”h]”hŒ Cortex-A76”…””}”(hj&3h!j$3ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMh!j!3ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!j3ubj)”}”(hhh]”j£)”}”(hŒ``ERRATA_A76_1165522``”h]”já)”}”(hj=3h]”hŒERRATA_A76_1165522”…””}”(hhh!j?3ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j;3ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMh!j83ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!j3ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j h!j3ubj)”}”(hhh]”(j)”}”(hhh]”j£)”}”(hŒ1319367”h]”hŒ1319367”…””}”(hjf3h!jd3ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMh!ja3ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!j^3ubj)”}”(hhh]”j£)”}”(hŒ Cortex-A72”h]”hŒ Cortex-A72”…””}”(hj}3h!j{3ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMh!jx3ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!j^3ubj)”}”(hhh]”j£)”}”(hŒ``ERRATA_A72_1319367``”h]”já)”}”(hj”3h]”hŒERRATA_A72_1319367”…””}”(hhh!j–3ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j’3ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMh!j3ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!j^3ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j h!j3ubj)”}”(hhh]”(j)”}”(hhh]”j£)”}”(hŒ1319537”h]”hŒ1319537”…””}”(hj½3h!j»3ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMh!j¸3ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jµ3ubj)”}”(hhh]”j£)”}”(hŒ Cortex-A57”h]”hŒ Cortex-A57”…””}”(hjÔ3h!jÒ3ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMh!jÏ3ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jµ3ubj)”}”(hhh]”j£)”}”(hŒ``ERRATA_A57_1319537``”h]”já)”}”(hjë3h]”hŒERRATA_A57_1319537”…””}”(hhh!jí3ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jé3ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMh!jæ3ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jµ3ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j h!j3ubj)”}”(hhh]”(j)”}”(hhh]”j£)”}”(hŒ1530923”h]”hŒ1530923”…””}”(hj4h!j4ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMh!j4ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!j4ubj)”}”(hhh]”j£)”}”(hŒ Cortex-A55”h]”hŒ Cortex-A55”…””}”(hj+4h!j)4ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMh!j&4ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!j4ubj)”}”(hhh]”j£)”}”(hŒ``ERRATA_A55_1530923``”h]”já)”}”(hjB4h]”hŒERRATA_A55_1530923”…””}”(hhh!jD4ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j@4ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMh!j=4ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!j4ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j h!j3ubj)”}”(hhh]”(j)”}”(hhh]”j£)”}”(hŒ1530924”h]”hŒ1530924”…””}”(hjk4h!ji4ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMh!jf4ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jc4ubj)”}”(hhh]”j£)”}”(hŒ Cortex-A53”h]”hŒ Cortex-A53”…””}”(hj‚4h!j€4ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMh!j}4ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jc4ubj)”}”(hhh]”j£)”}”(hŒ``ERRATA_A53_1530924``”h]”já)”}”(hj™4h]”hŒERRATA_A53_1530924”…””}”(hhh!j›4ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j—4ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMh!j”4ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jc4ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j h!j3ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j|h!jŒ2ubeh"}”(h$]”h&]”h+]”h-]”h/]”Œcols”Kuh1jÙh!j‰2ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÔh!jß1ubjã.)”}”(hXHThis option is enabled by build only if platform sets any of above defines mentioned in â€™Workaround Define' column in the table. If this option is enabled for the EL3 software then EL2 software also must implement this workaround due to the behaviour of the errata mentioned in new SDEN document which will get published soon.”h]”j£)”}”(hXHThis option is enabled by build only if platform sets any of above defines mentioned in â€™Workaround Define' column in the table. If this option is enabled for the EL3 software then EL2 software also must implement this workaround due to the behaviour of the errata mentioned in new SDEN document which will get published soon.”h]”hXJThis option is enabled by build only if platform sets any of above defines mentioned in â€™Workaround Defineâ€™ column in the table. If this option is enabled for the EL3 software then EL2 software also must implement this workaround due to the behaviour of the errata mentioned in new SDEN document which will get published soon.”…””}”(hjÓ4h!jÑ4ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCM h!jÍ4ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jâ.h!jß1ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhANhCNubj×)”}”(hŒ¹``RAS_TRAP_LOWER_EL_ERR_ACCESS``: This flag enables/disables the SCR_EL3.TERR bit, to trap access to the RAS ERR and RAS ERX registers from lower ELs. This flag is disabled by default. ”h]”j£)”}”(hŒ¸``RAS_TRAP_LOWER_EL_ERR_ACCESS``: This flag enables/disables the SCR_EL3.TERR bit, to trap access to the RAS ERR and RAS ERX registers from lower ELs. This flag is disabled by default.”h]”(já)”}”(hŒ ``RAS_TRAP_LOWER_EL_ERR_ACCESS``”h]”hŒRAS_TRAP_LOWER_EL_ERR_ACCESS”…””}”(hhh!jó4ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jï4ubhŒ˜: This flag enables/disables the SCR_EL3.TERR bit, to trap access to the RAS ERR and RAS ERX registers from lower ELs. This flag is disabled by default.”…””}”(hŒ˜: This flag enables/disables the SCR_EL3.TERR bit, to trap access to the RAS ERR and RAS ERX registers from lower ELs. This flag is disabled by default.”h!jï4ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCM&h!jë4ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hŒ³``OPENSSL_DIR``: This flag is used to provide the installed openssl directory path on the host machine which is used to build certificate generation and firmware encryption tool. ”h]”j£)”}”(hŒ²``OPENSSL_DIR``: This flag is used to provide the installed openssl directory path on the host machine which is used to build certificate generation and firmware encryption tool.”h]”(já)”}”(hŒ``OPENSSL_DIR``”h]”hŒOPENSSL_DIR”…””}”(hhh!j5ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j5ubhŒ£: This flag is used to provide the installed openssl directory path on the host machine which is used to build certificate generation and firmware encryption tool.”…””}”(hŒ£: This flag is used to provide the installed openssl directory path on the host machine which is used to build certificate generation and firmware encryption tool.”h!j5ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCM*h!j5ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hŒ¨``USE_SP804_TIMER``: Use the SP804 timer instead of the Generic Timer for functions that wait for an arbitrary time length (udelay and mdelay). The default value is 0. ”h]”j£)”}”(hŒ§``USE_SP804_TIMER``: Use the SP804 timer instead of the Generic Timer for functions that wait for an arbitrary time length (udelay and mdelay). The default value is 0.”h]”(já)”}”(hŒ``USE_SP804_TIMER``”h]”hŒUSE_SP804_TIMER”…””}”(hhh!jA5ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j=5ubhŒ”: Use the SP804 timer instead of the Generic Timer for functions that wait for an arbitrary time length (udelay and mdelay). The default value is 0.”…””}”(hŒ”: Use the SP804 timer instead of the Generic Timer for functions that wait for an arbitrary time length (udelay and mdelay). The default value is 0.”h!j=5ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCM.h!j95ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hXS``ENABLE_TRBE_FOR_NS``: This flag is used to enable access of trace buffer control registers from NS ELs, NS-EL2 or NS-EL1(when NS-EL2 is implemented but unused) when FEAT_TRBE is implemented. TRBE is an optional architectural feature for AArch64. The default is 0 and it is automatically disabled when the target architecture is AArch32. ”h]”j£)”}”(hXR``ENABLE_TRBE_FOR_NS``: This flag is used to enable access of trace buffer control registers from NS ELs, NS-EL2 or NS-EL1(when NS-EL2 is implemented but unused) when FEAT_TRBE is implemented. TRBE is an optional architectural feature for AArch64. The default is 0 and it is automatically disabled when the target architecture is AArch32.”h]”(já)”}”(hŒ``ENABLE_TRBE_FOR_NS``”h]”hŒENABLE_TRBE_FOR_NS”…””}”(hhh!jh5ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jd5ubhX<: This flag is used to enable access of trace buffer control registers from NS ELs, NS-EL2 or NS-EL1(when NS-EL2 is implemented but unused) when FEAT_TRBE is implemented. TRBE is an optional architectural feature for AArch64. The default is 0 and it is automatically disabled when the target architecture is AArch32.”…””}”(hX<: This flag is used to enable access of trace buffer control registers from NS ELs, NS-EL2 or NS-EL1(when NS-EL2 is implemented but unused) when FEAT_TRBE is implemented. TRBE is an optional architectural feature for AArch64. The default is 0 and it is automatically disabled when the target architecture is AArch32.”h!jd5ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCM2h!j`5ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hX)``ENABLE_SYS_REG_TRACE_FOR_NS``: Boolean option to enable trace system registers access from NS ELs, NS-EL2 or NS-EL1 (when NS-EL2 is implemented but unused). This feature is available if trace unit such as ETMv4.x, and ETE(extending ETM feature) is implemented. This flag is disabled by default. ”h]”j£)”}”(hX(``ENABLE_SYS_REG_TRACE_FOR_NS``: Boolean option to enable trace system registers access from NS ELs, NS-EL2 or NS-EL1 (when NS-EL2 is implemented but unused). This feature is available if trace unit such as ETMv4.x, and ETE(extending ETM feature) is implemented. This flag is disabled by default.”h]”(já)”}”(hŒ``ENABLE_SYS_REG_TRACE_FOR_NS``”h]”hŒENABLE_SYS_REG_TRACE_FOR_NS”…””}”(hhh!j5ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j‹5ubhX : Boolean option to enable trace system registers access from NS ELs, NS-EL2 or NS-EL1 (when NS-EL2 is implemented but unused). This feature is available if trace unit such as ETMv4.x, and ETE(extending ETM feature) is implemented. This flag is disabled by default.”…””}”(hX : Boolean option to enable trace system registers access from NS ELs, NS-EL2 or NS-EL1 (when NS-EL2 is implemented but unused). This feature is available if trace unit such as ETMv4.x, and ETE(extending ETM feature) is implemented. This flag is disabled by default.”h!j‹5ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCM8h!j‡5ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubj×)”}”(hŒÛ``ENABLE_TRF_FOR_NS``: Boolean option to enable trace filter control registers access from NS ELs, NS-EL2 or NS-EL1 (when NS-EL2 is implemented but unused), if FEAT_TRF is implemented. This flag is disabled by default. ”h]”j£)”}”(hŒÚ``ENABLE_TRF_FOR_NS``: Boolean option to enable trace filter control registers access from NS ELs, NS-EL2 or NS-EL1 (when NS-EL2 is implemented but unused), if FEAT_TRF is implemented. This flag is disabled by default.”h]”(já)”}”(hŒ``ENABLE_TRF_FOR_NS``”h]”hŒENABLE_TRF_FOR_NS”…””}”(hhh!j¶5ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j²5ubhŒÅ: Boolean option to enable trace filter control registers access from NS ELs, NS-EL2 or NS-EL1 (when NS-EL2 is implemented but unused), if FEAT_TRF is implemented. This flag is disabled by default.”…””}”(hŒÅ: Boolean option to enable trace filter control registers access from NS ELs, NS-EL2 or NS-EL1 (when NS-EL2 is implemented but unused), if FEAT_TRF is implemented. This flag is disabled by default.”h!j²5ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCM=h!j®5ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jÓhhhAj¡hCNubeh"}”(h$]”h&]”h+]”h-]”h/]”jó$Œ-”uh1jÑhAj¡hCKh!jÀhhubeh"}”(h$]”(Œcommon-build-options”j¿eh&]”h+]”(Œcommon build options”Œbuild_options_common”eh-]”h/]”uh1jŒh!jŽhhhAj¡hCKŒexpect_referenced_by_name”}”jâ5j´sŒexpect_referenced_by_id”}”j¿j´subj)”}”(hhh]”(j’)”}”(hŒGICv3 driver options”h]”hŒGICv3 driver options”…””}”(hjî5h!jì5hhhANhCNubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j‘h!jé5hhhAj¡hCMBubj£)”}”(hŒ0GICv3 driver files are included using directive:”h]”hŒ0GICv3 driver files are included using directive:”…””}”(hjü5h!jú5hhhANhCNubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMDh!jé5hhubj£)”}”(hŒ'``include drivers/arm/gic/v3/gicv3.mk``”h]”já)”}”(hj 6h]”hŒ#include drivers/arm/gic/v3/gicv3.mk”…””}”(hhh!j6ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j6ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMFh!jé5hhubj£)”}”(hŒUThe driver can be configured with the following options set in the platform makefile:”h]”hŒUThe driver can be configured with the following options set in the platform makefile:”…””}”(hj!6h!j6hhhANhCNubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMHh!jé5hhubjÒ)”}”(hhh]”(j×)”}”(hŒä``GICV3_SUPPORT_GIC600``: Add support for the GIC-600 variants of GICv3. Enabling this option will add runtime detection support for the GIC-600, so is safe to select even for a GIC500 implementation. This option defaults to 0. ”h]”j£)”}”(hŒã``GICV3_SUPPORT_GIC600``: Add support for the GIC-600 variants of GICv3. Enabling this option will add runtime detection support for the GIC-600, so is safe to select even for a GIC500 implementation. This option defaults to 0.”h]”(já)”}”(hŒ``GICV3_SUPPORT_GIC600``”h]”hŒGICV3_SUPPORT_GIC600”…””}”(hhh!j86ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j46ubhŒË: Add support for the GIC-600 variants of GICv3. Enabling this option will add runtime detection support for the GIC-600, so is safe to select even for a GIC500 implementation. This option defaults to 0.”…””}”(hŒË: Add support for the GIC-600 variants of GICv3. Enabling this option will add runtime detection support for the GIC-600, so is safe to select even for a GIC500 implementation. This option defaults to 0.”h!j46ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMKh!j06ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!j-6hhhAj¡hCNubj×)”}”(hX``GICV3_SUPPORT_GIC600AE_FMU``: Add support for the Fault Management Unit for GIC-600 AE. Enabling this option will introduce support to initialize the FMU. Platforms should call the init function during boot to enable the FMU and its safety mechanisms. This option defaults to 0. ”h]”j‡)”}”(hhh]”jŒ)”}”(hX``GICV3_SUPPORT_GIC600AE_FMU``: Add support for the Fault Management Unit for GIC-600 AE. Enabling this option will introduce support to initialize the FMU. Platforms should call the init function during boot to enable the FMU and its safety mechanisms. This option defaults to 0. ”h]”(j’)”}”(hŒI``GICV3_SUPPORT_GIC600AE_FMU``: Add support for the Fault Management Unit”h]”(já)”}”(hŒ``GICV3_SUPPORT_GIC600AE_FMU``”h]”hŒGICV3_SUPPORT_GIC600AE_FMU”…””}”(hhh!jf6ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jb6ubhŒ+: Add support for the Fault Management Unit”…””}”(hŒ+: Add support for the Fault Management Unit”h!jb6ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j‘hAj¡hCMSh!j^6ubj±)”}”(hhh]”j£)”}”(hŒÎfor GIC-600 AE. Enabling this option will introduce support to initialize the FMU. Platforms should call the init function during boot to enable the FMU and its safety mechanisms. This option defaults to 0.”h]”hŒÎfor GIC-600 AE. Enabling this option will introduce support to initialize the FMU. Platforms should call the init function during boot to enable the FMU and its safety mechanisms. This option defaults to 0.”…””}”(hj„6h!j‚6ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMQh!j6ubah"}”(h$]”h&]”h+]”h-]”h/•W]”uh1j°h!j^6ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j‹hAj¡hCMSh!j[6ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j†h!jW6ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!j-6hhhANhCNubj×)”}”(hŒq``GICV3_IMPL_GIC600_MULTICHIP``: Selects GIC-600 variant with multichip functionality. This option defaults to 0 ”h]”j£)”}”(hŒp``GICV3_IMPL_GIC600_MULTICHIP``: Selects GIC-600 variant with multichip functionality. This option defaults to 0”h]”(já)”}”(hŒ``GICV3_IMPL_GIC600_MULTICHIP``”h]”hŒGICV3_IMPL_GIC600_MULTICHIP”…””}”(hhh!j°6ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j¬6ubhŒQ: Selects GIC-600 variant with multichip functionality. This option defaults to 0”…””}”(hŒQ: Selects GIC-600 variant with multichip functionality. This option defaults to 0”h!j¬6ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMUh!j¨6ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!j-6hhhAj¡hCNubj×)”}”(hX,``GICV3_OVERRIDE_DISTIF_PWR_OPS``: Allows override of default implementation of ``arm_gicv3_distif_pre_save`` and ``arm_gicv3_distif_post_restore`` functions. This is required for FVP platform which need to simulate GIC save and restore during SYSTEM_SUSPEND without powering down GIC. Default is 0. ”h]”j£)”}”(hX+``GICV3_OVERRIDE_DISTIF_PWR_OPS``: Allows override of default implementation of ``arm_gicv3_distif_pre_save`` and ``arm_gicv3_distif_post_restore`` functions. This is required for FVP platform which need to simulate GIC save and restore during SYSTEM_SUSPEND without powering down GIC. Default is 0.”h]”(já)”}”(hŒ!``GICV3_OVERRIDE_DISTIF_PWR_OPS``”h]”hŒGICV3_OVERRIDE_DISTIF_PWR_OPS”…””}”(hhh!j×6ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jÓ6ubhŒ/: Allows override of default implementation of ”…””}”(hŒ/: Allows override of default implementation of ”h!jÓ6ubjá)”}”(hŒ``arm_gicv3_distif_pre_save``”h]”hŒarm_gicv3_distif_pre_save”…””}”(hhh!jê6ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jÓ6ubhŒ and ”…””}”(hŒ and ”h!jÓ6ubjá)”}”(hŒ!``arm_gicv3_distif_post_restore``”h]”hŒarm_gicv3_distif_post_restore”…””}”(hhh!jý6ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jÓ6ubhŒ˜ functions. This is required for FVP platform which need to simulate GIC save and restore during SYSTEM_SUSPEND without powering down GIC. Default is 0.”…””}”(hŒ˜ functions. This is required for FVP platform which need to simulate GIC save and restore during SYSTEM_SUSPEND without powering down GIC. Default is 0.”h!jÓ6ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMXh!jÏ6ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!j-6hhhAj¡hCNubj×)”}”(hŒc``GIC_ENABLE_V4_EXTN`` : Enables GICv4 related changes in GICv3 driver. This option defaults to 0. ”h]”j£)”}”(hŒb``GIC_ENABLE_V4_EXTN`` : Enables GICv4 related changes in GICv3 driver. This option defaults to 0.”h]”(já)”}”(hŒ``GIC_ENABLE_V4_EXTN``”h]”hŒGIC_ENABLE_V4_EXTN”…””}”(hhh!j$7ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j 7ubhŒL : Enables GICv4 related changes in GICv3 driver. This option defaults to 0.”…””}”(hŒL : Enables GICv4 related changes in GICv3 driver. This option defaults to 0.”h!j 7ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCM]h!j7ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!j-6hhhAj¡hCNubj×)”}”(hŒ``GIC_EXT_INTID``: When set to ``1``, GICv3 driver will support extended PPI (1056-1119) and SPI (4096-5119) range. This option defaults to 0. ”h]”j£)”}”(hŒŽ``GIC_EXT_INTID``: When set to ``1``, GICv3 driver will support extended PPI (1056-1119) and SPI (4096-5119) range. This option defaults to 0.”h]”(já)”}”(hŒ``GIC_EXT_INTID``”h]”hŒ GIC_EXT_INTID”…””}”(hhh!jK7ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jG7ubhŒ: When set to ”…””}”(hŒ: When set to ”h!jG7ubjá)”}”(hŒ``1``”h]”hŒ1”…””}”(hhh!j^7ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jG7ubhŒj, GICv3 driver will support extended PPI (1056-1119) and SPI (4096-5119) range. This option defaults to 0.”…””}”(hŒj, GICv3 driver will support extended PPI (1056-1119) and SPI (4096-5119) range. This option defaults to 0.”h!jG7ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCM`h!jC7ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!j-6hhhAj¡hCNubeh"}”(h$]”h&]”h+]”h-]”h/]”jó$jÛ5uh1jÑhAj¡hCMKh!jé5hhubeh"}”(h$]”Œgicv3-driver-options”ah&]”h+]”Œgicv3 driver options”ah-]”h/]”uh1jŒh!jŽhhhAj¡hCMBubj)”}”(hhh]”(j’)”}”(hŒDebugging options”h]”hŒDebugging options”…””}”(hj7h!jŽ7hhhANhCNubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j‘h!j‹7hhhAj¡hCMdubj£)”}”(hŒ>To compile a debug version and make the build more verbose use”h]”hŒ>To compile a debug version and make the build more verbose use”…””}”(hjž7h!jœ7hhhANhCNubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMfh!j‹7hhubjõ)”}”(hŒ$make PLAT= DEBUG=1 V=1 all”h]”hŒ$make PLAT= DEBUG=1 V=1 all”…””}”(hhh!jª7ubah"}”(h$]”h&]”h+]”h-]”h/]”Œforce”‰Œhighlight_args”}”j j Œlanguage”Œshell”uh1jôhAj¡hCMhh!j‹7hhubj£)”}”(hXgAArch64 GCC uses DWARF version 4 debugging symbols by default. Some tools (for example DS-5) might not support this and may need an older version of DWARF symbols to be emitted by GCC. This can be achieved by using the ``-gdwarf-`` flag, with the version being set to 2 or 3. Setting the version to 2 is recommended for DS-5 versions older than 5.16.”h]”(hŒÛAArch64 GCC uses DWARF version 4 debugging symbols by default. Some tools (for example DS-5) might not support this and may need an older version of DWARF symbols to be emitted by GCC. This can be achieved by using the ”…””}”(hŒÛAArch64 GCC uses DWARF version 4 debugging symbols by default. Some tools (for example DS-5) might not support this and may need an older version of DWARF symbols to be emitted by GCC. This can be achieved by using the ”h!j½7hhhANhCNubjá)”}”(hŒ``-gdwarf-``”h]”hŒ-gdwarf-”…””}”(hhh!jÆ7ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j½7ubhŒw flag, with the version being set to 2 or 3. Setting the version to 2 is recommended for DS-5 versions older than 5.16.”…””}”(hŒw flag, with the version being set to 2 or 3. Setting the version to 2 is recommended for DS-5 versions older than 5.16.”h!j½7hhhANhCNubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMlh!j‹7hhubj£)”}”(hŒmWhen debugging logic problems it might also be useful to disable all compiler optimizations by using ``-O0``.”h]”(hŒeWhen debugging logic problems it might also be useful to disable all compiler optimizations by using ”…””}”(hŒeWhen debugging logic problems it might also be useful to disable all compiler optimizations by using ”h!jß7hhhANhCNubjá)”}”(hŒ``-O0``”h]”hŒ-O0”…””}”(hhh!jè7ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jß7ubhŒ.”…””}”(hjTh!jß7hhhANhCNubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMrh!j‹7hhubjõ-)”}”(hŒÅUsing ``-O0`` could cause output images to be larger and base addresses might need to be recalculated (see the **Memory layout on Arm development platforms** section in the :ref:`Firmware Design`).”h]”j£)”}”(hŒÅUsing ``-O0`` could cause output images to be larger and base addresses might need to be recalculated (see the **Memory layout on Arm development platforms** section in the :ref:`Firmware Design`).”h]”(hŒUsing ”…””}”(hŒUsing ”h!j8ubjá)”}”(hŒ``-O0``”h]”hŒ-O0”…””}”(hhh!j 8ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j8ubhŒb could cause output images to be larger and base addresses might need to be recalculated (see the ”…””}”(hŒb could cause output images to be larger and base addresses might need to be recalculated (see the ”h!j8ubh Œstrong”“”)”}”(hŒ.**Memory layout on Arm development platforms**”h]”hŒ*Memory layout on Arm development platforms”…””}”(hhh!j"8ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j 8h!j8ubhŒ section in the ”…””}”(hŒ section in the ”h!j8ubh)”}”(hŒ:ref:`Firmware Design`”h]”h)”}”(hj78h]”hŒFirmware Design”…””}”(hhh!j98ubah"}”(h$]”h&]”(h(Œstd”Œstd-ref”eh+]”h-]”h/]”uh1hh!j58ubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”jC8Œreftype”Œref”Œrefexplicit”‰Œrefwarn”ˆh?Œfirmware design”uh1hhAj¡hCMvh!j8ubhŒ).”…””}”(hŒ).”h!j8ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMvh!j8ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jô-h!j‹7hhhAj¡hCNubj£)”}”(hŒ[Extra debug options can be passed to the build system by setting ``CFLAGS`` or ``LDFLAGS``:”h]”(hŒAExtra debug options can be passed to the build system by setting ”…””}”(hŒAExtra debug options can be passed to the build system by setting ”h!jf8hhhANhCNubjá)”}”(hŒ ``CFLAGS``”h]”hŒCFLAGS”…””}”(hhh!jo8ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jf8ubhŒ or ”…””}”(hŒ or ”h!jf8hhhANhCNubjá)”}”(hŒ``LDFLAGS``”h]”hŒLDFLAGS”…””}”(hhh!j‚8ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jf8ubhŒ:”…””}”(hŒ:”h!jf8hhhANhCNubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMzh!j‹7hhubjõ)”}”(hŒaCFLAGS='-O0 -gdwarf-2' \ make PLAT= DEBUG=1 V=1 all”h]”hŒaCFLAGS='-O0 -gdwarf-2' \ make PLAT= DEBUG=1 V=1 all”…””}”(hhh!j›8ubah"}”(h$]”h&]”h+]”h-]”h/]”Œforce”‰Œhighlight_args”}”j j j»7Œshell”uh1jôhAj¡hCM}h!j‹7hhubj£)”}”(hŒyNote that using ``-Wl,`` style compilation driver options in ``CFLAGS`` will be ignored as the linker is called directly.”h]”(hŒNote that using ”…””}”(hŒNote that using ”h!j8hhhANhCNubjá)”}”(hŒ``-Wl,``”h]”hŒ-Wl,”…””}”(hhh!j¶8ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j8ubhŒ% style compilation driver options in ”…””}”(hŒ% style compilation driver options in ”h!j8hhhANhCNubjá)”}”(hŒ ``CFLAGS``”h]”hŒCFLAGS”…””}”(hhh!jÉ8ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j8ubhŒ2 will be ignored as the linker is called directly.”…””}”(hŒ2 will be ignored as the linker is called directly.”h!j8hhhANhCNubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCM‚h!j‹7hhubj£)”}”(hXŠIt is also possible to introduce an infinite loop to help in debugging the post-BL2 phase of TF-A. This can be done by rebuilding BL1 with the ``SPIN_ON_BL1_EXIT=1`` build flag. Refer to the :ref:`build_options_common` section. In this case, the developer may take control of the target using a debugger when indicated by the console output. When using DS-5, the following commands can be used:”h]”(hŒIt is also possible to introduce an infinite loop to help in debugging the post-BL2 phase of TF-A. This can be done by rebuilding BL1 with the ”…””}”(hŒIt is also possible to introduce an infinite loop to help in debugging the post-BL2 phase of TF-A. This can be done by rebuilding BL1 with the ”h!jâ8hhhANhCNubjá)”}”(hŒ``SPIN_ON_BL1_EXIT=1``”h]”hŒSPIN_ON_BL1_EXIT=1”…””}”(hhh!jë8ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jâ8ubhŒ build flag. Refer to the ”…””}”(hŒ build flag. Refer to the ”h!jâ8hhhANhCNubh)”}”(hŒ:ref:`build_options_common`”h]”h)”}”(hj9h]”hŒbuild_options_common”…””}”(hhh!j9ubah"}”(h$]”h&]”(h(Œstd”Œstd-ref”eh+]”h-]”h/]”uh1hh!jþ8ubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”j9Œreftype”Œref”Œrefexplicit”‰Œrefwarn”ˆh?Œbuild_options_common”uh1hhAj¡hCM…h!jâ8ubhŒ° section. In this case, the developer may take control of the target using a debugger when indicated by the console output. When using DS-5, the following commands can be used:”…””}”(hŒ° section. In this case, the developer may take control of the target using a debugger when indicated by the console output. When using DS-5, the following commands can be used:”h!jâ8hhhANhCNubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCM…h!j‹7hhubjõ)”}”(hŒÒ# Stop target execution interrupt # # Prepare your debugging environment, e.g. set breakpoints # # Jump over the debug loop set var $AARCH64::$Core::$PC = $AARCH64::$Core::$PC + 4 # Resume execution continue”h]”hŒÒ# Stop target execution interrupt # # Prepare your debugging environment, e.g. set breakpoints # # Jump over the debug loop set var $AARCH64::$Core::$PC = $AARCH64::$Core::$PC + 4 # Resume execution continue”…””}”(hhh!j)9ubah"}”(h$]”h&]”h+]”h-]”h/]”j j uh1jôhAj¡hCMŽh!j‹7hhubeh"}”(h$]”Œdebugging-options”ah&]”h+]”Œdebugging options”ah-]”h/]”uh1jŒh!jŽhhhAj¡hCMdubj)”}”(hhh]”(j’)”}”(hŒFirmware update options”h]”hŒFirmware update options”…””}”(hjD9h!jB9hhhANhCNubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j‘h!j?9hhhAj¡hCMœubjÒ)”}”(hhh]”(j×)”}”(hŒ£``NR_OF_FW_BANKS``: Define the number of firmware banks. This flag is used in defining the firmware update metadata structure. This flag is by default set to '2'. ”h]”j£)”}”(hŒ¢``NR_OF_FW_BANKS``: Define the number of firmware banks. This flag is used in defining the firmware update metadata structure. This flag is by default set to '2'.”h]”(já)”}”(hŒ``NR_OF_FW_BANKS``”h]”hŒNR_OF_FW_BANKS”…””}”(hhh!j[9ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!jW9ubhŒ”: Define the number of firmware banks. This flag is used in defining the firmware update metadata structure. This flag is by default set to â€˜2â€™.”…””}”(hŒ: Define the number of firmware banks. This flag is used in defining the firmware update metadata structure. This flag is by default set to '2'.”h!jW9ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCMžh!jS9ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jP9hhhAj¡hCNubj×)”}”(hX%``NR_OF_IMAGES_IN_FW_BANK``: Define the number of firmware images in each firmware bank. Each firmware bank must have the same number of images as per the `PSA FW update specification`_. This flag is used in defining the firmware update metadata structure. This flag is by default set to '1'. ”h]”j£)”}”(hX$``NR_OF_IMAGES_IN_FW_BANK``: Define the number of firmware images in each firmware bank. Each firmware bank must have the same number of images as per the `PSA FW update specification`_. This flag is used in defining the firmware update metadata structure. This flag is by default set to '1'.”h]”(já)”}”(hŒ``NR_OF_IMAGES_IN_FW_BANK``”h]”hŒNR_OF_IMAGES_IN_FW_BANK”…””}”(hhh!j‚9ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j~9ubhŒ€: Define the number of firmware images in each firmware bank. Each firmware bank must have the same number of images as per the ”…””}”(hŒ€: Define the number of firmware images in each firmware bank. Each firmware bank must have the same number of images as per the ”h!j~9ubjá+)”}”(hŒ`PSA FW update specification`_”h]”hŒPSA FW update specification”…””}”(hŒPSA FW update specification”h!j•9ubah"}”(h$]”h&]”h+]”h-]”h/]”Œname”ŒPSA FW update specification”jò+Œ2https://developer.arm.com/documentation/den0118/a/”uh1jà+h!j~9jô+KubhŒo. This flag is used in defining the firmware update metadata structure. This flag is by default set to â€˜1â€™.”…””}”(hŒk. This flag is used in defining the firmware update metadata structure. This flag is by default set to '1'.”h!j~9ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCM¢h!jz9ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jP9hhhAj¡hCNubj×)”}”(hX½``PSA_FWU_SUPPORT``: Enable the firmware update mechanism as per the `PSA FW update specification`_. The default value is 0, and this is an experimental feature. PSA firmware update implementation has some limitations, such as BL2 is not part of the protocol-updatable images, if BL2 needs to be updated, then it should be done through another platform-defined mechanism, and it assumes that the platform's hardware supports CRC32 instructions. ”h]”j£)”}”(hX¼``PSA_FWU_SUPPORT``: Enable the firmware update mechanism as per the `PSA FW update specification`_. The default value is 0, and this is an experimental feature. PSA firmware update implementation has some limitations, such as BL2 is not part of the protocol-updatable images, if BL2 needs to be updated, then it should be done through another platform-defined mechanism, and it assumes that the platform's hardware supports CRC32 instructions.”h]”(já)”}”(hŒ``PSA_FWU_SUPPORT``”h]”hŒPSA_FWU_SUPPORT”…””}”(hhh!jÀ9ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jàh!j¼9ubhŒ2: Enable the firmware update mechanism as per the ”…””}”(hŒ2: Enable the firmware update mechanism as per the ”h!j¼9ubjá+)”}”(hŒ`PSA FW update specification`_”h]”hŒPSA FW update specification”…””}”(hŒPSA FW update specification”h!jÓ9ubah"}”(h$]”h&]”h+]”h-]”h/]”Œname”ŒPSA FW update specification”jò+j¦9uh1jà+h!j¼9jô+KubhX[. The default value is 0, and this is an experimental feature. PSA firmware update implementation has some limitations, such as BL2 is not part of the protocol-updatable images, if BL2 needs to be updated, then it should be done through another platform-defined mechanism, and it assumes that the platformâ€™s hardware supports CRC32 instructions.”…””}”(hXY. The default value is 0, and this is an experimental feature. PSA firmware update implementation has some limitations, such as BL2 is not part of the protocol-updatable images, if BL2 needs to be updated, then it should be done through another platform-defined mechanism, and it assumes that the platform's hardware supports CRC32 instructions.”h!j¼9ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCM¨h!j¸9ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jÖh!jP9hhhAj¡hCNubeh"}”(h$]”h&]”h+]”h-]”h/]”jó$jÛ5uh1jÑhAj¡hCMžh!j?9hhubh Œ transition”“”)”}”(hŒ--------------”h]”h"}”(h$]”h&]”h+]”h-]”h/]”uh1jû9hAj¡hCM°h!j?9hhubj£)”}”(hŒ<*Copyright (c) 2019-2021, Arm Limited. All rights reserved.*”h]”jc )”}”(hj :h]”hŒ:Copyright (c) 2019-2021, Arm Limited. All rights reserved.”…””}”(hhh!j:ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jb h!j:ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢hAj¡hCM²h!j?9hhubj³)”}”(hŒ:.. _DEN0115: https://developer.arm.com/docs/den0115/latest”h]”h"}”(h$]”Œden0115”ah&]”h+]”Œden0115”ah-]”h/]”jò+jó+uh1j²hCMùh!j?9hhhAj¡Œ referenced”Kubj³)”}”(hŒS.. _PSA FW update specification: https://developer.arm.com/documentation/den0118/a/”h]”h"}”(h$]”Œpsa-fw-update-specification”ah&]”h+]”Œpsa fw update specification”ah-]”h/]”jò+j¦9uh1j²hCMúh!j?9hhhAj¡j*:Kubeh"}”(h$]”Œfirmware-update-options”ah&]”h+]”Œfirmware update options”ah-]”h/]”uh1jŒh!jŽhhhAj¡hCMœubeh"}”(h$]”Œ build-options”ah&]”h+]”Œ build options”ah-]”h/]”uh1jŒh!hhhhAj¡hCKubeh"}”(h$]”h&]”h+]”h-]”h/]”Œsource”j¡uh1hŒcurrent_source”NŒcurrent_line”NŒsettings”Œdocutils.frontend”ŒValues”“”)”}”(j‘NŒ generator”NŒ datestamp”NŒsource_link”NŒ source_url”NŒ toc_backlinks”jŒfootnote_backlinks”KŒ sectnum_xform”KŒstrip_comments”NŒstrip_elements_with_classes”NŒ strip_classes”NŒreport_level”KŒ halt_level”KŒexit_status_level”KŒdebug”NŒwarning_stream”NŒ traceback”ˆŒinput_encoding”Œ utf-8-sig”Œinput_encoding_error_handler”Œstrict”Œoutput_encoding”Œutf-8”Œoutput_encoding_error_handler”ji:Œerror_encoding”Œutf-8”Œerror_encoding_error_handler”Œbackslashreplace”Œ language_code”Œen”Œrecord_dependencies”NŒconfig”NŒ id_prefix”hŒauto_id_prefix”Œid”Œ dump_settings”NŒdump_internals”NŒdump_transforms”NŒdump_pseudo_xml”NŒexpose_internals”NŒstrict_visitor”NŒ_disable_config”NŒ_source”j¡Œ_destination”NŒ _config_files”]”Œpep_references”NŒpep_base_url”Œ https://www.python.org/dev/peps/”Œpep_file_url_template”Œpep-%04d”Œrfc_references”NŒrfc_base_url”Œhttps://tools.ietf.org/html/”Œ tab_width”KŒtrim_footnote_reference_space”‰Œfile_insertion_enabled”ˆŒraw_enabled”KŒsyntax_highlight”Œlong”Œsmart_quotes”ˆŒsmartquotes_locales”]”Œcharacter_level_inline_markup”‰Œdoctitle_xform”‰Œ docinfo_xform”KŒsectsubtitle_xform”‰Œembed_stylesheet”‰Œcloak_email_addresses”ˆŒenv”NubŒreporter”NŒindirect_targets”]”Œsubstitution_defs”}”(hHhhshKhžhvhÉh¡hôhÌjh÷jJj"jujMj jxjËj£jöjÎj!jùjLj$jwjOj¢jzjÍj¥jøjÐj#jûjNj&jyjQj¤j|jÏj§jújÒj%jýjPj(j{jSj¦j~jÑj©jüjÔj'jÿjRj*j}jUj¨j€jÓj«jþjÖj)jjTj,jjWjªj‚jÕjjjØj+jjVj.jjYj¬j„j×j¯jjÚj-jjXj0jƒj[j®j†jÙj±j jÜj/ j jZ j2 j… j] j° jˆ jÛ j³ j jÞ j1 j j\ j4 j‡ j_ j² jŠ jÝ jµ jjà j3jj^j6j‰jauŒsubstitution_names”}”(Œaarch32”hHŒaarch64”hsŒamu”hžŒamus”hÉŒapi”hôŒbti”jŒcot”juŒcss”j Œcve”jËŒdtb”jöŒds-5”j!Œdsu”jLŒdt”jwŒel”j¢Œehf”jÍŒfconf”jøŒfdt”j#Œff-a”jNŒfip”jyŒfvp”j¤Œfwu”jÏŒgic”júŒisa”j%Œlinaro”jPŒmmu”j{Œmpam”j¦Œmpmm”jÑŒmpidr”jüŒmte”j'Œoen”jRŒop-tee”j}Œote”j¨Œpdd”jÓŒpauth”jþŒpmf”j)Œpsci”jTŒras”jŒrot”jªŒscmi”jÕŒscp”jŒsdei”j+Œsds”jVŒsea”jŒsip”j×Œsmc”jŒsmccc”j-Œsoc”jXŒsp”jƒŒspd”j®Œspm”jÙŒssbs”j Œsve”j/ Œtbb”jZ Œtbbr”j… Œtee”j° Œtf-a”jÛ Œtf-m”j Œtlb”j1 Œtlk”j\ Œtrng”j‡ Œtsp”j² Œtzc”jÝ Œubsan”jŒuefi”j3Œwdog”j^Œxlat”j‰uŒrefnames”}”(Œden0115”]”jâ+aŒpsa fw update specification”]”(j•9jÓ9euŒrefids”}”j¿]”j´asŒnameids”}”(jD:jA:jâ5j¿já5jÞ5jˆ7j…7j<9j99j<:j9:j':j$:j4:j1:uŒ nametypes”}”(jD:Njâ5ˆjá5Njˆ7Nj<9Nj<:Nj':ˆj4:ˆuh$}”(jA:jŽj¿jÀjÞ5jÀj…7jé5j99j‹7j9:j?9j$:j:j1:j+:uŒ footnote_refs”}”Œ citation_refs”}”Œ autofootnotes”]”Œautofootnote_refs”]”Œsymbol_footnotes”]”Œsymbol_footnote_refs”]”Œ footnotes”]”Œ citations”]”Œautofootnote_start”KŒsymbol_footnote_start”KŒ id_counter”Œcollections”ŒCounter”“”}”…”R”Œparse_messages”]”Œtransform_messages”]”h Œsystem_message”“”)”}”(hhh]”j£)”}”(hhh]”hŒ:Hyperlink target "build-options-common" is not referenced.”…””}”(hhh!j;ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j¢h!j;ubah"}”(h$]”h&]”h+]”h-]”h/]”Œlevel”KŒtype”ŒINFO”Œsource”j¡Œline”KPuh1j;ubaŒtransformer”NŒ decoration”Nhhub.