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:term:`TEE`”h]”h)”}”(hŒ:term:`TEE`”h]”h)”}”(hjŽ h]”hŒTEE”…””}”(hhh!j ubah"}”(h$]”h&]”(h(Œstd”Œstd-term”eh+]”h-]”h/]”uh1hh!jŒ ubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”jš Œreftype”Œterm”Œrefexplicit”‰Œrefwarn”ˆh?ŒTEE”uh1hhAhBhCK9h!jˆ ubah"}”(h$]”h&]”h+]”ŒTEE”ah-]”h/]”uh1h hAhBhCK9h!hhhubh)”}”(hŒ .. |TF-A| replace:: :term:`TF-A`”h]”h)”}”(hŒ:term:`TF-A`”h]”h)”}”(hj¹ h]”hŒTF-A”…””}”(hhh!j» ubah"}”(h$]”h&]”(h(Œstd”Œstd-term”eh+]”h-]”h/]”uh1hh!j· ubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”jÅ Œreftype”Œterm”Œrefexplicit”‰Œrefwarn”ˆh?ŒTF-A”uh1hhAhBhCK:h!j³ ubah"}”(h$]”h&]”h+]”ŒTF-A”ah-]”h/]”uh1h hAhBhCK:h!hhhubh)”}”(hŒ .. |TF-M| replace:: :term:`TF-M`”h]”h)”}”(hŒ:term:`TF-M`”h]”h)”}”(hjä h]”hŒTF-M”…””}”(hhh!jæ ubah"}”(h$]”h&]”(h(Œstd”Œstd-term”eh+]”h-]”h/]”uh1hh!jâ ubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”jð Œreftype”Œterm”Œrefexplicit”‰Œrefwarn”ˆh?ŒTF-M”uh1hhAhBhCK;h!jÞ ubah"}”(h$]”h&]”h+]”ŒTF-M”ah-]”h/]”uh1h hAhBhCK;h!hhhubh)”}”(hŒ.. |TLB| replace:: :term:`TLB`”h]”h)”}”(hŒ:term:`TLB`”h]”h)”}”(hj h]”hŒTLB”…””}”(hhh!j ubah"}”(h$]”h&]”(h(Œstd”Œstd-term”eh+]”h-]”h/]”uh1hh!j ubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”j Œreftype”Œterm”Œrefexplicit”‰Œrefwarn”ˆh?ŒTLB”uh1hhAhBhCKh!j_ ubah"}”(h$]”h&]”h+]”ŒTRNG”ah-]”h/]”uh1h hAhBhCK>h!hhhubh)”}”(hŒ.. |TSP| replace:: :term:`TSP`”h]”h)”}”(hŒ:term:`TSP`”h]”h)”}”(hj h]”hŒTSP”…””}”(hhh!j’ ubah"}”(h$]”h&]”(h(Œstd”Œstd-term”eh+]”h-]”h/]”uh1hh!jŽ ubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”jœ Œreftype”Œterm”Œrefexplicit”‰Œrefwarn”ˆh?ŒTSP”uh1hhAhBhCK?h!jŠ ubah"}”(h$]”h&]”h+]”ŒTSP”ah-]”h/]”uh1h hAhBhCK?h!hhhubh)”}”(hŒ.. |TZC| replace:: :term:`TZC`”h]”h)”}”(hŒ:term:`TZC`”h]”h)”}”(hj» h]”hŒTZC”…””}”(hhh!j½ ubah"}”(h$]”h&]”(h(Œstd”Œstd-term”eh+]”h-]”h/]”uh1hh!j¹ ubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”jÇ Œreftype”Œterm”Œrefexplicit”‰Œrefwarn”ˆh?ŒTZC”uh1hhAhBhCK@h!jµ ubah"}”(h$]”h&]”h+]”ŒTZC”ah-]”h/]”uh1h hAhBhCK@h!hhhubh)”}”(hŒ".. |UBSAN| replace:: :term:`UBSAN`”h]”h)”}”(hŒ :term:`UBSAN`”h]”h)”}”(hjæ h]”hŒUBSAN”…””}”(hhh!jè ubah"}”(h$]”h&]”(h(Œstd”Œstd-term”eh+]”h-]”h/]”uh1hh!jä ubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”jò Œreftype”Œterm”Œrefexplicit”‰Œrefwarn”ˆh?ŒUBSAN”uh1hhAhBhCKAh!jà ubah"}”(h$]”h&]”h+]”ŒUBSAN”ah-]”h/]”uh1h hAhBhCKAh!hhhubh)”}”(hŒ .. |UEFI| replace:: :term:`UEFI`”h]”h)”}”(hŒ:term:`UEFI`”h]”h)”}”(hjh]”hŒUEFI”…””}”(hhh!jubah"}”(h$]”h&]”(h(Œstd”Œstd-term”eh+]”h-]”h/]”uh1hh!jubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”jŒreftype”Œterm”Œrefexplicit”‰Œrefwarn”ˆh?ŒUEFI”uh1hhAhBhCKBh!jubah"}”(h$]”h&]”h+]”ŒUEFI”ah-]”h/]”uh1h hAhBhCKBh!hhhubh)”}”(hŒ .. |WDOG| replace:: :term:`WDOG`”h]”h)”}”(hŒ:term:`WDOG`”h]”h)”}”(hj<h]”hŒWDOG”…””}”(hhh!j>ubah"}”(h$]”h&]”(h(Œstd”Œstd-term”eh+]”h-]”h/]”uh1hh!j:ubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”jHŒreftype”Œterm”Œrefexplicit”‰Œrefwarn”ˆh?ŒWDOG”uh1hhAhBhCKCh!j6ubah"}”(h$]”h&]”h+]”ŒWDOG”ah-]”h/]”uh1h hAhBhCKCh!hhhubh)”}”(hŒ!.. |XLAT| replace:: :term:`XLAT` ”h]”h)”}”(hŒ:term:`XLAT`”h]”h)”}”(hjgh]”hŒXLAT”…””}”(hhh!jiubah"}”(h$]”h&]”(h(Œstd”Œstd-term”eh+]”h-]”h/]”uh1hh!jeubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”jsŒreftype”Œterm”Œrefexplicit”‰Œrefwarn”ˆh?ŒXLAT”uh1hhAhBhCKDh!jaubah"}”(h$]”h&]”h+]”ŒXLAT”ah-]”h/]”uh1h hAhBhCKDh!hhhubh Œsection”“”)”}”(hhh]”(h Œtitle”“”)”}”(hŒ!Arm Fixed Virtual Platforms (FVP)”h]”hŒ!Arm Fixed Virtual Platforms (FVP)”…””}”(hj•h!j“hhhANhCNubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j‘h!jŽhhhAŒS/home/test/workspace/code/optee_3.16/trusted-firmware-a/docs/plat/arm/fvp/index.rst”hCKubj)”}”(hhh]”(j’)”}”(hŒ$Fixed Virtual Platform (FVP) Support”h]”hŒ$Fixed Virtual Platform (FVP) Support”…””}”(hj§h!j¥hhhANhCNubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j‘h!j¢hhhAj¡hCKubh Œ paragraph”“”)”}”(hŒ–This section lists the supported Arm |FVP| platforms. Please refer to the FVP documentation for a detailed description of the model parameter options.”h]”(hŒ%This section lists the supported Arm ”…””}”(hŒ%This section lists the supported Arm ”h!jµhhhANhCNubh)”}”(hj‚h]”h)”}”(hj‚h]”hŒFVP”…””}”(hhh!jÁubah"}”(h$]”h&]”(h(jŽjeh+]”h-]”h/]”uh1hhANhCNh!j¾ubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”jŽŒreftype”jœŒrefexplicit”‰Œrefwarn”ˆŒ reftarget”jŸuh1hhAhBhCKh!jµhhubhŒl platforms. Please refer to the FVP documentation for a detailed description of the model parameter options.”…””}”(hŒl platforms. Please refer to the FVP documentation for a detailed description of the model parameter options.”h!jµhhhANhCNubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j³hAj¡hCKh!j¢hhubj´)”}”(hŒ¼The latest version of the AArch64 build of TF-A has been tested on the following Arm FVPs without shifted affinities, and that do not support threaded CPU cores (64-bit host machine only).”h]”hŒ¼The latest version of the AArch64 build of TF-A has been tested on the following Arm FVPs without shifted affinities, and that do not support threaded CPU cores (64-bit host machine only).”…””}”(hjçh!jåhhhANhCNubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j³hAj¡hCK h!j¢hhubh Œnote”“”)”}”(hŒHThe FVP models used are Version 11.16 Build 16, unless otherwise stated.”h]”j´)”}”(hj÷h]”hŒHThe FVP models used are Version 11.16 Build 16, unless otherwise stated.”…””}”(hj÷h!jùubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j³hAj¡hCKh!jõubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jóh!j¢hhhAj¡hCNubh Œbullet_list”“”)”}”(hhh]”(h Œ list_item”“”)”}”(hŒ``Foundation_Platform``”h]”j´)”}”(hjh]”h Œliteral”“”)”}”(hjh]”hŒFoundation_Platform”…””}”(hhh!jubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j³hAj¡hCKh!jubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jhhhAj¡hCNubj)”}”(hŒ/``FVP_Base_AEMv8A-AEMv8A-AEMv8A-AEMv8A-CCN502``”h]”j´)”}”(hj7h]”j)”}”(hj7h]”hŒ+FVP_Base_AEMv8A-AEMv8A-AEMv8A-AEMv8A-CCN502”…””}”(hhh!j<ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!j9ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j³hAj¡hCKh!j5ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jhhhAj¡hCNubj)”}”(hŒJ``FVP_Base_AEMv8A-AEMv8A`` (For certain configurations also uses 11.14/21)”h]”j´)”}”(hjWh]”(j)”}”(hŒ``FVP_Base_AEMv8A-AEMv8A``”h]”hŒFVP_Base_AEMv8A-AEMv8A”…””}”(hhh!j\ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jYubhŒ0 (For certain configurations also uses 11.14/21)”…””}”(hŒ0 (For certain configurations also uses 11.14/21)”h!jYubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j³hAj¡hCKh!jUubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jhhhAj¡hCNubj)”}”(hŒ``FVP_Base_AEMv8A-GIC600AE``”h]”j´)”}”(hj}h]”j)”}”(hj}h]”hŒFVP_Base_AEMv8A-GIC600AE”…””}”(hhh!j‚ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j³hAj¡hCKh!j{ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jhhhAj¡hCNubj)”}”(hŒJ``FVP_Base_AEMvA`` (For certain configurations also uses 0.0/6684)”h]”j´)”}”(hjh]”(j)”}”(hŒ``FVP_Base_AEMvA``”h]”hŒFVP_Base_AEMvA”…””}”(hhh!j¢ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jŸubhŒ8 (For certain configurations also uses 0.0/6684)”…””}”(hŒ8 (For certain configurations also uses 0.0/6684)”h!jŸubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j³hAj¡hCKh!j›ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jhhhAj¡hCNubj)”}”(hŒ-``FVP_Base_Cortex-A32x4`` (Version 11.12/38)”h]”j´)”}”(hjÃh]”(j)”}”(hŒ``FVP_Base_Cortex-A32x4``”h]”hŒFVP_Base_Cortex-A32x4”…””}”(hhh!jÈubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jÅubhŒ (Version 11.12/38)”…””}”(hŒ (Version 11.12/38)”h!jÅubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j³hAj¡hCKh!jÁubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jhhhAj¡hCNubj)”}”(hŒ``FVP_Base_Cortex-A35x4``”h]”j´)”}”(hjéh]”j)”}”(hjéh]”hŒFVP_Base_Cortex-A35x4”…””}”(hhh!jîubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jëubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j³hAj¡hCKh!jçubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jhhhAj¡hCNubj)”}”(hŒ``FVP_Base_Cortex-A53x4``”h]”j´)”}”(hj h]”j)”}”(hj h]”hŒFVP_Base_Cortex-A53x4”…””}”(hhh!j ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!j ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j³hAj¡hCKh!j ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jhhhAj¡hCNubj)”}”(hŒ``FVP_Base_Cortex-A55x4``”h]”j´)”}”(hj) h]”j)”}”(hj) h]”hŒFVP_Base_Cortex-A55x4”…””}”(hhh!j. ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!j+ ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j³hAj¡hCKh!j' ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jhhhAj¡hCNubj)”}”(hŒ&``FVP_Base_Cortex-A55x4+Cortex-A75x4``”h]”j´)”}”(hjI h]”j)”}”(hjI h]”hŒ"FVP_Base_Cortex-A55x4+Cortex-A75x4”…””}”(hhh!jN ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jK ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j³hAj¡hCKh!jG ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jhhhAj¡hCNubj)”}”(hŒ``FVP_Base_Cortex-A57x1-A53x1``”h]”j´)”}”(hji h]”j)”}”(hji h]”hŒFVP_Base_Cortex-A57x1-A53x1”…””}”(hhh!jn ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jk ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j³hAj¡hCKh!jg ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jhhhAj¡hCNubj)”}”(hŒ``FVP_Base_Cortex-A57x2-A53x4``”h]”j´)”}”(hj‰ h]”j)”}”(hj‰ h]”hŒFVP_Base_Cortex-A57x2-A53x4”…””}”(hhh!jŽ ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!j‹ ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j³hAj¡hCKh!j‡ ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jhhhAj¡hCNubj)”}”(hŒ``FVP_Base_Cortex-A57x4-A53x4``”h]”j´)”}”(hj© h]”j)”}”(hj© h]”hŒFVP_Base_Cortex-A57x4-A53x4”…””}”(hhh!j® ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!j« ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j³hAj¡hCKh!j§ ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jhhhAj¡hCNubj)”}”(hŒ``FVP_Base_Cortex-A57x4``”h]”j´)”}”(hjÉ h]”j)”}”(hjÉ h]”hŒFVP_Base_Cortex-A57x4”…””}”(hhh!jÎ ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jË ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j³hAj¡hCKh!jÇ ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jhhhAj¡hCNubj)”}”(hŒ``FVP_Base_Cortex-A65AEx8``”h]”j´)”}”(hjé h]”j)”}”(hjé h]”hŒFVP_Base_Cortex-A65AEx8”…””}”(hhh!jî ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jë ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j³hAj¡hCKh!jç ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jhhhAj¡hCNubj)”}”(hŒ``FVP_Base_Cortex-A65x4``”h]”j´)”}”(hj h]”j)”}”(hj h]”hŒFVP_Base_Cortex-A65x4”…””}”(hhh!jubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j³hAj¡hCK h!jubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jhhhAj¡hCNubj)”}”(hŒ``FVP_Base_Cortex-A710x4``”h]”j´)”}”(hj)h]”j)”}”(hj)h]”hŒFVP_Base_Cortex-A710x4”…””}”(hhh!j.ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!j+ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j³hAj¡hCK!h!j'ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jhhhAj¡hCNubj)”}”(hŒ``FVP_Base_Cortex-A72x4-A53x4``”h]”j´)”}”(hjIh]”j)”}”(hjIh]”hŒFVP_Base_Cortex-A72x4-A53x4”…””}”(hhh!jNubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jKubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j³hAj¡hCK"h!jGubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jhhhAj¡hCNubj)”}”(hŒ``FVP_Base_Cortex-A72x4``”h]”j´)”}”(hjih]”j)”}”(hjih]”hŒFVP_Base_Cortex-A72x4”…””}”(hhh!jnubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jkubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j³hAj¡hCK#h!jgubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jhhhAj¡hCNubj)”}”(hŒ``FVP_Base_Cortex-A73x4-A53x4``”h]”j´)”}”(hj‰h]”j)”}”(hj‰h]”hŒFVP_Base_Cortex-A73x4-A53x4”…””}”(hhh!jŽubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!j‹ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j³hAj¡hCK$h!j‡ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jhhhAj¡hCNubj)”}”(hŒ``FVP_Base_Cortex-A73x4``”h]”j´)”}”(hj©h]”j)”}”(hj©h]”hŒFVP_Base_Cortex-A73x4”…””}”(hhh!j®ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!j«ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j³hAj¡hCK%h!j§ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jhhhAj¡hCNubj)”}”(hŒ``FVP_Base_Cortex-A75x4``”h]”j´)”}”(hjÉh]”j)”}”(hjÉh]”hŒFVP_Base_Cortex-A75x4”…””}”(hhh!jÎubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jËubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j³hAj¡hCK&h!jÇubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jhhhAj¡hCNubj)”}”(hŒ``FVP_Base_Cortex-A76AEx4``”h]”j´)”}”(hjéh]”j)”}”(hjéh]”hŒFVP_Base_Cortex-A76AEx4”…””}”(hhh!jîubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jëubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j³hAj¡hCK'h!jçubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jhhhAj¡hCNubj)”}”(hŒ``FVP_Base_Cortex-A76AEx8``”h]”j´)”}”(hj h]”j)”}”(hj h]”hŒFVP_Base_Cortex-A76AEx8”…””}”(hhh!jubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j³hAj¡hCK(h!jubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jhhhAj¡hCNubj)”}”(hŒ``FVP_Base_Cortex-A76x4``”h]”j´)”}”(hj)h]”j)”}”(hj)h]”hŒFVP_Base_Cortex-A76x4”…””}”(hhh!j.ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!j+ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j³hAj¡hCK)h!j'ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jhhhAj¡hCNubj)”}”(hŒ``FVP_Base_Cortex-A77x4``”h]”j´)”}”(hjIh]”j)”}”(hjIh]”hŒFVP_Base_Cortex-A77x4”…””}”(hhh!jNubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jKubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j³hAj¡hCK*h!jGubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jhhhAj¡hCNubj)”}”(hŒ``FVP_Base_Cortex-A78x4``”h]”j´)”}”(hjih]”j)”}”(hjih]”hŒFVP_Base_Cortex-A78x4”…””}”(hhh!jnubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jkubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j³hAj¡hCK+h!jgubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jhhhAj¡hCNubj)”}”(hŒ``FVP_Base_Neoverse-E1x1``”h]”j´)”}”(hj‰h]”j)”}”(hj‰h]”hŒFVP_Base_Neoverse-E1x1”…””}”(hhh!jŽubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!j‹ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j³hAj¡hCK,h!j‡ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jhhhAj¡hCNubj)”}”(hŒ``FVP_Base_Neoverse-E1x2``”h]”j´)”}”(hj©h]”j)”}”(hj©h]”hŒFVP_Base_Neoverse-E1x2”…””}”(hhh!j®ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!j«ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j³hAj¡hCK-h!j§ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jhhhAj¡hCNubj)”}”(hŒ``FVP_Base_Neoverse-E1x4``”h]”j´)”}”(hjÉh]”j)”}”(hjÉh]”hŒFVP_Base_Neoverse-E1x4”…””}”(hhh!jÎubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jËubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j³hAj¡hCK.h!jÇubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jhhhAj¡hCNubj)”}”(hŒ``FVP_Base_Neoverse-N1x4``”h]”j´)”}”(hjéh]”j)”}”(hjéh]”hŒFVP_Base_Neoverse-N1x4”…””}”(hhh!jîubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jëubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j³hAj¡hCK/h!jçubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jhhhAj¡hCNubj)”}”(hŒ3``FVP_Base_Neoverse-N2x4`` (Version 11.12 build 38)”h]”j´)”}”(hj h]”(j)”}”(hŒ``FVP_Base_Neoverse-N2x4``”h]”hŒFVP_Base_Neoverse-N2x4”…””}”(hhh!jubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jubhŒ (Version 11.12 build 38)”…””}”(hŒ (Version 11.12 build 38)”h!jubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j³hAj¡hCK0h!jubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jhhhAj¡hCNubj)”}”(hŒ``FVP_Base_Neoverse-V1x4``”h]”j´)”}”(hj/h]”j)”}”(hj/h]”hŒFVP_Base_Neoverse-V1x4”…””}”(hhh!j4ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!j1ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j³hAj¡hCK1h!j-ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jhhhAj¡hCNubj)”}”(hŒJ``FVP_Base_RevC-2xAEMvA`` (For certain configurations also uses 0.0/6557)”h]”j´)”}”(hjOh]”(j)”}”(hŒ``FVP_Base_RevC-2xAEMvA``”h]”hŒFVP_Base_RevC-2xAEMvA”…””}”(hhh!jTubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jQubhŒ1 (For certain configurations also uses 0.0/6557)”…””}”(hŒ1 (For certain configurations also uses 0.0/6557)”h!jQubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j³hAj¡hCK2h!jMubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jhhhAj¡hCNubj)”}”(hŒ-``FVP_CSS_SGI-575`` (Version 11.15/26)”h]”j´)”}”(hjuh]”(j)”}”(hŒ``FVP_CSS_SGI-575``”h]”hŒFVP_CSS_SGI-575”…””}”(hhh!jzubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jwubhŒ (Version 11.15/26)”…””}”(hŒ (Version 11.15/26)”h!jwubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j³hAj¡hCK3h!jsubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jhhhAj¡hCNubj)”}”(hŒ,``FVP_Morello`` (Version 0.11/19)”h]”j´)”}”(hj›h]”(j)”}”(hŒ``FVP_Morello``”h]”hŒFVP_Morello”…””}”(hhh!j ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jubhŒ (Version 0.11/19)”…””}”(hŒ (Version 0.11/19)”h!jubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j³hAj¡hCK4h!j™ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jhhhAj¡hCNubj)”}”(hŒ-``FVP_RD_E1_edge`` (Version 11.15/26)”h]”j´)”}”(hjÁh]”(j)”}”(hŒ``FVP_RD_E1_edge``”h]”hŒFVP_RD_E1_edge”…””}”(hhh!jÆubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jÃubhŒ (Version 11.15/26)”…””}”(hŒ (Version 11.15/26)”h!jÃubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j³hAj¡hCK5h!j¿ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jhhhAj¡hCNubj)”}”(hŒ-``FVP_RD_N1_edge_dual`` (Version 11.15/26)”h]”j´)”}”(hjçh]”(j)”}”(hŒ``FVP_RD_N1_edge_dual``”h]”hŒFVP_RD_N1_edge_dual”…””}”(hhh!jìubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jéubhŒ (Version 11.15/26)”…””}”(hŒ (Version 11.15/26)”h!jéubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j³hAj¡hCK6h!jåubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jhhhAj¡hCNubj)”}”(hŒ-``FVP_RD_N1_edge`` (Version 11.15/26)”h]”j´)”}”(hj h]”(j)”}”(hŒ``FVP_RD_N1_edge``”h]”hŒFVP_RD_N1_edge”…””}”(hhh!jubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jubhŒ (Version 11.15/26)”…””}”(hŒ (Version 11.15/26)”h!jubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j³hAj¡hCK7h!jubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jhhhAj¡hCNubj)”}”(hŒ-``FVP_RD_V1`` (Version 11.15/26)”h]”j´)”}”(hj3h]”(j)”}”(hŒ ``FVP_RD_V1``”h]”hŒ FVP_RD_V1”…””}”(hhh!j8ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!j5ubhŒ (Version 11.15/26)”…””}”(hŒ (Version 11.15/26)”h!j5ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j³hAj¡hCK8h!j1ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jhhhAj¡hCNubj)”}”(hŒ``FVP_TC0``”h]”j´)”}”(hjYh]”j)”}”(hjYh]”hŒFVP_TC0”…””}”(hhh!j^ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!j[ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j³hAj¡hCK9h!jWubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jhhhAj¡hCNubj)”}”(hŒ``FVP_TC1`` ”h]”j´)”}”(hŒ``FVP_TC1``”h]”j)”}”(hj}h]”hŒFVP_TC1”…””}”(hhh!jubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!j{ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j³hAj¡hCK:h!jwubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jhhhAj¡hCNubeh"}”(h$]”h&]”h+]”h-]”h/]”Œbullet”Œ-”uh1jhAj¡hCKh!j¢hhubj´)”}”(hŒ¼The latest version of the AArch32 build of TF-A has been tested on the following Arm FVPs without shifted affinities, and that do not support threaded CPU cores (64-bit host machine only).”h]”hŒ¼The latest version of the AArch32 build of TF-A has been tested on the following Arm FVPs without shifted affinities, and that do not support threaded CPU cores (64-bit host machine only).”…””}”(hj¢h!j hhhANhCNubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j³hAj¡hCK/`` can be used.”h]”(hŒÍLinaro provides a ramdisk image in prebuilt FVP configurations and full file systems that can be downloaded separately. To run an FVP with a virtio file system image an additional FVP configuration option ”…””}”(hŒÍLinaro provides a ramdisk image in prebuilt FVP configurations and full file systems that can be downloaded separately. To run an FVP with a virtio file system image an additional FVP configuration option ”h!jÝubj)”}”(hŒE``-C bp.virtioblockdevice.image_path="/``”h]”hŒA-C bp.virtioblockdevice.image_path="/”…””}”(hhh!jæubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jÝubhŒ can be used.”…””}”(hŒ can be used.”h!jÝubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j³hAj¡hCKRh!jÙubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jóh!j¢hhhAj¡hCNubjô)”}”(hŒŽThe software will not work on Version 1.0 of the Foundation FVP. The commands below would report an ``unhandled argument`` error in this case.”h]”j´)”}”(hŒŽThe software will not work on Version 1.0 of the Foundation FVP. The commands below would report an ``unhandled argument`` error in this case.”h]”(hŒdThe software will not work on Version 1.0 of the Foundation FVP. The commands below would report an ”…””}”(hŒdThe software will not work on Version 1.0 of the Foundation FVP. The commands below would report an ”h!j ubj)”}”(hŒ``unhandled argument``”h]”hŒunhandled argument”…””}”(hhh!jubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!j ubhŒ error in this case.”…””}”(hŒ error in this case.”h!j ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j³hAj¡hCKYh!jubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jóh!j¢hhhAj¡hCNubjô)”}”(hŒ˜FVPs can be launched with ``--cadi-server`` option such that a CADI-compliant debugger (for example, Arm DS-5) can connect to and control its execution.”h]”j´)”}”(hŒ˜FVPs can be launched with ``--cadi-server`` option such that a CADI-compliant debugger (for example, Arm DS-5) can connect to and control its execution.”h]”(hŒFVPs can be launched with ”…””}”(hŒFVPs can be launched with ”h!j5ubj)”}”(hŒ``--cadi-server``”h]”hŒ --cadi-server”…””}”(hhh!j>ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!j5ubhŒm option such that a CADI-compliant debugger (for example, Arm DS-5) can connect to and control its execution.”…””}”(hŒm option such that a CADI-compliant debugger (for example, Arm DS-5) can connect to and control its execution.”h!j5ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j³hAj¡hCK]h!j1ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jóh!j¢hhhAj¡hCNubh Œwarning”“”)”}”(hX$Since FVP model Version 11.0 Build 11.0.34 and Version 8.5 Build 0.8.5202 the internal synchronisation timings changed compared to older versions of the models. The models can be launched with ``-Q 100`` option if they are required to match the run time characteristics of the older versions.”h]”j´)”}”(hX$Since FVP model Version 11.0 Build 11.0.34 and Version 8.5 Build 0.8.5202 the internal synchronisation timings changed compared to older versions of the models. The models can be launched with ``-Q 100`` option if they are required to match the run time characteristics of the older versions.”h]”(hŒÁSince FVP model Version 11.0 Build 11.0.34 and Version 8.5 Build 0.8.5202 the internal synchronisation timings changed compared to older versions of the models. The models can be launched with ”…””}”(hŒÁSince FVP model Version 11.0 Build 11.0.34 and Version 8.5 Build 0.8.5202 the internal synchronisation timings changed compared to older versions of the models. The models can be launched with ”h!jcubj)”}”(hŒ ``-Q 100``”h]”hŒ-Q 100”…””}”(hhh!jlubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jcubhŒY option if they are required to match the run time characteristics of the older versions.”…””}”(hŒY option if they are required to match the run time characteristics of the older versions.”h!jcubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j³hAj¡hCKbh!j_ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j]h!j¢hhhAj¡hCNubj´)”}”(hŒFAll the above platforms have been tested with `Linaro Release 20.01`_.”h]”(hŒ.All the above platforms have been tested with ”…””}”(hŒ.All the above platforms have been tested with ”h!j‹hhhANhCNubjv)”}”(hŒ`Linaro Release 20.01`_”h]”hŒLinaro Release 20.01”…””}”(hŒLinaro Release 20.01”h!j”ubah"}”(h$]”h&]”h+]”h-]”h/]”Œname”ŒLinaro Release 20.01”jˆŒ6http://releases.linaro.org/members/arm/platforms/20.01”uh1juh!j‹jŠKubhŒ.”…””}”(hj¦h!j‹hhhANhCNubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j³hAj¡hCKgh!j¢hhubh Œtarget”“”)”}”(hŒ#.. _build_options_arm_fvp_platform:”h]”h"}”(h$]”h&]”h+]”h-]”h/]”Œrefid”Œbuild-options-arm-fvp-platform”uh1j°hCK®h!j¢hhhAj¡ubeh"}”(h$]”Œ"fixed-virtual-platform-fvp-support”ah&]”h+]”Œ$fixed virtual platform (fvp) support”ah-]”h/]”uh1jŒh!jŽhhhAj¡hCKubj)”}”(hhh]”(j’)”}”(hŒ'Arm FVP Platform Specific Build Options”h]”hŒ'Arm FVP Platform Specific Build Options”…””}”(hjËh!jÉhhhANhCNubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j‘h!jÆhhhAj¡hCKlubj )”}”(hhh]”(j)”}”(hŒÛ``FVP_CLUSTER_COUNT`` : Configures the cluster count to be used to build the topology tree within TF-A. By default TF-A is configured for dual cluster topology and this option can be used to override the default value. ”h]”j´)”}”(hŒÚ``FVP_CLUSTER_COUNT`` : Configures the cluster count to be used to build the topology tree within TF-A. By default TF-A is configured for dual cluster topology and this option can be used to override the default value.”h]”(j)”}”(hŒ``FVP_CLUSTER_COUNT``”h]”hŒFVP_CLUSTER_COUNT”…””}”(hhh!jâubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jÞubhŒÅ : Configures the cluster count to be used to build the topology tree within TF-A. By default TF-A is configured for dual cluster topology and this option can be used to override the default value.”…””}”(hŒÅ : Configures the cluster count to be used to build the topology tree within TF-A. By default TF-A is configured for dual cluster topology and this option can be used to override the default value.”h!jÞubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j³hAj¡hCKnh!jÚubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!j×hhhAj¡hCNubj)”}”(hX…``FVP_INTERCONNECT_DRIVER``: Selects the interconnect driver to be built. The default interconnect driver depends on the value of ``FVP_CLUSTER_COUNT`` as explained in the options below: - ``FVP_CCI`` : The CCI driver is selected. This is the default if 0 < ``FVP_CLUSTER_COUNT`` <= 2. - ``FVP_CCN`` : The CCN driver is selected. This is the default if ``FVP_CLUSTER_COUNT`` > 2. ”h]”(j´)”}”(hŒº``FVP_INTERCONNECT_DRIVER``: Selects the interconnect driver to be built. The default interconnect driver depends on the value of ``FVP_CLUSTER_COUNT`` as explained in the options below:”h]”(j)”}”(hŒ``FVP_INTERCONNECT_DRIVER``”h]”hŒFVP_INTERCONNECT_DRIVER”…””}”(hhh!j ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jubhŒg: Selects the interconnect driver to be built. The default interconnect driver depends on the value of ”…””}”(hŒg: Selects the interconnect driver to be built. The default interconnect driver depends on the value of ”h!jubj)”}”(hŒ``FVP_CLUSTER_COUNT``”h]”hŒFVP_CLUSTER_COUNT”…””}”(hhh!jubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jubhŒ# as explained in the options below:”…””}”(hŒ# as explained in the options below:”h!jubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j³hAj¡hCKrh!jubj )”}”(hhh]”(j)”}”(hŒ```FVP_CCI`` : The CCI driver is selected. This is the default if 0 < ``FVP_CLUSTER_COUNT`` <= 2.”h]”j´)”}”(hŒ```FVP_CCI`` : The CCI driver is selected. This is the default if 0 < ``FVP_CLUSTER_COUNT`` <= 2.”h]”(j)”}”(hŒ``FVP_CCI``”h]”hŒFVP_CCI”…””}”(hhh!j@ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!j<ubhŒ: : The CCI driver is selected. This is the default if 0 < ”…””}”(hŒ: : The CCI driver is selected. This is the default if 0 < ”h!j<ubj)”}”(hŒ``FVP_CLUSTER_COUNT``”h]”hŒFVP_CLUSTER_COUNT”…””}”(hhh!jSubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!j<ubhŒ <= 2.”…””}”(hŒ <= 2.”h!j<ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j³hAj¡hCKvh!j8ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!j5ubj)”}”(hŒ\``FVP_CCN`` : The CCN driver is selected. This is the default if ``FVP_CLUSTER_COUNT`` > 2. ”h]”j´)”}”(hŒ[``FVP_CCN`` : The CCN driver is selected. This is the default if ``FVP_CLUSTER_COUNT`` > 2.”h]”(j)”}”(hŒ``FVP_CCN``”h]”hŒFVP_CCN”…””}”(hhh!jzubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jvubhŒ6 : The CCN driver is selected. This is the default if ”…””}”(hŒ6 : The CCN driver is selected. This is the default if ”h!jvubj)”}”(hŒ``FVP_CLUSTER_COUNT``”h]”hŒFVP_CLUSTER_COUNT”…””}”(hhh!jubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jvubhŒ > 2.”…””}”(hŒ > 2.”h!jvubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j³hAj¡hCKxh!jrubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!j5ubeh"}”(h$]”h&]”h+]”h-]”h/]”jžjŸuh1jhAj¡hCKvh!jubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!j×hhhANhCNubj)”}”(hŒ{``FVP_MAX_CPUS_PER_CLUSTER``: Sets the maximum number of CPUs implemented in a single cluster. This option defaults to 4. ”h]”j´)”}”(hŒz``FVP_MAX_CPUS_PER_CLUSTER``: Sets the maximum number of CPUs implemented in a single cluster. This option defaults to 4.”h]”(j)”}”(hŒ``FVP_MAX_CPUS_PER_CLUSTER``”h]”hŒFVP_MAX_CPUS_PER_CLUSTER”…””}”(hhh!jÀubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!j¼ubhŒ^: Sets the maximum number of CPUs implemented in a single cluster. This option defaults to 4.”…””}”(hŒ^: Sets the maximum number of CPUs implemented in a single cluster. This option defaults to 4.”h!j¼ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j³hAj¡hCK{h!j¸ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!j×hhhAj¡hCNubj)”}”(hŒÍ``FVP_MAX_PE_PER_CPU``: Sets the maximum number of PEs implemented on any CPU in the system. This option defaults to 1. Note that the build option ``ARM_PLAT_MT`` doesn't have any effect on FVP platforms. ”h]”j´)”}”(hŒÌ``FVP_MAX_PE_PER_CPU``: Sets the maximum number of PEs implemented on any CPU in the system. This option defaults to 1. Note that the build option ``ARM_PLAT_MT`` doesn't have any effect on FVP platforms.”h]”(j)”}”(hŒ``FVP_MAX_PE_PER_CPU``”h]”hŒFVP_MAX_PE_PER_CPU”…””}”(hhh!jçubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jãubhŒ}: Sets the maximum number of PEs implemented on any CPU in the system. This option defaults to 1. Note that the build option ”…””}”(hŒ}: Sets the maximum number of PEs implemented on any CPU in the system. This option defaults to 1. Note that the build option ”h!jãubj)”}”(hŒ``ARM_PLAT_MT``”h]”hŒARM_PLAT_MT”…””}”(hhh!júubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jãubhŒ, doesnâ€™t have any effect on FVP platforms.”…””}”(hŒ* doesn't have any effect on FVP platforms.”h!jãubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j³hAj¡hCK~h!jßubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!j×hhhAj¡hCNubj)”}”(hŒÂ``FVP_USE_GIC_DRIVER`` : Selects the GIC driver to be built. Options: - ``FVP_GICV2`` : The GICv2 only driver is selected - ``FVP_GICV3`` : The GICv3 only driver is selected (default option) ”h]”(j´)”}”(hŒE``FVP_USE_GIC_DRIVER`` : Selects the GIC driver to be built. Options:”h]”(j)”}”(hŒ``FVP_USE_GIC_DRIVER``”h]”hŒFVP_USE_GIC_DRIVER”…””}”(hhh!j!ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jubhŒ/ : Selects the GIC driver to be built. Options:”…””}”(hŒ/ : Selects the GIC driver to be built. Options:”h!jubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j³hAj¡hCK‚h!jubj )”}”(hhh]”(j)”}”(hŒ1``FVP_GICV2`` : The GICv2 only driver is selected”h]”j´)”}”(hj?h]”(j)”}”(hŒ ``FVP_GICV2``”h]”hŒ FVP_GICV2”…””}”(hhh!jDubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jAubhŒ$ : The GICv2 only driver is selected”…””}”(hŒ$ : The GICv2 only driver is selected”h!jAubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j³hAj¡hCK„h!j=ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!j:ubj)”}”(hŒC``FVP_GICV3`` : The GICv3 only driver is selected (default option) ”h]”j´)”}”(hŒB``FVP_GICV3`` : The GICv3 only driver is selected (default option)”h]”(j)”}”(hŒ ``FVP_GICV3``”h]”hŒ FVP_GICV3”…””}”(hhh!jkubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jgubhŒ5 : The GICv3 only driver is selected (default option)”…””}”(hŒ5 : The GICv3 only driver is selected (default option)”h!jgubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j³hAj¡hCK…h!jcubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!j:ubeh"}”(h$]”h&]”h+]”h-]”h/]”jžjŸuh1jhAj¡hCK„h!jubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!j×hhhANhCNubj)”}”(hX¯``FVP_HW_CONFIG_DTS`` : Specify the path to the DTS file to be compiled to DTB and packaged in FIP as the HW_CONFIG. See :ref:`Firmware Design` for details on HW_CONFIG. By default, this is initialized to a sensible DTS file in ``fdts/`` folder depending on other build options. But some cases, like shifted affinity format for MPIDR, cannot be detected at build time and this option is needed to specify the appropriate DTS file. ”h]”j´)”}”(hX®``FVP_HW_CONFIG_DTS`` : Specify the path to the DTS file to be compiled to DTB and packaged in FIP as the HW_CONFIG. See :ref:`Firmware Design` for details on HW_CONFIG. By default, this is initialized to a sensible DTS file in ``fdts/`` folder depending on other build options. But some cases, like shifted affinity format for MPIDR, cannot be detected at build time and this option is needed to specify the appropriate DTS file.”h]”(j)”}”(hŒ``FVP_HW_CONFIG_DTS``”h]”hŒFVP_HW_CONFIG_DTS”…””}”(hhh!jžubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jšubhŒd : Specify the path to the DTS file to be compiled to DTB and packaged in FIP as the HW_CONFIG. See ”…””}”(hŒd : Specify the path to the DTS file to be compiled to DTB and packaged in FIP as the HW_CONFIG. See ”h!jšubh)”}”(hŒ:ref:`Firmware Design`”h]”h)”}”(hj³h]”hŒFirmware Design”…””}”(hhh!jµubah"}”(h$]”h&]”(h(Œstd”Œstd-ref”eh+]”h-]”h/]”uh1hh!j±ubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”j¿Œreftype”Œref”Œrefexplicit”‰Œrefwarn”ˆh?Œfirmware design”uh1hhAj¡hCK‡h!jšubhŒU for details on HW_CONFIG. By default, this is initialized to a sensible DTS file in ”…””}”(hŒU for details on HW_CONFIG. By default, this is initialized to a sensible DTS file in ”h!jšubj)”}”(hŒ ``fdts/``”h]”hŒfdts/”…””}”(hhh!jÖubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jšubhŒÁ folder depending on other build options. But some cases, like shifted affinity format for MPIDR, cannot be detected at build time and this option is needed to specify the appropriate DTS file.”…””}”(hŒÁ folder depending on other build options. But some cases, like shifted affinity format for MPIDR, cannot be detected at build time and this option is needed to specify the appropriate DTS file.”h!jšubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j³hAj¡hCK‡h!j–ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!j×hhhAj¡hCNubj)”}”(hX_``FVP_HW_CONFIG`` : Specify the path to the HW_CONFIG blob to be packaged in FIP. See :ref:`Firmware Design` for details on HW_CONFIG. This option is similar to the ``FVP_HW_CONFIG_DTS`` option, but it directly specifies the HW_CONFIG blob instead of the DTS file. This option is useful to override the default HW_CONFIG selected by the build system. ”h]”j´)”}”(hX^``FVP_HW_CONFIG`` : Specify the path to the HW_CONFIG blob to be packaged in FIP. See :ref:`Firmware Design` for details on HW_CONFIG. This option is similar to the ``FVP_HW_CONFIG_DTS`` option, but it directly specifies the HW_CONFIG blob instead of the DTS file. This option is useful to override the default HW_CONFIG selected by the build system.”h]”(j)”}”(hŒ``FVP_HW_CONFIG``”h]”hŒ FVP_HW_CONFIG”…””}”(hhh!jýubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jùubhŒE : Specify the path to the HW_CONFIG blob to be packaged in FIP. See ”…””}”(hŒE : Specify the path to the HW_CONFIG blob to be packaged in FIP. See ”h!jùubh)”}”(hŒ:ref:`Firmware Design`”h]”h)”}”(hjh]”hŒFirmware Design”…””}”(hhh!jubah"}”(h$]”h&]”(h(Œstd”Œstd-ref”eh+]”h-]”h/]”uh1hh!jubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”jŒreftype”Œref”Œrefexplicit”‰Œrefwarn”ˆh?Œfirmware design”uh1hhAj¡hCKŽh!jùubhŒ9 for details on HW_CONFIG. This option is similar to the ”…””}”(hŒ9 for details on HW_CONFIG. This option is similar to the ”h!jùubj)”}”(hŒ``FVP_HW_CONFIG_DTS``”h]”hŒFVP_HW_CONFIG_DTS”…””}”(hhh!j5ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jùubhŒ¤ option, but it directly specifies the HW_CONFIG blob instead of the DTS file. This option is useful to override the default HW_CONFIG selected by the build system.”…””}”(hŒ¤ option, but it directly specifies the HW_CONFIG blob instead of the DTS file. This option is useful to override the default HW_CONFIG selected by the build system.”h!jùubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j³hAj¡hCKŽh!jõubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!j×hhhAj¡hCNubj)”}”(hŒå``FVP_GICR_REGION_PROTECTION``: Mark the redistributor pages of inactive/fused CPU cores as read-only. The default value of this option is ``0``, which means the redistributor pages of all CPU cores are marked as read and write. ”h]”j´)”}”(hŒä``FVP_GICR_REGION_PROTECTION``: Mark the redistributor pages of inactive/fused CPU cores as read-only. The default value of this option is ``0``, which means the redistributor pages of all CPU cores are marked as read and write.”h]”(j)”}”(hŒ``FVP_GICR_REGION_PROTECTION``”h]”hŒFVP_GICR_REGION_PROTECTION”…””}”(hhh!j\ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jXubhŒm: Mark the redistributor pages of inactive/fused CPU cores as read-only. The default value of this option is ”…””}”(hŒm: Mark the redistributor pages of inactive/fused CPU cores as read-only. The default value of this option is ”h!jXubj)”}”(hŒ``0``”h]”hŒ0”…””}”(hhh!joubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jXubhŒT, which means the redistributor pages of all CPU cores are marked as read and write.”…””}”(hŒT, which means the redistributor pages of all CPU cores are marked as read and write.”h!jXubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j³hAj¡hCK”h!jTubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!j×hhhAj¡hCNubeh"}”(h$]”h&]”h+]”h-]”h/]”jžjŸuh1jhAj¡hCKnh!jÆhhubeh"}”(h$]”(Œ'arm-fvp-platform-specific-build-options”j½eh&]”h+]”(Œ'arm fvp platform specific build options”Œbuild_options_arm_fvp_platform”eh-]”h/]”uh1jŒh!jŽhhhAj¡hCKlŒexpect_referenced_by_name”}”jšj²sŒexpect_referenced_by_id”}”j½j²subj)”}”(hhh]”(j’)”}”(hŒBooting Firmware Update images”h]”hŒBooting Firmware Update images”…””•(}”(hj¦h!j¤hhhANhCNubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j‘h!j¡hhhAj¡hCKšubj´)”}”(hŒWhen Firmware Update (FWU) is enabled there are at least 2 new images that have to be loaded, the Non-Secure FWU ROM (NS-BL1U), and the FWU FIP.”h]”hŒWhen Firmware Update (FWU) is enabled there are at least 2 new images that have to be loaded, the Non-Secure FWU ROM (NS-BL1U), and the FWU FIP.”…””}”(hj´h!j²hhhANhCNubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j³hAj¡hCKœh!j¡hhubj´)”}”(hŒ.The additional fip images must be loaded with:”h]”hŒ.The additional fip images must be loaded with:”…””}”(hjÂh!jÀhhhANhCNubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j³hAj¡hCK h!j¡hhubh Œ literal_block”“”)”}”(hŒ¥--data cluster0.cpu0="/ns_bl1u.bin"@0x0beb8000 [ns_bl1u_base_address] --data cluster0.cpu0="/fwu_fip.bin"@0x08400000 [ns_bl2u_base_address]”h]”hŒ¥--data cluster0.cpu0="/ns_bl1u.bin"@0x0beb8000 [ns_bl1u_base_address] --data cluster0.cpu0="/fwu_fip.bin"@0x08400000 [ns_bl2u_base_address]”…””}”(hhh!jÐubah"}”(h$]”h&]”h+]”h-]”h/]”Œ xml:space”Œpreserve”uh1jÎhAj¡hCK¤h!j¡hhubj´)”}”(hŒŽThe address ns_bl1u_base_address is the value of NS_BL1U_BASE. In the same way, the address ns_bl2u_base_address is the value of NS_BL2U_BASE.”h]”hŒŽThe address ns_bl1u_base_address is the value of NS_BL1U_BASE. In the same way, the address ns_bl2u_base_address is the value of NS_BL2U_BASE.”…””}”(hjâh!jàhhhANhCNubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j³hAj¡hCK§h!j¡hhubeh"}”(h$]”Œbooting-firmware-update-images”ah&]”h+]”Œbooting firmware update images”ah-]”h/]”uh1jŒh!jŽhhhAj¡hCKšubj)”}”(hhh]”(j’)”}”(hŒBooting an EL3 payload”h]”hŒBooting an EL3 payload”…””}”(hjûh!jùhhhANhCNubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j‘h!jöhhhAj¡hCK¬ubj´)”}”(hXYThe EL3 payloads boot flow requires the CPU's mailbox to be cleared at reset for the secondary CPUs holding pen to work properly. Unfortunately, its reset value is undefined on the FVP platform and the FVP platform code doesn't clear it. Therefore, one must modify the way the model is normally invoked in order to clear the mailbox at start-up.”h]”hX]The EL3 payloads boot flow requires the CPUâ€™s mailbox to be cleared at reset for the secondary CPUs holding pen to work properly. Unfortunately, its reset value is undefined on the FVP platform and the FVP platform code doesnâ€™t clear it. Therefore, one must modify the way the model is normally invoked in order to clear the mailbox at start-up.”…””}”(hj h!jhhhANhCNubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j³hAj¡hCK®h!jöhhubj´)”}”(hŒeOne way to do that is to create an 8-byte file containing all zero bytes using the following command:”h]”hŒeOne way to do that is to create an 8-byte file containing all zero bytes using the following command:”…””}”(hjh!jhhhANhCNubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j³hAj¡hCK´h!jöhhubjÏ)”}”(hŒ+dd if=/dev/zero of=mailbox.dat bs=1 count=8”h]”hŒ+dd if=/dev/zero of=mailbox.dat bs=1 count=8”…””}”(hhh!j#ubah"}”(h$]”h&]”h+]”h-]”h/]”Œforce”‰Œhighlight_args”}”jÞjßŒlanguage”Œshell”uh1jÎhAj¡hCK·h!jöhhubj´)”}”(hŒvand pre-load it into the FVP memory at the mailbox address (i.e. ``0x04000000``) using the following model parameters:”h]”(hŒAand pre-load it into the FVP memory at the mailbox address (i.e. ”…””}”(hŒAand pre-load it into the FVP memory at the mailbox address (i.e. ”h!j6hhhANhCNubj)”}”(hŒ``0x04000000``”h]”hŒ 0x04000000”…””}”(hhh!j?ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!j6ubhŒ') using the following model parameters:”…””}”(hŒ') using the following model parameters:”h!j6hhhANhCNubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j³hAj¡hCK»h!jöhhubjÏ)”}”(hŒx--data cluster0.cpu0=mailbox.dat@0x04000000 [Base FVPs] --data=mailbox.dat@0x04000000 [Foundation FVP]”h]”hŒx--data cluster0.cpu0=mailbox.dat@0x04000000 [Base FVPs] --data=mailbox.dat@0x04000000 [Foundation FVP]”…””}”(hhh!jXubah"}”(h$]”h&]”h+]”h-]”h/]”jÞjßuh1jÎhAj¡hCKÀh!jöhhubj´)”}”(hŒSTo provide the model with the EL3 payload image, the following methods may be used:”h]”hŒSTo provide the model with the EL3 payload image, the following methods may be used:”…””}”(hjhh!jfhhhANhCNubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j³hAj¡hCKÃh!jöhhubh Œenumerated_list”“”)”}”(hhh]”(j)”}”(hX±If the EL3 payload is able to execute in place, it may be programmed into flash memory. On Base Cortex and AEM FVPs, the following model parameter loads it at the base address of the NOR FLASH1 (the NOR FLASH0 is already used for the FIP): :: -C bp.flashloader1.fname="/" On Foundation FVP, there is no flash loader component and the EL3 payload may be programmed anywhere in flash using method 3 below. ”h]”(j´)”}”(hŒïIf the EL3 payload is able to execute in place, it may be programmed into flash memory. On Base Cortex and AEM FVPs, the following model parameter loads it at the base address of the NOR FLASH1 (the NOR FLASH0 is already used for the FIP):”h]”hŒïIf the EL3 payload is able to execute in place, it may be programmed into flash memory. On Base Cortex and AEM FVPs, the following model parameter loads it at the base address of the NOR FLASH1 (the NOR FLASH0 is already used for the FIP):”…””}”(hjh!j}ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j³hAj¡hCKÆh!jyubjÏ)”}”(hŒ2-C bp.flashloader1.fname="/"”h]”hŒ2-C bp.flashloader1.fname="/"”…””}”(hhh!j‹ubah"}”(h$]”h&]”h+]”h-]”h/]”jÞjßuh1jÎhAj¡hCKÍh!jyubj´)”}”(hŒƒOn Foundation FVP, there is no flash loader component and the EL3 payload may be programmed anywhere in flash using method 3 below.”h]”hŒƒOn Foundation FVP, there is no flash loader component and the EL3 payload may be programmed anywhere in flash using method 3 below.”…””}”(hj›h!j™ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j³hAj¡hCKÏh!jyubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jvhhhAj¡hCNubj)”}”(hŒ²When using the ``SPIN_ON_BL1_EXIT=1`` loading method, the following DS-5 command may be used to load the EL3 payload ELF image over JTAG: :: load /el3-payload.elf ”h]”(j´)”}”(hŒ‰When using the ``SPIN_ON_BL1_EXIT=1`` loading method, the following DS-5 command may be used to load the EL3 payload ELF image over JTAG:”h]”(hŒWhen using the ”…””}”(hŒWhen using the ”h!j±ubj)”}”(hŒ``SPIN_ON_BL1_EXIT=1``”h]”hŒSPIN_ON_BL1_EXIT=1”…””}”(hhh!jºubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!j±ubhŒd loading method, the following DS-5 command may be used to load the EL3 payload ELF image over JTAG:”…””}”(hŒd loading method, the following DS-5 command may be used to load the EL3 payload ELF image over JTAG:”h!j±ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j³hAj¡hCKÒh!jubjÏ)”}”(hŒload /el3-payload.elf”h]”hŒload /el3-payload.elf”…””}”(hhh!jÓubah"}”(h$]”h&]”h+]”h-]”h/]”jÞjßuh1jÎhAj¡hCK×h!jubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jvhhhAj¡hCNubj)”}”(hX[The EL3 payload may be pre-loaded in volatile memory using the following model parameters: :: --data cluster0.cpu0="/el3-payload>"@address [Base FVPs] --data="/"@address [Foundation FVP] The address provided to the FVP must match the ``EL3_PAYLOAD_BASE`` address used when building TF-A. ”h]”(j´)”}”(hŒZThe EL3 payload may be pre-loaded in volatile memory using the following model parameters:”h]”hŒZThe EL3 payload may be pre-loaded in volatile memory using the following model parameters:”…””}”(hjíh!jëubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j³hAj¡hCKÙh!jçubjÏ)”}”(hŒŒ--data cluster0.cpu0="/el3-payload>"@address [Base FVPs] --data="/"@address [Foundation FVP]”h]”hŒŒ--data cluster0.cpu0="/el3-payload>"@address [Base FVPs] --data="/"@address [Foundation FVP]”…””}”(hhh!jùubah"}”(h$]”h&]”h+]”h-]”h/]”jÞjßuh1jÎhAj¡hCKÞh!jçubj´)”}”(hŒdThe address provided to the FVP must match the ``EL3_PAYLOAD_BASE`` address used when building TF-A.”h]”(hŒ/The address provided to the FVP must match the ”…””}”(hŒ/The address provided to the FVP must match the ”h!jubj)”}”(hŒ``EL3_PAYLOAD_BASE``”h]”hŒEL3_PAYLOAD_BASE”…””}”(hhh!jubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jubhŒ! address used when building TF-A.”…””}”(hŒ! address used when building TF-A.”h!jubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j³hAj¡hCKáh!jçubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jvhhhAj¡hCNubeh"}”(h$]”h&]”h+]”h-]”h/]”Œenumtype”Œarabic”Œprefix”hŒsuffix”j¦uh1jth!jöhhhAj¡hCKÆubeh"}”(h$]”Œbooting-an-el3-payload”ah&]”h+]”Œbooting an el3 payload”ah-]”h/]”uh1jŒh!jŽhhhAj¡hCK¬ubj)”}”(hhh]”(j’)”}”(hŒ+Booting a preloaded kernel image (Base FVP)”h]”hŒ+Booting a preloaded kernel image (Base FVP)”…””}”(hjFh!jDhhhANhCNubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j‘h!jAhhhAj¡hCKåubj´)”}”(hXThe following example uses a simplified boot flow by directly jumping from the TF-A to the Linux kernel, which will use a ramdisk as filesystem. This can be useful if both the kernel and the device tree blob (DTB) are already present in memory (like in FVP).”h]”hXThe following example uses a simplified boot flow by directly jumping from the TF-A to the Linux kernel, which will use a ramdisk as filesystem. This can be useful if both the kernel and the device tree blob (DTB) are already present in memory (like in FVP).”…””}”(hjTh!jRhhhANhCNubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j³hAj¡hCKçh!jAhhubj´)”}”(hŒŒFor example, if the kernel is loaded at ``0x80080000`` and the DTB is loaded at address ``0x82000000``, the firmware can be built like this:”h]”(hŒ(For example, if the kernel is loaded at ”…””}”(hŒ(For example, if the kernel is loaded at ”h!j`hhhANhCNubj)”}”(hŒ``0x80080000``”h]”hŒ 0x80080000”…””}”(hhh!jiubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!j`ubhŒ" and the DTB is loaded at address ”…””}”(hŒ" and the DTB is loaded at address ”h!j`hhhANhCNubj)”}”(hŒ``0x82000000``”h]”hŒ 0x82000000”…””}”(hhh!j|ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!j`ubhŒ&, the firmware can be built like this:”…””}”(hŒ&, the firmware can be built like this:”h!j`hhhANhCNubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j³hAj¡hCKìh!jAhhubjÏ)”}”(hŒÞCROSS_COMPILE=aarch64-none-elf- \ make PLAT=fvp DEBUG=1 \ RESET_TO_BL31=1 \ ARM_LINUX_KERNEL_AS_BL33=1 \ PRELOADED_BL33_BASE=0x80080000 \ ARM_PRELOADED_DTB_BASE=0x82000000 \ all fip”h]”hŒÞCROSS_COMPILE=aarch64-none-elf- \ make PLAT=fvp DEBUG=1 \ RESET_TO_BL31=1 \ ARM_LINUX_KERNEL_AS_BL33=1 \ PRELOADED_BL33_BASE=0x80080000 \ ARM_PRELOADED_DTB_BASE=0x82000000 \ all fip”…””}”(hhh!j•ubah"}”(h$]”h&]”h+]”h-]”h/]”Œforce”‰Œhighlight_args”}”jÞjßj4Œshell”uh1jÎhAj¡hCKïh!jAhhubj´)”}”(hX¹Now, it is needed to modify the DTB so that the kernel knows the address of the ramdisk. The following script generates a patched DTB from the provided one, assuming that the ramdisk is loaded at address ``0x84000000``. Note that this script assumes that the user is using a ramdisk image prepared for U-Boot, like the ones provided by Linaro. If using a ramdisk without this header,the ``0x40`` offset in ``INITRD_START`` has to be removed.”h]”(hŒÌNow, it is needed to modify the DTB so that the kernel knows the address of the ramdisk. The following script generates a patched DTB from the provided one, assuming that the ramdisk is loaded at address ”…””}”(hŒÌNow, it is needed to modify the DTB so that the kernel knows the address of the ramdisk. The following script generates a patched DTB from the provided one, assuming that the ramdisk is loaded at address ”h!j§hhhANhCNubj)”}”(hŒ``0x84000000``”h]”hŒ 0x84000000”…””}”(hhh!j°ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!j§ubhŒ©. Note that this script assumes that the user is using a ramdisk image prepared for U-Boot, like the ones provided by Linaro. If using a ramdisk without this header,the ”…””}”(hŒ©. Note that this script assumes that the user is using a ramdisk image prepared for U-Boot, like the ones provided by Linaro. If using a ramdisk without this header,the ”h!j§hhhANhCNubj)”}”(hŒ``0x40``”h]”hŒ0x40”…””}”(hhh!jÃubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!j§ubhŒ offset in ”…””}”(hŒ offset in ”h!j§hhhANhCNubj)”}”(hŒ``INITRD_START``”h]”hŒINITRD_START”…””}”(hhh!jÖubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!j§ubhŒ has to be removed.”…””}”(hŒ has to be removed.”h!j§hhhANhCNubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j³hAj¡hCKùh!jAhhubjÏ)”}”(hX‡#!/bin/bash # Path to the input DTB KERNEL_DTB=/ # Path to the output DTB PATCHED_KERNEL_DTB=/ # Base address of the ramdisk INITRD_BASE=0x84000000 # Path to the ramdisk INITRD=/ # Skip uboot header (64 bytes) INITRD_START=$(printf "0x%x" $((${INITRD_BASE} + 0x40)) ) INITRD_SIZE=$(stat -Lc %s ${INITRD}) INITRD_END=$(printf "0x%x" $((${INITRD_BASE} + ${INITRD_SIZE})) ) CHOSEN_NODE=$(echo \ "/ { \ chosen { \ linux,initrd-start = <${INITRD_START}>; \ linux,initrd-end = <${INITRD_END}>; \ }; \ };") echo $(dtc -O dts -I dtb ${KERNEL_DTB}) ${CHOSEN_NODE} | \ dtc -O dtb -o ${PATCHED_KERNEL_DTB} -”h]”hX‡#!/bin/bash # Path to the input DTB KERNEL_DTB=/ # Path to the output DTB PATCHED_KERNEL_DTB=/ # Base address of the ramdisk INITRD_BASE=0x84000000 # Path to the ramdisk INITRD=/ # Skip uboot header (64 bytes) INITRD_START=$(printf "0x%x" $((${INITRD_BASE} + 0x40)) ) INITRD_SIZE=$(stat -Lc %s ${INITRD}) INITRD_END=$(printf "0x%x" $((${INITRD_BASE} + ${INITRD_SIZE})) ) CHOSEN_NODE=$(echo \ "/ { \ chosen { \ linux,initrd-start = <${INITRD_START}>; \ linux,initrd-end = <${INITRD_END}>; \ }; \ };") echo $(dtc -O dts -I dtb ${KERNEL_DTB}) ${CHOSEN_NODE} | \ dtc -O dtb -o ${PATCHED_KERNEL_DTB} -”…””}”(hhh!jïubah"}”(h$]”h&]”h+]”h-]”h/]”Œforce”‰Œhighlight_args”}”jÞjßj4Œbash”uh1jÎhAj¡hCMh!jAhhubj´)”}”(hŒ9And the FVP binary can be run with the following command:”h]”hŒ9And the FVP binary can be run with the following command:”…””}”(hjh!jhhhANhCNubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j³hAj¡hCMh!jAhhubjÏ)”}”(hXW/FVP_Base_AEMv8A-AEMv8A \ -C pctl.startup=0.0.0.0 \ -C bp.secure_memory=1 \ -C cluster0.NUM_CORES=4 \ -C cluster1.NUM_CORES=4 \ -C cache_state_modelled=1 \ -C cluster0.cpu0.RVBAR=0x04001000 \ -C cluster0.cpu1.RVBAR=0x04001000 \ -C cluster0.cpu2.RVBAR=0x04001000 \ -C cluster0.cpu3.RVBAR=0x04001000 \ -C cluster1.cpu0.RVBAR=0x04001000 \ -C cluster1.cpu1.RVBAR=0x04001000 \ -C cluster1.cpu2.RVBAR=0x04001000 \ -C cluster1.cpu3.RVBAR=0x04001000 \ --data cluster0.cpu0="/bl31.bin"@0x04001000 \ --data cluster0.cpu0="/"@0x82000000 \ --data cluster0.cpu0="/"@0x80080000 \ --data cluster0.cpu0="/"@0x84000000”h]”hXW/FVP_Base_AEMv8A-AEMv8A \ -C pctl.startup=0.0.0.0 \ -C bp.secure_memory=1 \ -C cluster0.NUM_CORES=4 \ -C cluster1.NUM_CORES=4 \ -C cache_state_modelled=1 \ -C cluster0.cpu0.RVBAR=0x04001000 \ -C cluster0.cpu1.RVBAR=0x04001000 \ -C cluster0.cpu2.RVBAR=0x04001000 \ -C cluster0.cpu3.RVBAR=0x04001000 \ -C cluster1.cpu0.RVBAR=0x04001000 \ -C cluster1.cpu1.RVBAR=0x04001000 \ -C cluster1.cpu2.RVBAR=0x04001000 \ -C cluster1.cpu3.RVBAR=0x04001000 \ --data cluster0.cpu0="/bl31.bin"@0x04001000 \ --data cluster0.cpu0="/"@0x82000000 \ --data cluster0.cpu0="/"@0x80080000 \ --data cluster0.cpu0="/"@0x84000000”…””}”(hhh!jubah"}”(h$]”h&]”h+]”h-]”h/]”Œforce”‰Œhighlight_args”}”jÞjßj4Œshell”uh1jÎhAj¡hCMh!jAhhubj)”}”(hhh]”(j’)”}”(hŒ$Obtaining the Flattened Device Trees”h]”hŒ$Obtaining the Flattened Device Trees”…””}”(hj&h!j$hhhANhCNubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j‘h!j!hhhAj¡hCM5ubj´)”}”(hXeDepending on the FVP configuration and Linux configuration used, different FDT files are required. FDT source files for the Foundation and Base FVPs can be found in the TF-A source directory under ``fdts/``. The Foundation FVP has a subset of the Base FVP components. For example, the Foundation FVP lacks CLCD and MMC support, and has only one CPU cluster.”h]”(hŒÅDepending on the FVP configuration and Linux configuration used, different FDT files are required. FDT source files for the Foundation and Base FVPs can be found in the TF-A source directory under ”…””}”(hŒÅDepending on the FVP configuration and Linux configuration used, different FDT files are required. FDT source files for the Foundation and Base FVPs can be found in the TF-A source directory under ”h!j2hhhANhCNubj)”}”(hŒ ``fdts/``”h]”hŒfdts/”…””}”(hhh!j;ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!j2ubhŒ—. The Foundation FVP has a subset of the Base FVP components. For example, the Foundation FVP lacks CLCD and MMC support, and has only one CPU cluster.”…””}”(hŒ—. The Foundation FVP has a subset of the Base FVP components. For example, the Foundation FVP lacks CLCD and MMC support, and has only one CPU cluster.”h!j2hhhANhCNubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j³hAj¡hCM7h!j!hhubjô)”}”(hŒkIt is not recommended to use the FDTs built along the kernel because not all FDTs are available from there.”h]”j´)”}”(hŒkIt is not recommended to use the FDTs built along the kernel because not all FDTs are available from there.”h]”hŒkIt is not recommended to use the FDTs built along the kernel because not all FDTs are available from there.”…””}”(hjZh!jXubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j³hAj¡hCM>h!jTubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jóh!j!hhhAj¡hCNubj´)”}”(hX›The dynamic configuration capability is enabled in the firmware for FVPs. This means that the firmware can authenticate and load the FDT if present in FIP. A default FDT is packaged into FIP during the build based on the build configuration. This can be overridden by using the ``FVP_HW_CONFIG`` or ``FVP_HW_CONFIG_DTS`` build options (refer to :ref:`build_options_arm_fvp_platform` for details on the options).”h]”(hXThe dynamic configuration capability is enabled in the firmware for FVPs. This means that the firmware can authenticate and load the FDT if present in FIP. A default FDT is packaged into FIP during the build based on the build configuration. This can be overridden by using the ”…””}”(hXThe dynamic configuration capability is enabled in the firmware for FVPs. This means that the firmware can authenticate and load the FDT if present in FIP. A default FDT is packaged into FIP during the build based on the build configuration. This can be overridden by using the ”h!jlhhhANhCNubj)”}”(hŒ``FVP_HW_CONFIG``”h]”hŒ FVP_HW_CONFIG”…””}”(hhh!juubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jlubhŒ or ”…””}”(hŒ or ”h!jlhhhANhCNubj)”}”(hŒ``FVP_HW_CONFIG_DTS``”h]”hŒFVP_HW_CONFIG_DTS”…””}”(hhh!jˆubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jlubhŒ build options (refer to ”…””}”(hŒ build options (refer to ”h!jlhhhANhCNubh)”}”(hŒ%:ref:`build_options_arm_fvp_platform`”h]”h)”}”(hjh]”hŒbuild_options_arm_fvp_platform”…””}”(hhh!jŸubah"}”(h$]”h&]”(h(Œstd”Œstd-ref”eh+]”h-]”h/]”uh1hh!j›ubah"}”(h$]”h&]”h+]”h-]”h/]”Œrefdoc”h9Œ refdomain”j©Œreftype”Œref”Œrefexplicit”‰Œrefwarn”ˆh?Œbuild_options_arm_fvp_platform”uh1hhAj¡hCMAh!jlubhŒ for details on the options).”…””}”(hŒ for details on the options).”h!jlhhhANhCNubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j³hAj¡hCMAh!j!hhubj )”}”(hhh]”(j)”}”(hŒ™``fvp-base-gicv2-psci.dts`` For use with models such as the Cortex-A57-A53 Base FVPs without shifted affinities and with Base memory map configuration. ”h]”(j´)”}”(hŒ``fvp-base-gicv2-psci.dts``”h]”j)”}”(hjÏh]”hŒfvp-base-gicv2-psci.dts”…””}”(hhh!jÑubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jÍubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j³hAj¡hCMHh!jÉubj´)”}”(hŒ{For use with models such as the Cortex-A57-A53 Base FVPs without shifted affinities and with Base memory map configuration.”h]”hŒ{For use with models such as the Cortex-A57-A53 Base FVPs without shifted affinities and with Base memory map configuration.”…””}”(hjæh!jäubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j³hAj¡hCMJh!jÉubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jÆhhhAj¡hCNubj)”}”(hŒ¼``fvp-base-gicv2-psci-aarch32.dts`` For use with models such as the Cortex-A32 Base FVPs without shifted affinities and running Linux in AArch32 state with Base memory map configuration. ”h]”(j´)”}”(hŒ#``fvp-base-gicv2-psci-aarch32.dts``”h]”j)”}”(hjþh]”hŒfvp-base-gicv2-psci-aarch32.dts”…””}”(hhh!jubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jüubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j³hAj¡hCMMh!jøubj´)”}”(hŒ–For use with models such as the Cortex-A32 Base FVPs without shifted affinities and running Linux in AArch32 state with Base memory map configuration.”h]”hŒ–For use with models such as the Cortex-A32 Base FVPs without shifted affinities and running Linux in AArch32 state with Base memory map configuration.”…””}”(hjh!jubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j³hAj¡hCMOh!jøubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jÆhhhAj¡hCNubj)”}”(hŒ±``fvp-base-gicv3-psci.dts`` For use with models such as the Cortex-A57-A53 Base FVPs without shifted affinities and with Base memory map configuration and Linux GICv3 support. ”h]”(j´)”}”(hŒ``fvp-base-gicv3-psci.dts``”h]”j)”}”(hj-h]”hŒfvp-base-gicv3-psci.dts”…””}”(hhh!j/ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!j+ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j³hAj¡hCMSh!j'ubj´)”}”(hŒ“For use with models such as the Cortex-A57-A53 Base FVPs without shifted affinities and with Base memory map configuration and Linux GICv3 support.”h]”hŒ“For use with models such as the Cortex-A57-A53 Base FVPs without shifted affinities and with Base memory map configuration and Linux GICv3 support.”…””}”(hjDh!jBubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j³hAj¡hCMUh!j'ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jÆhhhAj¡hCNubj)”}”(hŒº``fvp-base-gicv3-psci-1t.dts`` For use with models such as the AEMv8-RevC Base FVP with shifted affinities, single threaded CPUs, Base memory map configuration and Linux GICv3 support. ”h]”(j´)”}”(hŒ``fvp-base-gicv3-psci-1t.dts``”h]”j)”}”(hj\h]”hŒfvp-base-gicv3-psci-1t.dts”…””}”(hhh!j^ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jZubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j³hAj¡hCMXh!jVubj´)”}”(hŒ™For use with models such as the AEMv8-RevC Base FVP with shifted affinities, single threaded CPUs, Base memory map configuration and Linux GICv3 support.”h]”hŒ™For use with models such as the AEMv8-RevC Base FVP with shifted affinities, single threaded CPUs, Base memory map configuration and Linux GICv3 support.”…””}”(hjsh!jqubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j³hAj¡hCMZh!jVubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jÆhhhAj¡hCNubj)”}”(hŒÏ``fvp-base-gicv3-psci-dynamiq.dts`` For use with models as the Cortex-A55-A75 Base FVPs with shifted affinities, single cluster, single threaded CPUs, Base memory map configuration and Linux GICv3 support. ”h]”(j´)”}”(hŒ#``fvp-base-gicv3-psci-dynamiq.dts``”h]”j)”}”(hj‹h]”hŒfvp-base-gicv3-psci-dynamiq.dts”…””}”(hhh!jubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!j‰ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j³hAj¡hCM]h!j…ubj´)”}”(hŒ©For use with models as the Cortex-A55-A75 Base FVPs with shifted affinities, single cluster, single threaded CPUs, Base memory map configuration and Linux GICv3 support.”h]”hŒ©For use with models as the Cortex-A55-A75 Base FVPs with shifted affinities, single cluster, single threaded CPUs, Base memory map configuration and Linux GICv3 support.”…””}”(hj¢h!j ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j³hAj¡hCM_h!j…ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jÆhhhAj¡hCNubj)”}”(hŒÔ``fvp-base-gicv3-psci-aarch32.dts`` For use with models such as the Cortex-A32 Base FVPs without shifted affinities and running Linux in AArch32 state with Base memory map configuration and Linux GICv3 support. ”h]”(j´)”}”(hŒ#``fvp-base-gicv3-psci-aarch32.dts``”h]”j)”}”(hjºh]”hŒfvp-base-gicv3-psci-aarch32.dts”…””}”(hhh!j¼ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!j¸ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j³hAj¡hCMch!j´ubj´)”}”(hŒ®For use with models such as the Cortex-A32 Base FVPs without shifted affinities and running Linux in AArch32 state with Base memory map configuration and Linux GICv3 support.”h]”hŒ®For use with models such as the Cortex-A32 Base FVPs without shifted affinities and running Linux in AArch32 state with Base memory map configuration and Linux GICv3 support.”…””}”(hjÑh!jÏubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j³hAj¡hCMeh!j´ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jÆhhhAj¡hCNubj)”}”(hŒc``fvp-foundation-gicv2-psci.dts`` For use with Foundation FVP with Base memory map configuration. ”h]”(j´)”}”(hŒ!``fvp-foundation-gicv2-psci.dts``”h]”j)”}”(hjéh]”hŒfvp-foundation-gicv2-psci.dts”…””}”(hhh!jëubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jçubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j³hAj¡hCMih!jãubj´)”}”(hŒ?For use with Foundation FVP with Base memory map configuration.”h]”hŒ?For use with Foundation FVP with Base memory map configuration.”…””}”(hjh!jþubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j³hAj¡hCMkh!jãubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jÆhhhAj¡hCNubj)”}”(hŒ†``fvp-foundation-gicv3-psci.dts`` (Default) For use with Foundation FVP with Base memory map configuration and Linux GICv3 support. ”h]”(j´)”}”(hŒ!``fvp-foundation-gicv3-psci.dts``”h]”j)”}”(hjh]”hŒfvp-foundation-gicv3-psci.dts”…””}”(hhh!jubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j³hAj¡hCMmh!jubj´)”}”(hŒa(Default) For use with Foundation FVP with Base memory map configuration and Linux GICv3 support.”h]”hŒa(Default) For use with Foundation FVP with Base memory map configuration and Linux GICv3 support.”…””}”(hj/h!j-ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j³hAj¡hCMoh!jubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jÆhhhAj¡hCNubeh"}”(h$]”h&]”h+]”h-]”h/]”jžjŸuh1jhAj¡hCMHh!j!hhubeh"}”(h$]”Œ$obtaining-the-flattened-device-trees”ah&]”h+]”Œ$obtaining the flattened device trees”ah-]”h/]”uh1jŒh!jAhhhAj¡hCM5ubj)”}”(hhh]”(j’)”}”(hŒ:Running on the Foundation FVP with reset to BL1 entrypoint”h]”hŒ:Running on the Foundation FVP with reset to BL1 entrypoint”…””}”(hjTh!jRhhhANhCNubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j‘h!jOhhhAj¡hCMtubj´)”}”(hŒzThe following ``Foundation_Platform`` parameters should be used to boot Linux with 4 CPUs using the AArch64 build of TF-A.”h]”(hŒThe following ”…””}”(hŒThe following ”h!j`hhhANhCNubj)”}”(hŒ``Foundation_Platform``”h]”hŒFoundation_Platform”…””}”(hhh!jiubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!j`ubhŒU parameters should be used to boot Linux with 4 CPUs using the AArch64 build of TF-A.”…””}”(hŒU parameters should be used to boot Linux with 4 CPUs using the AArch64 build of TF-A.”h!j`hhhANhCNubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j³hAj¡hCMvh!jOhhubjÏ)”}”(hXð/Foundation_Platform \ --cores=4 \ --arm-v8.0 \ --secure-memory \ --visualization \ --gicv3 \ --data="/"@0x0 \ --data="/"@0x08000000 \ --data="/"@0x80080000 \ --data="/"@0x84000000”h]”hXð/Foundation_Platform \ --cores=4 \ --arm-v8.0 \ --secure-memory \ --visualization \ --gicv3 \ --data="/"@0x0 \ --data="/"@0x08000000 \ --data="/"@0x80080000 \ --data="/"@0x84000000”…””}”(hhh!j‚ubah"}”(h$]”h&]”h+]”h-]”h/]”Œforce”‰Œhighlight_args”}”jÞjßj4Œshell”uh1jÎhAj¡hCMyh!jOhhubj´)”}”(hŒNotes:”h]”hŒNotes:”…””}”(hj–h!j”hhhANhCNubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j³hAj¡hCM†h!jOhhubj )”}”(hhh]”(j)”}”(hŒ.BL1 is loaded at the start of the Trusted ROM.”h]”j´)”}”(hj§h]”hŒ.BL1 is loaded at the start of the Trusted ROM.”…””}”(hj§h!j©ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j³hAj¡hCMˆh!j¥ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!j¢hhhAj¡hCNubj)”}”(hŒ@The Firmware Image Package is loaded at the start of NOR FLASH0.”h]”j´)”}”(hj¾h]”hŒ@The Firmware Image Package is loaded at the start of NOR FLASH0.”…””}”(hj¾h!jÀubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j³hAj¡hCM‰h!j¼ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!j¢hhhAj¡hCNubj)”}”(hŒ™The firmware loads the FDT packaged in FIP to the DRAM. The FDT load address is specified via the ``hw_config_addr`` property in `TB_FW_CONFIG for FVP`_.”h]”j´)”}”(hŒ™The firmware loads the FDT packaged in FIP to the DRAM. The FDT load address is specified via the ``hw_config_addr`` property in `TB_FW_CONFIG for FVP`_.”h]”(hŒbThe firmware loads the FDT packaged in FIP to the DRAM. The FDT load address is specified via the ”…””}”(hŒbThe firmware loads the FDT packaged in FIP to the DRAM. The FDT load address is specified via the ”h!j×ubj)”}”(hŒ``hw_config_addr``”h]”hŒhw_config_addr”…””}”(hhh!jàubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!j×ubhŒ property in ”…””}”(hŒ property in ”h!j×ubjv)”}”(hŒ`TB_FW_CONFIG for FVP`_”h]”hŒTB_FW_CONFIG for FVP”…””}”(hŒTB_FW_CONFIG for FVP”h!jóubah"}”(h$]”h&]”h+]”h-]”h/]”Œname”ŒTB_FW_CONFIG for FVP”jˆŒmhttps://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/tree/plat/arm/board/fvp/fdts/fvp_tb_fw_config.dts”uh1juh!j×jŠKubhŒ.”…””}”(hj¦h!j×ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j³hAj¡hCMŠh!jÓubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!j¢hhhAj¡hCNubj)”}”(hŒúThe default use-case for the Foundation FVP is to use the ``--gicv3`` option and enable the GICv3 device in the model. Note that without this option, the Foundation FVP defaults to legacy (Versatile Express) memory map which is not supported by TF-A.”h]”j´)”}”(hŒúThe default use-case for the Foundation FVP is to use the ``--gicv3`` option and enable the GICv3 device in the model. Note that without this option, the Foundation FVP defaults to legacy (Versatile Express) memory map which is not supported by TF-A.”h]”(hŒ:The default use-case for the Foundation FVP is to use the ”…””}”(hŒ:The default use-case for the Foundation FVP is to use the ”h!jubj)”}”(hŒ``--gicv3``”h]”hŒ--gicv3”…””}”(hhh!j"ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jubhŒµ option and enable the GICv3 device in the model. Note that without this option, the Foundation FVP defaults to legacy (Versatile Express) memory map which is not supported by TF-A.”…””}”(hŒµ option and enable the GICv3 device in the model. Note that without this option, the Foundation FVP defaults to legacy (Versatile Express) memory map which is not supported by TF-A.”h!jubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j³hAj¡hCMŒh!jubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!j¢hhhAj¡hCNubj)”}”(hXzIn order for TF-A to run correctly on the Foundation FVP, the architecture versions must match. The Foundation FVP defaults to the highest v8.x version it supports but the default build for TF-A is for v8.0. To avoid issues either start the Foundation FVP to use v8.0 architecture using the ``--arm-v8.0`` option, or build TF-A with an appropriate value for ``ARM_ARCH_MINOR``. ”h]”j´)”}”(hXyIn order for TF-A to run correctly on the Foundation FVP, the architecture versions must match. The Foundation FVP defaults to the highest v8.x version it supports but the default build for TF-A is for v8.0. To avoid issues either start the Foundation FVP to use v8.0 architecture using the ``--arm-v8.0`` option, or build TF-A with an appropriate value for ``ARM_ARCH_MINOR``.”h]”(hX#In order for TF-A to run correctly on the Foundation FVP, the architecture versions must match. The Foundation FVP defaults to the highest v8.x version it supports but the default build for TF-A is for v8.0. To avoid issues either start the Foundation FVP to use v8.0 architecture using the ”…””}”(hX#In order for TF-A to run correctly on the Foundation FVP, the architecture versions must match. The Foundation FVP defaults to the highest v8.x version it supports but the default build for TF-A is for v8.0. To avoid issues either start the Foundation FVP to use v8.0 architecture using the ”h!jEubj)”}”(hŒ``--arm-v8.0``”h]”hŒ --arm-v8.0”…””}”(hhh!jNubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jEubhŒ5 option, or build TF-A with an appropriate value for ”…””}”(hŒ5 option, or build TF-A with an appropriate value for ”h!jEubj)”}”(hŒ``ARM_ARCH_MINOR``”h]”hŒARM_ARCH_MINOR”…””}”(hhh!jaubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jEubhŒ.”…””}”(hj¦h!jEubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j³hAj¡hCMh!jAubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!j¢hhhAj¡hCNubeh"}”(h$]”h&]”h+]”h-]”h/]”jžjŸuh1jhAj¡hCMˆh!jOhhubeh"}”(h$]”Œ:running-on-the-foundation-fvp-with-reset-to-bl1-entrypoint”ah&]”h+]”Œ:running on the foundation fvp with reset to bl1 entrypoint”ah-]”h/]”uh1jŒh!jAhhhAj¡hCMtubj)”}”(hhh]”(j’)”}”(hŒ:Running on the AEMv8 Base FVP with reset to BL1 entrypoint”h]”hŒ:Running on the AEMv8 Base FVP with reset to BL1 entrypoint”…””}”(hj’h!jhhhANhCNubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j‘h!jhhhAj¡hCM˜ubj´)”}”(hŒ}The following ``FVP_Base_RevC-2xAEMv8A`` parameters should be used to boot Linux with 8 CPUs using the AArch64 build of TF-A.”h]”(hŒThe following ”…””}”(hŒThe following ”h!jžhhhANhCNubj)”}”(hŒ``FVP_Base_RevC-2xAEMv8A``”h]”hŒFVP_Base_RevC-2xAEMv8A”…””}”(hhh!j§ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jžubhŒU parameters should be used to boot Linux with 8 CPUs using the AArch64 build of TF-A.”…””}”(hŒU parameters should be used to boot Linux with 8 CPUs using the AArch64 build of TF-A.”h!jžhhhANhCNubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j³hAj¡hCMšh!jhhubjÏ)”}”(hX¡/FVP_Base_RevC-2xAEMv8A \ -C pctl.startup=0.0.0.0 \ -C bp.secure_memory=1 \ -C bp.tzc_400.diagnostics=1 \ -C cluster0.NUM_CORES=4 \ -C cluster1.NUM_CORES=4 \ -C cache_state_modelled=1 \ -C bp.secureflashloader.fname="/" \ -C bp.flashloader0.fname="/" \ --data cluster0.cpu0="/"@0x80080000 \ --data cluster0.cpu0="/"@0x84000000”h]”hX¡/FVP_Base_RevC-2xAEMv8A \ -C pctl.startup=0.0.0.0 \ -C bp.secure_memory=1 \ -C bp.tzc_400.diagnostics=1 \ -C cluster0.NUM_CORES=4 \ -C cluster1.NUM_CORES=4 \ -C cache_state_modelled=1 \ -C bp.secureflashloader.fname="/" \ -C bp.flashloader0.fname="/" \ --data cluster0.cpu0="/"@0x80080000 \ --data cluster0.cpu0="/"@0x84000000”…””}”(hhh!jÀubah"}”(h$]”h&]”h+]”h-]”h/]”Œforce”‰Œhighlight_args”}”jÞjßj4Œshell”uh1jÎhAj¡hCMh!jhhubjô)”}”(hŒpThe ``FVP_Base_RevC-2xAEMv8A`` has shifted affinities and requires a specific DTS for all the CPUs to be loaded.”h]”j´)”}”(hŒpThe ``FVP_Base_RevC-2xAEMv8A`` has shifted affinities and requires a specific DTS for all the CPUs to be loaded.”h]”(hŒThe ”…””}”(hŒThe ”h!jÖubj)”}”(hŒ``FVP_Base_RevC-2xAEMv8A``”h]”hŒFVP_Base_RevC-2xAEMv8A”…””}”(hhh!jßubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jÖubhŒR has shifted affinities and requires a specific DTS for all the CPUs to be loaded.”…””}”(hŒR has shifted affinities and requires a specific DTS for all the CPUs to be loaded.”h!jÖubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j³hAj¡hCM¬h!jÒubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jóh!jhhhAj¡hCNubeh"}”(h$]”Œ:running-on-the-aemv8-base-fvp-with-reset-to-bl1-entrypoint”ah&]”h+]”Œ:running on the aemv8 base fvp with reset to bl1 entrypoint”ah-]”h/]”uh1jŒh!jAhhhAj¡hCM˜ubj)”}”(hhh]”(j’)”}”(hŒDRunning on the AEMv8 Base FVP (AArch32) with reset to BL1 entrypoint”h]”hŒDRunning on the AEMv8 Base FVP (AArch32) with reset to BL1 entrypoint”…””}”(hjh!j hhhANhCNubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j‘h!jhhhAj¡hCM°ubj´)”}”(hŒ}The following ``FVP_Base_AEMv8A-AEMv8A`` parameters should be used to boot Linux with 8 CPUs using the AArch32 build of TF-A.”h]”(hŒThe following ”…””}”(hŒThe following ”h!jhhhANhCNubj)”}”(hŒ``FVP_Base_AEMv8A-AEMv8A``”h]”hŒFVP_Base_AEMv8A-AEMv8A”…””}”(hhh!j ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jubhŒU parameters should be used to boot Linux with 8 CPUs using the AArch32 build of TF-A.”…””}”(hŒU parameters should be used to boot Linux with 8 CPUs using the AArch32 build of TF-A.”h!jhhhANhCNubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j³hAj¡hCM²h!jhhubjÏ)”}”(hX‘/FVP_Base_AEMv8A-AEMv8A \ -C pctl.startup=0.0.0.0 \ -C bp.secure_memory=1 \ -C bp.tzc_400.diagnostics=1 \ -C cluster0.NUM_CORES=4 \ -C cluster1.NUM_CORES=4 \ -C cache_state_modelled=1 \ -C cluster0.cpu0.CONFIG64=0 \ -C cluster0.cpu1.CONFIG64=0 \ -C cluster0.cpu2.CONFIG64=0 \ -C cluster0.cpu3.CONFIG64=0 \ -C cluster1.cpu0.CONFIG64=0 \ -C cluster1.cpu1.CONFIG64=0 \ -C cluster1.cpu2.CONFIG64=0 \ -C cluster1.cpu3.CONFIG64=0 \ -C bp.secureflashloader.fname="/" \ -C bp.flashloader0.fname="/" \ --data cluster0.cpu0="/"@0x80080000 \ --data cluster0.cpu0="/"@0x84000000”h]”hX‘/FVP_Base_AEMv8A-AEMv8A \ -C pctl.startup=0.0.0.0 \ -C bp.secure_memory=1 \ -C bp.tzc_400.diagnostics=1 \ -C cluster0.NUM_CORES=4 \ -C cluster1.NUM_CORES=4 \ -C cache_state_modelled=1 \ -C cluster0.cpu0.CONFIG64=0 \ -C cluster0.cpu1.CONFIG64=0 \ -C cluster0.cpu2.CONFIG64=0 \ -C cluster0.cpu3.CONFIG64=0 \ -C cluster1.cpu0.CONFIG64=0 \ -C cluster1.cpu1.CONFIG64=0 \ -C cluster1.cpu2.CONFIG64=0 \ -C cluster1.cpu3.CONFIG64=0 \ -C bp.secureflashloader.fname="/" \ -C bp.flashloader0.fname="/" \ --data cluster0.cpu0="/"@0x80080000 \ --data cluster0.cpu0="/"@0x84000000”…””}”(hhh!j9ubah"}”(h$]”h&]”h+]”h-]”h/]”Œforce”‰Œhighlight_args”}”jÞjßj4Œshell”uh1jÎhAj¡hCMµh!jhhubeh"}”(h$]”ŒBrunning-on-the-aemv8-base-fvp-aarch32-with-reset-to-bl1-entrypoint”ah&]”h+]”ŒDrunning on the aemv8 base fvp (aarch32) with reset to bl1 entrypoint”ah-]”h/]”uh1jŒh!jAhhhAj¡hCM°ubj)”}”(hhh]”(j’)”}”(hŒCRunning on the Cortex-A57-A53 Base FVP with reset to BL1 entrypoint”h]”hŒCRunning on the Cortex-A57-A53 Base FVP with reset to BL1 entrypoint”…””}”(hjXh!jVhhhANhCNubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j‘h!jShhhAj¡hCMÌubj´)”}”(hŒˆThe following ``FVP_Base_Cortex-A57x4-A53x4`` model parameters should be used to boot Linux with 8 CPUs using the AArch64 build of TF-A.”h]”(hŒThe following ”…””}”(hŒThe following ”h!jdhhhANhCNubj)”}”(hŒ``FVP_Base_Cortex-A57x4-A53x4``”h]”hŒFVP_Base_Cortex-A57x4-A53x4”…””}”(hhh!jmubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jdubhŒ[ model parameters should be used to boot Linux with 8 CPUs using the AArch64 build of TF-A.”…””}”(hŒ[ model parameters should be used to boot Linux with 8 CPUs using the AArch64 build of TF-A.”h!jdhhhANhCNubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j³hAj¡hCMÎh!jShhubjÏ)”}”(hX%/FVP_Base_Cortex-A57x4-A53x4 \ -C pctl.startup=0.0.0.0 \ -C bp.secure_memory=1 \ -C bp.tzc_400.diagnostics=1 \ -C cache_state_modelled=1 \ -C bp.secureflashloader.fname="/" \ -C bp.flashloader0.fname="/" \ --data cluster0.cpu0="/"@0x80080000 \ --data cluster0.cpu0="/"@0x84000000”h]”hX%/FVP_Base_Cortex-A57x4-A53x4 \ -C pctl.startup=0.0.0.0 \ -C bp.secure_memory=1 \ -C bp.tzc_400.diagnostics=1 \ -C cache_state_modelled=1 \ -C bp.secureflashloader.fname="/" \ -C bp.flashloader0.fname="/" \ --data cluster0.cpu0="/"@0x80080000 \ --data cluster0.cpu0="/"@0x84000000”…””}”(hhh!j†ubah"}”(h$]”h&]”h+]”h-]”h/]”Œforce”‰Œhighlight_args”}”jÞjßj4Œshell”uh1jÎhAj¡hCMÑh!jShhubeh"}”(h$]”ŒCrunning-on-the-cortex-a57-a53-base-fvp-with-reset-to-bl1-entrypoint”ah&]”h+]”ŒCrunning on the cortex-a57-a53 base fvp with reset to bl1 entrypoint”ah-]”h/]”uh1jŒh!jAhhhAj¡hCMÌubj)”}”(hhh]”(j’)”}”(hŒIRunning on the Cortex-A32 Base FVP (AArch32) with reset to BL1 entrypoint”h]”hŒIRunning on the Cortex-A32 Base FVP (AArch32) with reset to BL1 entrypoint”…””}”(hj¥h!j£hhhANhCNubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j‘h!j hhhAj¡hCMÞubj´)”}”(hŒ‚The following ``FVP_Base_Cortex-A32x4`` model parameters should be used to boot Linux with 4 CPUs using the AArch32 build of TF-A.”h]”(hŒThe following ”…””}”(hŒThe following ”h!j±hhhANhCNubj)”}”(hŒ``FVP_Base_Cortex-A32x4``”h]”hŒFVP_Base_Cortex-A32x4”…””}”(hhh!jºubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!j±ubhŒ[ model parameters should be used to boot Linux with 4 CPUs using the AArch32 build of TF-A.”…””}”(hŒ[ model parameters should be used to boot Linux with 4 CPUs using the AArch32 build of TF-A.”h!j±hhhANhCNubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j³hAj¡hCMàh!j hhubjÏ)”}”(hX%/FVP_Base_Cortex-A32x4 \ -C pctl.startup=0.0.0.0 \ -C bp.secure_memory=1 \ -C bp.tzc_400.diagnostics=1 \ -C cache_state_modelled=1 \ -C bp.secureflashloader.fname="/" \ -C bp.flashloader0.fname="/" \ --data cluster0.cpu0="/"@0x80080000 \ --data cluster0.cpu0="/"@0x84000000”h]”hX%/FVP_Base_Cortex-A32x4 \ -C pctl.startup=0.0.0.0 \ -C bp.secure_memory=1 \ -C bp.tzc_400.diagnostics=1 \ -C cache_state_modelled=1 \ -C bp.secureflashloader.fname="/" \ -C bp.flashloader0.fname="/" \ --data cluster0.cpu0="/"@0x80080000 \ --data cluster0.cpu0="/"@0x84000000”…””}”(hhh!jÓubah"}”(h$]”h&]”h+]”h-]”h/]”Œforce”‰Œhighlight_args”}”jÞjßj4Œshell”uh1jÎhAj¡hCMãh!j hhubeh"}”(h$]”ŒGrunning-on-the-cortex-a32-base-fvp-aarch32-with-reset-to-bl1-entrypoint”ah&]”h+]”ŒIrunning on the cortex-a32 base fvp (aarch32) with reset to bl1 entrypoint”ah-]”h/]”uh1jŒh!jAhhhAj¡hCMÞubj)”}”(hhh]”(j’)”}”(hŒ;Running on the AEMv8 Base FVP with reset to BL31 entrypoint”h]”hŒ;Running on the AEMv8 Base FVP with reset to BL31 entrypoint”…””}”(hjòh!jðhhhANhCNubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j‘h!jíhhhAj¡hCMñubj´)”}”(hŒ}The following ``FVP_Base_RevC-2xAEMv8A`` parameters should be used to boot Linux with 8 CPUs using the AArch64 build of TF-A.”h]”(hŒThe following ”…””}”(hŒThe following ”h!jþhhhANhCNubj)”}”(hŒ``FVP_Base_RevC-2xAEMv8A``”h]”hŒFVP_Base_RevC-2xAEMv8A”…””}”(hhh!jubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jþubhŒU parameters should be used to boot Linux with 8 CPUs using the AArch64 build of TF-A.”…””}”(hŒU parameters should be used to boot Linux with 8 CPUs using the AArch64 build of TF-A.”h!jþhhhANhCNubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j³hAj¡hCMóh!jíhhubjÏ)”}”(hX!/FVP_Base_RevC-2xAEMv8A \ -C pctl.startup=0.0.0.0 \ -C bp.secure_memory=1 \ -C bp.tzc_400.diagnostics=1 \ -C cluster0.NUM_CORES=4 \ -C cluster1.NUM_CORES=4 \ -C cache_state_modelled=1 \ -C cluster0.cpu0.RVBAR=0x04010000 \ -C cluster0.cpu1.RVBAR=0x04010000 \ -C cluster0.cpu2.RVBAR=0x04010000 \ -C cluster0.cpu3.RVBAR=0x04010000 \ -C cluster1.cpu0.RVBAR=0x04010000 \ -C cluster1.cpu1.RVBAR=0x04010000 \ -C cluster1.cpu2.RVBAR=0x04010000 \ -C cluster1.cpu3.RVBAR=0x04010000 \ --data cluster0.cpu0="/"@0x04010000 \ --data cluster0.cpu0="/"@0xff000000 \ --data cluster0.cpu0="/"@0x88000000 \ --data cluster0.cpu0="/"@0x82000000 \ --data cluster0.cpu0="/"@0x80080000 \ --data cluster0.cpu0="/"@0x84000000”h]”hX!/FVP_Base_RevC-2xAEMv8A \ -C pctl.startup=0.0.0.0 \ -C bp.secure_memory=1 \ -C bp.tzc_400.diagnostics=1 \ -C cluster0.NUM_CORES=4 \ -C cluster1.NUM_CORES=4 \ -C cache_state_modelled=1 \ -C cluster0.cpu0.RVBAR=0x04010000 \ -C cluster0.cpu1.RVBAR=0x04010000 \ -C cluster0.cpu2.RVBAR=0x04010000 \ -C cluster0.cpu3.RVBAR=0x04010000 \ -C cluster1.cpu0.RVBAR=0x04010000 \ -C cluster1.cpu1.RVBAR=0x04010000 \ -C cluster1.cpu2.RVBAR=0x04010000 \ -C cluster1.cpu3.RVBAR=0x04010000 \ --data cluster0.cpu0="/"@0x04010000 \ --data cluster0.cpu0="/"@0xff000000 \ --data cluster0.cpu0="/"@0x88000000 \ --data cluster0.cpu0="/"@0x82000000 \ --data cluster0.cpu0="/"@0x80080000 \ --data cluster0.cpu0="/"@0x84000000”…””}”(hhh!j ubah"}”(h$]”h&]”h+]”h-]”h/]”Œforce”‰Œhighlight_args”}”jÞjßj4Œshell”uh1jÎhAj¡hCMöh!jíhhubj´)”}”(hŒNotes:”h]”hŒNotes:”…””}”(hj4h!j2hhhANhCNubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j³hAj¡hCMh!jíhhubj )”}”(hhh]”(j)”}”(hŒ‡Position Independent Executable (PIE) support is enabled in this config allowing BL31 to be loaded at any valid address for execution. ”h]”j´)”}”(hŒ†Position Independent Executable (PIE) support is enabled in this config allowing BL31 to be loaded at any valid address for execution.”h]”hŒ†Position Independent Executable (PIE) support is enabled in this config allowing BL31 to be loaded at any valid address for execution.”…””}”(hjIh!jGubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j³hAj¡hCMh!jCubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!j@hhhAj¡hCNubj)”}”(hX¼Since a FIP is not loaded when using BL31 as reset entrypoint, the ``--data="

"@`` parameter is needed to load the individual bootloader images in memory. BL32 image is only needed if BL31 has been built to expect a Secure-EL1 Payload. For the same reason, the FDT needs to be compiled from the DT source and loaded via the ``--data cluster0.cpu0="/"@0x82000000`` parameter. ”h]”j´)”}”(hX»Since a FIP is not loaded when using BL31 as reset entrypoint, the ``--data="

"@`` parameter is needed to load the individual bootloader images in memory. BL32 image is only needed if BL31 has been built to expect a Secure-EL1 Payload. For the same reason, the FDT needs to be compiled from the DT source and loaded via the ``--data cluster0.cpu0="/"@0x82000000`` parameter.”h]”(hŒCSince a FIP is not loaded when using BL31 as reset entrypoint, the ”…””}”(hŒCSince a FIP is not loaded when using BL31 as reset entrypoint, the ”h!j_ubj)”}”(hŒF``--data="

"@``”h]”hŒB--data="

"@”…””}”(hhh!jhubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!j_ubhŒò parameter is needed to load the individual bootloader images in memory. BL32 image is only needed if BL31 has been built to expect a Secure-EL1 Payload. For the same reason, the FDT needs to be compiled from the DT source and loaded via the ”…””}”(hŒò parameter is needed to load the individual bootloader images in memory. BL32 image is only needed if BL31 has been built to expect a Secure-EL1 Payload. For the same reason, the FDT needs to be compiled from the DT source and loaded via the ”h!j_ubj)”}”(hŒ5``--data cluster0.cpu0="/"@0x82000000``”h]”hŒ1--data cluster0.cpu0="/"@0x82000000”…””}”(hhh!j{ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!j_ubhŒ parameter.”…””}”(hŒ parameter.”h!j_ubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j³hAj¡hCMh!j[ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!j@hhhAj¡hCNubj)”}”(hŒqThe ``FVP_Base_RevC-2xAEMv8A`` has shifted affinities and requires a specific DTS for all the CPUs to be loaded. ”h]”j´)”}”(hŒpThe ``FVP_Base_RevC-2xAEMv8A`` has shifted affinities and requires a specific DTS for all the CPUs to be loaded.”h]”(hŒThe ”…””}”(hŒThe ”h!jžubj)”}”(hŒ``FVP_Base_RevC-2xAEMv8A``”h]”hŒFVP_Base_RevC-2xAEMv8A”…””}”(hhh!j§ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jžubhŒR has shifted affinities and requires a specific DTS for all the CPUs to be loaded.”…””}”(hŒR has shifted affinities and requires a specific DTS for all the CPUs to be loaded.”h!jžubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j³hAj¡hCMh!jšubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!j@hhhAj¡hCNubj)”}”(hŒ±The ``-C cluster.cpu.RVBAR=@`` parameter, where X and Y are the cluster and CPU numbers respectively, is used to set the reset vector for each core. ”h]”j´)”}”(hŒ°The ``-C cluster.cpu.RVBAR=@`` parameter, where X and Y are the cluster and CPU numbers respectively, is used to set the reset vector for each core.”h]”(hŒThe ”…””}”(hŒThe ”h!jÊubj)”}”(hŒ6``-C cluster.cpu.RVBAR=@``”h]”hŒ2-C cluster.cpu.RVBAR=@”…””}”(hhh!jÓubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jÊubhŒv parameter, where X and Y are the cluster and CPU numbers respectively, is used to set the reset vector for each core.”…””}”(hŒv parameter, where X and Y are the cluster and CPU numbers respectively, is used to set the reset vector for each core.”h!jÊubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j³hAj¡hCMh!jÆubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!j@hhhAj¡hCNubj)”}”(hŒ¾Changing the default value of ``ARM_TSP_RAM_LOCATION`` will also require changing the value of ``--data="

"@`` to the new value of ``BL32_BASE``. ”h]”j´)”}”(hŒ¼Changing the default value of ``ARM_TSP_RAM_LOCATION`` will also require changing the value of ``--data="

"@`` to the new value of ``BL32_BASE``.”h]”(hŒChanging the default value of ”…””}”(hŒChanging the default value of ”h!jöubj)”}”(hŒ``ARM_TSP_RAM_LOCATION``”h]”hŒARM_TSP_RAM_LOCATION”…””}”(hhh!jÿubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jöubhŒ) will also require changing the value of ”…””}”(hŒ) will also require changing the value of ”h!jöubj)”}”(hŒ:``--data="

"@``”h]”hŒ6--data="

"@”…””}”(hhh!jubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jöubhŒ to the new value of ”…””}”(hŒ to the new value of ”h!jöubj)”}”(hŒ ``BL32_BASE``”h]”hŒ BL32_BASE”…””}”(hhh!j%ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jöubhŒ.”…””}”(hj¦h!jöubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j³hAj¡hCM"h!jòubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!j@hhhAj¡hCNubeh"}”(h$]”h&]”h+]”h-]”h/]”jžjŸuh1jhAj¡hCMh!jíhhubeh"}”(h$]”Œ;running-on-the-aemv8-base-fvp-with-reset-to-bl31-entrypoint”ah&]”h+]”Œ;running on the aemv8 base fvp with reset to bl31 entrypoint”ah-]”h/]”uh1jŒh!jAhhhAj¡hCMñubj)”}”(hhh]”(j’)”}”(hŒGRunning on the AEMv8 Base FVP (AArch32) with reset to SP_MIN entrypoint”h]”hŒGRunning on the AEMv8 Base FVP (AArch32) with reset to SP_MIN entrypoint”…””}”(hjVh!jThhhANhCNubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j‘h!jQhhhAj¡hCM)ubj´)”}”(hŒ}The following ``FVP_Base_AEMv8A-AEMv8A`` parameters should be used to boot Linux with 8 CPUs using the AArch32 build of TF-A.”h]”(hŒThe following ”…””}”(hŒThe following ”h!jbhhhANhCNubj)”}”(hŒ``FVP_Base_AEMv8A-AEMv8A``”h]”hŒFVP_Base_AEMv8A-AEMv8A”…””}”(hhh!jkubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jbubhŒU parameters should be used to boot Linux with 8 CPUs using the AArch32 build of TF-A.”…””}”(hŒU parameters should be used to boot Linux with 8 CPUs using the AArch32 build of TF-A.”h!jbhhhANhCNubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j³hAj¡hCM+h!jQhhubjÏ)”}”(hXÚ/FVP_Base_AEMv8A-AEMv8A \ -C pctl.startup=0.0.0.0 \ -C bp.secure_memory=1 \ -C bp.tzc_400.diagnostics=1 \ -C cluster0.NUM_CORES=4 \ -C cluster1.NUM_CORES=4 \ -C cache_state_modelled=1 \ -C cluster0.cpu0.CONFIG64=0 \ -C cluster0.cpu1.CONFIG64=0 \ -C cluster0.cpu2.CONFIG64=0 \ -C cluster0.cpu3.CONFIG64=0 \ -C cluster1.cpu0.CONFIG64=0 \ -C cluster1.cpu1.CONFIG64=0 \ -C cluster1.cpu2.CONFIG64=0 \ -C cluster1.cpu3.CONFIG64=0 \ -C cluster0.cpu0.RVBAR=0x04002000 \ -C cluster0.cpu1.RVBAR=0x04002000 \ -C cluster0.cpu2.RVBAR=0x04002000 \ -C cluster0.cpu3.RVBAR=0x04002000 \ -C cluster1.cpu0.RVBAR=0x04002000 \ -C cluster1.cpu1.RVBAR=0x04002000 \ -C cluster1.cpu2.RVBAR=0x04002000 \ -C cluster1.cpu3.RVBAR=0x04002000 \ --data cluster0.cpu0="/"@0x04002000 \ --data cluster0.cpu0="/"@0x88000000 \ --data cluster0.cpu0="/"@0x82000000 \ --data cluster0.cpu0="/"@0x80080000 \ --data cluster0.cpu0="/"@0x84000000”h]”hXÚ/FVP_Base_AEMv8A-AEMv8A \ -C pctl.startup=0.0.0.0 \ -C bp.secure_memory=1 \ -C bp.tzc_400.diagnostics=1 \ -C cluster0.NUM_CORES=4 \ -C cluster1.NUM_CORES=4 \ -C cache_state_modelled=1 \ -C cluster0.cpu0.CONFIG64=0 \ -C cluster0.cpu1.CONFIG64=0 \ -C cluster0.cpu2.CONFIG64=0 \ -C cluster0.cpu3.CONFIG64=0 \ -C cluster1.cpu0.CONFIG64=0 \ -C cluster1.cpu1.CONFIG64=0 \ -C cluster1.cpu2.CONFIG64=0 \ -C cluster1.cpu3.CONFIG64=0 \ -C cluster0.cpu0.RVBAR=0x04002000 \ -C cluster0.cpu1.RVBAR=0x04002000 \ -C cluster0.cpu2.RVBAR=0x04002000 \ -C cluster0.cpu3.RVBAR=0x04002000 \ -C cluster1.cpu0.RVBAR=0x04002000 \ -C cluster1.cpu1.RVBAR=0x04002000 \ -C cluster1.cpu2.RVBAR=0x04002000 \ -C cluster1.cpu3.RVBAR=0x04002000 \ --data cluster0.cpu0="/"@0x04002000 \ --data cluster0.cpu0="/"@0x88000000 \ --data cluster0.cpu0="/"@0x82000000 \ --data cluster0.cpu0="/"@0x80080000 \ --data cluster0.cpu0="/"@0x84000000”…””}”(hhh!j„ubah"}”(h$]”h&]”h+]”h-]”h/]”Œforce”‰Œhighlight_args”}”jÞjßj4Œshell”uh1jÎhAj¡hCM.h!jQhhubjô)”}”(hŒˆPosition Independent Executable (PIE) support is enabled in this config allowing SP_MIN to be loaded at any valid address for execution.”h]”j´)”}”(hŒˆPosition Independent Executable (PIE) support is enabled in this config allowing SP_MIN to be loaded at any valid address for execution.”h]”hŒˆPosition Independent Executable (PIE) support is enabled in this config allowing SP_MIN to be loaded at any valid address for execution.”…””}”(hjœh!jšubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j³hAj¡hCMNh!j–ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jóh!jQhhhAj¡hCNubeh"}”(h$]”ŒErunning-on-the-aemv8-base-fvp-aarch32-with-reset-to-sp-min-entrypoint”ah&]”h+]”ŒGrunning on the aemv8 base fvp (aarch32) with reset to sp_min entrypoint”ah-]”h/]”uh1jŒh!jAhhhAj¡hCM)ubj)”}”(hhh]”(j’)”}”(hŒDRunning on the Cortex-A57-A53 Base FVP with reset to BL31 entrypoint”h]”hŒDRunning on the Cortex-A57-A53 Base FVP with reset to BL31 entrypoint”…””}”(hj»h!j¹hhhANhCNubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j‘h!j¶hhhAj¡hCMRubj´)”}”(hŒˆThe following ``FVP_Base_Cortex-A57x4-A53x4`` model parameters should be used to boot Linux with 8 CPUs using the AArch64 build of TF-A.”h]”(hŒThe following ”…””}”(hŒThe following ”h!jÇhhhANhCNubj)”}”(hŒ``FVP_Base_Cortex-A57x4-A53x4``”h]”hŒFVP_Base_Cortex-A57x4-A53x4”…””}”(hhh!jÐubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!jÇubhŒ[ model parameters should be used to boot Linux with 8 CPUs using the AArch64 build of TF-A.”…””}”(hŒ[ model parameters should be used to boot Linux with 8 CPUs using the AArch64 build of TF-A.”h!jÇhhhANhCNubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j³hAj¡hCMTh!j¶hhubjÏ)”}”(hX£/FVP_Base_Cortex-A57x4-A53x4 \ -C pctl.startup=0.0.0.0 \ -C bp.secure_memory=1 \ -C bp.tzc_400.diagnostics=1 \ -C cache_state_modelled=1 \ -C cluster0.cpu0.RVBARADDR=0x04010000 \ -C cluster0.cpu1.RVBARADDR=0x04010000 \ -C cluster0.cpu2.RVBARADDR=0x04010000 \ -C cluster0.cpu3.RVBARADDR=0x04010000 \ -C cluster1.cpu0.RVBARADDR=0x04010000 \ -C cluster1.cpu1.RVBARADDR=0x04010000 \ -C cluster1.cpu2.RVBARADDR=0x04010000 \ -C cluster1.cpu3.RVBARADDR=0x04010000 \ --data cluster0.cpu0="/"@0x04010000 \ --data cluster0.cpu0="/"@0xff000000 \ --data cluster0.cpu0="/"@0x88000000 \ --data cluster0.cpu0="/"@0x82000000 \ --data cluster0.cpu0="/"@0x80080000 \ --data cluster0.cpu0="/"@0x84000000”h]”hX£/FVP_Base_Cortex-A57x4-A53x4 \ -C pctl.startup=0.0.0.0 \ -C bp.secure_memory=1 \ -C bp.tzc_400.diagnostics=1 \ -C cache_state_modelled=1 \ -C cluster0.cpu0.RVBARADDR=0x04010000 \ -C cluster0.cpu1.RVBARADDR=0x04010000 \ -C cluster0.cpu2.RVBARADDR=0x04010000 \ -C cluster0.cpu3.RVBARADDR=0x04010000 \ -C cluster1.cpu0.RVBARADDR=0x04010000 \ -C cluster1.cpu1.RVBARADDR=0x04010000 \ -C cluster1.cpu2.RVBARADDR=0x04010000 \ -C cluster1.cpu3.RVBARADDR=0x04010000 \ --data cluster0.cpu0="/"@0x04010000 \ --data cluster0.cpu0="/"@0xff000000 \ --data cluster0.cpu0="/"@0x88000000 \ --data cluster0.cpu0="/"@0x82000000 \ --data cluster0.cpu0="/"@0x80080000 \ --data cluster0.cpu0="/"@0x84000000”…””•¡$}”(hhh!jéubah"}”(h$]”h&]”h+]”h-]”h/]”Œforce”‰Œhighlight_args”}”jÞjßj4Œshell”uh1jÎhAj¡hCMWh!j¶hhubeh"}”(h$]”ŒDrunning-on-the-cortex-a57-a53-base-fvp-with-reset-to-bl31-entrypoint”ah&]”h+]”ŒDrunning on the cortex-a57-a53 base fvp with reset to bl31 entrypoint”ah-]”h/]”uh1jŒh!jAhhhAj¡hCMRubj)”}”(hhh]”(j’)”}”(hŒLRunning on the Cortex-A32 Base FVP (AArch32) with reset to SP_MIN entrypoint”h]”hŒLRunning on the Cortex-A32 Base FVP (AArch32) with reset to SP_MIN entrypoint”…””}”(hj h!j hhhANhCNubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j‘h!j hhhAj¡hCMnubj´)”}”(hŒ‚The following ``FVP_Base_Cortex-A32x4`` model parameters should be used to boot Linux with 4 CPUs using the AArch32 build of TF-A.”h]”(hŒThe following ”…””}”(hŒThe following ”h!j hhhANhCNubj)”}”(hŒ``FVP_Base_Cortex-A32x4``”h]”hŒFVP_Base_Cortex-A32x4”…””}”(hhh!j ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jh!j ubhŒ[ model parameters should be used to boot Linux with 4 CPUs using the AArch32 build of TF-A.”…””}”(hŒ[ model parameters should be used to boot Linux with 4 CPUs using the AArch32 build of TF-A.”h!j hhhANhCNubeh"}”(h$]”h&]”h+]”h-]”h/]”uh1j³hAj¡hCMph!j hhubjÏ)”}”(hX[/FVP_Base_Cortex-A32x4 \ -C pctl.startup=0.0.0.0 \ -C bp.secure_memory=1 \ -C bp.tzc_400.diagnostics=1 \ -C cache_state_modelled=1 \ -C cluster0.cpu0.RVBARADDR=0x04002000 \ -C cluster0.cpu1.RVBARADDR=0x04002000 \ -C cluster0.cpu2.RVBARADDR=0x04002000 \ -C cluster0.cpu3.RVBARADDR=0x04002000 \ --data cluster0.cpu0="/"@0x04002000 \ --data cluster0.cpu0="/"@0x88000000 \ --data cluster0.cpu0="/"@0x82000000 \ --data cluster0.cpu0="/"@0x80080000 \ --data cluster0.cpu0="/"@0x84000000”h]”hX[/FVP_Base_Cortex-A32x4 \ -C pctl.startup=0.0.0.0 \ -C bp.secure_memory=1 \ -C bp.tzc_400.diagnostics=1 \ -C cache_state_modelled=1 \ -C cluster0.cpu0.RVBARADDR=0x04002000 \ -C cluster0.cpu1.RVBARADDR=0x04002000 \ -C cluster0.cpu2.RVBARADDR=0x04002000 \ -C cluster0.cpu3.RVBARADDR=0x04002000 \ --data cluster0.cpu0="/"@0x04002000 \ --data cluster0.cpu0="/"@0x88000000 \ --data cluster0.cpu0="/"@0x82000000 \ --data cluster0.cpu0="/"@0x80080000 \ --data cluster0.cpu0="/"@0x84000000”…””}”(hhh!j6 ubah"}”(h$]”h&]”h+]”h-]”h/]”Œforce”‰Œhighlight_args”}”jÞjßj4Œshell”uh1jÎhAj¡hCMsh!j hhubh Œ transition”“”)”}”(hŒ--------------”h]”h"}”(h$]”h&]”h+]”h-]”h/]”uh1jH hAj¡hCM„h!j hhubj´)”}”(hŒ<*Copyright (c) 2019-2021, Arm Limited. All rights reserved.*”h]”jN)”}”(hjV h]”hŒ:Copyright (c) 2019-2021, Arm Limited. All rights reserved.”…””}”(hhh!jX ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1jMh!jT ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j³hAj¡hCM†h!j hhubj±)”}”(hŒ‡.. _TB_FW_CONFIG for FVP: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/tree/plat/arm/board/fvp/fdts/fvp_tb_fw_config.dts”h]”h"}”(h$]”Œtb-fw-config-for-fvp”ah&]”h+]”Œtb_fw_config for fvp”ah-]”h/]”jˆjuh1j°hCMÍh!j hhhAj¡Œ referenced”Kubj±)”}”(hŒ .. _Arm's website: `FVP models`_”h]”h"}”(h$]”Œ arm-s-website”ah&]”h+]”Œ arm's website”ah-]”h/]”jˆj¡uh1j°Œindirect_reference_name”Œ FVP models”hCMÎh!j hhhAj¡jŠKjw Kubj±)”}”(hŒX.. _FVP models: https://developer.arm.com/products/system-design/fixed-virtual-platforms”h]”h"}”(h$]”Œ fvp-models”ah&]”h+]”Œ fvp models”ah-]”h/]”jˆj¡uh1j°hCMÏh!j hhhAj¡jw Kubj±)”}”(hŒP.. _Linaro Release 20.01: http://releases.linaro.org/members/arm/platforms/20.01”h]”h"}”(h$]”Œlinaro-release-20-01”ah&]”h+]”Œlinaro release 20.01”ah-]”h/]”jˆj¥uh1j°hCMÐh!j hhhAj¡jw Kubj±)”}”(hŒ].. _Arm FVP website: https://developer.arm.com/products/system-design/fixed-virtual-platforms”h]”h"}”(h$]”Œarm-fvp-website”ah&]”h+]”Œarm fvp website”ah-]”h/]”jˆj‰uh1j°hCMÑh!j hhhAj¡jw Kubeh"}”(h$]”ŒJrunning-on-the-cortex-a32-base-fvp-aarch32-with-reset-to-sp-min-entrypoint”ah&]”h+]”ŒLrunning on the cortex-a32 base fvp (aarch32) with reset to sp_min entrypoint”ah-]”h/]”uh1jŒh!jAhhhAj¡hCMnubeh"}”(h$]”Œ)booting-a-preloaded-kernel-image-base-fvp”ah&]”h+]”Œ+booting a preloaded kernel image (base fvp)”ah-]”h/]”uh1jŒh!jŽhhhAj¡hCKåubeh"}”(h$]”Œarm-fixed-virtual-platforms-fvp”ah&]”h+]”Œ!arm fixed virtual platforms (fvp)”ah-]”h/]”uh1jŒh!hhhhAj¡hCKubeh"}”(h$]”h&]”h+]”h-]”h/]”Œsource”j¡uh1hŒcurrent_source”NŒcurrent_line”NŒsettings”Œdocutils.frontend”ŒValues”“”)”}”(j‘NŒ generator”NŒ datestamp”NŒsource_link”NŒ source_url”NŒ toc_backlinks”Œentry”Œfootnote_backlinks”KŒ sectnum_xform”KŒstrip_comments”NŒstrip_elements_with_classes”NŒ strip_classes”NŒreport_level”KŒ halt_level”KŒexit_status_level”KŒdebug”NŒwarning_stream”NŒ traceback”ˆŒinput_encoding”Œ utf-8-sig”Œinput_encoding_error_handler”Œstrict”Œoutput_encoding”Œutf-8”Œoutput_encoding_error_handler”jå Œerror_encoding”Œutf-8”Œerror_encoding_error_handler”Œbackslashreplace”Œ language_code”Œen”Œrecord_dependencies”NŒconfig”NŒ id_prefix”hŒauto_id_prefix”Œid”Œ dump_settings”NŒdump_internals”NŒdump_transforms”NŒdump_pseudo_xml”NŒexpose_internals”NŒstrict_visitor”NŒ_disable_config”NŒ_source”j¡Œ_destination”NŒ _config_files”]”Œpep_references”NŒpep_base_url”Œ https://www.python.org/dev/peps/”Œpep_file_url_template”Œpep-%04d”Œrfc_references”NŒrfc_base_url”Œhttps://tools.ietf.org/html/”Œ tab_width”KŒtrim_footnote_reference_space”‰Œfile_insertion_enabled”ˆŒraw_enabled”KŒsyntax_highlight”Œlong”Œsmart_quotes”ˆŒsmartquotes_locales”]”Œcharacter_level_inline_markup”‰Œdoctitle_xform”‰Œ docinfo_xform”KŒsectsubtitle_xform”‰Œembed_stylesheet”‰Œcloak_email_addresses”ˆŒenv”NubŒreporter”NŒindirect_targets”]”jx aŒsubstitution_defs”}”(hHhhshKhžhvhÉh¡hôhÌjh÷jJj"jujMj jxjËj£jöjÎj!jùjLj$jwjOj¢jzjÍj¥jøjÐj#jûjNj&jyjQj¤j|jÏj§jújÒj%jýjPj(j{jSj¦j~jÑj©jüjÔj'jÿjRj*j}jUj¨j€jÓj«jþjÖj)jjTj,jjWjªj‚jÕjjjØj+jjVj.jjYj¬j„j×j¯jjÚj-jjXj0jƒj[j®j†jÙj±j jÜj/ j jZ j2 j… j] j° jˆ jÛ j³ j jÞ j1 j j\ j4 j‡ j_ j² jŠ jÝ jµ jjà j3jj^j6j‰jauŒsubstitution_names”}”(Œaarch32”hHŒaarch64”hsŒamu”hžŒamus”hÉŒapi”hôŒbti”jŒcot”juŒcss”j Œcve”jËŒdtb”jöŒds-5”j!Œdsu”jLŒdt”jwŒel”j¢Œehf”jÍŒfconf”jøŒfdt”j#Œff-a”jNŒfip”jyŒfvp”j¤Œfwu”jÏŒgic”júŒisa”j%Œlinaro”jPŒmmu”j{Œmpam”j¦Œmpmm”jÑŒmpidr”jüŒmte”j'Œoen”jRŒop-tee”j}Œote”j¨Œpdd”jÓŒpauth”jþŒpmf”j)Œpsci”jTŒras”jŒrot”jªŒscmi”jÕŒscp”jŒsdei”j+Œsds”jVŒsea”jŒsip”j×Œsmc”jŒsmccc”j-Œsoc”jXŒsp”jƒŒspd”j®Œspm”jÙŒssbs”j Œsve”j/ Œtbb”jZ Œtbbr”j… Œtee”j° Œtf-a”jÛ Œtf-m”j Œtlb”j1 Œtlk”j\ Œtrng”j‡ Œtsp”j² Œtzc”jÝ Œubsan”jŒuefi”j3Œwdog”j^Œxlat”j‰uŒrefnames”}”(Œarm fvp website”]”jwaŒ arm's website”]”jaŒlinaro release 20.01”]”j”aŒtb_fw_config for fvp”]”jóaŒ fvp models”]”jx auŒrefids”}”j½]”j²asŒnameids”}”(j¿ j¼ jÃjÀjšj½j™j–jójðj>j;j· j´ jLjIjŠj‡jjjPjMjjšjêjçjNjKj³j°j jýj¯ j¬ jt jq j j~ j jŒ j› j˜ j§ j¤ uŒ nametypes”}”(j¿ NjÃNjšˆj™NjóNj>Nj· NjLNjŠNjNjPNjNjêNjNNj³Nj Nj¯ Njt ˆj ˆj ˆj› ˆj§ ˆuh$}”(j¼ jŽjÀj¢j½jÆj–jÆjðj¡j;jöj´ jAjIj!j‡jOjjjMjjšjSjçj jKjíj°jQjýj¶j¬ j jq jk j~ jx jŒ j† j˜ j’ j¤ jž uŒ footnote_refs”}”Œ citation_refs”}”Œ autofootnotes”]”Œautofootnote_refs”]”Œsymbol_footnotes”]”Œsymbol_footnote_refs”]”Œ footnotes”]”Œ citations”]”Œautofootnote_start”KŒsymbol_footnote_start”KŒ id_counter”Œcollections”ŒCounter”“”}”…”R”Œparse_messages”]”Œtransform_messages”]”h Œsystem_message”“”)”}”(hhh]”j´)”}”(hhh]”hŒDHyperlink target "build-options-arm-fvp-platform" is not referenced.”…””}”(hhh!j–!ubah"}”(h$]”h&]”h+]”h-]”h/]”uh1j³h!j“!ubah"}”(h$]”h&]”h+]”h-]”h/]”Œlevel”KŒtype”ŒINFO”Œsource”j¡Œline”K®uh1j‘!ubaŒtransformer”NŒ decoration”Nhhub.