1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * 4 * Configuration settings for the Armadeus Project motherboard APF27 5 * 6 * Copyright (C) 2008-2013 Eric Jarrige <eric.jarrige@armadeus.org> 7 */ 8 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 #include <linux/stringify.h> 13 14 #define CONFIG_ENV_VERSION 10 15 #define CONFIG_BOARD_NAME apf27 16 17 /* 18 * SoC configurations 19 */ 20 #define CONFIG_MX27 /* This is a Freescale i.MX27 Chip */ 21 #define CONFIG_MACH_TYPE 1698 /* APF27 */ 22 23 /* 24 * Enable the call to miscellaneous platform dependent initialization. 25 */ 26 27 /* 28 * SPL 29 */ 30 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 31 #define CONFIG_SPL_MAX_SIZE 2048 32 33 /* NAND boot config */ 34 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 35 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x800 36 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE 37 #define CONFIG_SYS_NAND_U_BOOT_SIZE CONFIG_SYS_MONITOR_LEN - 0x800 38 39 /* 40 * BOOTP options 41 */ 42 #define CONFIG_BOOTP_BOOTFILESIZE 43 44 #define CONFIG_HOSTNAME "apf27" 45 #define CONFIG_ROOTPATH "/tftpboot/" __stringify(CONFIG_BOARD_NAME) "-root" 46 47 /* 48 * Memory configurations 49 */ 50 #define CONFIG_NR_DRAM_POPULATED 1 51 52 #define ACFG_SDRAM_MBYTE_SYZE 64 53 54 #define PHYS_SDRAM_1 0xA0000000 55 #define PHYS_SDRAM_2 0xB0000000 56 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 57 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (512<<10)) 58 59 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE \ 60 + PHYS_SDRAM_1_SIZE - 0x0100000) 61 62 /* 63 * FLASH organization 64 */ 65 #define ACFG_MONITOR_OFFSET 0x00000000 66 #define CONFIG_SYS_MONITOR_LEN 0x00100000 /* 1MiB */ 67 #define CONFIG_ENV_RANGE 0X00080000 /* 512kB */ 68 #define CONFIG_FIRMWARE_OFFSET 0x00200000 69 #define CONFIG_FIRMWARE_SIZE 0x00080000 /* 512kB */ 70 #define CONFIG_KERNEL_OFFSET 0x00300000 71 #define CONFIG_ROOTFS_OFFSET 0x00800000 72 73 /* 74 * U-Boot general configurations 75 */ 76 #define CONFIG_SYS_CBSIZE 2048 /* console I/O buffer */ 77 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 78 /* Boot argument buffer size */ 79 80 /* 81 * Boot Linux 82 */ 83 #define CONFIG_CMDLINE_TAG /* send commandline to Kernel */ 84 #define CONFIG_SETUP_MEMORY_TAGS /* send memory definition to kernel */ 85 #define CONFIG_INITRD_TAG /* send initrd params */ 86 87 #define CONFIG_BOOTFILE __stringify(CONFIG_BOARD_NAME) "-linux.bin" 88 89 #define ACFG_CONSOLE_DEV ttySMX0 90 #define CONFIG_BOOTCOMMAND "run ubifsboot" 91 #define CONFIG_SYS_AUTOLOAD "no" 92 /* 93 * Default load address for user programs and kernel 94 */ 95 #define CONFIG_LOADADDR 0xA0000000 96 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR 97 98 /* 99 * Extra Environments 100 */ 101 #define CONFIG_EXTRA_ENV_SETTINGS \ 102 "env_version=" __stringify(CONFIG_ENV_VERSION) "\0" \ 103 "consoledev=" __stringify(ACFG_CONSOLE_DEV) "\0" \ 104 "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ 105 "partition=nand0,6\0" \ 106 "u-boot_addr=" __stringify(ACFG_MONITOR_OFFSET) "\0" \ 107 "env_addr=" __stringify(CONFIG_ENV_OFFSET) "\0" \ 108 "firmware_addr=" __stringify(CONFIG_FIRMWARE_OFFSET) "\0" \ 109 "firmware_size=" __stringify(CONFIG_FIRMWARE_SIZE) "\0" \ 110 "kernel_addr=" __stringify(CONFIG_KERNEL_OFFSET) "\0" \ 111 "rootfs_addr=" __stringify(CONFIG_ROOTFS_OFFSET) "\0" \ 112 "board_name=" __stringify(CONFIG_BOARD_NAME) "\0" \ 113 "kernel_addr_r=A0000000\0" \ 114 "check_env=if test -n ${flash_env_version}; " \ 115 "then env default env_version; " \ 116 "else env set flash_env_version ${env_version}; env save; "\ 117 "fi; " \ 118 "if itest ${flash_env_version} < ${env_version}; then " \ 119 "echo \"*** Warning - Environment version" \ 120 " change suggests: run flash_reset_env; reset\"; "\ 121 "env default flash_reset_env; "\ 122 "fi; \0" \ 123 "check_flash=nand lock; nand unlock ${env_addr}; \0" \ 124 "flash_reset_env=env default -f -a; saveenv; run update_env;" \ 125 "echo Flash environment variables erased!\0" \ 126 "download_uboot=tftpboot ${loadaddr} ${board_name}" \ 127 "-u-boot-with-spl.bin\0" \ 128 "flash_uboot=nand unlock ${u-boot_addr} ;" \ 129 "nand erase.part u-boot;" \ 130 "if nand write.trimffs ${fileaddr} ${u-boot_addr} ${filesize};"\ 131 "then nand lock; nand unlock ${env_addr};" \ 132 "echo Flashing of uboot succeed;" \ 133 "else echo Flashing of uboot failed;" \ 134 "fi; \0" \ 135 "update_uboot=run download_uboot flash_uboot\0" \ 136 "download_env=tftpboot ${loadaddr} ${board_name}" \ 137 "-u-boot-env.txt\0" \ 138 "flash_env=env import -t ${loadaddr}; env save; \0" \ 139 "update_env=run download_env flash_env\0" \ 140 "update_all=run update_env update_uboot\0" \ 141 "unlock_regs=mw 10000008 0; mw 10020008 0\0" \ 142 143 /* 144 * Serial Driver 145 */ 146 #define CONFIG_MXC_UART_BASE UART1_BASE 147 148 /* 149 * NOR 150 */ 151 152 /* 153 * NAND 154 */ 155 156 #define CONFIG_MXC_NAND_REGS_BASE 0xD8000000 157 #define CONFIG_SYS_NAND_BASE CONFIG_MXC_NAND_REGS_BASE 158 #define CONFIG_SYS_MAX_NAND_DEVICE 1 159 160 #define CONFIG_MXC_NAND_HWECC 161 #define CONFIG_SYS_NAND_LARGEPAGE 162 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 163 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 164 #define CONFIG_SYS_NAND_PAGE_COUNT CONFIG_SYS_NAND_BLOCK_SIZE / \ 165 CONFIG_SYS_NAND_PAGE_SIZE 166 #define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024) 167 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 11 168 #define NAND_MAX_CHIPS 1 169 170 #define CONFIG_FLASH_SHOW_PROGRESS 45 171 #define CONFIG_SYS_NAND_QUIET 1 172 173 /* 174 * Partitions & Filsystems 175 */ 176 177 /* 178 * Ethernet (on SOC imx FEC) 179 */ 180 #define CONFIG_FEC_MXC 181 #define CONFIG_FEC_MXC_PHYADDR 0x1f 182 183 /* 184 * FPGA 185 */ 186 #define CONFIG_FPGA_COUNT 1 187 #define CONFIG_SYS_FPGA_WAIT 250 /* 250 ms */ 188 #define CONFIG_SYS_FPGA_PROG_FEEDBACK 189 #define CONFIG_SYS_FPGA_CHECK_CTRLC 190 #define CONFIG_SYS_FPGA_CHECK_ERROR 191 192 /* 193 * Fuses - IIM 194 */ 195 #ifdef CONFIG_CMD_IMX_FUSE 196 #define IIM_MAC_BANK 0 197 #define IIM_MAC_ROW 5 198 #define IIM0_SCC_KEY 11 199 #define IIM1_SUID 1 200 #endif 201 202 /* 203 * I2C 204 */ 205 206 #ifdef CONFIG_CMD_I2C 207 #define CONFIG_SYS_I2C 208 #define CONFIG_SYS_I2C_MXC 209 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ 210 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ 211 #define CONFIG_SYS_MXC_I2C1_SPEED 100000 /* 100 kHz */ 212 #define CONFIG_SYS_MXC_I2C1_SLAVE 0x7F 213 #define CONFIG_SYS_MXC_I2C2_SPEED 100000 /* 100 kHz */ 214 #define CONFIG_SYS_MXC_I2C2_SLAVE 0x7F 215 #define CONFIG_SYS_I2C_NOPROBES { } 216 217 #ifdef CONFIG_CMD_EEPROM 218 # define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM 24LC02 */ 219 # define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */ 220 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 221 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* msec */ 222 #endif /* CONFIG_CMD_EEPROM */ 223 #endif /* CONFIG_CMD_I2C */ 224 225 /* 226 * SD/MMC 227 */ 228 #ifdef CONFIG_CMD_MMC 229 #define CONFIG_MXC_MCI_REGS_BASE 0x10014000 230 #endif 231 232 /* 233 * RTC 234 */ 235 #ifdef CONFIG_CMD_DATE 236 #define CONFIG_RTC_DS1374 237 #define CONFIG_SYS_RTC_BUS_NUM 0 238 #endif /* CONFIG_CMD_DATE */ 239 240 /* 241 * PLL 242 * 243 * 31 | x |x| x x x x |x x x x x x x x x x |x x|x x x x|x x x x x x x x x x| 0 244 * |CPLM|X|----PD---|--------MFD---------|XXX|--MFI--|-----MFN-----------| 245 */ 246 #define CONFIG_MX27_CLK32 32768 /* 32768 or 32000 Hz crystal */ 247 248 #if (ACFG_SDRAM_MBYTE_SYZE == 64) /* micron MT46H16M32LF -6 */ 249 /* micron 64MB */ 250 #define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ 251 #define PHYS_SDRAM_2_SIZE 0x04000000 /* 64 MB */ 252 #endif 253 254 #if (ACFG_SDRAM_MBYTE_SYZE == 128) 255 /* micron 128MB */ 256 #define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */ 257 #define PHYS_SDRAM_2_SIZE 0x08000000 /* 128 MB */ 258 #endif 259 260 #if (ACFG_SDRAM_MBYTE_SYZE == 256) 261 /* micron 256MB */ 262 #define PHYS_SDRAM_1_SIZE 0x10000000 /* 256 MB */ 263 #define PHYS_SDRAM_2_SIZE 0x10000000 /* 256 MB */ 264 #endif 265 266 #endif /* __CONFIG_H */ 267