1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Copyright © 2006-2015, Intel Corporation.
4 *
5 * Authors: Ashok Raj <ashok.raj@intel.com>
6 * Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>
7 * David Woodhouse <David.Woodhouse@intel.com>
8 */
9
10 #ifndef _INTEL_IOMMU_H_
11 #define _INTEL_IOMMU_H_
12
13 #include <linux/types.h>
14 #include <linux/iova.h>
15 #include <linux/io.h>
16 #include <linux/idr.h>
17 #include <linux/mmu_notifier.h>
18 #include <linux/list.h>
19 #include <linux/iommu.h>
20 #include <linux/io-64-nonatomic-lo-hi.h>
21 #include <linux/dmar.h>
22 #include <linux/ioasid.h>
23 #include <linux/bitfield.h>
24
25 #include <asm/cacheflush.h>
26 #include <asm/iommu.h>
27
28 /*
29 * VT-d hardware uses 4KiB page size regardless of host page size.
30 */
31 #define VTD_PAGE_SHIFT (12)
32 #define VTD_PAGE_SIZE (1UL << VTD_PAGE_SHIFT)
33 #define VTD_PAGE_MASK (((u64)-1) << VTD_PAGE_SHIFT)
34 #define VTD_PAGE_ALIGN(addr) (((addr) + VTD_PAGE_SIZE - 1) & VTD_PAGE_MASK)
35
36 #define VTD_STRIDE_SHIFT (9)
37 #define VTD_STRIDE_MASK (((u64)-1) << VTD_STRIDE_SHIFT)
38
39 #define DMA_PTE_READ BIT_ULL(0)
40 #define DMA_PTE_WRITE BIT_ULL(1)
41 #define DMA_PTE_LARGE_PAGE BIT_ULL(7)
42 #define DMA_PTE_SNP BIT_ULL(11)
43
44 #define DMA_FL_PTE_PRESENT BIT_ULL(0)
45 #define DMA_FL_PTE_US BIT_ULL(2)
46 #define DMA_FL_PTE_ACCESS BIT_ULL(5)
47 #define DMA_FL_PTE_DIRTY BIT_ULL(6)
48 #define DMA_FL_PTE_XD BIT_ULL(63)
49
50 #define ADDR_WIDTH_5LEVEL (57)
51 #define ADDR_WIDTH_4LEVEL (48)
52
53 #define CONTEXT_TT_MULTI_LEVEL 0
54 #define CONTEXT_TT_DEV_IOTLB 1
55 #define CONTEXT_TT_PASS_THROUGH 2
56 #define CONTEXT_PASIDE BIT_ULL(3)
57
58 /*
59 * Intel IOMMU register specification per version 1.0 public spec.
60 */
61 #define DMAR_VER_REG 0x0 /* Arch version supported by this IOMMU */
62 #define DMAR_CAP_REG 0x8 /* Hardware supported capabilities */
63 #define DMAR_ECAP_REG 0x10 /* Extended capabilities supported */
64 #define DMAR_GCMD_REG 0x18 /* Global command register */
65 #define DMAR_GSTS_REG 0x1c /* Global status register */
66 #define DMAR_RTADDR_REG 0x20 /* Root entry table */
67 #define DMAR_CCMD_REG 0x28 /* Context command reg */
68 #define DMAR_FSTS_REG 0x34 /* Fault Status register */
69 #define DMAR_FECTL_REG 0x38 /* Fault control register */
70 #define DMAR_FEDATA_REG 0x3c /* Fault event interrupt data register */
71 #define DMAR_FEADDR_REG 0x40 /* Fault event interrupt addr register */
72 #define DMAR_FEUADDR_REG 0x44 /* Upper address register */
73 #define DMAR_AFLOG_REG 0x58 /* Advanced Fault control */
74 #define DMAR_PMEN_REG 0x64 /* Enable Protected Memory Region */
75 #define DMAR_PLMBASE_REG 0x68 /* PMRR Low addr */
76 #define DMAR_PLMLIMIT_REG 0x6c /* PMRR low limit */
77 #define DMAR_PHMBASE_REG 0x70 /* pmrr high base addr */
78 #define DMAR_PHMLIMIT_REG 0x78 /* pmrr high limit */
79 #define DMAR_IQH_REG 0x80 /* Invalidation queue head register */
80 #define DMAR_IQT_REG 0x88 /* Invalidation queue tail register */
81 #define DMAR_IQ_SHIFT 4 /* Invalidation queue head/tail shift */
82 #define DMAR_IQA_REG 0x90 /* Invalidation queue addr register */
83 #define DMAR_ICS_REG 0x9c /* Invalidation complete status register */
84 #define DMAR_IQER_REG 0xb0 /* Invalidation queue error record register */
85 #define DMAR_IRTA_REG 0xb8 /* Interrupt remapping table addr register */
86 #define DMAR_PQH_REG 0xc0 /* Page request queue head register */
87 #define DMAR_PQT_REG 0xc8 /* Page request queue tail register */
88 #define DMAR_PQA_REG 0xd0 /* Page request queue address register */
89 #define DMAR_PRS_REG 0xdc /* Page request status register */
90 #define DMAR_PECTL_REG 0xe0 /* Page request event control register */
91 #define DMAR_PEDATA_REG 0xe4 /* Page request event interrupt data register */
92 #define DMAR_PEADDR_REG 0xe8 /* Page request event interrupt addr register */
93 #define DMAR_PEUADDR_REG 0xec /* Page request event Upper address register */
94 #define DMAR_MTRRCAP_REG 0x100 /* MTRR capability register */
95 #define DMAR_MTRRDEF_REG 0x108 /* MTRR default type register */
96 #define DMAR_MTRR_FIX64K_00000_REG 0x120 /* MTRR Fixed range registers */
97 #define DMAR_MTRR_FIX16K_80000_REG 0x128
98 #define DMAR_MTRR_FIX16K_A0000_REG 0x130
99 #define DMAR_MTRR_FIX4K_C0000_REG 0x138
100 #define DMAR_MTRR_FIX4K_C8000_REG 0x140
101 #define DMAR_MTRR_FIX4K_D0000_REG 0x148
102 #define DMAR_MTRR_FIX4K_D8000_REG 0x150
103 #define DMAR_MTRR_FIX4K_E0000_REG 0x158
104 #define DMAR_MTRR_FIX4K_E8000_REG 0x160
105 #define DMAR_MTRR_FIX4K_F0000_REG 0x168
106 #define DMAR_MTRR_FIX4K_F8000_REG 0x170
107 #define DMAR_MTRR_PHYSBASE0_REG 0x180 /* MTRR Variable range registers */
108 #define DMAR_MTRR_PHYSMASK0_REG 0x188
109 #define DMAR_MTRR_PHYSBASE1_REG 0x190
110 #define DMAR_MTRR_PHYSMASK1_REG 0x198
111 #define DMAR_MTRR_PHYSBASE2_REG 0x1a0
112 #define DMAR_MTRR_PHYSMASK2_REG 0x1a8
113 #define DMAR_MTRR_PHYSBASE3_REG 0x1b0
114 #define DMAR_MTRR_PHYSMASK3_REG 0x1b8
115 #define DMAR_MTRR_PHYSBASE4_REG 0x1c0
116 #define DMAR_MTRR_PHYSMASK4_REG 0x1c8
117 #define DMAR_MTRR_PHYSBASE5_REG 0x1d0
118 #define DMAR_MTRR_PHYSMASK5_REG 0x1d8
119 #define DMAR_MTRR_PHYSBASE6_REG 0x1e0
120 #define DMAR_MTRR_PHYSMASK6_REG 0x1e8
121 #define DMAR_MTRR_PHYSBASE7_REG 0x1f0
122 #define DMAR_MTRR_PHYSMASK7_REG 0x1f8
123 #define DMAR_MTRR_PHYSBASE8_REG 0x200
124 #define DMAR_MTRR_PHYSMASK8_REG 0x208
125 #define DMAR_MTRR_PHYSBASE9_REG 0x210
126 #define DMAR_MTRR_PHYSMASK9_REG 0x218
127 #define DMAR_VCCAP_REG 0xe30 /* Virtual command capability register */
128 #define DMAR_VCMD_REG 0xe00 /* Virtual command register */
129 #define DMAR_VCRSP_REG 0xe10 /* Virtual command response register */
130
131 #define DMAR_IQER_REG_IQEI(reg) FIELD_GET(GENMASK_ULL(3, 0), reg)
132 #define DMAR_IQER_REG_ITESID(reg) FIELD_GET(GENMASK_ULL(47, 32), reg)
133 #define DMAR_IQER_REG_ICESID(reg) FIELD_GET(GENMASK_ULL(63, 48), reg)
134
135 #define OFFSET_STRIDE (9)
136
137 #define dmar_readq(a) readq(a)
138 #define dmar_writeq(a,v) writeq(v,a)
139 #define dmar_readl(a) readl(a)
140 #define dmar_writel(a, v) writel(v, a)
141
142 #define DMAR_VER_MAJOR(v) (((v) & 0xf0) >> 4)
143 #define DMAR_VER_MINOR(v) ((v) & 0x0f)
144
145 /*
146 * Decoding Capability Register
147 */
148 #define cap_5lp_support(c) (((c) >> 60) & 1)
149 #define cap_pi_support(c) (((c) >> 59) & 1)
150 #define cap_fl1gp_support(c) (((c) >> 56) & 1)
151 #define cap_read_drain(c) (((c) >> 55) & 1)
152 #define cap_write_drain(c) (((c) >> 54) & 1)
153 #define cap_max_amask_val(c) (((c) >> 48) & 0x3f)
154 #define cap_num_fault_regs(c) ((((c) >> 40) & 0xff) + 1)
155 #define cap_pgsel_inv(c) (((c) >> 39) & 1)
156
157 #define cap_super_page_val(c) (((c) >> 34) & 0xf)
158 #define cap_super_offset(c) (((find_first_bit(&cap_super_page_val(c), 4)) \
159 * OFFSET_STRIDE) + 21)
160
161 #define cap_fault_reg_offset(c) ((((c) >> 24) & 0x3ff) * 16)
162 #define cap_max_fault_reg_offset(c) \
163 (cap_fault_reg_offset(c) + cap_num_fault_regs(c) * 16)
164
165 #define cap_zlr(c) (((c) >> 22) & 1)
166 #define cap_isoch(c) (((c) >> 23) & 1)
167 #define cap_mgaw(c) ((((c) >> 16) & 0x3f) + 1)
168 #define cap_sagaw(c) (((c) >> 8) & 0x1f)
169 #define cap_caching_mode(c) (((c) >> 7) & 1)
170 #define cap_phmr(c) (((c) >> 6) & 1)
171 #define cap_plmr(c) (((c) >> 5) & 1)
172 #define cap_rwbf(c) (((c) >> 4) & 1)
173 #define cap_afl(c) (((c) >> 3) & 1)
174 #define cap_ndoms(c) (((unsigned long)1) << (4 + 2 * ((c) & 0x7)))
175 /*
176 * Extended Capability Register
177 */
178
179 #define ecap_rps(e) (((e) >> 49) & 0x1)
180 #define ecap_smpwc(e) (((e) >> 48) & 0x1)
181 #define ecap_flts(e) (((e) >> 47) & 0x1)
182 #define ecap_slts(e) (((e) >> 46) & 0x1)
183 #define ecap_slads(e) (((e) >> 45) & 0x1)
184 #define ecap_vcs(e) (((e) >> 44) & 0x1)
185 #define ecap_smts(e) (((e) >> 43) & 0x1)
186 #define ecap_dit(e) (((e) >> 41) & 0x1)
187 #define ecap_pds(e) (((e) >> 42) & 0x1)
188 #define ecap_pasid(e) (((e) >> 40) & 0x1)
189 #define ecap_pss(e) (((e) >> 35) & 0x1f)
190 #define ecap_eafs(e) (((e) >> 34) & 0x1)
191 #define ecap_nwfs(e) (((e) >> 33) & 0x1)
192 #define ecap_srs(e) (((e) >> 31) & 0x1)
193 #define ecap_ers(e) (((e) >> 30) & 0x1)
194 #define ecap_prs(e) (((e) >> 29) & 0x1)
195 #define ecap_broken_pasid(e) (((e) >> 28) & 0x1)
196 #define ecap_dis(e) (((e) >> 27) & 0x1)
197 #define ecap_nest(e) (((e) >> 26) & 0x1)
198 #define ecap_mts(e) (((e) >> 25) & 0x1)
199 #define ecap_ecs(e) (((e) >> 24) & 0x1)
200 #define ecap_iotlb_offset(e) ((((e) >> 8) & 0x3ff) * 16)
201 #define ecap_max_iotlb_offset(e) (ecap_iotlb_offset(e) + 16)
202 #define ecap_coherent(e) ((e) & 0x1)
203 #define ecap_qis(e) ((e) & 0x2)
204 #define ecap_pass_through(e) (((e) >> 6) & 0x1)
205 #define ecap_eim_support(e) (((e) >> 4) & 0x1)
206 #define ecap_ir_support(e) (((e) >> 3) & 0x1)
207 #define ecap_dev_iotlb_support(e) (((e) >> 2) & 0x1)
208 #define ecap_max_handle_mask(e) (((e) >> 20) & 0xf)
209 #define ecap_sc_support(e) (((e) >> 7) & 0x1) /* Snooping Control */
210
211 /* Virtual command interface capability */
212 #define vccap_pasid(v) (((v) & DMA_VCS_PAS)) /* PASID allocation */
213
214 /* IOTLB_REG */
215 #define DMA_TLB_FLUSH_GRANU_OFFSET 60
216 #define DMA_TLB_GLOBAL_FLUSH (((u64)1) << 60)
217 #define DMA_TLB_DSI_FLUSH (((u64)2) << 60)
218 #define DMA_TLB_PSI_FLUSH (((u64)3) << 60)
219 #define DMA_TLB_IIRG(type) ((type >> 60) & 3)
220 #define DMA_TLB_IAIG(val) (((val) >> 57) & 3)
221 #define DMA_TLB_READ_DRAIN (((u64)1) << 49)
222 #define DMA_TLB_WRITE_DRAIN (((u64)1) << 48)
223 #define DMA_TLB_DID(id) (((u64)((id) & 0xffff)) << 32)
224 #define DMA_TLB_IVT (((u64)1) << 63)
225 #define DMA_TLB_IH_NONLEAF (((u64)1) << 6)
226 #define DMA_TLB_MAX_SIZE (0x3f)
227
228 /* INVALID_DESC */
229 #define DMA_CCMD_INVL_GRANU_OFFSET 61
230 #define DMA_ID_TLB_GLOBAL_FLUSH (((u64)1) << 4)
231 #define DMA_ID_TLB_DSI_FLUSH (((u64)2) << 4)
232 #define DMA_ID_TLB_PSI_FLUSH (((u64)3) << 4)
233 #define DMA_ID_TLB_READ_DRAIN (((u64)1) << 7)
234 #define DMA_ID_TLB_WRITE_DRAIN (((u64)1) << 6)
235 #define DMA_ID_TLB_DID(id) (((u64)((id & 0xffff) << 16)))
236 #define DMA_ID_TLB_IH_NONLEAF (((u64)1) << 6)
237 #define DMA_ID_TLB_ADDR(addr) (addr)
238 #define DMA_ID_TLB_ADDR_MASK(mask) (mask)
239
240 /* PMEN_REG */
241 #define DMA_PMEN_EPM (((u32)1)<<31)
242 #define DMA_PMEN_PRS (((u32)1)<<0)
243
244 /* GCMD_REG */
245 #define DMA_GCMD_TE (((u32)1) << 31)
246 #define DMA_GCMD_SRTP (((u32)1) << 30)
247 #define DMA_GCMD_SFL (((u32)1) << 29)
248 #define DMA_GCMD_EAFL (((u32)1) << 28)
249 #define DMA_GCMD_WBF (((u32)1) << 27)
250 #define DMA_GCMD_QIE (((u32)1) << 26)
251 #define DMA_GCMD_SIRTP (((u32)1) << 24)
252 #define DMA_GCMD_IRE (((u32) 1) << 25)
253 #define DMA_GCMD_CFI (((u32) 1) << 23)
254
255 /* GSTS_REG */
256 #define DMA_GSTS_TES (((u32)1) << 31)
257 #define DMA_GSTS_RTPS (((u32)1) << 30)
258 #define DMA_GSTS_FLS (((u32)1) << 29)
259 #define DMA_GSTS_AFLS (((u32)1) << 28)
260 #define DMA_GSTS_WBFS (((u32)1) << 27)
261 #define DMA_GSTS_QIES (((u32)1) << 26)
262 #define DMA_GSTS_IRTPS (((u32)1) << 24)
263 #define DMA_GSTS_IRES (((u32)1) << 25)
264 #define DMA_GSTS_CFIS (((u32)1) << 23)
265
266 /* DMA_RTADDR_REG */
267 #define DMA_RTADDR_RTT (((u64)1) << 11)
268 #define DMA_RTADDR_SMT (((u64)1) << 10)
269
270 /* CCMD_REG */
271 #define DMA_CCMD_ICC (((u64)1) << 63)
272 #define DMA_CCMD_GLOBAL_INVL (((u64)1) << 61)
273 #define DMA_CCMD_DOMAIN_INVL (((u64)2) << 61)
274 #define DMA_CCMD_DEVICE_INVL (((u64)3) << 61)
275 #define DMA_CCMD_FM(m) (((u64)((m) & 0x3)) << 32)
276 #define DMA_CCMD_MASK_NOBIT 0
277 #define DMA_CCMD_MASK_1BIT 1
278 #define DMA_CCMD_MASK_2BIT 2
279 #define DMA_CCMD_MASK_3BIT 3
280 #define DMA_CCMD_SID(s) (((u64)((s) & 0xffff)) << 16)
281 #define DMA_CCMD_DID(d) ((u64)((d) & 0xffff))
282
283 /* FECTL_REG */
284 #define DMA_FECTL_IM (((u32)1) << 31)
285
286 /* FSTS_REG */
287 #define DMA_FSTS_PFO (1 << 0) /* Primary Fault Overflow */
288 #define DMA_FSTS_PPF (1 << 1) /* Primary Pending Fault */
289 #define DMA_FSTS_IQE (1 << 4) /* Invalidation Queue Error */
290 #define DMA_FSTS_ICE (1 << 5) /* Invalidation Completion Error */
291 #define DMA_FSTS_ITE (1 << 6) /* Invalidation Time-out Error */
292 #define DMA_FSTS_PRO (1 << 7) /* Page Request Overflow */
293 #define dma_fsts_fault_record_index(s) (((s) >> 8) & 0xff)
294
295 /* FRCD_REG, 32 bits access */
296 #define DMA_FRCD_F (((u32)1) << 31)
297 #define dma_frcd_type(d) ((d >> 30) & 1)
298 #define dma_frcd_fault_reason(c) (c & 0xff)
299 #define dma_frcd_source_id(c) (c & 0xffff)
300 #define dma_frcd_pasid_value(c) (((c) >> 8) & 0xfffff)
301 #define dma_frcd_pasid_present(c) (((c) >> 31) & 1)
302 /* low 64 bit */
303 #define dma_frcd_page_addr(d) (d & (((u64)-1) << PAGE_SHIFT))
304
305 /* PRS_REG */
306 #define DMA_PRS_PPR ((u32)1)
307 #define DMA_PRS_PRO ((u32)2)
308
309 #define DMA_VCS_PAS ((u64)1)
310
311 #define IOMMU_WAIT_OP(iommu, offset, op, cond, sts) \
312 do { \
313 cycles_t start_time = get_cycles(); \
314 while (1) { \
315 sts = op(iommu->reg + offset); \
316 if (cond) \
317 break; \
318 if (DMAR_OPERATION_TIMEOUT < (get_cycles() - start_time))\
319 panic("DMAR hardware is malfunctioning\n"); \
320 cpu_relax(); \
321 } \
322 } while (0)
323
324 #define QI_LENGTH 256 /* queue length */
325
326 enum {
327 QI_FREE,
328 QI_IN_USE,
329 QI_DONE,
330 QI_ABORT
331 };
332
333 #define QI_CC_TYPE 0x1
334 #define QI_IOTLB_TYPE 0x2
335 #define QI_DIOTLB_TYPE 0x3
336 #define QI_IEC_TYPE 0x4
337 #define QI_IWD_TYPE 0x5
338 #define QI_EIOTLB_TYPE 0x6
339 #define QI_PC_TYPE 0x7
340 #define QI_DEIOTLB_TYPE 0x8
341 #define QI_PGRP_RESP_TYPE 0x9
342 #define QI_PSTRM_RESP_TYPE 0xa
343
344 #define QI_IEC_SELECTIVE (((u64)1) << 4)
345 #define QI_IEC_IIDEX(idx) (((u64)(idx & 0xffff) << 32))
346 #define QI_IEC_IM(m) (((u64)(m & 0x1f) << 27))
347
348 #define QI_IWD_STATUS_DATA(d) (((u64)d) << 32)
349 #define QI_IWD_STATUS_WRITE (((u64)1) << 5)
350 #define QI_IWD_FENCE (((u64)1) << 6)
351 #define QI_IWD_PRQ_DRAIN (((u64)1) << 7)
352
353 #define QI_IOTLB_DID(did) (((u64)did) << 16)
354 #define QI_IOTLB_DR(dr) (((u64)dr) << 7)
355 #define QI_IOTLB_DW(dw) (((u64)dw) << 6)
356 #define QI_IOTLB_GRAN(gran) (((u64)gran) >> (DMA_TLB_FLUSH_GRANU_OFFSET-4))
357 #define QI_IOTLB_ADDR(addr) (((u64)addr) & VTD_PAGE_MASK)
358 #define QI_IOTLB_IH(ih) (((u64)ih) << 6)
359 #define QI_IOTLB_AM(am) (((u8)am) & 0x3f)
360
361 #define QI_CC_FM(fm) (((u64)fm) << 48)
362 #define QI_CC_SID(sid) (((u64)sid) << 32)
363 #define QI_CC_DID(did) (((u64)did) << 16)
364 #define QI_CC_GRAN(gran) (((u64)gran) >> (DMA_CCMD_INVL_GRANU_OFFSET-4))
365
366 #define QI_DEV_IOTLB_SID(sid) ((u64)((sid) & 0xffff) << 32)
367 #define QI_DEV_IOTLB_QDEP(qdep) (((qdep) & 0x1f) << 16)
368 #define QI_DEV_IOTLB_ADDR(addr) ((u64)(addr) & VTD_PAGE_MASK)
369 #define QI_DEV_IOTLB_PFSID(pfsid) (((u64)(pfsid & 0xf) << 12) | \
370 ((u64)((pfsid >> 4) & 0xfff) << 52))
371 #define QI_DEV_IOTLB_SIZE 1
372 #define QI_DEV_IOTLB_MAX_INVS 32
373
374 #define QI_PC_PASID(pasid) (((u64)pasid) << 32)
375 #define QI_PC_DID(did) (((u64)did) << 16)
376 #define QI_PC_GRAN(gran) (((u64)gran) << 4)
377
378 /* PASID cache invalidation granu */
379 #define QI_PC_ALL_PASIDS 0
380 #define QI_PC_PASID_SEL 1
381 #define QI_PC_GLOBAL 3
382
383 #define QI_EIOTLB_ADDR(addr) ((u64)(addr) & VTD_PAGE_MASK)
384 #define QI_EIOTLB_IH(ih) (((u64)ih) << 6)
385 #define QI_EIOTLB_AM(am) (((u64)am) & 0x3f)
386 #define QI_EIOTLB_PASID(pasid) (((u64)pasid) << 32)
387 #define QI_EIOTLB_DID(did) (((u64)did) << 16)
388 #define QI_EIOTLB_GRAN(gran) (((u64)gran) << 4)
389
390 /* QI Dev-IOTLB inv granu */
391 #define QI_DEV_IOTLB_GRAN_ALL 1
392 #define QI_DEV_IOTLB_GRAN_PASID_SEL 0
393
394 #define QI_DEV_EIOTLB_ADDR(a) ((u64)(a) & VTD_PAGE_MASK)
395 #define QI_DEV_EIOTLB_SIZE (((u64)1) << 11)
396 #define QI_DEV_EIOTLB_PASID(p) ((u64)((p) & 0xfffff) << 32)
397 #define QI_DEV_EIOTLB_SID(sid) ((u64)((sid) & 0xffff) << 16)
398 #define QI_DEV_EIOTLB_QDEP(qd) ((u64)((qd) & 0x1f) << 4)
399 #define QI_DEV_EIOTLB_PFSID(pfsid) (((u64)(pfsid & 0xf) << 12) | \
400 ((u64)((pfsid >> 4) & 0xfff) << 52))
401 #define QI_DEV_EIOTLB_MAX_INVS 32
402
403 /* Page group response descriptor QW0 */
404 #define QI_PGRP_PASID_P(p) (((u64)(p)) << 4)
405 #define QI_PGRP_PDP(p) (((u64)(p)) << 5)
406 #define QI_PGRP_RESP_CODE(res) (((u64)(res)) << 12)
407 #define QI_PGRP_DID(rid) (((u64)(rid)) << 16)
408 #define QI_PGRP_PASID(pasid) (((u64)(pasid)) << 32)
409
410 /* Page group response descriptor QW1 */
411 #define QI_PGRP_LPIG(x) (((u64)(x)) << 2)
412 #define QI_PGRP_IDX(idx) (((u64)(idx)) << 3)
413
414
415 #define QI_RESP_SUCCESS 0x0
416 #define QI_RESP_INVALID 0x1
417 #define QI_RESP_FAILURE 0xf
418
419 #define QI_GRAN_NONG_PASID 2
420 #define QI_GRAN_PSI_PASID 3
421
422 #define qi_shift(iommu) (DMAR_IQ_SHIFT + !!ecap_smts((iommu)->ecap))
423
424 struct qi_desc {
425 u64 qw0;
426 u64 qw1;
427 u64 qw2;
428 u64 qw3;
429 };
430
431 struct q_inval {
432 raw_spinlock_t q_lock;
433 void *desc; /* invalidation queue */
434 int *desc_status; /* desc status */
435 int free_head; /* first free entry */
436 int free_tail; /* last free entry */
437 int free_cnt;
438 };
439
440 struct dmar_pci_notify_info;
441
442 #ifdef CONFIG_IRQ_REMAP
443 /* 1MB - maximum possible interrupt remapping table size */
444 #define INTR_REMAP_PAGE_ORDER 8
445 #define INTR_REMAP_TABLE_REG_SIZE 0xf
446 #define INTR_REMAP_TABLE_REG_SIZE_MASK 0xf
447
448 #define INTR_REMAP_TABLE_ENTRIES 65536
449
450 struct irq_domain;
451
452 struct ir_table {
453 struct irte *base;
454 unsigned long *bitmap;
455 };
456
457 void intel_irq_remap_add_device(struct dmar_pci_notify_info *info);
458 #else
459 static inline void
intel_irq_remap_add_device(struct dmar_pci_notify_info * info)460 intel_irq_remap_add_device(struct dmar_pci_notify_info *info) { }
461 #endif
462
463 struct iommu_flush {
464 void (*flush_context)(struct intel_iommu *iommu, u16 did, u16 sid,
465 u8 fm, u64 type);
466 void (*flush_iotlb)(struct intel_iommu *iommu, u16 did, u64 addr,
467 unsigned int size_order, u64 type);
468 };
469
470 enum {
471 SR_DMAR_FECTL_REG,
472 SR_DMAR_FEDATA_REG,
473 SR_DMAR_FEADDR_REG,
474 SR_DMAR_FEUADDR_REG,
475 MAX_SR_DMAR_REGS
476 };
477
478 #define VTD_FLAG_TRANS_PRE_ENABLED (1 << 0)
479 #define VTD_FLAG_IRQ_REMAP_PRE_ENABLED (1 << 1)
480 #define VTD_FLAG_SVM_CAPABLE (1 << 2)
481
482 extern int intel_iommu_sm;
483 extern spinlock_t device_domain_lock;
484
485 #define sm_supported(iommu) (intel_iommu_sm && ecap_smts((iommu)->ecap))
486 #define pasid_supported(iommu) (sm_supported(iommu) && \
487 ecap_pasid((iommu)->ecap))
488
489 struct pasid_entry;
490 struct pasid_state_entry;
491 struct page_req_dsc;
492
493 /*
494 * 0: Present
495 * 1-11: Reserved
496 * 12-63: Context Ptr (12 - (haw-1))
497 * 64-127: Reserved
498 */
499 struct root_entry {
500 u64 lo;
501 u64 hi;
502 };
503
504 /*
505 * low 64 bits:
506 * 0: present
507 * 1: fault processing disable
508 * 2-3: translation type
509 * 12-63: address space root
510 * high 64 bits:
511 * 0-2: address width
512 * 3-6: aval
513 * 8-23: domain id
514 */
515 struct context_entry {
516 u64 lo;
517 u64 hi;
518 };
519
520 /*
521 * When VT-d works in the scalable mode, it allows DMA translation to
522 * happen through either first level or second level page table. This
523 * bit marks that the DMA translation for the domain goes through the
524 * first level page table, otherwise, it goes through the second level.
525 */
526 #define DOMAIN_FLAG_USE_FIRST_LEVEL BIT(1)
527
528 /*
529 * Domain represents a virtual machine which demands iommu nested
530 * translation mode support.
531 */
532 #define DOMAIN_FLAG_NESTING_MODE BIT(2)
533
534 struct dmar_domain {
535 int nid; /* node id */
536
537 unsigned int iommu_refcnt[DMAR_UNITS_SUPPORTED];
538 /* Refcount of devices per iommu */
539
540
541 u16 iommu_did[DMAR_UNITS_SUPPORTED];
542 /* Domain ids per IOMMU. Use u16 since
543 * domain ids are 16 bit wide according
544 * to VT-d spec, section 9.3 */
545
546 u8 has_iotlb_device: 1;
547 u8 iommu_coherency: 1; /* indicate coherency of iommu access */
548 u8 iommu_snooping: 1; /* indicate snooping control feature */
549
550 struct list_head devices; /* all devices' list */
551 struct list_head subdevices; /* all subdevices' list */
552 struct iova_domain iovad; /* iova's that belong to this domain */
553
554 struct dma_pte *pgd; /* virtual address */
555 int gaw; /* max guest address width */
556
557 /* adjusted guest address width, 0 is level 2 30-bit */
558 int agaw;
559
560 int flags; /* flags to find out type of domain */
561 int iommu_superpage;/* Level of superpages supported:
562 0 == 4KiB (no superpages), 1 == 2MiB,
563 2 == 1GiB, 3 == 512GiB, 4 == 1TiB */
564 u64 max_addr; /* maximum mapped address */
565
566 u32 default_pasid; /*
567 * The default pasid used for non-SVM
568 * traffic on mediated devices.
569 */
570
571 struct iommu_domain domain; /* generic domain data structure for
572 iommu core */
573 };
574
575 struct intel_iommu {
576 void __iomem *reg; /* Pointer to hardware regs, virtual addr */
577 u64 reg_phys; /* physical address of hw register set */
578 u64 reg_size; /* size of hw register set */
579 u64 cap;
580 u64 ecap;
581 u64 vccap;
582 u32 gcmd; /* Holds TE, EAFL. Don't need SRTP, SFL, WBF */
583 raw_spinlock_t register_lock; /* protect register handling */
584 int seq_id; /* sequence id of the iommu */
585 int agaw; /* agaw of this iommu */
586 int msagaw; /* max sagaw of this iommu */
587 unsigned int irq, pr_irq;
588 u16 segment; /* PCI segment# */
589 unsigned char name[13]; /* Device Name */
590
591 #ifdef CONFIG_INTEL_IOMMU
592 unsigned long *domain_ids; /* bitmap of domains */
593 struct dmar_domain ***domains; /* ptr to domains */
594 spinlock_t lock; /* protect context, domain ids */
595 struct root_entry *root_entry; /* virtual address */
596
597 struct iommu_flush flush;
598 #endif
599 #ifdef CONFIG_INTEL_IOMMU_SVM
600 struct page_req_dsc *prq;
601 unsigned char prq_name[16]; /* Name for PRQ interrupt */
602 struct completion prq_complete;
603 struct ioasid_allocator_ops pasid_allocator; /* Custom allocator for PASIDs */
604 #endif
605 struct iopf_queue *iopf_queue;
606 unsigned char iopfq_name[16];
607 struct q_inval *qi; /* Queued invalidation info */
608 u32 *iommu_state; /* Store iommu states between suspend and resume.*/
609
610 #ifdef CONFIG_IRQ_REMAP
611 struct ir_table *ir_table; /* Interrupt remapping info */
612 struct irq_domain *ir_domain;
613 struct irq_domain *ir_msi_domain;
614 #endif
615 struct iommu_device iommu; /* IOMMU core code handle */
616 int node;
617 u32 flags; /* Software defined flags */
618
619 struct dmar_drhd_unit *drhd;
620 void *perf_statistic;
621 };
622
623 /* Per subdevice private data */
624 struct subdev_domain_info {
625 struct list_head link_phys; /* link to phys device siblings */
626 struct list_head link_domain; /* link to domain siblings */
627 struct device *pdev; /* physical device derived from */
628 struct dmar_domain *domain; /* aux-domain */
629 int users; /* user count */
630 };
631
632 /* PCI domain-device relationship */
633 struct device_domain_info {
634 struct list_head link; /* link to domain siblings */
635 struct list_head global; /* link to global list */
636 struct list_head table; /* link to pasid table */
637 struct list_head subdevices; /* subdevices sibling */
638 u32 segment; /* PCI segment number */
639 u8 bus; /* PCI bus number */
640 u8 devfn; /* PCI devfn number */
641 u16 pfsid; /* SRIOV physical function source ID */
642 u8 pasid_supported:3;
643 u8 pasid_enabled:1;
644 u8 pri_supported:1;
645 u8 pri_enabled:1;
646 u8 ats_supported:1;
647 u8 ats_enabled:1;
648 u8 auxd_enabled:1; /* Multiple domains per device */
649 u8 ats_qdep;
650 struct device *dev; /* it's NULL for PCIe-to-PCI bridge */
651 struct intel_iommu *iommu; /* IOMMU used by this device */
652 struct dmar_domain *domain; /* pointer to domain */
653 struct pasid_table *pasid_table; /* pasid table */
654 };
655
__iommu_flush_cache(struct intel_iommu * iommu,void * addr,int size)656 static inline void __iommu_flush_cache(
657 struct intel_iommu *iommu, void *addr, int size)
658 {
659 if (!ecap_coherent(iommu->ecap))
660 clflush_cache_range(addr, size);
661 }
662
663 /* Convert generic struct iommu_domain to private struct dmar_domain */
to_dmar_domain(struct iommu_domain * dom)664 static inline struct dmar_domain *to_dmar_domain(struct iommu_domain *dom)
665 {
666 return container_of(dom, struct dmar_domain, domain);
667 }
668
669 /*
670 * 0: readable
671 * 1: writable
672 * 2-6: reserved
673 * 7: super page
674 * 8-10: available
675 * 11: snoop behavior
676 * 12-63: Host physical address
677 */
678 struct dma_pte {
679 u64 val;
680 };
681
dma_clear_pte(struct dma_pte * pte)682 static inline void dma_clear_pte(struct dma_pte *pte)
683 {
684 pte->val = 0;
685 }
686
dma_pte_addr(struct dma_pte * pte)687 static inline u64 dma_pte_addr(struct dma_pte *pte)
688 {
689 #ifdef CONFIG_64BIT
690 return pte->val & VTD_PAGE_MASK & (~DMA_FL_PTE_XD);
691 #else
692 /* Must have a full atomic 64-bit read */
693 return __cmpxchg64(&pte->val, 0ULL, 0ULL) &
694 VTD_PAGE_MASK & (~DMA_FL_PTE_XD);
695 #endif
696 }
697
dma_pte_present(struct dma_pte * pte)698 static inline bool dma_pte_present(struct dma_pte *pte)
699 {
700 return (pte->val & 3) != 0;
701 }
702
dma_pte_superpage(struct dma_pte * pte)703 static inline bool dma_pte_superpage(struct dma_pte *pte)
704 {
705 return (pte->val & DMA_PTE_LARGE_PAGE);
706 }
707
first_pte_in_page(struct dma_pte * pte)708 static inline bool first_pte_in_page(struct dma_pte *pte)
709 {
710 return IS_ALIGNED((unsigned long)pte, VTD_PAGE_SIZE);
711 }
712
nr_pte_to_next_page(struct dma_pte * pte)713 static inline int nr_pte_to_next_page(struct dma_pte *pte)
714 {
715 return first_pte_in_page(pte) ? BIT_ULL(VTD_STRIDE_SHIFT) :
716 (struct dma_pte *)ALIGN((unsigned long)pte, VTD_PAGE_SIZE) - pte;
717 }
718
719 extern struct dmar_drhd_unit * dmar_find_matched_drhd_unit(struct pci_dev *dev);
720 extern int dmar_find_matched_atsr_unit(struct pci_dev *dev);
721
722 extern int dmar_enable_qi(struct intel_iommu *iommu);
723 extern void dmar_disable_qi(struct intel_iommu *iommu);
724 extern int dmar_reenable_qi(struct intel_iommu *iommu);
725 extern void qi_global_iec(struct intel_iommu *iommu);
726
727 extern void qi_flush_context(struct intel_iommu *iommu, u16 did, u16 sid,
728 u8 fm, u64 type);
729 extern void qi_flush_iotlb(struct intel_iommu *iommu, u16 did, u64 addr,
730 unsigned int size_order, u64 type);
731 extern void qi_flush_dev_iotlb(struct intel_iommu *iommu, u16 sid, u16 pfsid,
732 u16 qdep, u64 addr, unsigned mask);
733
734 void qi_flush_piotlb(struct intel_iommu *iommu, u16 did, u32 pasid, u64 addr,
735 unsigned long npages, bool ih);
736
737 void qi_flush_dev_iotlb_pasid(struct intel_iommu *iommu, u16 sid, u16 pfsid,
738 u32 pasid, u16 qdep, u64 addr,
739 unsigned int size_order);
740 void qi_flush_pasid_cache(struct intel_iommu *iommu, u16 did, u64 granu,
741 u32 pasid);
742
743 int qi_submit_sync(struct intel_iommu *iommu, struct qi_desc *desc,
744 unsigned int count, unsigned long options);
745 /*
746 * Options used in qi_submit_sync:
747 * QI_OPT_WAIT_DRAIN - Wait for PRQ drain completion, spec 6.5.2.8.
748 */
749 #define QI_OPT_WAIT_DRAIN BIT(0)
750
751 extern int dmar_ir_support(void);
752
753 void *alloc_pgtable_page(int node);
754 void free_pgtable_page(void *vaddr);
755 struct intel_iommu *domain_get_iommu(struct dmar_domain *domain);
756 int for_each_device_domain(int (*fn)(struct device_domain_info *info,
757 void *data), void *data);
758 void iommu_flush_write_buffer(struct intel_iommu *iommu);
759 int intel_iommu_enable_pasid(struct intel_iommu *iommu, struct device *dev);
760 struct dmar_domain *find_domain(struct device *dev);
761 struct device_domain_info *get_domain_info(struct device *dev);
762 struct intel_iommu *device_to_iommu(struct device *dev, u8 *bus, u8 *devfn);
763
764 #ifdef CONFIG_INTEL_IOMMU_SVM
765 extern void intel_svm_check(struct intel_iommu *iommu);
766 extern int intel_svm_enable_prq(struct intel_iommu *iommu);
767 extern int intel_svm_finish_prq(struct intel_iommu *iommu);
768 int intel_svm_bind_gpasid(struct iommu_domain *domain, struct device *dev,
769 struct iommu_gpasid_bind_data *data);
770 int intel_svm_unbind_gpasid(struct device *dev, u32 pasid);
771 struct iommu_sva *intel_svm_bind(struct device *dev, struct mm_struct *mm,
772 void *drvdata);
773 void intel_svm_unbind(struct iommu_sva *handle);
774 u32 intel_svm_get_pasid(struct iommu_sva *handle);
775 int intel_svm_page_response(struct device *dev, struct iommu_fault_event *evt,
776 struct iommu_page_response *msg);
777
778 struct intel_svm_dev {
779 struct list_head list;
780 struct rcu_head rcu;
781 struct device *dev;
782 struct intel_iommu *iommu;
783 struct iommu_sva sva;
784 unsigned long prq_seq_number;
785 u32 pasid;
786 int users;
787 u16 did;
788 u16 dev_iotlb:1;
789 u16 sid, qdep;
790 };
791
792 struct intel_svm {
793 struct mmu_notifier notifier;
794 struct mm_struct *mm;
795
796 unsigned int flags;
797 u32 pasid;
798 int gpasid; /* In case that guest PASID is different from host PASID */
799 struct list_head devs;
800 };
801 #else
intel_svm_check(struct intel_iommu * iommu)802 static inline void intel_svm_check(struct intel_iommu *iommu) {}
803 #endif
804
805 #ifdef CONFIG_INTEL_IOMMU_DEBUGFS
806 void intel_iommu_debugfs_init(void);
807 #else
intel_iommu_debugfs_init(void)808 static inline void intel_iommu_debugfs_init(void) {}
809 #endif /* CONFIG_INTEL_IOMMU_DEBUGFS */
810
811 extern const struct attribute_group *intel_iommu_groups[];
812 bool context_present(struct context_entry *context);
813 struct context_entry *iommu_context_addr(struct intel_iommu *iommu, u8 bus,
814 u8 devfn, int alloc);
815
816 #ifdef CONFIG_INTEL_IOMMU
817 extern int iommu_calculate_agaw(struct intel_iommu *iommu);
818 extern int iommu_calculate_max_sagaw(struct intel_iommu *iommu);
819 extern int dmar_disabled;
820 extern int intel_iommu_enabled;
821 extern int intel_iommu_gfx_mapped;
822 #else
iommu_calculate_agaw(struct intel_iommu * iommu)823 static inline int iommu_calculate_agaw(struct intel_iommu *iommu)
824 {
825 return 0;
826 }
iommu_calculate_max_sagaw(struct intel_iommu * iommu)827 static inline int iommu_calculate_max_sagaw(struct intel_iommu *iommu)
828 {
829 return 0;
830 }
831 #define dmar_disabled (1)
832 #define intel_iommu_enabled (0)
833 #endif
834
decode_prq_descriptor(char * str,size_t size,u64 dw0,u64 dw1,u64 dw2,u64 dw3)835 static inline const char *decode_prq_descriptor(char *str, size_t size,
836 u64 dw0, u64 dw1, u64 dw2, u64 dw3)
837 {
838 char *buf = str;
839 int bytes;
840
841 bytes = snprintf(buf, size,
842 "rid=0x%llx addr=0x%llx %c%c%c%c%c pasid=0x%llx index=0x%llx",
843 FIELD_GET(GENMASK_ULL(31, 16), dw0),
844 FIELD_GET(GENMASK_ULL(63, 12), dw1),
845 dw1 & BIT_ULL(0) ? 'r' : '-',
846 dw1 & BIT_ULL(1) ? 'w' : '-',
847 dw0 & BIT_ULL(52) ? 'x' : '-',
848 dw0 & BIT_ULL(53) ? 'p' : '-',
849 dw1 & BIT_ULL(2) ? 'l' : '-',
850 FIELD_GET(GENMASK_ULL(51, 32), dw0),
851 FIELD_GET(GENMASK_ULL(11, 3), dw1));
852
853 /* Private Data */
854 if (dw0 & BIT_ULL(9)) {
855 size -= bytes;
856 buf += bytes;
857 snprintf(buf, size, " private=0x%llx/0x%llx\n", dw2, dw3);
858 }
859
860 return str;
861 }
862
863 #endif
864