1 /* 2 * Copyright (c) 2014-2021, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <drivers/arm/tzc400.h> 11 #include <lib/utils_def.h> 12 #include <plat/arm/board/common/v2m_def.h> 13 #include <plat/arm/common/arm_def.h> 14 #include <plat/arm/common/arm_spm_def.h> 15 #include <plat/common/common_def.h> 16 17 #include "../fvp_def.h" 18 19 /* Required platform porting definitions */ 20 #define PLATFORM_CORE_COUNT (U(FVP_CLUSTER_COUNT) * \ 21 U(FVP_MAX_CPUS_PER_CLUSTER) * \ 22 U(FVP_MAX_PE_PER_CPU)) 23 24 #define PLAT_NUM_PWR_DOMAINS (U(FVP_CLUSTER_COUNT) + \ 25 PLATFORM_CORE_COUNT + U(1)) 26 27 #define PLAT_MAX_PWR_LVL ARM_PWR_LVL2 28 29 /* 30 * Other platform porting definitions are provided by included headers 31 */ 32 33 /* 34 * Required ARM standard platform porting definitions 35 */ 36 #define PLAT_ARM_CLUSTER_COUNT U(FVP_CLUSTER_COUNT) 37 38 #define PLAT_ARM_TRUSTED_SRAM_SIZE UL(0x00040000) /* 256 KB */ 39 40 #define PLAT_ARM_TRUSTED_ROM_BASE UL(0x00000000) 41 #define PLAT_ARM_TRUSTED_ROM_SIZE UL(0x04000000) /* 64 MB */ 42 43 #define PLAT_ARM_TRUSTED_DRAM_BASE UL(0x06000000) 44 #define PLAT_ARM_TRUSTED_DRAM_SIZE UL(0x02000000) /* 32 MB */ 45 46 /* 47 * Max size of SPMC is 2MB for fvp. With SPMD enabled this value corresponds to 48 * max size of BL32 image. 49 */ 50 #if defined(SPD_spmd) 51 #define PLAT_ARM_SPMC_BASE PLAT_ARM_TRUSTED_DRAM_BASE 52 #define PLAT_ARM_SPMC_SIZE UL(0x200000) /* 2 MB */ 53 #endif 54 55 /* virtual address used by dynamic mem_protect for chunk_base */ 56 #define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xc0000000) 57 58 /* No SCP in FVP */ 59 #define PLAT_ARM_SCP_TZC_DRAM1_SIZE UL(0x0) 60 61 #define PLAT_ARM_DRAM2_BASE ULL(0x880000000) 62 #define PLAT_ARM_DRAM2_SIZE UL(0x80000000) 63 64 #define PLAT_HW_CONFIG_DTB_BASE ULL(0x82000000) 65 #define PLAT_HW_CONFIG_DTB_SIZE ULL(0x8000) 66 67 #define ARM_DTB_DRAM_NS MAP_REGION_FLAT( \ 68 PLAT_HW_CONFIG_DTB_BASE, \ 69 PLAT_HW_CONFIG_DTB_SIZE, \ 70 MT_MEMORY | MT_RO | MT_NS) 71 72 /* Reserve memory for storing FF-A memory descriptors. */ 73 # if SPMC_AT_EL3 74 # define SPMC_SHARED_MEMORY_OBJ_SIZE 16 * 1024 75 #endif 76 77 /* 78 * Load address of BL33 for this platform port 79 */ 80 #define PLAT_ARM_NS_IMAGE_BASE (ARM_DRAM1_BASE + UL(0x8000000)) 81 82 /* 83 * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the 84 * plat_arm_mmap array defined for each BL stage. 85 */ 86 #if defined(IMAGE_BL31) 87 # if SPM_MM || SPMC_AT_EL3 88 # define PLAT_ARM_MMAP_ENTRIES 13 89 # define MAX_XLAT_TABLES 11 90 # define PLAT_SP_IMAGE_MMAP_REGIONS 30 91 # define PLAT_SP_IMAGE_MAX_XLAT_TABLES 10 92 # else 93 # define PLAT_ARM_MMAP_ENTRIES 9 94 # if USE_DEBUGFS 95 # define MAX_XLAT_TABLES 8 96 # else 97 # define MAX_XLAT_TABLES 7 98 # endif 99 # endif 100 #elif defined(IMAGE_BL32) 101 # define PLAT_ARM_MMAP_ENTRIES 270 102 # define MAX_XLAT_TABLES 10 103 #elif !USE_ROMLIB 104 # define PLAT_ARM_MMAP_ENTRIES 11 105 # define MAX_XLAT_TABLES 5 106 #else 107 # define PLAT_ARM_MMAP_ENTRIES 12 108 # define MAX_XLAT_TABLES 6 109 #endif 110 111 /* 112 * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size 113 * plus a little space for growth. 114 */ 115 #define PLAT_ARM_MAX_BL1_RW_SIZE UL(0xB000) 116 117 /* 118 * PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full page 119 */ 120 121 #if USE_ROMLIB 122 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0x1000) 123 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0xe000) 124 #define FVP_BL2_ROMLIB_OPTIMIZATION UL(0x5000) 125 #else 126 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0) 127 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0) 128 #define FVP_BL2_ROMLIB_OPTIMIZATION UL(0) 129 #endif 130 131 /* 132 * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a 133 * little space for growth. 134 */ 135 #if TRUSTED_BOARD_BOOT 136 #if COT_DESC_IN_DTB 137 # define PLAT_ARM_MAX_BL2_SIZE (UL(0x1E000) - FVP_BL2_ROMLIB_OPTIMIZATION) 138 #else 139 # define PLAT_ARM_MAX_BL2_SIZE (UL(0x1D000) - FVP_BL2_ROMLIB_OPTIMIZATION) 140 #endif 141 #else 142 # define PLAT_ARM_MAX_BL2_SIZE (UL(0x13000) - FVP_BL2_ROMLIB_OPTIMIZATION) 143 #endif 144 145 #if RESET_TO_BL31 146 /* Size of Trusted SRAM - the first 4KB of shared memory */ 147 #define PLAT_ARM_MAX_BL31_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ 148 ARM_SHARED_RAM_SIZE) 149 #else 150 /* 151 * Since BL31 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL31_SIZE is 152 * calculated using the current BL31 PROGBITS debug size plus the sizes of 153 * BL2 and BL1-RW 154 */ 155 #define PLAT_ARM_MAX_BL31_SIZE UL(0x3D000) 156 #endif /* RESET_TO_BL31 */ 157 158 #ifndef __aarch64__ 159 #if RESET_TO_SP_MIN 160 /* Size of Trusted SRAM - the first 4KB of shared memory */ 161 #define PLAT_ARM_MAX_BL32_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ 162 ARM_SHARED_RAM_SIZE) 163 #else 164 /* 165 * Since BL32 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL32_SIZE is 166 * calculated using the current SP_MIN PROGBITS debug size plus the sizes of 167 * BL2 and BL1-RW 168 */ 169 # define PLAT_ARM_MAX_BL32_SIZE UL(0x3B000) 170 #endif /* RESET_TO_SP_MIN */ 171 #endif 172 173 /* 174 * Size of cacheable stacks 175 */ 176 #if defined(IMAGE_BL1) 177 # if TRUSTED_BOARD_BOOT 178 # define PLATFORM_STACK_SIZE UL(0x1000) 179 # else 180 # define PLATFORM_STACK_SIZE UL(0x500) 181 # endif 182 #elif defined(IMAGE_BL2) 183 # if TRUSTED_BOARD_BOOT 184 # define PLATFORM_STACK_SIZE UL(0x1000) 185 # else 186 # define PLATFORM_STACK_SIZE UL(0x440) 187 # endif 188 #elif defined(IMAGE_BL2U) 189 # define PLATFORM_STACK_SIZE UL(0x400) 190 #elif defined(IMAGE_BL31) 191 # define PLATFORM_STACK_SIZE UL(0x800) 192 #elif defined(IMAGE_BL32) 193 # define PLATFORM_STACK_SIZE UL(0x440) 194 #endif 195 196 #define MAX_IO_DEVICES 3 197 #define MAX_IO_HANDLES 4 198 199 /* Reserve the last block of flash for PSCI MEM PROTECT flag */ 200 #define PLAT_ARM_FLASH_IMAGE_BASE V2M_FLASH0_BASE 201 #define PLAT_ARM_FLASH_IMAGE_MAX_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) 202 203 #if ARM_GPT_SUPPORT 204 /* 205 * Offset of the FIP in the GPT image. BL1 component uses this option 206 * as it does not load the partition table to get the FIP base 207 * address. At sector 34 by default (i.e. after reserved sectors 0-33) 208 * Offset = 34 * 512(sector size) = 17408 i.e. 0x4400 209 */ 210 #define PLAT_ARM_FIP_OFFSET_IN_GPT 0x4400 211 #endif /* ARM_GPT_SUPPORT */ 212 213 #define PLAT_ARM_NVM_BASE V2M_FLASH0_BASE 214 #define PLAT_ARM_NVM_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) 215 216 /* 217 * PL011 related constants 218 */ 219 #define PLAT_ARM_BOOT_UART_BASE V2M_IOFPGA_UART0_BASE 220 #define PLAT_ARM_BOOT_UART_CLK_IN_HZ V2M_IOFPGA_UART0_CLK_IN_HZ 221 222 #define PLAT_ARM_RUN_UART_BASE V2M_IOFPGA_UART1_BASE 223 #define PLAT_ARM_RUN_UART_CLK_IN_HZ V2M_IOFPGA_UART1_CLK_IN_HZ 224 225 #define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_RUN_UART_BASE 226 #define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_RUN_UART_CLK_IN_HZ 227 228 #define PLAT_ARM_TSP_UART_BASE V2M_IOFPGA_UART2_BASE 229 #define PLAT_ARM_TSP_UART_CLK_IN_HZ V2M_IOFPGA_UART2_CLK_IN_HZ 230 231 #define PLAT_FVP_SMMUV3_BASE UL(0x2b400000) 232 233 /* CCI related constants */ 234 #define PLAT_FVP_CCI400_BASE UL(0x2c090000) 235 #define PLAT_FVP_CCI400_CLUS0_SL_PORT 3 236 #define PLAT_FVP_CCI400_CLUS1_SL_PORT 4 237 238 /* CCI-500/CCI-550 on Base platform */ 239 #define PLAT_FVP_CCI5XX_BASE UL(0x2a000000) 240 #define PLAT_FVP_CCI5XX_CLUS0_SL_PORT 5 241 #define PLAT_FVP_CCI5XX_CLUS1_SL_PORT 6 242 243 /* CCN related constants. Only CCN 502 is currently supported */ 244 #define PLAT_ARM_CCN_BASE UL(0x2e000000) 245 #define PLAT_ARM_CLUSTER_TO_CCN_ID_MAP 1, 5, 7, 11 246 247 /* System timer related constants */ 248 #define PLAT_ARM_NSTIMER_FRAME_ID U(1) 249 250 /* Mailbox base address */ 251 #define PLAT_ARM_TRUSTED_MAILBOX_BASE ARM_TRUSTED_SRAM_BASE 252 253 254 /* TrustZone controller related constants 255 * 256 * Currently only filters 0 and 2 are connected on Base FVP. 257 * Filter 0 : CPU clusters (no access to DRAM by default) 258 * Filter 1 : not connected 259 * Filter 2 : LCDs (access to VRAM allowed by default) 260 * Filter 3 : not connected 261 * Programming unconnected filters will have no effect at the 262 * moment. These filter could, however, be connected in future. 263 * So care should be taken not to configure the unused filters. 264 * 265 * Allow only non-secure access to all DRAM to supported devices. 266 * Give access to the CPUs and Virtio. Some devices 267 * would normally use the default ID so allow that too. 268 */ 269 #define PLAT_ARM_TZC_BASE UL(0x2a4a0000) 270 #define PLAT_ARM_TZC_FILTERS TZC_400_REGION_ATTR_FILTER_BIT(0) 271 272 #define PLAT_ARM_TZC_NS_DEV_ACCESS ( \ 273 TZC_REGION_ACCESS_RDWR(FVP_NSAID_DEFAULT) | \ 274 TZC_REGION_ACCESS_RDWR(FVP_NSAID_PCI) | \ 275 TZC_REGION_ACCESS_RDWR(FVP_NSAID_AP) | \ 276 TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO) | \ 277 TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO_OLD)) 278 279 /* 280 * GIC related constants to cater for both GICv2 and GICv3 instances of an 281 * FVP. They could be overridden at runtime in case the FVP implements the 282 * legacy VE memory map. 283 */ 284 #define PLAT_ARM_GICD_BASE BASE_GICD_BASE 285 #define PLAT_ARM_GICR_BASE BASE_GICR_BASE 286 #define PLAT_ARM_GICC_BASE BASE_GICC_BASE 287 288 /* 289 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 290 * terminology. On a GICv2 system or mode, the lists will be merged and treated 291 * as Group 0 interrupts. 292 */ 293 #define PLAT_ARM_G1S_IRQ_PROPS(grp) \ 294 ARM_G1S_IRQ_PROPS(grp), \ 295 INTR_PROP_DESC(FVP_IRQ_TZ_WDOG, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 296 GIC_INTR_CFG_LEVEL), \ 297 INTR_PROP_DESC(FVP_IRQ_SEC_SYS_TIMER, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 298 GIC_INTR_CFG_LEVEL) 299 300 #define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp) 301 302 #if SDEI_IN_FCONF 303 #define PLAT_SDEI_DP_EVENT_MAX_CNT ARM_SDEI_DP_EVENT_MAX_CNT 304 #define PLAT_SDEI_DS_EVENT_MAX_CNT ARM_SDEI_DS_EVENT_MAX_CNT 305 #else 306 #define PLAT_ARM_PRIVATE_SDEI_EVENTS ARM_SDEI_PRIVATE_EVENTS 307 #define PLAT_ARM_SHARED_SDEI_EVENTS ARM_SDEI_SHARED_EVENTS 308 #endif 309 310 #define PLAT_ARM_SP_IMAGE_STACK_BASE (PLAT_SP_IMAGE_NS_BUF_BASE + \ 311 PLAT_SP_IMAGE_NS_BUF_SIZE) 312 313 #define PLAT_SP_PRI PLAT_RAS_PRI 314 315 /* 316 * Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes 317 */ 318 #ifdef __aarch64__ 319 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 36) 320 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 36) 321 #else 322 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 323 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 324 #endif 325 326 #endif /* PLATFORM_DEF_H */ 327