1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2009 Felix Fietkau <nbd@nbd.name> 4 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org> 5 * Copyright (c) 2015, The Linux Foundation. All rights reserved. 6 */ 7 8 #ifndef __QCA8K_H 9 #define __QCA8K_H 10 11 #include <linux/delay.h> 12 #include <linux/regmap.h> 13 #include <linux/gpio.h> 14 15 #define QCA8K_NUM_PORTS 7 16 #define QCA8K_NUM_CPU_PORTS 2 17 #define QCA8K_MAX_MTU 9000 18 19 #define PHY_ID_QCA8327 0x004dd034 20 #define QCA8K_ID_QCA8327 0x12 21 #define PHY_ID_QCA8337 0x004dd036 22 #define QCA8K_ID_QCA8337 0x13 23 24 #define QCA8K_BUSY_WAIT_TIMEOUT 2000 25 26 #define QCA8K_NUM_FDB_RECORDS 2048 27 28 #define QCA8K_PORT_VID_DEF 1 29 30 /* Global control registers */ 31 #define QCA8K_REG_MASK_CTRL 0x000 32 #define QCA8K_MASK_CTRL_REV_ID_MASK GENMASK(7, 0) 33 #define QCA8K_MASK_CTRL_REV_ID(x) ((x) >> 0) 34 #define QCA8K_MASK_CTRL_DEVICE_ID_MASK GENMASK(15, 8) 35 #define QCA8K_MASK_CTRL_DEVICE_ID(x) ((x) >> 8) 36 #define QCA8K_REG_PORT0_PAD_CTRL 0x004 37 #define QCA8K_PORT0_PAD_MAC06_EXCHANGE_EN BIT(31) 38 #define QCA8K_PORT0_PAD_SGMII_RXCLK_FALLING_EDGE BIT(19) 39 #define QCA8K_PORT0_PAD_SGMII_TXCLK_FALLING_EDGE BIT(18) 40 #define QCA8K_REG_PORT5_PAD_CTRL 0x008 41 #define QCA8K_REG_PORT6_PAD_CTRL 0x00c 42 #define QCA8K_PORT_PAD_RGMII_EN BIT(26) 43 #define QCA8K_PORT_PAD_RGMII_TX_DELAY_MASK GENMASK(23, 22) 44 #define QCA8K_PORT_PAD_RGMII_TX_DELAY(x) ((x) << 22) 45 #define QCA8K_PORT_PAD_RGMII_RX_DELAY_MASK GENMASK(21, 20) 46 #define QCA8K_PORT_PAD_RGMII_RX_DELAY(x) ((x) << 20) 47 #define QCA8K_PORT_PAD_RGMII_TX_DELAY_EN BIT(25) 48 #define QCA8K_PORT_PAD_RGMII_RX_DELAY_EN BIT(24) 49 #define QCA8K_MAX_DELAY 3 50 #define QCA8K_PORT_PAD_SGMII_EN BIT(7) 51 #define QCA8K_REG_PWS 0x010 52 #define QCA8K_PWS_POWER_ON_SEL BIT(31) 53 /* This reg is only valid for QCA832x and toggle the package 54 * type from 176 pin (by default) to 148 pin used on QCA8327 55 */ 56 #define QCA8327_PWS_PACKAGE148_EN BIT(30) 57 #define QCA8K_PWS_LED_OPEN_EN_CSR BIT(24) 58 #define QCA8K_PWS_SERDES_AEN_DIS BIT(7) 59 #define QCA8K_REG_MODULE_EN 0x030 60 #define QCA8K_MODULE_EN_MIB BIT(0) 61 #define QCA8K_REG_MIB 0x034 62 #define QCA8K_MIB_FLUSH BIT(24) 63 #define QCA8K_MIB_CPU_KEEP BIT(20) 64 #define QCA8K_MIB_BUSY BIT(17) 65 #define QCA8K_MDIO_MASTER_CTRL 0x3c 66 #define QCA8K_MDIO_MASTER_BUSY BIT(31) 67 #define QCA8K_MDIO_MASTER_EN BIT(30) 68 #define QCA8K_MDIO_MASTER_READ BIT(27) 69 #define QCA8K_MDIO_MASTER_WRITE 0 70 #define QCA8K_MDIO_MASTER_SUP_PRE BIT(26) 71 #define QCA8K_MDIO_MASTER_PHY_ADDR(x) ((x) << 21) 72 #define QCA8K_MDIO_MASTER_REG_ADDR(x) ((x) << 16) 73 #define QCA8K_MDIO_MASTER_DATA(x) (x) 74 #define QCA8K_MDIO_MASTER_DATA_MASK GENMASK(15, 0) 75 #define QCA8K_MDIO_MASTER_MAX_PORTS 5 76 #define QCA8K_MDIO_MASTER_MAX_REG 32 77 #define QCA8K_GOL_MAC_ADDR0 0x60 78 #define QCA8K_GOL_MAC_ADDR1 0x64 79 #define QCA8K_MAX_FRAME_SIZE 0x78 80 #define QCA8K_REG_PORT_STATUS(_i) (0x07c + (_i) * 4) 81 #define QCA8K_PORT_STATUS_SPEED GENMASK(1, 0) 82 #define QCA8K_PORT_STATUS_SPEED_10 0 83 #define QCA8K_PORT_STATUS_SPEED_100 0x1 84 #define QCA8K_PORT_STATUS_SPEED_1000 0x2 85 #define QCA8K_PORT_STATUS_TXMAC BIT(2) 86 #define QCA8K_PORT_STATUS_RXMAC BIT(3) 87 #define QCA8K_PORT_STATUS_TXFLOW BIT(4) 88 #define QCA8K_PORT_STATUS_RXFLOW BIT(5) 89 #define QCA8K_PORT_STATUS_DUPLEX BIT(6) 90 #define QCA8K_PORT_STATUS_LINK_UP BIT(8) 91 #define QCA8K_PORT_STATUS_LINK_AUTO BIT(9) 92 #define QCA8K_PORT_STATUS_LINK_PAUSE BIT(10) 93 #define QCA8K_PORT_STATUS_FLOW_AUTO BIT(12) 94 #define QCA8K_REG_PORT_HDR_CTRL(_i) (0x9c + (_i * 4)) 95 #define QCA8K_PORT_HDR_CTRL_RX_MASK GENMASK(3, 2) 96 #define QCA8K_PORT_HDR_CTRL_RX_S 2 97 #define QCA8K_PORT_HDR_CTRL_TX_MASK GENMASK(1, 0) 98 #define QCA8K_PORT_HDR_CTRL_TX_S 0 99 #define QCA8K_PORT_HDR_CTRL_ALL 2 100 #define QCA8K_PORT_HDR_CTRL_MGMT 1 101 #define QCA8K_PORT_HDR_CTRL_NONE 0 102 #define QCA8K_REG_SGMII_CTRL 0x0e0 103 #define QCA8K_SGMII_EN_PLL BIT(1) 104 #define QCA8K_SGMII_EN_RX BIT(2) 105 #define QCA8K_SGMII_EN_TX BIT(3) 106 #define QCA8K_SGMII_EN_SD BIT(4) 107 #define QCA8K_SGMII_CLK125M_DELAY BIT(7) 108 #define QCA8K_SGMII_MODE_CTRL_MASK (BIT(22) | BIT(23)) 109 #define QCA8K_SGMII_MODE_CTRL_BASEX (0 << 22) 110 #define QCA8K_SGMII_MODE_CTRL_PHY (1 << 22) 111 #define QCA8K_SGMII_MODE_CTRL_MAC (2 << 22) 112 113 /* MAC_PWR_SEL registers */ 114 #define QCA8K_REG_MAC_PWR_SEL 0x0e4 115 #define QCA8K_MAC_PWR_RGMII1_1_8V BIT(18) 116 #define QCA8K_MAC_PWR_RGMII0_1_8V BIT(19) 117 118 /* EEE control registers */ 119 #define QCA8K_REG_EEE_CTRL 0x100 120 #define QCA8K_REG_EEE_CTRL_LPI_EN(_i) ((_i + 1) * 2) 121 122 /* ACL registers */ 123 #define QCA8K_REG_PORT_VLAN_CTRL0(_i) (0x420 + (_i * 8)) 124 #define QCA8K_PORT_VLAN_CVID(x) (x << 16) 125 #define QCA8K_PORT_VLAN_SVID(x) x 126 #define QCA8K_REG_PORT_VLAN_CTRL1(_i) (0x424 + (_i * 8)) 127 #define QCA8K_REG_IPV4_PRI_BASE_ADDR 0x470 128 #define QCA8K_REG_IPV4_PRI_ADDR_MASK 0x474 129 130 /* Lookup registers */ 131 #define QCA8K_REG_ATU_DATA0 0x600 132 #define QCA8K_ATU_ADDR2_S 24 133 #define QCA8K_ATU_ADDR3_S 16 134 #define QCA8K_ATU_ADDR4_S 8 135 #define QCA8K_REG_ATU_DATA1 0x604 136 #define QCA8K_ATU_PORT_M 0x7f 137 #define QCA8K_ATU_PORT_S 16 138 #define QCA8K_ATU_ADDR0_S 8 139 #define QCA8K_REG_ATU_DATA2 0x608 140 #define QCA8K_ATU_VID_M 0xfff 141 #define QCA8K_ATU_VID_S 8 142 #define QCA8K_ATU_STATUS_M 0xf 143 #define QCA8K_ATU_STATUS_STATIC 0xf 144 #define QCA8K_REG_ATU_FUNC 0x60c 145 #define QCA8K_ATU_FUNC_BUSY BIT(31) 146 #define QCA8K_ATU_FUNC_PORT_EN BIT(14) 147 #define QCA8K_ATU_FUNC_MULTI_EN BIT(13) 148 #define QCA8K_ATU_FUNC_FULL BIT(12) 149 #define QCA8K_ATU_FUNC_PORT_M 0xf 150 #define QCA8K_ATU_FUNC_PORT_S 8 151 #define QCA8K_REG_VTU_FUNC0 0x610 152 #define QCA8K_VTU_FUNC0_VALID BIT(20) 153 #define QCA8K_VTU_FUNC0_IVL_EN BIT(19) 154 #define QCA8K_VTU_FUNC0_EG_MODE_S(_i) (4 + (_i) * 2) 155 #define QCA8K_VTU_FUNC0_EG_MODE_MASK 3 156 #define QCA8K_VTU_FUNC0_EG_MODE_UNMOD 0 157 #define QCA8K_VTU_FUNC0_EG_MODE_UNTAG 1 158 #define QCA8K_VTU_FUNC0_EG_MODE_TAG 2 159 #define QCA8K_VTU_FUNC0_EG_MODE_NOT 3 160 #define QCA8K_REG_VTU_FUNC1 0x614 161 #define QCA8K_VTU_FUNC1_BUSY BIT(31) 162 #define QCA8K_VTU_FUNC1_VID_S 16 163 #define QCA8K_VTU_FUNC1_FULL BIT(4) 164 #define QCA8K_REG_GLOBAL_FW_CTRL0 0x620 165 #define QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN BIT(10) 166 #define QCA8K_REG_GLOBAL_FW_CTRL1 0x624 167 #define QCA8K_GLOBAL_FW_CTRL1_IGMP_DP_S 24 168 #define QCA8K_GLOBAL_FW_CTRL1_BC_DP_S 16 169 #define QCA8K_GLOBAL_FW_CTRL1_MC_DP_S 8 170 #define QCA8K_GLOBAL_FW_CTRL1_UC_DP_S 0 171 #define QCA8K_PORT_LOOKUP_CTRL(_i) (0x660 + (_i) * 0xc) 172 #define QCA8K_PORT_LOOKUP_MEMBER GENMASK(6, 0) 173 #define QCA8K_PORT_LOOKUP_VLAN_MODE GENMASK(9, 8) 174 #define QCA8K_PORT_LOOKUP_VLAN_MODE_NONE (0 << 8) 175 #define QCA8K_PORT_LOOKUP_VLAN_MODE_FALLBACK (1 << 8) 176 #define QCA8K_PORT_LOOKUP_VLAN_MODE_CHECK (2 << 8) 177 #define QCA8K_PORT_LOOKUP_VLAN_MODE_SECURE (3 << 8) 178 #define QCA8K_PORT_LOOKUP_STATE_MASK GENMASK(18, 16) 179 #define QCA8K_PORT_LOOKUP_STATE_DISABLED (0 << 16) 180 #define QCA8K_PORT_LOOKUP_STATE_BLOCKING (1 << 16) 181 #define QCA8K_PORT_LOOKUP_STATE_LISTENING (2 << 16) 182 #define QCA8K_PORT_LOOKUP_STATE_LEARNING (3 << 16) 183 #define QCA8K_PORT_LOOKUP_STATE_FORWARD (4 << 16) 184 #define QCA8K_PORT_LOOKUP_STATE GENMASK(18, 16) 185 #define QCA8K_PORT_LOOKUP_LEARN BIT(20) 186 187 #define QCA8K_REG_GLOBAL_FC_THRESH 0x800 188 #define QCA8K_GLOBAL_FC_GOL_XON_THRES(x) ((x) << 16) 189 #define QCA8K_GLOBAL_FC_GOL_XON_THRES_S GENMASK(24, 16) 190 #define QCA8K_GLOBAL_FC_GOL_XOFF_THRES(x) ((x) << 0) 191 #define QCA8K_GLOBAL_FC_GOL_XOFF_THRES_S GENMASK(8, 0) 192 193 #define QCA8K_REG_PORT_HOL_CTRL0(_i) (0x970 + (_i) * 0x8) 194 #define QCA8K_PORT_HOL_CTRL0_EG_PRI0_BUF GENMASK(3, 0) 195 #define QCA8K_PORT_HOL_CTRL0_EG_PRI0(x) ((x) << 0) 196 #define QCA8K_PORT_HOL_CTRL0_EG_PRI1_BUF GENMASK(7, 4) 197 #define QCA8K_PORT_HOL_CTRL0_EG_PRI1(x) ((x) << 4) 198 #define QCA8K_PORT_HOL_CTRL0_EG_PRI2_BUF GENMASK(11, 8) 199 #define QCA8K_PORT_HOL_CTRL0_EG_PRI2(x) ((x) << 8) 200 #define QCA8K_PORT_HOL_CTRL0_EG_PRI3_BUF GENMASK(15, 12) 201 #define QCA8K_PORT_HOL_CTRL0_EG_PRI3(x) ((x) << 12) 202 #define QCA8K_PORT_HOL_CTRL0_EG_PRI4_BUF GENMASK(19, 16) 203 #define QCA8K_PORT_HOL_CTRL0_EG_PRI4(x) ((x) << 16) 204 #define QCA8K_PORT_HOL_CTRL0_EG_PRI5_BUF GENMASK(23, 20) 205 #define QCA8K_PORT_HOL_CTRL0_EG_PRI5(x) ((x) << 20) 206 #define QCA8K_PORT_HOL_CTRL0_EG_PORT_BUF GENMASK(29, 24) 207 #define QCA8K_PORT_HOL_CTRL0_EG_PORT(x) ((x) << 24) 208 209 #define QCA8K_REG_PORT_HOL_CTRL1(_i) (0x974 + (_i) * 0x8) 210 #define QCA8K_PORT_HOL_CTRL1_ING_BUF GENMASK(3, 0) 211 #define QCA8K_PORT_HOL_CTRL1_ING(x) ((x) << 0) 212 #define QCA8K_PORT_HOL_CTRL1_EG_PRI_BUF_EN BIT(6) 213 #define QCA8K_PORT_HOL_CTRL1_EG_PORT_BUF_EN BIT(7) 214 #define QCA8K_PORT_HOL_CTRL1_WRED_EN BIT(8) 215 #define QCA8K_PORT_HOL_CTRL1_EG_MIRROR_EN BIT(16) 216 217 /* Pkt edit registers */ 218 #define QCA8K_EGRESS_VLAN(x) (0x0c70 + (4 * (x / 2))) 219 220 /* L3 registers */ 221 #define QCA8K_HROUTER_CONTROL 0xe00 222 #define QCA8K_HROUTER_CONTROL_GLB_LOCKTIME_M GENMASK(17, 16) 223 #define QCA8K_HROUTER_CONTROL_GLB_LOCKTIME_S 16 224 #define QCA8K_HROUTER_CONTROL_ARP_AGE_MODE 1 225 #define QCA8K_HROUTER_PBASED_CONTROL1 0xe08 226 #define QCA8K_HROUTER_PBASED_CONTROL2 0xe0c 227 #define QCA8K_HNAT_CONTROL 0xe38 228 229 /* MIB registers */ 230 #define QCA8K_PORT_MIB_COUNTER(_i) (0x1000 + (_i) * 0x100) 231 232 /* QCA specific MII registers */ 233 #define MII_ATH_MMD_ADDR 0x0d 234 #define MII_ATH_MMD_DATA 0x0e 235 236 enum { 237 QCA8K_PORT_SPEED_10M = 0, 238 QCA8K_PORT_SPEED_100M = 1, 239 QCA8K_PORT_SPEED_1000M = 2, 240 QCA8K_PORT_SPEED_ERR = 3, 241 }; 242 243 enum qca8k_fdb_cmd { 244 QCA8K_FDB_FLUSH = 1, 245 QCA8K_FDB_LOAD = 2, 246 QCA8K_FDB_PURGE = 3, 247 QCA8K_FDB_NEXT = 6, 248 QCA8K_FDB_SEARCH = 7, 249 }; 250 251 enum qca8k_vlan_cmd { 252 QCA8K_VLAN_FLUSH = 1, 253 QCA8K_VLAN_LOAD = 2, 254 QCA8K_VLAN_PURGE = 3, 255 QCA8K_VLAN_REMOVE_PORT = 4, 256 QCA8K_VLAN_NEXT = 5, 257 QCA8K_VLAN_READ = 6, 258 }; 259 260 struct ar8xxx_port_status { 261 int enabled; 262 }; 263 264 struct qca8k_match_data { 265 u8 id; 266 bool reduced_package; 267 }; 268 269 enum { 270 QCA8K_CPU_PORT0, 271 QCA8K_CPU_PORT6, 272 }; 273 274 struct qca8k_ports_config { 275 bool sgmii_rx_clk_falling_edge; 276 bool sgmii_tx_clk_falling_edge; 277 bool sgmii_enable_pll; 278 u8 rgmii_rx_delay[QCA8K_NUM_CPU_PORTS]; /* 0: CPU port0, 1: CPU port6 */ 279 u8 rgmii_tx_delay[QCA8K_NUM_CPU_PORTS]; /* 0: CPU port0, 1: CPU port6 */ 280 }; 281 282 struct qca8k_priv { 283 u8 switch_id; 284 u8 switch_revision; 285 bool legacy_phy_port_mapping; 286 struct qca8k_ports_config ports_config; 287 struct regmap *regmap; 288 struct mii_bus *bus; 289 struct ar8xxx_port_status port_sts[QCA8K_NUM_PORTS]; 290 struct dsa_switch *ds; 291 struct mutex reg_mutex; 292 struct device *dev; 293 struct dsa_switch_ops ops; 294 struct gpio_desc *reset_gpio; 295 unsigned int port_mtu[QCA8K_NUM_PORTS]; 296 }; 297 298 struct qca8k_mib_desc { 299 unsigned int size; 300 unsigned int offset; 301 const char *name; 302 }; 303 304 struct qca8k_fdb { 305 u16 vid; 306 u8 port_mask; 307 u8 aging; 308 u8 mac[6]; 309 }; 310 311 #endif /* __QCA8K_H */ 312