1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2019-2020 Realtek Corporation
3 */
4
5 #ifndef __RTW89_MAC_H__
6 #define __RTW89_MAC_H__
7
8 #include "core.h"
9
10 #define MAC_MEM_DUMP_PAGE_SIZE 0x40000
11 #define ADDR_CAM_ENT_SIZE 0x40
12 #define BSSID_CAM_ENT_SIZE 0x08
13 #define HFC_PAGE_UNIT 64
14
15 enum rtw89_mac_hwmod_sel {
16 RTW89_DMAC_SEL = 0,
17 RTW89_CMAC_SEL = 1,
18
19 RTW89_MAC_INVALID,
20 };
21
22 enum rtw89_mac_fwd_target {
23 RTW89_FWD_DONT_CARE = 0,
24 RTW89_FWD_TO_HOST = 1,
25 RTW89_FWD_TO_WLAN_CPU = 2
26 };
27
28 enum rtw89_mac_wd_dma_intvl {
29 RTW89_MAC_WD_DMA_INTVL_0S,
30 RTW89_MAC_WD_DMA_INTVL_256NS,
31 RTW89_MAC_WD_DMA_INTVL_512NS,
32 RTW89_MAC_WD_DMA_INTVL_768NS,
33 RTW89_MAC_WD_DMA_INTVL_1US,
34 RTW89_MAC_WD_DMA_INTVL_1_5US,
35 RTW89_MAC_WD_DMA_INTVL_2US,
36 RTW89_MAC_WD_DMA_INTVL_4US,
37 RTW89_MAC_WD_DMA_INTVL_8US,
38 RTW89_MAC_WD_DMA_INTVL_16US,
39 RTW89_MAC_WD_DMA_INTVL_DEF = 0xFE
40 };
41
42 enum rtw89_mac_multi_tag_num {
43 RTW89_MAC_TAG_NUM_1,
44 RTW89_MAC_TAG_NUM_2,
45 RTW89_MAC_TAG_NUM_3,
46 RTW89_MAC_TAG_NUM_4,
47 RTW89_MAC_TAG_NUM_5,
48 RTW89_MAC_TAG_NUM_6,
49 RTW89_MAC_TAG_NUM_7,
50 RTW89_MAC_TAG_NUM_8,
51 RTW89_MAC_TAG_NUM_DEF = 0xFE
52 };
53
54 enum rtw89_mac_lbc_tmr {
55 RTW89_MAC_LBC_TMR_8US = 0,
56 RTW89_MAC_LBC_TMR_16US,
57 RTW89_MAC_LBC_TMR_32US,
58 RTW89_MAC_LBC_TMR_64US,
59 RTW89_MAC_LBC_TMR_128US,
60 RTW89_MAC_LBC_TMR_256US,
61 RTW89_MAC_LBC_TMR_512US,
62 RTW89_MAC_LBC_TMR_1MS,
63 RTW89_MAC_LBC_TMR_2MS,
64 RTW89_MAC_LBC_TMR_4MS,
65 RTW89_MAC_LBC_TMR_8MS,
66 RTW89_MAC_LBC_TMR_DEF = 0xFE
67 };
68
69 enum rtw89_mac_cpuio_op_cmd_type {
70 CPUIO_OP_CMD_GET_1ST_PID = 0,
71 CPUIO_OP_CMD_GET_NEXT_PID = 1,
72 CPUIO_OP_CMD_ENQ_TO_TAIL = 4,
73 CPUIO_OP_CMD_ENQ_TO_HEAD = 5,
74 CPUIO_OP_CMD_DEQ = 8,
75 CPUIO_OP_CMD_DEQ_ENQ_ALL = 9,
76 CPUIO_OP_CMD_DEQ_ENQ_TO_TAIL = 12
77 };
78
79 enum rtw89_mac_wde_dle_port_id {
80 WDE_DLE_PORT_ID_DISPATCH = 0,
81 WDE_DLE_PORT_ID_PKTIN = 1,
82 WDE_DLE_PORT_ID_CMAC0 = 3,
83 WDE_DLE_PORT_ID_CMAC1 = 4,
84 WDE_DLE_PORT_ID_CPU_IO = 6,
85 WDE_DLE_PORT_ID_WDRLS = 7,
86 WDE_DLE_PORT_ID_END = 8
87 };
88
89 enum rtw89_mac_wde_dle_queid_wdrls {
90 WDE_DLE_QUEID_TXOK = 0,
91 WDE_DLE_QUEID_DROP_RETRY_LIMIT = 1,
92 WDE_DLE_QUEID_DROP_LIFETIME_TO = 2,
93 WDE_DLE_QUEID_DROP_MACID_DROP = 3,
94 WDE_DLE_QUEID_NO_REPORT = 4
95 };
96
97 enum rtw89_mac_ple_dle_port_id {
98 PLE_DLE_PORT_ID_DISPATCH = 0,
99 PLE_DLE_PORT_ID_MPDU = 1,
100 PLE_DLE_PORT_ID_SEC = 2,
101 PLE_DLE_PORT_ID_CMAC0 = 3,
102 PLE_DLE_PORT_ID_CMAC1 = 4,
103 PLE_DLE_PORT_ID_WDRLS = 5,
104 PLE_DLE_PORT_ID_CPU_IO = 6,
105 PLE_DLE_PORT_ID_PLRLS = 7,
106 PLE_DLE_PORT_ID_END = 8
107 };
108
109 enum rtw89_mac_ple_dle_queid_plrls {
110 PLE_DLE_QUEID_NO_REPORT = 0x0
111 };
112
113 enum rtw89_machdr_frame_type {
114 RTW89_MGNT = 0,
115 RTW89_CTRL = 1,
116 RTW89_DATA = 2,
117 };
118
119 enum rtw89_mac_dle_dfi_type {
120 DLE_DFI_TYPE_FREEPG = 0,
121 DLE_DFI_TYPE_QUOTA = 1,
122 DLE_DFI_TYPE_PAGELLT = 2,
123 DLE_DFI_TYPE_PKTINFO = 3,
124 DLE_DFI_TYPE_PREPKTLLT = 4,
125 DLE_DFI_TYPE_NXTPKTLLT = 5,
126 DLE_DFI_TYPE_QLNKTBL = 6,
127 DLE_DFI_TYPE_QEMPTY = 7,
128 };
129
130 enum rtw89_mac_dle_wde_quota_id {
131 WDE_QTAID_HOST_IF = 0,
132 WDE_QTAID_WLAN_CPU = 1,
133 WDE_QTAID_DATA_CPU = 2,
134 WDE_QTAID_PKTIN = 3,
135 WDE_QTAID_CPUIO = 4,
136 };
137
138 enum rtw89_mac_dle_ple_quota_id {
139 PLE_QTAID_B0_TXPL = 0,
140 PLE_QTAID_B1_TXPL = 1,
141 PLE_QTAID_C2H = 2,
142 PLE_QTAID_H2C = 3,
143 PLE_QTAID_WLAN_CPU = 4,
144 PLE_QTAID_MPDU = 5,
145 PLE_QTAID_CMAC0_RX = 6,
146 PLE_QTAID_CMAC1_RX = 7,
147 PLE_QTAID_CMAC1_BBRPT = 8,
148 PLE_QTAID_WDRLS = 9,
149 PLE_QTAID_CPUIO = 10,
150 };
151
152 enum rtw89_mac_dle_ctrl_type {
153 DLE_CTRL_TYPE_WDE = 0,
154 DLE_CTRL_TYPE_PLE = 1,
155 DLE_CTRL_TYPE_NUM = 2,
156 };
157
158 enum rtw89_mac_ax_l0_to_l1_event {
159 MAC_AX_L0_TO_L1_CHIF_IDLE = 0,
160 MAC_AX_L0_TO_L1_CMAC_DMA_IDLE = 1,
161 MAC_AX_L0_TO_L1_RLS_PKID = 2,
162 MAC_AX_L0_TO_L1_PTCL_IDLE = 3,
163 MAC_AX_L0_TO_L1_RX_QTA_LOST = 4,
164 MAC_AX_L0_TO_L1_DLE_STAT_HANG = 5,
165 MAC_AX_L0_TO_L1_PCIE_STUCK = 6,
166 MAC_AX_L0_TO_L1_EVENT_MAX = 15,
167 };
168
169 enum rtw89_mac_dbg_port_sel {
170 /* CMAC 0 related */
171 RTW89_DBG_PORT_SEL_PTCL_C0 = 0,
172 RTW89_DBG_PORT_SEL_SCH_C0,
173 RTW89_DBG_PORT_SEL_TMAC_C0,
174 RTW89_DBG_PORT_SEL_RMAC_C0,
175 RTW89_DBG_PORT_SEL_RMACST_C0,
176 RTW89_DBG_PORT_SEL_RMAC_PLCP_C0,
177 RTW89_DBG_PORT_SEL_TRXPTCL_C0,
178 RTW89_DBG_PORT_SEL_TX_INFOL_C0,
179 RTW89_DBG_PORT_SEL_TX_INFOH_C0,
180 RTW89_DBG_PORT_SEL_TXTF_INFOL_C0,
181 RTW89_DBG_PORT_SEL_TXTF_INFOH_C0,
182 /* CMAC 1 related */
183 RTW89_DBG_PORT_SEL_PTCL_C1,
184 RTW89_DBG_PORT_SEL_SCH_C1,
185 RTW89_DBG_PORT_SEL_TMAC_C1,
186 RTW89_DBG_PORT_SEL_RMAC_C1,
187 RTW89_DBG_PORT_SEL_RMACST_C1,
188 RTW89_DBG_PORT_SEL_RMAC_PLCP_C1,
189 RTW89_DBG_PORT_SEL_TRXPTCL_C1,
190 RTW89_DBG_PORT_SEL_TX_INFOL_C1,
191 RTW89_DBG_PORT_SEL_TX_INFOH_C1,
192 RTW89_DBG_PORT_SEL_TXTF_INFOL_C1,
193 RTW89_DBG_PORT_SEL_TXTF_INFOH_C1,
194 /* DLE related */
195 RTW89_DBG_PORT_SEL_WDE_BUFMGN_FREEPG,
196 RTW89_DBG_PORT_SEL_WDE_BUFMGN_QUOTA,
197 RTW89_DBG_PORT_SEL_WDE_BUFMGN_PAGELLT,
198 RTW89_DBG_PORT_SEL_WDE_BUFMGN_PKTINFO,
199 RTW89_DBG_PORT_SEL_WDE_QUEMGN_PREPKT,
200 RTW89_DBG_PORT_SEL_WDE_QUEMGN_NXTPKT,
201 RTW89_DBG_PORT_SEL_WDE_QUEMGN_QLNKTBL,
202 RTW89_DBG_PORT_SEL_WDE_QUEMGN_QEMPTY,
203 RTW89_DBG_PORT_SEL_PLE_BUFMGN_FREEPG,
204 RTW89_DBG_PORT_SEL_PLE_BUFMGN_QUOTA,
205 RTW89_DBG_PORT_SEL_PLE_BUFMGN_PAGELLT,
206 RTW89_DBG_PORT_SEL_PLE_BUFMGN_PKTINFO,
207 RTW89_DBG_PORT_SEL_PLE_QUEMGN_PREPKT,
208 RTW89_DBG_PORT_SEL_PLE_QUEMGN_NXTPKT,
209 RTW89_DBG_PORT_SEL_PLE_QUEMGN_QLNKTBL,
210 RTW89_DBG_PORT_SEL_PLE_QUEMGN_QEMPTY,
211 RTW89_DBG_PORT_SEL_PKTINFO,
212 /* PCIE related */
213 RTW89_DBG_PORT_SEL_PCIE_TXDMA,
214 RTW89_DBG_PORT_SEL_PCIE_RXDMA,
215 RTW89_DBG_PORT_SEL_PCIE_CVT,
216 RTW89_DBG_PORT_SEL_PCIE_CXPL,
217 RTW89_DBG_PORT_SEL_PCIE_IO,
218 RTW89_DBG_PORT_SEL_PCIE_MISC,
219 RTW89_DBG_PORT_SEL_PCIE_MISC2,
220
221 /* keep last */
222 RTW89_DBG_PORT_SEL_LAST,
223 RTW89_DBG_PORT_SEL_MAX = RTW89_DBG_PORT_SEL_LAST,
224 RTW89_DBG_PORT_SEL_INVALID = RTW89_DBG_PORT_SEL_LAST,
225 };
226
227 /* SRAM mem dump */
228 #define R_AX_INDIR_ACCESS_ENTRY 0x40000
229
230 #define STA_SCHED_BASE_ADDR 0x18808000
231 #define RXPLD_FLTR_CAM_BASE_ADDR 0x18813000
232 #define SECURITY_CAM_BASE_ADDR 0x18814000
233 #define WOW_CAM_BASE_ADDR 0x18815000
234 #define CMAC_TBL_BASE_ADDR 0x18840000
235 #define ADDR_CAM_BASE_ADDR 0x18850000
236 #define BSSID_CAM_BASE_ADDR 0x18853000
237 #define BA_CAM_BASE_ADDR 0x18854000
238 #define BCN_IE_CAM0_BASE_ADDR 0x18855000
239 #define SHARED_BUF_BASE_ADDR 0x18700000
240 #define DMAC_TBL_BASE_ADDR 0x18800000
241 #define SHCUT_MACHDR_BASE_ADDR 0x18800800
242 #define BCN_IE_CAM1_BASE_ADDR 0x188A0000
243
244 #define CCTL_INFO_SIZE 32
245
246 enum rtw89_mac_mem_sel {
247 RTW89_MAC_MEM_SHARED_BUF,
248 RTW89_MAC_MEM_DMAC_TBL,
249 RTW89_MAC_MEM_SHCUT_MACHDR,
250 RTW89_MAC_MEM_STA_SCHED,
251 RTW89_MAC_MEM_RXPLD_FLTR_CAM,
252 RTW89_MAC_MEM_SECURITY_CAM,
253 RTW89_MAC_MEM_WOW_CAM,
254 RTW89_MAC_MEM_CMAC_TBL,
255 RTW89_MAC_MEM_ADDR_CAM,
256 RTW89_MAC_MEM_BA_CAM,
257 RTW89_MAC_MEM_BCN_IE_CAM0,
258 RTW89_MAC_MEM_BCN_IE_CAM1,
259
260 /* keep last */
261 RTW89_MAC_MEM_LAST,
262 RTW89_MAC_MEM_MAX = RTW89_MAC_MEM_LAST,
263 RTW89_MAC_MEM_INVALID = RTW89_MAC_MEM_LAST,
264 };
265
266 enum rtw89_rpwm_req_pwr_state {
267 RTW89_MAC_RPWM_REQ_PWR_STATE_ACTIVE = 0,
268 RTW89_MAC_RPWM_REQ_PWR_STATE_BAND0_RFON = 1,
269 RTW89_MAC_RPWM_REQ_PWR_STATE_BAND1_RFON = 2,
270 RTW89_MAC_RPWM_REQ_PWR_STATE_BAND0_RFOFF = 3,
271 RTW89_MAC_RPWM_REQ_PWR_STATE_BAND1_RFOFF = 4,
272 RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED = 5,
273 RTW89_MAC_RPWM_REQ_PWR_STATE_PWR_GATED = 6,
274 RTW89_MAC_RPWM_REQ_PWR_STATE_HIOE_PWR_GATED = 7,
275 RTW89_MAC_RPWM_REQ_PWR_STATE_MAX,
276 };
277
278 struct rtw89_pwr_cfg {
279 u16 addr;
280 u8 cv_msk;
281 u8 intf_msk;
282 u8 base:4;
283 u8 cmd:4;
284 u8 msk;
285 u8 val;
286 };
287
288 enum rtw89_mac_c2h_ofld_func {
289 RTW89_MAC_C2H_FUNC_EFUSE_DUMP,
290 RTW89_MAC_C2H_FUNC_READ_RSP,
291 RTW89_MAC_C2H_FUNC_PKT_OFLD_RSP,
292 RTW89_MAC_C2H_FUNC_BCN_RESEND,
293 RTW89_MAC_C2H_FUNC_MACID_PAUSE,
294 RTW89_MAC_C2H_FUNC_OFLD_MAX,
295 };
296
297 enum rtw89_mac_c2h_info_func {
298 RTW89_MAC_C2H_FUNC_REC_ACK,
299 RTW89_MAC_C2H_FUNC_DONE_ACK,
300 RTW89_MAC_C2H_FUNC_C2H_LOG,
301 RTW89_MAC_C2H_FUNC_INFO_MAX,
302 };
303
304 enum rtw89_mac_c2h_class {
305 RTW89_MAC_C2H_CLASS_INFO,
306 RTW89_MAC_C2H_CLASS_OFLD,
307 RTW89_MAC_C2H_CLASS_TWT,
308 RTW89_MAC_C2H_CLASS_WOW,
309 RTW89_MAC_C2H_CLASS_MCC,
310 RTW89_MAC_C2H_CLASS_FWDBG,
311 RTW89_MAC_C2H_CLASS_MAX,
312 };
313
314 struct rtw89_mac_ax_coex {
315 #define RTW89_MAC_AX_COEX_RTK_MODE 0
316 #define RTW89_MAC_AX_COEX_CSR_MODE 1
317 u8 pta_mode;
318 #define RTW89_MAC_AX_COEX_INNER 0
319 #define RTW89_MAC_AX_COEX_OUTPUT 1
320 #define RTW89_MAC_AX_COEX_INPUT 2
321 u8 direction;
322 };
323
324 struct rtw89_mac_ax_plt {
325 #define RTW89_MAC_AX_PLT_LTE_RX BIT(0)
326 #define RTW89_MAC_AX_PLT_GNT_BT_TX BIT(1)
327 #define RTW89_MAC_AX_PLT_GNT_BT_RX BIT(2)
328 #define RTW89_MAC_AX_PLT_GNT_WL BIT(3)
329 u8 band;
330 u8 tx;
331 u8 rx;
332 };
333
334 enum rtw89_mac_bf_rrsc_rate {
335 RTW89_MAC_BF_RRSC_6M = 0,
336 RTW89_MAC_BF_RRSC_9M = 1,
337 RTW89_MAC_BF_RRSC_12M,
338 RTW89_MAC_BF_RRSC_18M,
339 RTW89_MAC_BF_RRSC_24M,
340 RTW89_MAC_BF_RRSC_36M,
341 RTW89_MAC_BF_RRSC_48M,
342 RTW89_MAC_BF_RRSC_54M,
343 RTW89_MAC_BF_RRSC_HT_MSC0,
344 RTW89_MAC_BF_RRSC_HT_MSC1,
345 RTW89_MAC_BF_RRSC_HT_MSC2,
346 RTW89_MAC_BF_RRSC_HT_MSC3,
347 RTW89_MAC_BF_RRSC_HT_MSC4,
348 RTW89_MAC_BF_RRSC_HT_MSC5,
349 RTW89_MAC_BF_RRSC_HT_MSC6,
350 RTW89_MAC_BF_RRSC_HT_MSC7,
351 RTW89_MAC_BF_RRSC_VHT_MSC0,
352 RTW89_MAC_BF_RRSC_VHT_MSC1,
353 RTW89_MAC_BF_RRSC_VHT_MSC2,
354 RTW89_MAC_BF_RRSC_VHT_MSC3,
355 RTW89_MAC_BF_RRSC_VHT_MSC4,
356 RTW89_MAC_BF_RRSC_VHT_MSC5,
357 RTW89_MAC_BF_RRSC_VHT_MSC6,
358 RTW89_MAC_BF_RRSC_VHT_MSC7,
359 RTW89_MAC_BF_RRSC_HE_MSC0,
360 RTW89_MAC_BF_RRSC_HE_MSC1,
361 RTW89_MAC_BF_RRSC_HE_MSC2,
362 RTW89_MAC_BF_RRSC_HE_MSC3,
363 RTW89_MAC_BF_RRSC_HE_MSC4,
364 RTW89_MAC_BF_RRSC_HE_MSC5,
365 RTW89_MAC_BF_RRSC_HE_MSC6,
366 RTW89_MAC_BF_RRSC_HE_MSC7 = 31,
367 RTW89_MAC_BF_RRSC_MAX = 32
368 };
369
370 #define RTW89_R32_EA 0xEAEAEAEA
371 #define RTW89_R32_DEAD 0xDEADBEEF
372 #define MAC_REG_POOL_COUNT 10
373 #define ACCESS_CMAC(_addr) \
374 ({typeof(_addr) __addr = (_addr); \
375 __addr >= R_AX_CMAC_REG_START && __addr <= R_AX_CMAC_REG_END; })
376
377 #define PTCL_IDLE_POLL_CNT 10000
378 #define SW_CVR_DUR_US 8
379 #define SW_CVR_CNT 8
380
381 #define DLE_BOUND_UNIT (8 * 1024)
382 #define DLE_WAIT_CNT 2000
383 #define TRXCFG_WAIT_CNT 2000
384
385 #define RTW89_WDE_PG_64 64
386 #define RTW89_WDE_PG_128 128
387 #define RTW89_WDE_PG_256 256
388
389 #define S_AX_WDE_PAGE_SEL_64 0
390 #define S_AX_WDE_PAGE_SEL_128 1
391 #define S_AX_WDE_PAGE_SEL_256 2
392
393 #define RTW89_PLE_PG_64 64
394 #define RTW89_PLE_PG_128 128
395 #define RTW89_PLE_PG_256 256
396
397 #define S_AX_PLE_PAGE_SEL_64 0
398 #define S_AX_PLE_PAGE_SEL_128 1
399 #define S_AX_PLE_PAGE_SEL_256 2
400
401 #define SDIO_LOCAL_BASE_ADDR 0x80000000
402
403 #define PWR_CMD_WRITE 0
404 #define PWR_CMD_POLL 1
405 #define PWR_CMD_DELAY 2
406 #define PWR_CMD_END 3
407
408 #define PWR_INTF_MSK_SDIO BIT(0)
409 #define PWR_INTF_MSK_USB BIT(1)
410 #define PWR_INTF_MSK_PCIE BIT(2)
411 #define PWR_INTF_MSK_ALL 0x7
412
413 #define PWR_BASE_MAC 0
414 #define PWR_BASE_USB 1
415 #define PWR_BASE_PCIE 2
416 #define PWR_BASE_SDIO 3
417
418 #define PWR_CV_MSK_A BIT(0)
419 #define PWR_CV_MSK_B BIT(1)
420 #define PWR_CV_MSK_C BIT(2)
421 #define PWR_CV_MSK_D BIT(3)
422 #define PWR_CV_MSK_E BIT(4)
423 #define PWR_CV_MSK_F BIT(5)
424 #define PWR_CV_MSK_G BIT(6)
425 #define PWR_CV_MSK_TEST BIT(7)
426 #define PWR_CV_MSK_ALL 0xFF
427
428 #define PWR_DELAY_US 0
429 #define PWR_DELAY_MS 1
430
431 /* STA scheduler */
432 #define SS_MACID_SH 8
433 #define SS_TX_LEN_MSK 0x1FFFFF
434 #define SS_CTRL1_R_TX_LEN 5
435 #define SS_CTRL1_R_NEXT_LINK 20
436 #define SS_LINK_SIZE 256
437
438 /* MAC debug port */
439 #define TMAC_DBG_SEL_C0 0xA5
440 #define RMAC_DBG_SEL_C0 0xA6
441 #define TRXPTCL_DBG_SEL_C0 0xA7
442 #define TMAC_DBG_SEL_C1 0xB5
443 #define RMAC_DBG_SEL_C1 0xB6
444 #define TRXPTCL_DBG_SEL_C1 0xB7
445 #define FW_PROG_CNTR_DBG_SEL 0xF2
446 #define PCIE_TXDMA_DBG_SEL 0x30
447 #define PCIE_RXDMA_DBG_SEL 0x31
448 #define PCIE_CVT_DBG_SEL 0x32
449 #define PCIE_CXPL_DBG_SEL 0x33
450 #define PCIE_IO_DBG_SEL 0x37
451 #define PCIE_MISC_DBG_SEL 0x38
452 #define PCIE_MISC2_DBG_SEL 0x00
453 #define MAC_DBG_SEL 1
454 #define RMAC_CMAC_DBG_SEL 1
455
456 /* TRXPTCL dbg port sel */
457 #define TRXPTRL_DBG_SEL_TMAC 0
458 #define TRXPTRL_DBG_SEL_RMAC 1
459
460 struct rtw89_cpuio_ctrl {
461 u16 pkt_num;
462 u16 start_pktid;
463 u16 end_pktid;
464 u8 cmd_type;
465 u8 macid;
466 u8 src_pid;
467 u8 src_qid;
468 u8 dst_pid;
469 u8 dst_qid;
470 u16 pktid;
471 };
472
473 struct rtw89_mac_dbg_port_info {
474 u32 sel_addr;
475 u8 sel_byte;
476 u32 sel_msk;
477 u32 srt;
478 u32 end;
479 u32 rd_addr;
480 u8 rd_byte;
481 u32 rd_msk;
482 };
483
484 #define QLNKTBL_ADDR_INFO_SEL BIT(0)
485 #define QLNKTBL_ADDR_INFO_SEL_0 0
486 #define QLNKTBL_ADDR_INFO_SEL_1 1
487 #define QLNKTBL_ADDR_TBL_IDX_MASK GENMASK(10, 1)
488 #define QLNKTBL_DATA_SEL1_PKT_CNT_MASK GENMASK(11, 0)
489
490 struct rtw89_mac_dle_dfi_ctrl {
491 enum rtw89_mac_dle_ctrl_type type;
492 u32 target;
493 u32 addr;
494 u32 out_data;
495 };
496
497 struct rtw89_mac_dle_dfi_quota {
498 enum rtw89_mac_dle_ctrl_type dle_type;
499 u32 qtaid;
500 u16 rsv_pgnum;
501 u16 use_pgnum;
502 };
503
504 struct rtw89_mac_dle_dfi_qempty {
505 enum rtw89_mac_dle_ctrl_type dle_type;
506 u32 grpsel;
507 u32 qempty;
508 };
509
510 /* Define DBG and recovery enum */
511 enum mac_ax_err_info {
512 /* Get error info */
513
514 /* L0 */
515 MAC_AX_ERR_L0_ERR_CMAC0 = 0x0001,
516 MAC_AX_ERR_L0_ERR_CMAC1 = 0x0002,
517 MAC_AX_ERR_L0_RESET_DONE = 0x0003,
518 MAC_AX_ERR_L0_PROMOTE_TO_L1 = 0x0010,
519
520 /* L1 */
521 MAC_AX_ERR_L1_ERR_DMAC = 0x1000,
522 MAC_AX_ERR_L1_RESET_DISABLE_DMAC_DONE = 0x1001,
523 MAC_AX_ERR_L1_RESET_RECOVERY_DONE = 0x1002,
524 MAC_AX_ERR_L1_PROMOTE_TO_L2 = 0x1010,
525 MAC_AX_ERR_L1_RCVY_STOP_DONE = 0x1011,
526
527 /* L2 */
528 /* address hole (master) */
529 MAC_AX_ERR_L2_ERR_AH_DMA = 0x2000,
530 MAC_AX_ERR_L2_ERR_AH_HCI = 0x2010,
531 MAC_AX_ERR_L2_ERR_AH_RLX4081 = 0x2020,
532 MAC_AX_ERR_L2_ERR_AH_IDDMA = 0x2030,
533 MAC_AX_ERR_L2_ERR_AH_HIOE = 0x2040,
534 MAC_AX_ERR_L2_ERR_AH_IPSEC = 0x2050,
535 MAC_AX_ERR_L2_ERR_AH_RX4281 = 0x2060,
536 MAC_AX_ERR_L2_ERR_AH_OTHERS = 0x2070,
537
538 /* AHB bridge timeout (master) */
539 MAC_AX_ERR_L2_ERR_AHB_TO_DMA = 0x2100,
540 MAC_AX_ERR_L2_ERR_AHB_TO_HCI = 0x2110,
541 MAC_AX_ERR_L2_ERR_AHB_TO_RLX4081 = 0x2120,
542 MAC_AX_ERR_L2_ERR_AHB_TO_IDDMA = 0x2130,
543 MAC_AX_ERR_L2_ERR_AHB_TO_HIOE = 0x2140,
544 MAC_AX_ERR_L2_ERR_AHB_TO_IPSEC = 0x2150,
545 MAC_AX_ERR_L2_ERR_AHB_TO_RX4281 = 0x2160,
546 MAC_AX_ERR_L2_ERR_AHB_TO_OTHERS = 0x2170,
547
548 /* APB_SA bridge timeout (master + slave) */
549 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WVA = 0x2200,
550 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_UART = 0x2201,
551 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_CPULOCAL = 0x2202,
552 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_AXIDMA = 0x2203,
553 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_HIOE = 0x2204,
554 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_IDDMA = 0x2205,
555 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_IPSEC = 0x2206,
556 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WON = 0x2207,
557 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WDMAC = 0x2208,
558 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WCMAC = 0x2209,
559 MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_OTHERS = 0x220A,
560 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_WVA = 0x2210,
561 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_UART = 0x2211,
562 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_CPULOCAL = 0x2212,
563 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_AXIDMA = 0x2213,
564 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_HIOE = 0x2214,
565 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_IDDMA = 0x2215,
566 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_IPSEC = 0x2216,
567 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_WDMAC = 0x2218,
568 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_WCMAC = 0x2219,
569 MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_OTHERS = 0x221A,
570 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WVA = 0x2220,
571 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_UART = 0x2221,
572 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_CPULOCAL = 0x2222,
573 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_AXIDMA = 0x2223,
574 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_HIOE = 0x2224,
575 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_IDDMA = 0x2225,
576 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_IPSEC = 0x2226,
577 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WON = 0x2227,
578 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WDMAC = 0x2228,
579 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WCMAC = 0x2229,
580 MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_OTHERS = 0x222A,
581 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WVA = 0x2230,
582 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_UART = 0x2231,
583 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_CPULOCAL = 0x2232,
584 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_AXIDMA = 0x2233,
585 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_HIOE = 0x2234,
586 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_IDDMA = 0x2235,
587 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_IPSEC = 0x2236,
588 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WON = 0x2237,
589 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WDMAC = 0x2238,
590 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WCMAC = 0x2239,
591 MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_OTHERS = 0x223A,
592 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WVA = 0x2240,
593 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_UART = 0x2241,
594 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_CPULOCAL = 0x2242,
595 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_AXIDMA = 0x2243,
596 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_HIOE = 0x2244,
597 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_IDDMA = 0x2245,
598 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_IPSEC = 0x2246,
599 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WON = 0x2247,
600 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WDMAC = 0x2248,
601 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WCMAC = 0x2249,
602 MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_OTHERS = 0x224A,
603 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WVA = 0x2250,
604 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_UART = 0x2251,
605 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_CPULOCAL = 0x2252,
606 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_AXIDMA = 0x2253,
607 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_HIOE = 0x2254,
608 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_IDDMA = 0x2255,
609 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_IPSEC = 0x2256,
610 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WON = 0x2257,
611 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WDMAC = 0x2258,
612 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WCMAC = 0x2259,
613 MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_OTHERS = 0x225A,
614 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WVA = 0x2260,
615 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_UART = 0x2261,
616 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_CPULOCAL = 0x2262,
617 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_AXIDMA = 0x2263,
618 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_HIOE = 0x2264,
619 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_IDDMA = 0x2265,
620 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_IPSEC = 0x2266,
621 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WON = 0x2267,
622 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WDMAC = 0x2268,
623 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WCMAC = 0x2269,
624 MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_OTHERS = 0x226A,
625 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WVA = 0x2270,
626 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_UART = 0x2271,
627 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_CPULOCAL = 0x2272,
628 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_AXIDMA = 0x2273,
629 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_HIOE = 0x2274,
630 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_IDDMA = 0x2275,
631 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_IPSEC = 0x2276,
632 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WON = 0x2277,
633 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WDMAC = 0x2278,
634 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WCMAC = 0x2279,
635 MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_OTHERS = 0x227A,
636
637 /* APB_BBRF bridge timeout (master) */
638 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_DMA = 0x2300,
639 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_HCI = 0x2310,
640 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_RLX4081 = 0x2320,
641 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_IDDMA = 0x2330,
642 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_HIOE = 0x2340,
643 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_IPSEC = 0x2350,
644 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_RX4281 = 0x2360,
645 MAC_AX_ERR_L2_ERR_APB_BBRF_TO_OTHERS = 0x2370,
646 MAC_AX_ERR_L2_RESET_DONE = 0x2400,
647 MAC_AX_ERR_CPU_EXCEPTION = 0x3000,
648 MAC_AX_GET_ERR_MAX,
649 MAC_AX_DUMP_SHAREBUFF_INDICATOR = 0x80000000,
650
651 /* set error info */
652 MAC_AX_ERR_L1_DISABLE_EN = 0x0001,
653 MAC_AX_ERR_L1_RCVY_EN = 0x0002,
654 MAC_AX_ERR_L1_RCVY_STOP_REQ = 0x0003,
655 MAC_AX_ERR_L1_RCVY_START_REQ = 0x0004,
656 MAC_AX_ERR_L0_CFG_NOTIFY = 0x0010,
657 MAC_AX_ERR_L0_CFG_DIS_NOTIFY = 0x0011,
658 MAC_AX_ERR_L0_CFG_HANDSHAKE = 0x0012,
659 MAC_AX_ERR_L0_RCVY_EN = 0x0013,
660 MAC_AX_SET_ERR_MAX,
661 };
662
663 extern const struct rtw89_hfc_prec_cfg rtw_hfc_preccfg_pcie;
664 extern const struct rtw89_dle_size wde_size0;
665 extern const struct rtw89_dle_size wde_size4;
666 extern const struct rtw89_dle_size ple_size0;
667 extern const struct rtw89_dle_size ple_size4;
668 extern const struct rtw89_wde_quota wde_qt0;
669 extern const struct rtw89_wde_quota wde_qt4;
670 extern const struct rtw89_ple_quota ple_qt4;
671 extern const struct rtw89_ple_quota ple_qt5;
672 extern const struct rtw89_ple_quota ple_qt13;
673
rtw89_mac_reg_by_idx(u32 reg_base,u8 band)674 static inline u32 rtw89_mac_reg_by_idx(u32 reg_base, u8 band)
675 {
676 return band == 0 ? reg_base : (reg_base + 0x2000);
677 }
678
rtw89_mac_reg_by_port(u32 base,u8 port,u8 mac_idx)679 static inline u32 rtw89_mac_reg_by_port(u32 base, u8 port, u8 mac_idx)
680 {
681 return rtw89_mac_reg_by_idx(base + port * 0x40, mac_idx);
682 }
683
684 static inline u32
rtw89_read32_port_mask(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif,u32 base,u32 mask)685 rtw89_read32_port_mask(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
686 u32 base, u32 mask)
687 {
688 u32 reg;
689
690 reg = rtw89_mac_reg_by_port(base, rtwvif->port, rtwvif->mac_idx);
691 return rtw89_read32_mask(rtwdev, reg, mask);
692 }
693
694 static inline void
rtw89_write32_port(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif,u32 base,u32 data)695 rtw89_write32_port(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, u32 base,
696 u32 data)
697 {
698 u32 reg;
699
700 reg = rtw89_mac_reg_by_port(base, rtwvif->port, rtwvif->mac_idx);
701 rtw89_write32(rtwdev, reg, data);
702 }
703
704 static inline void
rtw89_write32_port_mask(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif,u32 base,u32 mask,u32 data)705 rtw89_write32_port_mask(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
706 u32 base, u32 mask, u32 data)
707 {
708 u32 reg;
709
710 reg = rtw89_mac_reg_by_port(base, rtwvif->port, rtwvif->mac_idx);
711 rtw89_write32_mask(rtwdev, reg, mask, data);
712 }
713
714 static inline void
rtw89_write16_port_mask(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif,u32 base,u32 mask,u16 data)715 rtw89_write16_port_mask(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
716 u32 base, u32 mask, u16 data)
717 {
718 u32 reg;
719
720 reg = rtw89_mac_reg_by_port(base, rtwvif->port, rtwvif->mac_idx);
721 rtw89_write16_mask(rtwdev, reg, mask, data);
722 }
723
724 static inline void
rtw89_write32_port_clr(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif,u32 base,u32 bit)725 rtw89_write32_port_clr(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
726 u32 base, u32 bit)
727 {
728 u32 reg;
729
730 reg = rtw89_mac_reg_by_port(base, rtwvif->port, rtwvif->mac_idx);
731 rtw89_write32_clr(rtwdev, reg, bit);
732 }
733
734 static inline void
rtw89_write16_port_clr(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif,u32 base,u16 bit)735 rtw89_write16_port_clr(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
736 u32 base, u16 bit)
737 {
738 u32 reg;
739
740 reg = rtw89_mac_reg_by_port(base, rtwvif->port, rtwvif->mac_idx);
741 rtw89_write16_clr(rtwdev, reg, bit);
742 }
743
744 static inline void
rtw89_write32_port_set(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif,u32 base,u32 bit)745 rtw89_write32_port_set(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
746 u32 base, u32 bit)
747 {
748 u32 reg;
749
750 reg = rtw89_mac_reg_by_port(base, rtwvif->port, rtwvif->mac_idx);
751 rtw89_write32_set(rtwdev, reg, bit);
752 }
753
754 void rtw89_mac_pwr_off(struct rtw89_dev *rtwdev);
755 int rtw89_mac_partial_init(struct rtw89_dev *rtwdev);
756 int rtw89_mac_init(struct rtw89_dev *rtwdev);
757 int rtw89_mac_check_mac_en(struct rtw89_dev *rtwdev, u8 band,
758 enum rtw89_mac_hwmod_sel sel);
759 int rtw89_mac_write_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 val);
760 int rtw89_mac_read_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 *val);
761 int rtw89_mac_add_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *vif);
762 int rtw89_mac_port_update(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif);
763 int rtw89_mac_remove_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *vif);
764 void rtw89_mac_enable_bb_rf(struct rtw89_dev *rtwdev);
765 void rtw89_mac_disable_bb_rf(struct rtw89_dev *rtwdev);
766 u32 rtw89_mac_get_err_status(struct rtw89_dev *rtwdev);
767 int rtw89_mac_set_err_status(struct rtw89_dev *rtwdev, u32 err);
768 void rtw89_mac_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb,
769 u32 len, u8 class, u8 func);
770 int rtw89_mac_setup_phycap(struct rtw89_dev *rtwdev);
771 int rtw89_mac_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx,
772 u16 *tx_en, enum rtw89_sch_tx_sel sel);
773 int rtw89_mac_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u16 tx_en);
774 int rtw89_mac_cfg_ppdu_status(struct rtw89_dev *rtwdev, u8 mac_ids, bool enable);
775 void rtw89_mac_update_rts_threshold(struct rtw89_dev *rtwdev, u8 mac_idx);
776 void rtw89_mac_flush_txq(struct rtw89_dev *rtwdev, u32 queues, bool drop);
777 int rtw89_mac_coex_init(struct rtw89_dev *rtwdev, const struct rtw89_mac_ax_coex *coex);
778 int rtw89_mac_cfg_gnt(struct rtw89_dev *rtwdev,
779 const struct rtw89_mac_ax_coex_gnt *gnt_cfg);
780 int rtw89_mac_cfg_plt(struct rtw89_dev *rtwdev, struct rtw89_mac_ax_plt *plt);
781 void rtw89_mac_cfg_sb(struct rtw89_dev *rtwdev, u32 val);
782 u32 rtw89_mac_get_sb(struct rtw89_dev *rtwdev);
783 bool rtw89_mac_get_ctrl_path(struct rtw89_dev *rtwdev);
784 int rtw89_mac_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl);
785 bool rtw89_mac_get_txpwr_cr(struct rtw89_dev *rtwdev,
786 enum rtw89_phy_idx phy_idx,
787 u32 reg_base, u32 *cr);
788 void rtw89_mac_power_mode_change(struct rtw89_dev *rtwdev, bool enter);
789 void rtw89_mac_bf_assoc(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,
790 struct ieee80211_sta *sta);
791 void rtw89_mac_bf_disassoc(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,
792 struct ieee80211_sta *sta);
793 void rtw89_mac_bf_set_gid_table(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,
794 struct ieee80211_bss_conf *conf);
795 void rtw89_mac_bf_monitor_calc(struct rtw89_dev *rtwdev,
796 struct ieee80211_sta *sta, bool disconnect);
797 void _rtw89_mac_bf_monitor_track(struct rtw89_dev *rtwdev);
798 int rtw89_mac_vif_init(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif);
799 int rtw89_mac_vif_deinit(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif);
800 int rtw89_mac_set_hw_muedca_ctrl(struct rtw89_dev *rtwdev,
801 struct rtw89_vif *rtwvif, bool en);
802
rtw89_mac_bf_monitor_track(struct rtw89_dev * rtwdev)803 static inline void rtw89_mac_bf_monitor_track(struct rtw89_dev *rtwdev)
804 {
805 if (!test_bit(RTW89_FLAG_BFEE_MON, rtwdev->flags))
806 return;
807
808 _rtw89_mac_bf_monitor_track(rtwdev);
809 }
810
rtw89_mac_txpwr_read32(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,u32 reg_base,u32 * val)811 static inline int rtw89_mac_txpwr_read32(struct rtw89_dev *rtwdev,
812 enum rtw89_phy_idx phy_idx,
813 u32 reg_base, u32 *val)
814 {
815 u32 cr;
816
817 if (!rtw89_mac_get_txpwr_cr(rtwdev, phy_idx, reg_base, &cr))
818 return -EINVAL;
819
820 *val = rtw89_read32(rtwdev, cr);
821 return 0;
822 }
823
rtw89_mac_txpwr_write32(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,u32 reg_base,u32 val)824 static inline int rtw89_mac_txpwr_write32(struct rtw89_dev *rtwdev,
825 enum rtw89_phy_idx phy_idx,
826 u32 reg_base, u32 val)
827 {
828 u32 cr;
829
830 if (!rtw89_mac_get_txpwr_cr(rtwdev, phy_idx, reg_base, &cr))
831 return -EINVAL;
832
833 rtw89_write32(rtwdev, cr, val);
834 return 0;
835 }
836
rtw89_mac_txpwr_write32_mask(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,u32 reg_base,u32 mask,u32 val)837 static inline int rtw89_mac_txpwr_write32_mask(struct rtw89_dev *rtwdev,
838 enum rtw89_phy_idx phy_idx,
839 u32 reg_base, u32 mask, u32 val)
840 {
841 u32 cr;
842
843 if (!rtw89_mac_get_txpwr_cr(rtwdev, phy_idx, reg_base, &cr))
844 return -EINVAL;
845
846 rtw89_write32_mask(rtwdev, cr, mask, val);
847 return 0;
848 }
849
850 int rtw89_mac_set_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta,
851 bool resume, u32 tx_time);
852 int rtw89_mac_get_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta,
853 u32 *tx_time);
854 int rtw89_mac_set_tx_retry_limit(struct rtw89_dev *rtwdev,
855 struct rtw89_sta *rtwsta,
856 bool resume, u8 tx_retry);
857 int rtw89_mac_get_tx_retry_limit(struct rtw89_dev *rtwdev,
858 struct rtw89_sta *rtwsta, u8 *tx_retry);
859
860 #endif
861