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Searched defs:XCHAL_ICACHE_LINEWIDTH (Results 1 – 3 of 3) sorted by relevance

/u-boot/arch/xtensa/include/asm/arch-dc232b/
A Dcore.h121 #define XCHAL_ICACHE_LINEWIDTH 5 /* log2(I line size in bytes) */ macro
/u-boot/arch/xtensa/include/asm/arch-dc233c/
A Dcore.h140 #define XCHAL_ICACHE_LINEWIDTH 5 /* log2(I line size in bytes) */ macro
/u-boot/arch/xtensa/include/asm/arch-de212/
A Dcore.h188 #define XCHAL_ICACHE_LINEWIDTH 5 /* log2(I line size in bytes) */ macro

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