1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * core.c - ChipIdea USB IP core family device controller
4 *
5 * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
6 * Copyright (C) 2020 NXP
7 *
8 * Author: David Lopo
9 * Peter Chen <peter.chen@nxp.com>
10 *
11 * Main Features:
12 * - Four transfers are supported, usbtest is passed
13 * - USB Certification for gadget: CH9 and Mass Storage are passed
14 * - Low power mode
15 * - USB wakeup
16 */
17 #include <linux/delay.h>
18 #include <linux/device.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/extcon.h>
21 #include <linux/phy/phy.h>
22 #include <linux/platform_device.h>
23 #include <linux/module.h>
24 #include <linux/idr.h>
25 #include <linux/interrupt.h>
26 #include <linux/io.h>
27 #include <linux/kernel.h>
28 #include <linux/slab.h>
29 #include <linux/pm_runtime.h>
30 #include <linux/pinctrl/consumer.h>
31 #include <linux/usb/ch9.h>
32 #include <linux/usb/gadget.h>
33 #include <linux/usb/otg.h>
34 #include <linux/usb/chipidea.h>
35 #include <linux/usb/of.h>
36 #include <linux/of.h>
37 #include <linux/regulator/consumer.h>
38 #include <linux/usb/ehci_def.h>
39
40 #include "ci.h"
41 #include "udc.h"
42 #include "bits.h"
43 #include "host.h"
44 #include "otg.h"
45 #include "otg_fsm.h"
46
47 /* Controller register map */
48 static const u8 ci_regs_nolpm[] = {
49 [CAP_CAPLENGTH] = 0x00U,
50 [CAP_HCCPARAMS] = 0x08U,
51 [CAP_DCCPARAMS] = 0x24U,
52 [CAP_TESTMODE] = 0x38U,
53 [OP_USBCMD] = 0x00U,
54 [OP_USBSTS] = 0x04U,
55 [OP_USBINTR] = 0x08U,
56 [OP_DEVICEADDR] = 0x14U,
57 [OP_ENDPTLISTADDR] = 0x18U,
58 [OP_TTCTRL] = 0x1CU,
59 [OP_BURSTSIZE] = 0x20U,
60 [OP_ULPI_VIEWPORT] = 0x30U,
61 [OP_PORTSC] = 0x44U,
62 [OP_DEVLC] = 0x84U,
63 [OP_OTGSC] = 0x64U,
64 [OP_USBMODE] = 0x68U,
65 [OP_ENDPTSETUPSTAT] = 0x6CU,
66 [OP_ENDPTPRIME] = 0x70U,
67 [OP_ENDPTFLUSH] = 0x74U,
68 [OP_ENDPTSTAT] = 0x78U,
69 [OP_ENDPTCOMPLETE] = 0x7CU,
70 [OP_ENDPTCTRL] = 0x80U,
71 };
72
73 static const u8 ci_regs_lpm[] = {
74 [CAP_CAPLENGTH] = 0x00U,
75 [CAP_HCCPARAMS] = 0x08U,
76 [CAP_DCCPARAMS] = 0x24U,
77 [CAP_TESTMODE] = 0xFCU,
78 [OP_USBCMD] = 0x00U,
79 [OP_USBSTS] = 0x04U,
80 [OP_USBINTR] = 0x08U,
81 [OP_DEVICEADDR] = 0x14U,
82 [OP_ENDPTLISTADDR] = 0x18U,
83 [OP_TTCTRL] = 0x1CU,
84 [OP_BURSTSIZE] = 0x20U,
85 [OP_ULPI_VIEWPORT] = 0x30U,
86 [OP_PORTSC] = 0x44U,
87 [OP_DEVLC] = 0x84U,
88 [OP_OTGSC] = 0xC4U,
89 [OP_USBMODE] = 0xC8U,
90 [OP_ENDPTSETUPSTAT] = 0xD8U,
91 [OP_ENDPTPRIME] = 0xDCU,
92 [OP_ENDPTFLUSH] = 0xE0U,
93 [OP_ENDPTSTAT] = 0xE4U,
94 [OP_ENDPTCOMPLETE] = 0xE8U,
95 [OP_ENDPTCTRL] = 0xECU,
96 };
97
hw_alloc_regmap(struct ci_hdrc * ci,bool is_lpm)98 static void hw_alloc_regmap(struct ci_hdrc *ci, bool is_lpm)
99 {
100 int i;
101
102 for (i = 0; i < OP_ENDPTCTRL; i++)
103 ci->hw_bank.regmap[i] =
104 (i <= CAP_LAST ? ci->hw_bank.cap : ci->hw_bank.op) +
105 (is_lpm ? ci_regs_lpm[i] : ci_regs_nolpm[i]);
106
107 for (; i <= OP_LAST; i++)
108 ci->hw_bank.regmap[i] = ci->hw_bank.op +
109 4 * (i - OP_ENDPTCTRL) +
110 (is_lpm
111 ? ci_regs_lpm[OP_ENDPTCTRL]
112 : ci_regs_nolpm[OP_ENDPTCTRL]);
113
114 }
115
ci_get_revision(struct ci_hdrc * ci)116 static enum ci_revision ci_get_revision(struct ci_hdrc *ci)
117 {
118 int ver = hw_read_id_reg(ci, ID_ID, VERSION) >> __ffs(VERSION);
119 enum ci_revision rev = CI_REVISION_UNKNOWN;
120
121 if (ver == 0x2) {
122 rev = hw_read_id_reg(ci, ID_ID, REVISION)
123 >> __ffs(REVISION);
124 rev += CI_REVISION_20;
125 } else if (ver == 0x0) {
126 rev = CI_REVISION_1X;
127 }
128
129 return rev;
130 }
131
132 /**
133 * hw_read_intr_enable: returns interrupt enable register
134 *
135 * @ci: the controller
136 *
137 * This function returns register data
138 */
hw_read_intr_enable(struct ci_hdrc * ci)139 u32 hw_read_intr_enable(struct ci_hdrc *ci)
140 {
141 return hw_read(ci, OP_USBINTR, ~0);
142 }
143
144 /**
145 * hw_read_intr_status: returns interrupt status register
146 *
147 * @ci: the controller
148 *
149 * This function returns register data
150 */
hw_read_intr_status(struct ci_hdrc * ci)151 u32 hw_read_intr_status(struct ci_hdrc *ci)
152 {
153 return hw_read(ci, OP_USBSTS, ~0);
154 }
155
156 /**
157 * hw_port_test_set: writes port test mode (execute without interruption)
158 * @ci: the controller
159 * @mode: new value
160 *
161 * This function returns an error code
162 */
hw_port_test_set(struct ci_hdrc * ci,u8 mode)163 int hw_port_test_set(struct ci_hdrc *ci, u8 mode)
164 {
165 const u8 TEST_MODE_MAX = 7;
166
167 if (mode > TEST_MODE_MAX)
168 return -EINVAL;
169
170 hw_write(ci, OP_PORTSC, PORTSC_PTC, mode << __ffs(PORTSC_PTC));
171 return 0;
172 }
173
174 /**
175 * hw_port_test_get: reads port test mode value
176 *
177 * @ci: the controller
178 *
179 * This function returns port test mode value
180 */
hw_port_test_get(struct ci_hdrc * ci)181 u8 hw_port_test_get(struct ci_hdrc *ci)
182 {
183 return hw_read(ci, OP_PORTSC, PORTSC_PTC) >> __ffs(PORTSC_PTC);
184 }
185
hw_wait_phy_stable(void)186 static void hw_wait_phy_stable(void)
187 {
188 /*
189 * The phy needs some delay to output the stable status from low
190 * power mode. And for OTGSC, the status inputs are debounced
191 * using a 1 ms time constant, so, delay 2ms for controller to get
192 * the stable status, like vbus and id when the phy leaves low power.
193 */
194 usleep_range(2000, 2500);
195 }
196
197 /* The PHY enters/leaves low power mode */
ci_hdrc_enter_lpm_common(struct ci_hdrc * ci,bool enable)198 static void ci_hdrc_enter_lpm_common(struct ci_hdrc *ci, bool enable)
199 {
200 enum ci_hw_regs reg = ci->hw_bank.lpm ? OP_DEVLC : OP_PORTSC;
201 bool lpm = !!(hw_read(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm)));
202
203 if (enable && !lpm)
204 hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm),
205 PORTSC_PHCD(ci->hw_bank.lpm));
206 else if (!enable && lpm)
207 hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm),
208 0);
209 }
210
ci_hdrc_enter_lpm(struct ci_hdrc * ci,bool enable)211 static void ci_hdrc_enter_lpm(struct ci_hdrc *ci, bool enable)
212 {
213 return ci->platdata->enter_lpm(ci, enable);
214 }
215
hw_device_init(struct ci_hdrc * ci,void __iomem * base)216 static int hw_device_init(struct ci_hdrc *ci, void __iomem *base)
217 {
218 u32 reg;
219
220 /* bank is a module variable */
221 ci->hw_bank.abs = base;
222
223 ci->hw_bank.cap = ci->hw_bank.abs;
224 ci->hw_bank.cap += ci->platdata->capoffset;
225 ci->hw_bank.op = ci->hw_bank.cap + (ioread32(ci->hw_bank.cap) & 0xff);
226
227 hw_alloc_regmap(ci, false);
228 reg = hw_read(ci, CAP_HCCPARAMS, HCCPARAMS_LEN) >>
229 __ffs(HCCPARAMS_LEN);
230 ci->hw_bank.lpm = reg;
231 if (reg)
232 hw_alloc_regmap(ci, !!reg);
233 ci->hw_bank.size = ci->hw_bank.op - ci->hw_bank.abs;
234 ci->hw_bank.size += OP_LAST;
235 ci->hw_bank.size /= sizeof(u32);
236
237 reg = hw_read(ci, CAP_DCCPARAMS, DCCPARAMS_DEN) >>
238 __ffs(DCCPARAMS_DEN);
239 ci->hw_ep_max = reg * 2; /* cache hw ENDPT_MAX */
240
241 if (ci->hw_ep_max > ENDPT_MAX)
242 return -ENODEV;
243
244 ci_hdrc_enter_lpm(ci, false);
245
246 /* Disable all interrupts bits */
247 hw_write(ci, OP_USBINTR, 0xffffffff, 0);
248
249 /* Clear all interrupts status bits*/
250 hw_write(ci, OP_USBSTS, 0xffffffff, 0xffffffff);
251
252 ci->rev = ci_get_revision(ci);
253
254 dev_dbg(ci->dev,
255 "revision: %d, lpm: %d; cap: %px op: %px\n",
256 ci->rev, ci->hw_bank.lpm, ci->hw_bank.cap, ci->hw_bank.op);
257
258 /* setup lock mode ? */
259
260 /* ENDPTSETUPSTAT is '0' by default */
261
262 /* HCSPARAMS.bf.ppc SHOULD BE zero for device */
263
264 return 0;
265 }
266
hw_phymode_configure(struct ci_hdrc * ci)267 void hw_phymode_configure(struct ci_hdrc *ci)
268 {
269 u32 portsc, lpm, sts = 0;
270
271 switch (ci->platdata->phy_mode) {
272 case USBPHY_INTERFACE_MODE_UTMI:
273 portsc = PORTSC_PTS(PTS_UTMI);
274 lpm = DEVLC_PTS(PTS_UTMI);
275 break;
276 case USBPHY_INTERFACE_MODE_UTMIW:
277 portsc = PORTSC_PTS(PTS_UTMI) | PORTSC_PTW;
278 lpm = DEVLC_PTS(PTS_UTMI) | DEVLC_PTW;
279 break;
280 case USBPHY_INTERFACE_MODE_ULPI:
281 portsc = PORTSC_PTS(PTS_ULPI);
282 lpm = DEVLC_PTS(PTS_ULPI);
283 break;
284 case USBPHY_INTERFACE_MODE_SERIAL:
285 portsc = PORTSC_PTS(PTS_SERIAL);
286 lpm = DEVLC_PTS(PTS_SERIAL);
287 sts = 1;
288 break;
289 case USBPHY_INTERFACE_MODE_HSIC:
290 portsc = PORTSC_PTS(PTS_HSIC);
291 lpm = DEVLC_PTS(PTS_HSIC);
292 break;
293 default:
294 return;
295 }
296
297 if (ci->hw_bank.lpm) {
298 hw_write(ci, OP_DEVLC, DEVLC_PTS(7) | DEVLC_PTW, lpm);
299 if (sts)
300 hw_write(ci, OP_DEVLC, DEVLC_STS, DEVLC_STS);
301 } else {
302 hw_write(ci, OP_PORTSC, PORTSC_PTS(7) | PORTSC_PTW, portsc);
303 if (sts)
304 hw_write(ci, OP_PORTSC, PORTSC_STS, PORTSC_STS);
305 }
306 }
307 EXPORT_SYMBOL_GPL(hw_phymode_configure);
308
309 /**
310 * _ci_usb_phy_init: initialize phy taking in account both phy and usb_phy
311 * interfaces
312 * @ci: the controller
313 *
314 * This function returns an error code if the phy failed to init
315 */
_ci_usb_phy_init(struct ci_hdrc * ci)316 static int _ci_usb_phy_init(struct ci_hdrc *ci)
317 {
318 int ret;
319
320 if (ci->phy) {
321 ret = phy_init(ci->phy);
322 if (ret)
323 return ret;
324
325 ret = phy_power_on(ci->phy);
326 if (ret) {
327 phy_exit(ci->phy);
328 return ret;
329 }
330 } else {
331 ret = usb_phy_init(ci->usb_phy);
332 }
333
334 return ret;
335 }
336
337 /**
338 * ci_usb_phy_exit: deinitialize phy taking in account both phy and usb_phy
339 * interfaces
340 * @ci: the controller
341 */
ci_usb_phy_exit(struct ci_hdrc * ci)342 static void ci_usb_phy_exit(struct ci_hdrc *ci)
343 {
344 if (ci->platdata->flags & CI_HDRC_OVERRIDE_PHY_CONTROL)
345 return;
346
347 if (ci->phy) {
348 phy_power_off(ci->phy);
349 phy_exit(ci->phy);
350 } else {
351 usb_phy_shutdown(ci->usb_phy);
352 }
353 }
354
355 /**
356 * ci_usb_phy_init: initialize phy according to different phy type
357 * @ci: the controller
358 *
359 * This function returns an error code if usb_phy_init has failed
360 */
ci_usb_phy_init(struct ci_hdrc * ci)361 static int ci_usb_phy_init(struct ci_hdrc *ci)
362 {
363 int ret;
364
365 if (ci->platdata->flags & CI_HDRC_OVERRIDE_PHY_CONTROL)
366 return 0;
367
368 switch (ci->platdata->phy_mode) {
369 case USBPHY_INTERFACE_MODE_UTMI:
370 case USBPHY_INTERFACE_MODE_UTMIW:
371 case USBPHY_INTERFACE_MODE_HSIC:
372 ret = _ci_usb_phy_init(ci);
373 if (!ret)
374 hw_wait_phy_stable();
375 else
376 return ret;
377 hw_phymode_configure(ci);
378 break;
379 case USBPHY_INTERFACE_MODE_ULPI:
380 case USBPHY_INTERFACE_MODE_SERIAL:
381 hw_phymode_configure(ci);
382 ret = _ci_usb_phy_init(ci);
383 if (ret)
384 return ret;
385 break;
386 default:
387 ret = _ci_usb_phy_init(ci);
388 if (!ret)
389 hw_wait_phy_stable();
390 }
391
392 return ret;
393 }
394
395
396 /**
397 * ci_platform_configure: do controller configure
398 * @ci: the controller
399 *
400 */
ci_platform_configure(struct ci_hdrc * ci)401 void ci_platform_configure(struct ci_hdrc *ci)
402 {
403 bool is_device_mode, is_host_mode;
404
405 is_device_mode = hw_read(ci, OP_USBMODE, USBMODE_CM) == USBMODE_CM_DC;
406 is_host_mode = hw_read(ci, OP_USBMODE, USBMODE_CM) == USBMODE_CM_HC;
407
408 if (is_device_mode) {
409 phy_set_mode(ci->phy, PHY_MODE_USB_DEVICE);
410
411 if (ci->platdata->flags & CI_HDRC_DISABLE_DEVICE_STREAMING)
412 hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS,
413 USBMODE_CI_SDIS);
414 }
415
416 if (is_host_mode) {
417 phy_set_mode(ci->phy, PHY_MODE_USB_HOST);
418
419 if (ci->platdata->flags & CI_HDRC_DISABLE_HOST_STREAMING)
420 hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS,
421 USBMODE_CI_SDIS);
422 }
423
424 if (ci->platdata->flags & CI_HDRC_FORCE_FULLSPEED) {
425 if (ci->hw_bank.lpm)
426 hw_write(ci, OP_DEVLC, DEVLC_PFSC, DEVLC_PFSC);
427 else
428 hw_write(ci, OP_PORTSC, PORTSC_PFSC, PORTSC_PFSC);
429 }
430
431 if (ci->platdata->flags & CI_HDRC_SET_NON_ZERO_TTHA)
432 hw_write(ci, OP_TTCTRL, TTCTRL_TTHA_MASK, TTCTRL_TTHA);
433
434 hw_write(ci, OP_USBCMD, 0xff0000, ci->platdata->itc_setting << 16);
435
436 if (ci->platdata->flags & CI_HDRC_OVERRIDE_AHB_BURST)
437 hw_write_id_reg(ci, ID_SBUSCFG, AHBBRST_MASK,
438 ci->platdata->ahb_burst_config);
439
440 /* override burst size, take effect only when ahb_burst_config is 0 */
441 if (!hw_read_id_reg(ci, ID_SBUSCFG, AHBBRST_MASK)) {
442 if (ci->platdata->flags & CI_HDRC_OVERRIDE_TX_BURST)
443 hw_write(ci, OP_BURSTSIZE, TX_BURST_MASK,
444 ci->platdata->tx_burst_size << __ffs(TX_BURST_MASK));
445
446 if (ci->platdata->flags & CI_HDRC_OVERRIDE_RX_BURST)
447 hw_write(ci, OP_BURSTSIZE, RX_BURST_MASK,
448 ci->platdata->rx_burst_size);
449 }
450 }
451
452 /**
453 * hw_controller_reset: do controller reset
454 * @ci: the controller
455 *
456 * This function returns an error code
457 */
hw_controller_reset(struct ci_hdrc * ci)458 static int hw_controller_reset(struct ci_hdrc *ci)
459 {
460 int count = 0;
461
462 hw_write(ci, OP_USBCMD, USBCMD_RST, USBCMD_RST);
463 while (hw_read(ci, OP_USBCMD, USBCMD_RST)) {
464 udelay(10);
465 if (count++ > 1000)
466 return -ETIMEDOUT;
467 }
468
469 return 0;
470 }
471
472 /**
473 * hw_device_reset: resets chip (execute without interruption)
474 * @ci: the controller
475 *
476 * This function returns an error code
477 */
hw_device_reset(struct ci_hdrc * ci)478 int hw_device_reset(struct ci_hdrc *ci)
479 {
480 int ret;
481
482 /* should flush & stop before reset */
483 hw_write(ci, OP_ENDPTFLUSH, ~0, ~0);
484 hw_write(ci, OP_USBCMD, USBCMD_RS, 0);
485
486 ret = hw_controller_reset(ci);
487 if (ret) {
488 dev_err(ci->dev, "error resetting controller, ret=%d\n", ret);
489 return ret;
490 }
491
492 if (ci->platdata->notify_event) {
493 ret = ci->platdata->notify_event(ci,
494 CI_HDRC_CONTROLLER_RESET_EVENT);
495 if (ret)
496 return ret;
497 }
498
499 /* USBMODE should be configured step by step */
500 hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_IDLE);
501 hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_DC);
502 /* HW >= 2.3 */
503 hw_write(ci, OP_USBMODE, USBMODE_SLOM, USBMODE_SLOM);
504
505 if (hw_read(ci, OP_USBMODE, USBMODE_CM) != USBMODE_CM_DC) {
506 dev_err(ci->dev, "cannot enter in %s device mode\n",
507 ci_role(ci)->name);
508 dev_err(ci->dev, "lpm = %i\n", ci->hw_bank.lpm);
509 return -ENODEV;
510 }
511
512 ci_platform_configure(ci);
513
514 return 0;
515 }
516
ci_irq_handler(int irq,void * data)517 static irqreturn_t ci_irq_handler(int irq, void *data)
518 {
519 struct ci_hdrc *ci = data;
520 irqreturn_t ret = IRQ_NONE;
521 u32 otgsc = 0;
522
523 if (ci->in_lpm) {
524 disable_irq_nosync(irq);
525 ci->wakeup_int = true;
526 pm_runtime_get(ci->dev);
527 return IRQ_HANDLED;
528 }
529
530 if (ci->is_otg) {
531 otgsc = hw_read_otgsc(ci, ~0);
532 if (ci_otg_is_fsm_mode(ci)) {
533 ret = ci_otg_fsm_irq(ci);
534 if (ret == IRQ_HANDLED)
535 return ret;
536 }
537 }
538
539 /*
540 * Handle id change interrupt, it indicates device/host function
541 * switch.
542 */
543 if (ci->is_otg && (otgsc & OTGSC_IDIE) && (otgsc & OTGSC_IDIS)) {
544 ci->id_event = true;
545 /* Clear ID change irq status */
546 hw_write_otgsc(ci, OTGSC_IDIS, OTGSC_IDIS);
547 ci_otg_queue_work(ci);
548 return IRQ_HANDLED;
549 }
550
551 /*
552 * Handle vbus change interrupt, it indicates device connection
553 * and disconnection events.
554 */
555 if (ci->is_otg && (otgsc & OTGSC_BSVIE) && (otgsc & OTGSC_BSVIS)) {
556 ci->b_sess_valid_event = true;
557 /* Clear BSV irq */
558 hw_write_otgsc(ci, OTGSC_BSVIS, OTGSC_BSVIS);
559 ci_otg_queue_work(ci);
560 return IRQ_HANDLED;
561 }
562
563 /* Handle device/host interrupt */
564 if (ci->role != CI_ROLE_END)
565 ret = ci_role(ci)->irq(ci);
566
567 return ret;
568 }
569
ci_irq(struct ci_hdrc * ci)570 static void ci_irq(struct ci_hdrc *ci)
571 {
572 unsigned long flags;
573
574 local_irq_save(flags);
575 ci_irq_handler(ci->irq, ci);
576 local_irq_restore(flags);
577 }
578
ci_cable_notifier(struct notifier_block * nb,unsigned long event,void * ptr)579 static int ci_cable_notifier(struct notifier_block *nb, unsigned long event,
580 void *ptr)
581 {
582 struct ci_hdrc_cable *cbl = container_of(nb, struct ci_hdrc_cable, nb);
583 struct ci_hdrc *ci = cbl->ci;
584
585 cbl->connected = event;
586 cbl->changed = true;
587
588 ci_irq(ci);
589 return NOTIFY_DONE;
590 }
591
ci_usb_role_switch_get(struct usb_role_switch * sw)592 static enum usb_role ci_usb_role_switch_get(struct usb_role_switch *sw)
593 {
594 struct ci_hdrc *ci = usb_role_switch_get_drvdata(sw);
595 enum usb_role role;
596 unsigned long flags;
597
598 spin_lock_irqsave(&ci->lock, flags);
599 role = ci_role_to_usb_role(ci);
600 spin_unlock_irqrestore(&ci->lock, flags);
601
602 return role;
603 }
604
ci_usb_role_switch_set(struct usb_role_switch * sw,enum usb_role role)605 static int ci_usb_role_switch_set(struct usb_role_switch *sw,
606 enum usb_role role)
607 {
608 struct ci_hdrc *ci = usb_role_switch_get_drvdata(sw);
609 struct ci_hdrc_cable *cable = NULL;
610 enum usb_role current_role = ci_role_to_usb_role(ci);
611 enum ci_role ci_role = usb_role_to_ci_role(role);
612 unsigned long flags;
613
614 if ((ci_role != CI_ROLE_END && !ci->roles[ci_role]) ||
615 (current_role == role))
616 return 0;
617
618 pm_runtime_get_sync(ci->dev);
619 /* Stop current role */
620 spin_lock_irqsave(&ci->lock, flags);
621 if (current_role == USB_ROLE_DEVICE)
622 cable = &ci->platdata->vbus_extcon;
623 else if (current_role == USB_ROLE_HOST)
624 cable = &ci->platdata->id_extcon;
625
626 if (cable) {
627 cable->changed = true;
628 cable->connected = false;
629 ci_irq(ci);
630 spin_unlock_irqrestore(&ci->lock, flags);
631 if (ci->wq && role != USB_ROLE_NONE)
632 flush_workqueue(ci->wq);
633 spin_lock_irqsave(&ci->lock, flags);
634 }
635
636 cable = NULL;
637
638 /* Start target role */
639 if (role == USB_ROLE_DEVICE)
640 cable = &ci->platdata->vbus_extcon;
641 else if (role == USB_ROLE_HOST)
642 cable = &ci->platdata->id_extcon;
643
644 if (cable) {
645 cable->changed = true;
646 cable->connected = true;
647 ci_irq(ci);
648 }
649 spin_unlock_irqrestore(&ci->lock, flags);
650 pm_runtime_put_sync(ci->dev);
651
652 return 0;
653 }
654
655 static struct usb_role_switch_desc ci_role_switch = {
656 .set = ci_usb_role_switch_set,
657 .get = ci_usb_role_switch_get,
658 .allow_userspace_control = true,
659 };
660
ci_get_platdata(struct device * dev,struct ci_hdrc_platform_data * platdata)661 static int ci_get_platdata(struct device *dev,
662 struct ci_hdrc_platform_data *platdata)
663 {
664 struct extcon_dev *ext_vbus, *ext_id;
665 struct ci_hdrc_cable *cable;
666 int ret;
667
668 if (!platdata->phy_mode)
669 platdata->phy_mode = of_usb_get_phy_mode(dev->of_node);
670
671 if (!platdata->dr_mode)
672 platdata->dr_mode = usb_get_dr_mode(dev);
673
674 if (platdata->dr_mode == USB_DR_MODE_UNKNOWN)
675 platdata->dr_mode = USB_DR_MODE_OTG;
676
677 if (platdata->dr_mode != USB_DR_MODE_PERIPHERAL) {
678 /* Get the vbus regulator */
679 platdata->reg_vbus = devm_regulator_get_optional(dev, "vbus");
680 if (PTR_ERR(platdata->reg_vbus) == -EPROBE_DEFER) {
681 return -EPROBE_DEFER;
682 } else if (PTR_ERR(platdata->reg_vbus) == -ENODEV) {
683 /* no vbus regulator is needed */
684 platdata->reg_vbus = NULL;
685 } else if (IS_ERR(platdata->reg_vbus)) {
686 dev_err(dev, "Getting regulator error: %ld\n",
687 PTR_ERR(platdata->reg_vbus));
688 return PTR_ERR(platdata->reg_vbus);
689 }
690 /* Get TPL support */
691 if (!platdata->tpl_support)
692 platdata->tpl_support =
693 of_usb_host_tpl_support(dev->of_node);
694 }
695
696 if (platdata->dr_mode == USB_DR_MODE_OTG) {
697 /* We can support HNP and SRP of OTG 2.0 */
698 platdata->ci_otg_caps.otg_rev = 0x0200;
699 platdata->ci_otg_caps.hnp_support = true;
700 platdata->ci_otg_caps.srp_support = true;
701
702 /* Update otg capabilities by DT properties */
703 ret = of_usb_update_otg_caps(dev->of_node,
704 &platdata->ci_otg_caps);
705 if (ret)
706 return ret;
707 }
708
709 if (usb_get_maximum_speed(dev) == USB_SPEED_FULL)
710 platdata->flags |= CI_HDRC_FORCE_FULLSPEED;
711
712 of_property_read_u32(dev->of_node, "phy-clkgate-delay-us",
713 &platdata->phy_clkgate_delay_us);
714
715 platdata->itc_setting = 1;
716
717 of_property_read_u32(dev->of_node, "itc-setting",
718 &platdata->itc_setting);
719
720 ret = of_property_read_u32(dev->of_node, "ahb-burst-config",
721 &platdata->ahb_burst_config);
722 if (!ret) {
723 platdata->flags |= CI_HDRC_OVERRIDE_AHB_BURST;
724 } else if (ret != -EINVAL) {
725 dev_err(dev, "failed to get ahb-burst-config\n");
726 return ret;
727 }
728
729 ret = of_property_read_u32(dev->of_node, "tx-burst-size-dword",
730 &platdata->tx_burst_size);
731 if (!ret) {
732 platdata->flags |= CI_HDRC_OVERRIDE_TX_BURST;
733 } else if (ret != -EINVAL) {
734 dev_err(dev, "failed to get tx-burst-size-dword\n");
735 return ret;
736 }
737
738 ret = of_property_read_u32(dev->of_node, "rx-burst-size-dword",
739 &platdata->rx_burst_size);
740 if (!ret) {
741 platdata->flags |= CI_HDRC_OVERRIDE_RX_BURST;
742 } else if (ret != -EINVAL) {
743 dev_err(dev, "failed to get rx-burst-size-dword\n");
744 return ret;
745 }
746
747 if (of_find_property(dev->of_node, "non-zero-ttctrl-ttha", NULL))
748 platdata->flags |= CI_HDRC_SET_NON_ZERO_TTHA;
749
750 ext_id = ERR_PTR(-ENODEV);
751 ext_vbus = ERR_PTR(-ENODEV);
752 if (of_property_read_bool(dev->of_node, "extcon")) {
753 /* Each one of them is not mandatory */
754 ext_vbus = extcon_get_edev_by_phandle(dev, 0);
755 if (IS_ERR(ext_vbus) && PTR_ERR(ext_vbus) != -ENODEV)
756 return PTR_ERR(ext_vbus);
757
758 ext_id = extcon_get_edev_by_phandle(dev, 1);
759 if (IS_ERR(ext_id) && PTR_ERR(ext_id) != -ENODEV)
760 return PTR_ERR(ext_id);
761 }
762
763 cable = &platdata->vbus_extcon;
764 cable->nb.notifier_call = ci_cable_notifier;
765 cable->edev = ext_vbus;
766
767 if (!IS_ERR(ext_vbus)) {
768 ret = extcon_get_state(cable->edev, EXTCON_USB);
769 if (ret)
770 cable->connected = true;
771 else
772 cable->connected = false;
773 }
774
775 cable = &platdata->id_extcon;
776 cable->nb.notifier_call = ci_cable_notifier;
777 cable->edev = ext_id;
778
779 if (!IS_ERR(ext_id)) {
780 ret = extcon_get_state(cable->edev, EXTCON_USB_HOST);
781 if (ret)
782 cable->connected = true;
783 else
784 cable->connected = false;
785 }
786
787 if (device_property_read_bool(dev, "usb-role-switch"))
788 ci_role_switch.fwnode = dev->fwnode;
789
790 platdata->pctl = devm_pinctrl_get(dev);
791 if (!IS_ERR(platdata->pctl)) {
792 struct pinctrl_state *p;
793
794 p = pinctrl_lookup_state(platdata->pctl, "default");
795 if (!IS_ERR(p))
796 platdata->pins_default = p;
797
798 p = pinctrl_lookup_state(platdata->pctl, "host");
799 if (!IS_ERR(p))
800 platdata->pins_host = p;
801
802 p = pinctrl_lookup_state(platdata->pctl, "device");
803 if (!IS_ERR(p))
804 platdata->pins_device = p;
805 }
806
807 if (!platdata->enter_lpm)
808 platdata->enter_lpm = ci_hdrc_enter_lpm_common;
809
810 return 0;
811 }
812
ci_extcon_register(struct ci_hdrc * ci)813 static int ci_extcon_register(struct ci_hdrc *ci)
814 {
815 struct ci_hdrc_cable *id, *vbus;
816 int ret;
817
818 id = &ci->platdata->id_extcon;
819 id->ci = ci;
820 if (!IS_ERR_OR_NULL(id->edev)) {
821 ret = devm_extcon_register_notifier(ci->dev, id->edev,
822 EXTCON_USB_HOST, &id->nb);
823 if (ret < 0) {
824 dev_err(ci->dev, "register ID failed\n");
825 return ret;
826 }
827 }
828
829 vbus = &ci->platdata->vbus_extcon;
830 vbus->ci = ci;
831 if (!IS_ERR_OR_NULL(vbus->edev)) {
832 ret = devm_extcon_register_notifier(ci->dev, vbus->edev,
833 EXTCON_USB, &vbus->nb);
834 if (ret < 0) {
835 dev_err(ci->dev, "register VBUS failed\n");
836 return ret;
837 }
838 }
839
840 return 0;
841 }
842
843 static DEFINE_IDA(ci_ida);
844
ci_hdrc_add_device(struct device * dev,struct resource * res,int nres,struct ci_hdrc_platform_data * platdata)845 struct platform_device *ci_hdrc_add_device(struct device *dev,
846 struct resource *res, int nres,
847 struct ci_hdrc_platform_data *platdata)
848 {
849 struct platform_device *pdev;
850 int id, ret;
851
852 ret = ci_get_platdata(dev, platdata);
853 if (ret)
854 return ERR_PTR(ret);
855
856 id = ida_simple_get(&ci_ida, 0, 0, GFP_KERNEL);
857 if (id < 0)
858 return ERR_PTR(id);
859
860 pdev = platform_device_alloc("ci_hdrc", id);
861 if (!pdev) {
862 ret = -ENOMEM;
863 goto put_id;
864 }
865
866 pdev->dev.parent = dev;
867
868 ret = platform_device_add_resources(pdev, res, nres);
869 if (ret)
870 goto err;
871
872 ret = platform_device_add_data(pdev, platdata, sizeof(*platdata));
873 if (ret)
874 goto err;
875
876 ret = platform_device_add(pdev);
877 if (ret)
878 goto err;
879
880 return pdev;
881
882 err:
883 platform_device_put(pdev);
884 put_id:
885 ida_simple_remove(&ci_ida, id);
886 return ERR_PTR(ret);
887 }
888 EXPORT_SYMBOL_GPL(ci_hdrc_add_device);
889
ci_hdrc_remove_device(struct platform_device * pdev)890 void ci_hdrc_remove_device(struct platform_device *pdev)
891 {
892 int id = pdev->id;
893 platform_device_unregister(pdev);
894 ida_simple_remove(&ci_ida, id);
895 }
896 EXPORT_SYMBOL_GPL(ci_hdrc_remove_device);
897
898 /**
899 * ci_hdrc_query_available_role: get runtime available operation mode
900 *
901 * The glue layer can get current operation mode (host/peripheral/otg)
902 * This function should be called after ci core device has created.
903 *
904 * @pdev: the platform device of ci core.
905 *
906 * Return runtime usb_dr_mode.
907 */
ci_hdrc_query_available_role(struct platform_device * pdev)908 enum usb_dr_mode ci_hdrc_query_available_role(struct platform_device *pdev)
909 {
910 struct ci_hdrc *ci = platform_get_drvdata(pdev);
911
912 if (!ci)
913 return USB_DR_MODE_UNKNOWN;
914 if (ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET])
915 return USB_DR_MODE_OTG;
916 else if (ci->roles[CI_ROLE_HOST])
917 return USB_DR_MODE_HOST;
918 else if (ci->roles[CI_ROLE_GADGET])
919 return USB_DR_MODE_PERIPHERAL;
920 else
921 return USB_DR_MODE_UNKNOWN;
922 }
923 EXPORT_SYMBOL_GPL(ci_hdrc_query_available_role);
924
ci_role_destroy(struct ci_hdrc * ci)925 static inline void ci_role_destroy(struct ci_hdrc *ci)
926 {
927 ci_hdrc_gadget_destroy(ci);
928 ci_hdrc_host_destroy(ci);
929 if (ci->is_otg && ci->roles[CI_ROLE_GADGET])
930 ci_hdrc_otg_destroy(ci);
931 }
932
ci_get_otg_capable(struct ci_hdrc * ci)933 static void ci_get_otg_capable(struct ci_hdrc *ci)
934 {
935 if (ci->platdata->flags & CI_HDRC_DUAL_ROLE_NOT_OTG)
936 ci->is_otg = false;
937 else
938 ci->is_otg = (hw_read(ci, CAP_DCCPARAMS,
939 DCCPARAMS_DC | DCCPARAMS_HC)
940 == (DCCPARAMS_DC | DCCPARAMS_HC));
941 if (ci->is_otg) {
942 dev_dbg(ci->dev, "It is OTG capable controller\n");
943 /* Disable and clear all OTG irq */
944 hw_write_otgsc(ci, OTGSC_INT_EN_BITS | OTGSC_INT_STATUS_BITS,
945 OTGSC_INT_STATUS_BITS);
946 }
947 }
948
role_show(struct device * dev,struct device_attribute * attr,char * buf)949 static ssize_t role_show(struct device *dev, struct device_attribute *attr,
950 char *buf)
951 {
952 struct ci_hdrc *ci = dev_get_drvdata(dev);
953
954 if (ci->role != CI_ROLE_END)
955 return sprintf(buf, "%s\n", ci_role(ci)->name);
956
957 return 0;
958 }
959
role_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t n)960 static ssize_t role_store(struct device *dev,
961 struct device_attribute *attr, const char *buf, size_t n)
962 {
963 struct ci_hdrc *ci = dev_get_drvdata(dev);
964 enum ci_role role;
965 int ret;
966
967 if (!(ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET])) {
968 dev_warn(dev, "Current configuration is not dual-role, quit\n");
969 return -EPERM;
970 }
971
972 for (role = CI_ROLE_HOST; role < CI_ROLE_END; role++)
973 if (!strncmp(buf, ci->roles[role]->name,
974 strlen(ci->roles[role]->name)))
975 break;
976
977 if (role == CI_ROLE_END || role == ci->role)
978 return -EINVAL;
979
980 pm_runtime_get_sync(dev);
981 disable_irq(ci->irq);
982 ci_role_stop(ci);
983 ret = ci_role_start(ci, role);
984 if (!ret && ci->role == CI_ROLE_GADGET)
985 ci_handle_vbus_change(ci);
986 enable_irq(ci->irq);
987 pm_runtime_put_sync(dev);
988
989 return (ret == 0) ? n : ret;
990 }
991 static DEVICE_ATTR_RW(role);
992
993 static struct attribute *ci_attrs[] = {
994 &dev_attr_role.attr,
995 NULL,
996 };
997 ATTRIBUTE_GROUPS(ci);
998
ci_hdrc_probe(struct platform_device * pdev)999 static int ci_hdrc_probe(struct platform_device *pdev)
1000 {
1001 struct device *dev = &pdev->dev;
1002 struct ci_hdrc *ci;
1003 struct resource *res;
1004 void __iomem *base;
1005 int ret;
1006 enum usb_dr_mode dr_mode;
1007
1008 if (!dev_get_platdata(dev)) {
1009 dev_err(dev, "platform data missing\n");
1010 return -ENODEV;
1011 }
1012
1013 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1014 base = devm_ioremap_resource(dev, res);
1015 if (IS_ERR(base))
1016 return PTR_ERR(base);
1017
1018 ci = devm_kzalloc(dev, sizeof(*ci), GFP_KERNEL);
1019 if (!ci)
1020 return -ENOMEM;
1021
1022 spin_lock_init(&ci->lock);
1023 ci->dev = dev;
1024 ci->platdata = dev_get_platdata(dev);
1025 ci->imx28_write_fix = !!(ci->platdata->flags &
1026 CI_HDRC_IMX28_WRITE_FIX);
1027 ci->supports_runtime_pm = !!(ci->platdata->flags &
1028 CI_HDRC_SUPPORTS_RUNTIME_PM);
1029 platform_set_drvdata(pdev, ci);
1030
1031 ret = hw_device_init(ci, base);
1032 if (ret < 0) {
1033 dev_err(dev, "can't initialize hardware\n");
1034 return -ENODEV;
1035 }
1036
1037 ret = ci_ulpi_init(ci);
1038 if (ret)
1039 return ret;
1040
1041 if (ci->platdata->phy) {
1042 ci->phy = ci->platdata->phy;
1043 } else if (ci->platdata->usb_phy) {
1044 ci->usb_phy = ci->platdata->usb_phy;
1045 } else {
1046 /* Look for a generic PHY first */
1047 ci->phy = devm_phy_get(dev->parent, "usb-phy");
1048
1049 if (PTR_ERR(ci->phy) == -EPROBE_DEFER) {
1050 ret = -EPROBE_DEFER;
1051 goto ulpi_exit;
1052 } else if (IS_ERR(ci->phy)) {
1053 ci->phy = NULL;
1054 }
1055
1056 /* Look for a legacy USB PHY from device-tree next */
1057 if (!ci->phy) {
1058 ci->usb_phy = devm_usb_get_phy_by_phandle(dev->parent,
1059 "phys", 0);
1060
1061 if (PTR_ERR(ci->usb_phy) == -EPROBE_DEFER) {
1062 ret = -EPROBE_DEFER;
1063 goto ulpi_exit;
1064 } else if (IS_ERR(ci->usb_phy)) {
1065 ci->usb_phy = NULL;
1066 }
1067 }
1068
1069 /* Look for any registered legacy USB PHY as last resort */
1070 if (!ci->phy && !ci->usb_phy) {
1071 ci->usb_phy = devm_usb_get_phy(dev->parent,
1072 USB_PHY_TYPE_USB2);
1073
1074 if (PTR_ERR(ci->usb_phy) == -EPROBE_DEFER) {
1075 ret = -EPROBE_DEFER;
1076 goto ulpi_exit;
1077 } else if (IS_ERR(ci->usb_phy)) {
1078 ci->usb_phy = NULL;
1079 }
1080 }
1081
1082 /* No USB PHY was found in the end */
1083 if (!ci->phy && !ci->usb_phy) {
1084 ret = -ENXIO;
1085 goto ulpi_exit;
1086 }
1087 }
1088
1089 ret = ci_usb_phy_init(ci);
1090 if (ret) {
1091 dev_err(dev, "unable to init phy: %d\n", ret);
1092 return ret;
1093 }
1094
1095 ci->hw_bank.phys = res->start;
1096
1097 ci->irq = platform_get_irq(pdev, 0);
1098 if (ci->irq < 0) {
1099 ret = ci->irq;
1100 goto deinit_phy;
1101 }
1102
1103 ci_get_otg_capable(ci);
1104
1105 dr_mode = ci->platdata->dr_mode;
1106 /* initialize role(s) before the interrupt is requested */
1107 if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_HOST) {
1108 ret = ci_hdrc_host_init(ci);
1109 if (ret) {
1110 if (ret == -ENXIO)
1111 dev_info(dev, "doesn't support host\n");
1112 else
1113 goto deinit_phy;
1114 }
1115 }
1116
1117 if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_PERIPHERAL) {
1118 ret = ci_hdrc_gadget_init(ci);
1119 if (ret) {
1120 if (ret == -ENXIO)
1121 dev_info(dev, "doesn't support gadget\n");
1122 else
1123 goto deinit_host;
1124 }
1125 }
1126
1127 if (!ci->roles[CI_ROLE_HOST] && !ci->roles[CI_ROLE_GADGET]) {
1128 dev_err(dev, "no supported roles\n");
1129 ret = -ENODEV;
1130 goto deinit_gadget;
1131 }
1132
1133 if (ci->is_otg && ci->roles[CI_ROLE_GADGET]) {
1134 ret = ci_hdrc_otg_init(ci);
1135 if (ret) {
1136 dev_err(dev, "init otg fails, ret = %d\n", ret);
1137 goto deinit_gadget;
1138 }
1139 }
1140
1141 if (ci_role_switch.fwnode) {
1142 ci_role_switch.driver_data = ci;
1143 ci->role_switch = usb_role_switch_register(dev,
1144 &ci_role_switch);
1145 if (IS_ERR(ci->role_switch)) {
1146 ret = PTR_ERR(ci->role_switch);
1147 goto deinit_otg;
1148 }
1149 }
1150
1151 if (ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET]) {
1152 if (ci->is_otg) {
1153 ci->role = ci_otg_role(ci);
1154 /* Enable ID change irq */
1155 hw_write_otgsc(ci, OTGSC_IDIE, OTGSC_IDIE);
1156 } else {
1157 /*
1158 * If the controller is not OTG capable, but support
1159 * role switch, the defalt role is gadget, and the
1160 * user can switch it through debugfs.
1161 */
1162 ci->role = CI_ROLE_GADGET;
1163 }
1164 } else {
1165 ci->role = ci->roles[CI_ROLE_HOST]
1166 ? CI_ROLE_HOST
1167 : CI_ROLE_GADGET;
1168 }
1169
1170 if (!ci_otg_is_fsm_mode(ci)) {
1171 /* only update vbus status for peripheral */
1172 if (ci->role == CI_ROLE_GADGET) {
1173 /* Pull down DP for possible charger detection */
1174 hw_write(ci, OP_USBCMD, USBCMD_RS, 0);
1175 ci_handle_vbus_change(ci);
1176 }
1177
1178 ret = ci_role_start(ci, ci->role);
1179 if (ret) {
1180 dev_err(dev, "can't start %s role\n",
1181 ci_role(ci)->name);
1182 goto stop;
1183 }
1184 }
1185
1186 ret = devm_request_irq(dev, ci->irq, ci_irq_handler, IRQF_SHARED,
1187 ci->platdata->name, ci);
1188 if (ret)
1189 goto stop;
1190
1191 ret = ci_extcon_register(ci);
1192 if (ret)
1193 goto stop;
1194
1195 if (ci->supports_runtime_pm) {
1196 pm_runtime_set_active(&pdev->dev);
1197 pm_runtime_enable(&pdev->dev);
1198 pm_runtime_set_autosuspend_delay(&pdev->dev, 2000);
1199 pm_runtime_mark_last_busy(ci->dev);
1200 pm_runtime_use_autosuspend(&pdev->dev);
1201 }
1202
1203 if (ci_otg_is_fsm_mode(ci))
1204 ci_hdrc_otg_fsm_start(ci);
1205
1206 device_set_wakeup_capable(&pdev->dev, true);
1207 dbg_create_files(ci);
1208
1209 return 0;
1210
1211 stop:
1212 if (ci->role_switch)
1213 usb_role_switch_unregister(ci->role_switch);
1214 deinit_otg:
1215 if (ci->is_otg && ci->roles[CI_ROLE_GADGET])
1216 ci_hdrc_otg_destroy(ci);
1217 deinit_gadget:
1218 ci_hdrc_gadget_destroy(ci);
1219 deinit_host:
1220 ci_hdrc_host_destroy(ci);
1221 deinit_phy:
1222 ci_usb_phy_exit(ci);
1223 ulpi_exit:
1224 ci_ulpi_exit(ci);
1225
1226 return ret;
1227 }
1228
ci_hdrc_remove(struct platform_device * pdev)1229 static int ci_hdrc_remove(struct platform_device *pdev)
1230 {
1231 struct ci_hdrc *ci = platform_get_drvdata(pdev);
1232
1233 if (ci->role_switch)
1234 usb_role_switch_unregister(ci->role_switch);
1235
1236 if (ci->supports_runtime_pm) {
1237 pm_runtime_get_sync(&pdev->dev);
1238 pm_runtime_disable(&pdev->dev);
1239 pm_runtime_put_noidle(&pdev->dev);
1240 }
1241
1242 dbg_remove_files(ci);
1243 ci_role_destroy(ci);
1244 ci_hdrc_enter_lpm(ci, true);
1245 ci_usb_phy_exit(ci);
1246 ci_ulpi_exit(ci);
1247
1248 return 0;
1249 }
1250
1251 #ifdef CONFIG_PM
1252 /* Prepare wakeup by SRP before suspend */
ci_otg_fsm_suspend_for_srp(struct ci_hdrc * ci)1253 static void ci_otg_fsm_suspend_for_srp(struct ci_hdrc *ci)
1254 {
1255 if ((ci->fsm.otg->state == OTG_STATE_A_IDLE) &&
1256 !hw_read_otgsc(ci, OTGSC_ID)) {
1257 hw_write(ci, OP_PORTSC, PORTSC_W1C_BITS | PORTSC_PP,
1258 PORTSC_PP);
1259 hw_write(ci, OP_PORTSC, PORTSC_W1C_BITS | PORTSC_WKCN,
1260 PORTSC_WKCN);
1261 }
1262 }
1263
1264 /* Handle SRP when wakeup by data pulse */
ci_otg_fsm_wakeup_by_srp(struct ci_hdrc * ci)1265 static void ci_otg_fsm_wakeup_by_srp(struct ci_hdrc *ci)
1266 {
1267 if ((ci->fsm.otg->state == OTG_STATE_A_IDLE) &&
1268 (ci->fsm.a_bus_drop == 1) && (ci->fsm.a_bus_req == 0)) {
1269 if (!hw_read_otgsc(ci, OTGSC_ID)) {
1270 ci->fsm.a_srp_det = 1;
1271 ci->fsm.a_bus_drop = 0;
1272 } else {
1273 ci->fsm.id = 1;
1274 }
1275 ci_otg_queue_work(ci);
1276 }
1277 }
1278
ci_controller_suspend(struct ci_hdrc * ci)1279 static void ci_controller_suspend(struct ci_hdrc *ci)
1280 {
1281 disable_irq(ci->irq);
1282 ci_hdrc_enter_lpm(ci, true);
1283 if (ci->platdata->phy_clkgate_delay_us)
1284 usleep_range(ci->platdata->phy_clkgate_delay_us,
1285 ci->platdata->phy_clkgate_delay_us + 50);
1286 usb_phy_set_suspend(ci->usb_phy, 1);
1287 ci->in_lpm = true;
1288 enable_irq(ci->irq);
1289 }
1290
1291 /*
1292 * Handle the wakeup interrupt triggered by extcon connector
1293 * We need to call ci_irq again for extcon since the first
1294 * interrupt (wakeup int) only let the controller be out of
1295 * low power mode, but not handle any interrupts.
1296 */
ci_extcon_wakeup_int(struct ci_hdrc * ci)1297 static void ci_extcon_wakeup_int(struct ci_hdrc *ci)
1298 {
1299 struct ci_hdrc_cable *cable_id, *cable_vbus;
1300 u32 otgsc = hw_read_otgsc(ci, ~0);
1301
1302 cable_id = &ci->platdata->id_extcon;
1303 cable_vbus = &ci->platdata->vbus_extcon;
1304
1305 if (!IS_ERR(cable_id->edev) && ci->is_otg &&
1306 (otgsc & OTGSC_IDIE) && (otgsc & OTGSC_IDIS))
1307 ci_irq(ci);
1308
1309 if (!IS_ERR(cable_vbus->edev) && ci->is_otg &&
1310 (otgsc & OTGSC_BSVIE) && (otgsc & OTGSC_BSVIS))
1311 ci_irq(ci);
1312 }
1313
ci_controller_resume(struct device * dev)1314 static int ci_controller_resume(struct device *dev)
1315 {
1316 struct ci_hdrc *ci = dev_get_drvdata(dev);
1317 int ret;
1318
1319 dev_dbg(dev, "at %s\n", __func__);
1320
1321 if (!ci->in_lpm) {
1322 WARN_ON(1);
1323 return 0;
1324 }
1325
1326 ci_hdrc_enter_lpm(ci, false);
1327
1328 ret = ci_ulpi_resume(ci);
1329 if (ret)
1330 return ret;
1331
1332 if (ci->usb_phy) {
1333 usb_phy_set_suspend(ci->usb_phy, 0);
1334 usb_phy_set_wakeup(ci->usb_phy, false);
1335 hw_wait_phy_stable();
1336 }
1337
1338 ci->in_lpm = false;
1339 if (ci->wakeup_int) {
1340 ci->wakeup_int = false;
1341 pm_runtime_mark_last_busy(ci->dev);
1342 pm_runtime_put_autosuspend(ci->dev);
1343 enable_irq(ci->irq);
1344 if (ci_otg_is_fsm_mode(ci))
1345 ci_otg_fsm_wakeup_by_srp(ci);
1346 ci_extcon_wakeup_int(ci);
1347 }
1348
1349 return 0;
1350 }
1351
1352 #ifdef CONFIG_PM_SLEEP
ci_suspend(struct device * dev)1353 static int ci_suspend(struct device *dev)
1354 {
1355 struct ci_hdrc *ci = dev_get_drvdata(dev);
1356
1357 if (ci->wq)
1358 flush_workqueue(ci->wq);
1359 /*
1360 * Controller needs to be active during suspend, otherwise the core
1361 * may run resume when the parent is at suspend if other driver's
1362 * suspend fails, it occurs before parent's suspend has not started,
1363 * but the core suspend has finished.
1364 */
1365 if (ci->in_lpm)
1366 pm_runtime_resume(dev);
1367
1368 if (ci->in_lpm) {
1369 WARN_ON(1);
1370 return 0;
1371 }
1372
1373 if (device_may_wakeup(dev)) {
1374 if (ci_otg_is_fsm_mode(ci))
1375 ci_otg_fsm_suspend_for_srp(ci);
1376
1377 usb_phy_set_wakeup(ci->usb_phy, true);
1378 enable_irq_wake(ci->irq);
1379 }
1380
1381 ci_controller_suspend(ci);
1382
1383 return 0;
1384 }
1385
ci_resume(struct device * dev)1386 static int ci_resume(struct device *dev)
1387 {
1388 struct ci_hdrc *ci = dev_get_drvdata(dev);
1389 int ret;
1390
1391 if (device_may_wakeup(dev))
1392 disable_irq_wake(ci->irq);
1393
1394 ret = ci_controller_resume(dev);
1395 if (ret)
1396 return ret;
1397
1398 if (ci->supports_runtime_pm) {
1399 pm_runtime_disable(dev);
1400 pm_runtime_set_active(dev);
1401 pm_runtime_enable(dev);
1402 }
1403
1404 return ret;
1405 }
1406 #endif /* CONFIG_PM_SLEEP */
1407
ci_runtime_suspend(struct device * dev)1408 static int ci_runtime_suspend(struct device *dev)
1409 {
1410 struct ci_hdrc *ci = dev_get_drvdata(dev);
1411
1412 dev_dbg(dev, "at %s\n", __func__);
1413
1414 if (ci->in_lpm) {
1415 WARN_ON(1);
1416 return 0;
1417 }
1418
1419 if (ci_otg_is_fsm_mode(ci))
1420 ci_otg_fsm_suspend_for_srp(ci);
1421
1422 usb_phy_set_wakeup(ci->usb_phy, true);
1423 ci_controller_suspend(ci);
1424
1425 return 0;
1426 }
1427
ci_runtime_resume(struct device * dev)1428 static int ci_runtime_resume(struct device *dev)
1429 {
1430 return ci_controller_resume(dev);
1431 }
1432
1433 #endif /* CONFIG_PM */
1434 static const struct dev_pm_ops ci_pm_ops = {
1435 SET_SYSTEM_SLEEP_PM_OPS(ci_suspend, ci_resume)
1436 SET_RUNTIME_PM_OPS(ci_runtime_suspend, ci_runtime_resume, NULL)
1437 };
1438
1439 static struct platform_driver ci_hdrc_driver = {
1440 .probe = ci_hdrc_probe,
1441 .remove = ci_hdrc_remove,
1442 .driver = {
1443 .name = "ci_hdrc",
1444 .pm = &ci_pm_ops,
1445 .dev_groups = ci_groups,
1446 },
1447 };
1448
ci_hdrc_platform_register(void)1449 static int __init ci_hdrc_platform_register(void)
1450 {
1451 ci_hdrc_host_driver_init();
1452 return platform_driver_register(&ci_hdrc_driver);
1453 }
1454 module_init(ci_hdrc_platform_register);
1455
ci_hdrc_platform_unregister(void)1456 static void __exit ci_hdrc_platform_unregister(void)
1457 {
1458 platform_driver_unregister(&ci_hdrc_driver);
1459 }
1460 module_exit(ci_hdrc_platform_unregister);
1461
1462 MODULE_ALIAS("platform:ci_hdrc");
1463 MODULE_LICENSE("GPL v2");
1464 MODULE_AUTHOR("David Lopo <dlopo@chipidea.mips.com>");
1465 MODULE_DESCRIPTION("ChipIdea HDRC Driver");
1466