1 /*
2 * Standalone EHCI USB debug driver
3 *
4 * Hardware interface code based on the respective early console driver in
5 * Linux; see the Linux source for authorship and copyrights.
6 */
7
8 #include <xen/console.h>
9 #include <xen/delay.h>
10 #include <xen/errno.h>
11 #include <xen/param.h>
12 #include <xen/pci.h>
13 #include <xen/serial.h>
14 #include <asm/byteorder.h>
15 #include <asm/io.h>
16 #include <asm/fixmap.h>
17 #include <public/physdev.h>
18
19 /* #define DBGP_DEBUG */
20
21 /* EHCI register interface, corresponds to EHCI Revision 0.95 specification */
22
23 /* Section 2.2 Host Controller Capability Registers */
24 struct ehci_caps {
25 /*
26 * These fields are specified as 8 and 16 bit registers,
27 * but some hosts can't perform 8 or 16 bit PCI accesses.
28 * some hosts treat caplength and hciversion as parts of a 32-bit
29 * register, others treat them as two separate registers, this
30 * affects the memory map for big endian controllers.
31 */
32 u32 hc_capbase;
33 #define HC_LENGTH(p) (0x00ff & (p)) /* bits 7:0 / offset 0x00 */
34 #define HC_VERSION(p) (0xffff & ((p) >> 16)) /* bits 31:16 / offset 0x02 */
35
36 u32 hcs_params; /* HCSPARAMS - offset 0x04 */
37 #define HCS_DEBUG_PORT(p) (((p) >> 20) & 0xf) /* bits 23:20, debug port? */
38 #define HCS_INDICATOR(p) ((p) & (1 << 16)) /* true: has port indicators */
39 #define HCS_N_CC(p) (((p) >> 12) & 0xf) /* bits 15:12, #companion HCs */
40 #define HCS_N_PCC(p) (((p) >> 8) & 0xf) /* bits 11:8, ports per CC */
41 #define HCS_PORTROUTED(p) ((p) & (1 << 7)) /* true: port routing */
42 #define HCS_PPC(p) ((p) & (1 << 4)) /* true: port power control */
43 #define HCS_N_PORTS(p) (((p) >> 0) & 0xf) /* bits 3:0, ports on HC */
44
45 u32 hcc_params; /* HCCPARAMS - offset 0x08 */
46 /* EHCI 1.1 addendum */
47 #define HCC_32FRAME_PERIODIC_LIST(p) ((p) & (1 << 19))
48 #define HCC_PER_PORT_CHANGE_EVENT(p) ((p) & (1 << 18))
49 #define HCC_LPM(p) ((p) & (1 << 17))
50 #define HCC_HW_PREFETCH(p) ((p) & (1 << 16))
51 #define HCC_EXT_CAPS(p) (((p) >> 8) & 0xff) /* for pci extended caps */
52 #define HCC_ISOC_CACHE(p) ((p) & (1 << 7)) /* true: can cache isoc frame */
53 #define HCC_ISOC_THRES(p) (((p) >> 4) & 0x7) /* bits 6:4, uframes cached */
54 #define HCC_CANPARK(p) ((p) & (1 << 2)) /* true: can park on async qh */
55 #define HCC_PGM_FRAMELISTLEN(p) ((p) & (1 << 1)) /* true: periodic_size changes */
56 #define HCC_64BIT_ADDR(p) ((p) & 1) /* true: can use 64-bit addr */
57
58 u8 portroute[8]; /* nibbles for routing - offset 0x0C */
59 };
60
61 /* Section 2.3 Host Controller Operational Registers */
62 struct ehci_regs {
63 /* USBCMD: offset 0x00 */
64 u32 command;
65
66 /* EHCI 1.1 addendum */
67 #define CMD_HIRD (0xf << 24) /* host initiated resume duration */
68 #define CMD_PPCEE (1 << 15) /* per port change event enable */
69 #define CMD_FSP (1 << 14) /* fully synchronized prefetch */
70 #define CMD_ASPE (1 << 13) /* async schedule prefetch enable */
71 #define CMD_PSPE (1 << 12) /* periodic schedule prefetch enable */
72 /* 23:16 is r/w intr rate, in microframes; default "8" == 1/msec */
73 #define CMD_PARK (1 << 11) /* enable "park" on async qh */
74 #define CMD_PARK_CNT(c) (((c) >> 8) & 3) /* how many transfers to park for */
75 #define CMD_LRESET (1 << 7) /* partial reset (no ports, etc) */
76 #define CMD_IAAD (1 << 6) /* "doorbell" interrupt async advance */
77 #define CMD_ASE (1 << 5) /* async schedule enable */
78 #define CMD_PSE (1 << 4) /* periodic schedule enable */
79 /* 3:2 is periodic frame list size */
80 #define CMD_RESET (1 << 1) /* reset HC not bus */
81 #define CMD_RUN (1 << 0) /* start/stop HC */
82
83 /* USBSTS: offset 0x04 */
84 u32 status;
85 #define STS_PPCE_MASK (0xff << 16) /* Per-Port change event 1-16 */
86 #define STS_ASS (1 << 15) /* Async Schedule Status */
87 #define STS_PSS (1 << 14) /* Periodic Schedule Status */
88 #define STS_RECL (1 << 13) /* Reclamation */
89 #define STS_HALT (1 << 12) /* Not running (any reason) */
90 /* some bits reserved */
91 /* these STS_* flags are also intr_enable bits (USBINTR) */
92 #define STS_IAA (1 << 5) /* Interrupted on async advance */
93 #define STS_FATAL (1 << 4) /* such as some PCI access errors */
94 #define STS_FLR (1 << 3) /* frame list rolled over */
95 #define STS_PCD (1 << 2) /* port change detect */
96 #define STS_ERR (1 << 1) /* "error" completion (overflow, ...) */
97 #define STS_INT (1 << 0) /* "normal" completion (short, ...) */
98
99 /* USBINTR: offset 0x08 */
100 u32 intr_enable;
101
102 /* FRINDEX: offset 0x0C */
103 u32 frame_index; /* current microframe number */
104 /* CTRLDSSEGMENT: offset 0x10 */
105 u32 segment; /* address bits 63:32 if needed */
106 /* PERIODICLISTBASE: offset 0x14 */
107 u32 frame_list; /* points to periodic list */
108 /* ASYNCLISTADDR: offset 0x18 */
109 u32 async_next; /* address of next async queue head */
110
111 u32 reserved[9];
112
113 /* CONFIGFLAG: offset 0x40 */
114 u32 configured_flag;
115 #define FLAG_CF (1 << 0) /* true: we'll support "high speed" */
116
117 /* PORTSC: offset 0x44 */
118 u32 port_status[0]; /* up to N_PORTS */
119 /* EHCI 1.1 addendum */
120 #define PORTSC_SUSPEND_STS_ACK 0
121 #define PORTSC_SUSPEND_STS_NYET 1
122 #define PORTSC_SUSPEND_STS_STALL 2
123 #define PORTSC_SUSPEND_STS_ERR 3
124
125 #define PORT_DEV_ADDR (0x7f << 25) /* device address */
126 #define PORT_SSTS (0x3 << 23) /* suspend status */
127 /* 31:23 reserved */
128 #define PORT_WKOC_E (1 << 22) /* wake on overcurrent (enable) */
129 #define PORT_WKDISC_E (1 << 21) /* wake on disconnect (enable) */
130 #define PORT_WKCONN_E (1 << 20) /* wake on connect (enable) */
131 /* 19:16 for port testing */
132 #define PORT_TEST(x) (((x) & 0xf) << 16) /* Port Test Control */
133 #define PORT_TEST_PKT PORT_TEST(0x4) /* Port Test Control - packet test */
134 #define PORT_TEST_FORCE PORT_TEST(0x5) /* Port Test Control - force enable */
135 #define PORT_LED_OFF (0 << 14)
136 #define PORT_LED_AMBER (1 << 14)
137 #define PORT_LED_GREEN (2 << 14)
138 #define PORT_LED_MASK (3 << 14)
139 #define PORT_OWNER (1 << 13) /* true: companion hc owns this port */
140 #define PORT_POWER (1 << 12) /* true: has power (see PPC) */
141 #define PORT_USB11(x) (((x) & (3 << 10)) == (1 << 10)) /* USB 1.1 device */
142 /* 11:10 for detecting lowspeed devices (reset vs release ownership) */
143 /* 9 reserved */
144 #define PORT_LPM (1 << 9) /* LPM transaction */
145 #define PORT_RESET (1 << 8) /* reset port */
146 #define PORT_SUSPEND (1 << 7) /* suspend port */
147 #define PORT_RESUME (1 << 6) /* resume it */
148 #define PORT_OCC (1 << 5) /* over current change */
149 #define PORT_OC (1 << 4) /* over current active */
150 #define PORT_PEC (1 << 3) /* port enable change */
151 #define PORT_PE (1 << 2) /* port enable */
152 #define PORT_CSC (1 << 1) /* connect status change */
153 #define PORT_CONNECT (1 << 0) /* device connected */
154 #define PORT_RWC_BITS (PORT_CSC | PORT_PEC | PORT_OCC)
155 };
156
157 /*
158 * Appendix C, Debug port ... intended for use with special "debug devices"
159 * that can help if there's no serial console. (nonstandard enumeration.)
160 */
161 struct ehci_dbg_port {
162 u32 control;
163 #define DBGP_OWNER (1 << 30)
164 #define DBGP_ENABLED (1 << 28)
165 #define DBGP_DONE (1 << 16)
166 #define DBGP_INUSE (1 << 10)
167 #define DBGP_ERRCODE(x) (((x) >> 7) & 0x07)
168 # define DBGP_ERR_BAD 1
169 # define DBGP_ERR_SIGNAL 2
170 #define DBGP_ERROR (1 << 6)
171 #define DBGP_GO (1 << 5)
172 #define DBGP_OUT (1 << 4)
173 #define DBGP_LEN (0xf << 0)
174 #define DBGP_CLAIM (DBGP_OWNER | DBGP_ENABLED | DBGP_INUSE)
175 u32 pids;
176 #define DBGP_PID_GET(x) (((x) >> 16) & 0xff)
177 #define DBGP_PID_SET(data, tok) (((data) << 8) | (tok))
178 u32 data03;
179 u32 data47;
180 u32 address;
181 #define DBGP_EPADDR(dev, ep) (((dev) << 8) | (ep))
182 };
183
184 /* CONTROL REQUEST SUPPORT */
185
186 /*
187 * USB directions
188 *
189 * This bit flag is used in endpoint descriptors' bEndpointAddress field.
190 * It's also one of three fields in control requests bRequestType.
191 */
192 #define USB_DIR_OUT 0 /* to device */
193 #define USB_DIR_IN 0x80 /* to host */
194
195 /*
196 * USB types, the second of three bRequestType fields
197 */
198 #define USB_TYPE_MASK (0x03 << 5)
199 #define USB_TYPE_STANDARD (0x00 << 5)
200 #define USB_TYPE_CLASS (0x01 << 5)
201 #define USB_TYPE_VENDOR (0x02 << 5)
202 #define USB_TYPE_RESERVED (0x03 << 5)
203
204 /*
205 * USB recipients, the third of three bRequestType fields
206 */
207 #define USB_RECIP_MASK 0x1f
208 #define USB_RECIP_DEVICE 0x00
209 #define USB_RECIP_INTERFACE 0x01
210 #define USB_RECIP_ENDPOINT 0x02
211 #define USB_RECIP_OTHER 0x03
212 /* From Wireless USB 1.0 */
213 #define USB_RECIP_PORT 0x04
214 #define USB_RECIP_RPIPE 0x05
215
216 /*
217 * Standard requests, for the bRequest field of a SETUP packet.
218 *
219 * These are qualified by the bRequestType field, so that for example
220 * TYPE_CLASS or TYPE_VENDOR specific feature flags could be retrieved
221 * by a GET_STATUS request.
222 */
223 #define USB_REQ_GET_STATUS 0x00
224 #define USB_REQ_CLEAR_FEATURE 0x01
225 #define USB_REQ_SET_FEATURE 0x03
226 #define USB_REQ_SET_ADDRESS 0x05
227 #define USB_REQ_GET_DESCRIPTOR 0x06
228 #define USB_REQ_SET_DESCRIPTOR 0x07
229 #define USB_REQ_GET_CONFIGURATION 0x08
230 #define USB_REQ_SET_CONFIGURATION 0x09
231 #define USB_REQ_GET_INTERFACE 0x0A
232 #define USB_REQ_SET_INTERFACE 0x0B
233 #define USB_REQ_SYNCH_FRAME 0x0C
234
235 #define USB_DEVICE_DEBUG_MODE 6 /* (special devices only) */
236
237 /**
238 * struct usb_ctrlrequest - SETUP data for a USB device control request
239 * @bRequestType: matches the USB bmRequestType field
240 * @bRequest: matches the USB bRequest field
241 * @wValue: matches the USB wValue field (le16 byte order)
242 * @wIndex: matches the USB wIndex field (le16 byte order)
243 * @wLength: matches the USB wLength field (le16 byte order)
244 *
245 * This structure is used to send control requests to a USB device. It matches
246 * the different fields of the USB 2.0 Spec section 9.3, table 9-2. See the
247 * USB spec for a fuller description of the different fields, and what they are
248 * used for.
249 *
250 * Note that the driver for any interface can issue control requests.
251 * For most devices, interfaces don't coordinate with each other, so
252 * such requests may be made at any time.
253 */
254 struct __packed usb_ctrlrequest {
255 u8 bRequestType;
256 u8 bRequest;
257 __le16 wValue;
258 __le16 wIndex;
259 __le16 wLength;
260 };
261
262 /* USB_DT_DEBUG: for special highspeed devices, replacing serial console */
263
264 #define USB_DT_DEBUG 0x0a
265
266 struct __packed usb_debug_descriptor {
267 u8 bLength;
268 u8 bDescriptorType;
269 /* bulk endpoints with 8 byte maxpacket */
270 u8 bDebugInEndpoint;
271 u8 bDebugOutEndpoint;
272 };
273
274 #define USB_DEBUG_DEVNUM 127
275
276 /*
277 * USB Packet IDs (PIDs)
278 */
279
280 /* token */
281 #define USB_PID_OUT 0xe1
282 #define USB_PID_IN 0x69
283 #define USB_PID_SOF 0xa5
284 #define USB_PID_SETUP 0x2d
285 /* handshake */
286 #define USB_PID_ACK 0xd2
287 #define USB_PID_NAK 0x5a
288 #define USB_PID_STALL 0x1e
289 #define USB_PID_NYET 0x96
290 /* data */
291 #define USB_PID_DATA0 0xc3
292 #define USB_PID_DATA1 0x4b
293 #define USB_PID_DATA2 0x87
294 #define USB_PID_MDATA 0x0f
295 /* Special */
296 #define USB_PID_PREAMBLE 0x3c
297 #define USB_PID_ERR 0x3c
298 #define USB_PID_SPLIT 0x78
299 #define USB_PID_PING 0xb4
300 #define USB_PID_UNDEF_0 0xf0
301
302 #define PCI_CLASS_SERIAL_USB_EHCI 0x0c0320
303 #define PCI_CAP_ID_EHCI_DEBUG 0x0a
304
305 #define HUB_ROOT_RESET_TIME 50 /* times are in msec */
306 #define HUB_SHORT_RESET_TIME 10
307 #define HUB_LONG_RESET_TIME 200
308 #define HUB_RESET_TIMEOUT 500
309
310 #define DBGP_MAX_PACKET 8
311 #define DBGP_LOOPS 1000
312 #define DBGP_TIMEOUT (250 * 1000) /* us */
313 #define DBGP_CHECK_INTERVAL 100 /* us */
314 /* This one can be set arbitrarily - only affects input responsiveness: */
315 #define DBGP_IDLE_INTERVAL 100 /* ms */
316
317 struct ehci_dbgp {
318 struct ehci_dbg_port __iomem *ehci_debug;
319 enum dbgp_state {
320 dbgp_idle,
321 dbgp_out,
322 dbgp_in,
323 dbgp_ctrl,
324 dbgp_unsafe /* cannot use debug device during EHCI reset */
325 } state;
326 unsigned int phys_port;
327 struct {
328 unsigned int endpoint;
329 unsigned int chunk;
330 char buf[DBGP_MAX_PACKET];
331 } out, in;
332 unsigned long timeout;
333 struct timer timer;
334 spinlock_t *lock;
335 bool_t reset_run;
336 u8 bus, slot, func, bar;
337 u16 pci_cr;
338 u32 bar_val;
339 unsigned int cap;
340 struct ehci_regs __iomem *ehci_regs;
341 struct ehci_caps __iomem *ehci_caps;
342 };
343
344 static int ehci_dbgp_external_startup(struct ehci_dbgp *);
345
ehci_dbgp_status(struct ehci_dbgp * dbgp,const char * str)346 static void ehci_dbgp_status(struct ehci_dbgp *dbgp, const char *str)
347 {
348 #ifdef DBGP_DEBUG
349 #define dbgp_printk printk
350 if ( !dbgp->ehci_debug )
351 return;
352 dbgp_printk("dbgp: %s\n", str);
353 dbgp_printk(" debug control: %08x\n", readl(&dbgp->ehci_debug->control));
354 dbgp_printk(" EHCI cmd : %08x\n", readl(&dbgp->ehci_regs->command));
355 dbgp_printk(" EHCI conf flg: %08x\n",
356 readl(&dbgp->ehci_regs->configured_flag));
357 dbgp_printk(" EHCI status : %08x\n", readl(&dbgp->ehci_regs->status));
358 dbgp_printk(" EHCI portsc : %08x\n",
359 readl(&dbgp->ehci_regs->port_status[dbgp->phys_port - 1]));
360 #endif
361 }
362
363 #ifndef DBGP_DEBUG
364 static inline __attribute__ ((format (printf, 1, 2))) void
dbgp_printk(const char * fmt,...)365 dbgp_printk(const char *fmt, ...) { }
366 #endif
367
dbgp_len_update(u32 x,u32 len)368 static inline u32 dbgp_len_update(u32 x, u32 len)
369 {
370 return (x & ~DBGP_LEN) | (len & DBGP_LEN) | DBGP_OUT;
371 }
372
dbgp_pid_write_update(u32 x,u32 tok)373 static inline u32 dbgp_pid_write_update(u32 x, u32 tok)
374 {
375 static u8 data0 = USB_PID_DATA1;
376
377 data0 ^= USB_PID_DATA0 ^ USB_PID_DATA1;
378 return (x & 0xffff0000) | (data0 << 8) | (tok & 0xff);
379 }
380
dbgp_pid_read_update(u32 x,u32 tok)381 static inline u32 dbgp_pid_read_update(u32 x, u32 tok)
382 {
383 return (x & 0xffffff00) | (tok & 0xff);
384 }
385
dbgp_set_data(struct ehci_dbg_port __iomem * ehci_debug,const void * buf,unsigned int size)386 static inline void dbgp_set_data(struct ehci_dbg_port __iomem *ehci_debug,
387 const void *buf, unsigned int size)
388 {
389 const unsigned char *bytes = buf;
390 u32 lo = 0, hi = 0;
391 unsigned int i;
392
393 for ( i = 0; i < 4 && i < size; i++ )
394 lo |= bytes[i] << (8 * i);
395 for ( ; i < 8 && i < size; i++ )
396 hi |= bytes[i] << (8 * (i - 4));
397 writel(lo, &ehci_debug->data03);
398 writel(hi, &ehci_debug->data47);
399 }
400
dbgp_get_data(struct ehci_dbg_port __iomem * ehci_debug,void * buf,int size)401 static inline void dbgp_get_data(struct ehci_dbg_port __iomem *ehci_debug,
402 void *buf, int size)
403 {
404 unsigned char *bytes = buf;
405 u32 lo = readl(&ehci_debug->data03);
406 u32 hi = readl(&ehci_debug->data47);
407 unsigned int i;
408
409 for ( i = 0; i < 4 && i < size; i++ )
410 bytes[i] = (lo >> (8 * i)) & 0xff;
411 for ( ; i < 8 && i < size; i++ )
412 bytes[i] = (hi >> (8 * (i - 4))) & 0xff;
413 }
414
dbgp_issue_command(struct ehci_dbgp * dbgp,u32 ctrl,enum dbgp_state state)415 static void dbgp_issue_command(struct ehci_dbgp *dbgp, u32 ctrl,
416 enum dbgp_state state)
417 {
418 u32 cmd = readl(&dbgp->ehci_regs->command);
419
420 if ( unlikely(!(cmd & CMD_RUN)) )
421 {
422 /*
423 * If the EHCI controller is not in the run state do extended
424 * checks to see if ACPI or some other initialization also
425 * reset the EHCI debug port.
426 */
427 u32 ctrl = readl(&dbgp->ehci_debug->control);
428
429 if ( ctrl & DBGP_ENABLED )
430 {
431 cmd |= CMD_RUN;
432 writel(cmd, &dbgp->ehci_regs->command);
433 dbgp->reset_run = 1;
434 }
435 else if ( dbgp->state != dbgp_unsafe )
436 {
437 dbgp->state = dbgp_unsafe;
438 ehci_dbgp_external_startup(dbgp);
439 }
440 }
441
442 writel(ctrl | DBGP_GO, &dbgp->ehci_debug->control);
443 dbgp->timeout = DBGP_TIMEOUT;
444 if ( dbgp->state != dbgp_unsafe )
445 dbgp->state = state;
446 }
447
dbgp_check_for_completion(struct ehci_dbgp * dbgp,unsigned int interval,u8 * ppid)448 static int dbgp_check_for_completion(struct ehci_dbgp *dbgp,
449 unsigned int interval, u8 *ppid)
450 {
451 u32 ctrl;
452 int ret;
453
454 if ( dbgp->state == dbgp_idle )
455 return 0;
456
457 ctrl = readl(&dbgp->ehci_debug->control) & ~DBGP_GO;
458 if ( !(ctrl & DBGP_DONE) )
459 {
460 if ( dbgp->timeout > interval )
461 dbgp->timeout -= interval;
462 else if ( interval )
463 {
464 /* See the timeout related comment in dbgp_wait_until_done(). */
465 dbgp->state = dbgp_unsafe;
466 dbgp->timeout = 0;
467 }
468 return -DBGP_TIMEOUT;
469 }
470
471 if ( ctrl & DBGP_ERROR )
472 {
473 ret = -DBGP_ERRCODE(ctrl);
474 if ( ret == -DBGP_ERR_BAD && dbgp->timeout > interval )
475 ctrl |= DBGP_GO;
476 }
477 else
478 {
479 u8 pid = DBGP_PID_GET(readl(&dbgp->ehci_debug->pids));
480
481 ret = ctrl & DBGP_LEN;
482 if ( ppid )
483 *ppid = pid;
484 else if ( dbgp->state == dbgp_in )
485 {
486 dbgp_get_data(dbgp->ehci_debug, dbgp->in.buf, ret);
487 dbgp->in.chunk = ret;
488 }
489 else if ( pid == USB_PID_NAK && dbgp->timeout > interval )
490 ctrl |= DBGP_GO;
491 }
492
493 writel(ctrl, &dbgp->ehci_debug->control);
494 if ( ctrl & DBGP_GO )
495 {
496 dbgp->timeout -= interval;
497 return -DBGP_TIMEOUT;
498 }
499
500 if ( unlikely(dbgp->reset_run) )
501 {
502 writel(readl(&dbgp->ehci_regs->command) & ~CMD_RUN,
503 &dbgp->ehci_regs->command);
504 dbgp->reset_run = 0;
505 }
506
507 if ( dbgp->state != dbgp_unsafe )
508 dbgp->state = dbgp_idle;
509
510 return ret;
511 }
512
dbgp_wait_until_complete(struct ehci_dbgp * dbgp,u8 * ppid)513 static int dbgp_wait_until_complete(struct ehci_dbgp *dbgp, u8 *ppid)
514 {
515 unsigned int loop = DBGP_TIMEOUT;
516 int ret;
517
518 do {
519 ret = dbgp_check_for_completion(dbgp, 0, ppid);
520 if ( ret != -DBGP_TIMEOUT )
521 break;
522 udelay(1);
523 } while ( --loop );
524
525 if ( !ppid && !loop )
526 dbgp->state = dbgp_unsafe;
527
528 return ret;
529 }
530
dbgp_mdelay(unsigned int ms)531 static inline void dbgp_mdelay(unsigned int ms)
532 {
533 while ( ms-- )
534 {
535 unsigned int i;
536
537 for ( i = 0; i < 1000; i++ )
538 outb(0x1, 0x80);
539 }
540 }
541
dbgp_breathe(void)542 static void dbgp_breathe(void)
543 {
544 /* Sleep to give the debug port a chance to breathe. */
545 dbgp_mdelay(1);
546 }
547
dbgp_wait_until_done(struct ehci_dbgp * dbgp,u32 ctrl,unsigned int loop)548 static int dbgp_wait_until_done(struct ehci_dbgp *dbgp, u32 ctrl,
549 unsigned int loop)
550 {
551 int ret;
552
553 dbgp->timeout = 0;
554
555 for ( ; ; writel(ctrl | DBGP_GO, &dbgp->ehci_debug->control) )
556 {
557 u8 pid;
558
559 ret = dbgp_wait_until_complete(dbgp, &pid);
560 if ( ret < 0 )
561 {
562 /*
563 * A -DBGP_TIMEOUT failure here means the device has failed,
564 * perhaps because it was unplugged, in which case we do not
565 * want to hang the system so the dbgp will be marked as unsafe
566 * to use. EHCI reset is the only way to recover if you unplug
567 * the dbgp device.
568 */
569 if ( ret == -DBGP_TIMEOUT )
570 dbgp->state = dbgp_unsafe;
571 if ( ret != -DBGP_ERR_BAD || !--loop )
572 break;
573 }
574 else
575 {
576 /*
577 * If the port is getting full or it has dropped data
578 * start pacing ourselves, not necessary but it's friendly.
579 */
580 if ( pid == USB_PID_NAK || pid == USB_PID_NYET )
581 dbgp_breathe();
582
583 /* If we got a NACK, reissue the transmission. */
584 if ( pid != USB_PID_NAK || !--loop )
585 break;
586 }
587 }
588
589 return ret;
590 }
591
dbgp_bulk_write(struct ehci_dbgp * dbgp,unsigned int devnum,unsigned int endpoint,const void * bytes,unsigned int size,u32 * pctrl)592 static int dbgp_bulk_write(struct ehci_dbgp *dbgp,
593 unsigned int devnum, unsigned int endpoint,
594 const void *bytes, unsigned int size, u32 *pctrl)
595 {
596 u32 addr, pids, ctrl;
597
598 if ( size > DBGP_MAX_PACKET )
599 return -EINVAL;
600
601 addr = DBGP_EPADDR(devnum, endpoint);
602 pids = dbgp_pid_write_update(readl(&dbgp->ehci_debug->pids), USB_PID_OUT);
603 ctrl = dbgp_len_update(readl(&dbgp->ehci_debug->control), size);
604 if ( pctrl )
605 *pctrl = ctrl;
606
607 dbgp_set_data(dbgp->ehci_debug, bytes, size);
608 writel(addr, &dbgp->ehci_debug->address);
609 writel(pids, &dbgp->ehci_debug->pids);
610 dbgp_issue_command(dbgp, ctrl, dbgp_out);
611
612 return 0;
613 }
614
dbgp_bulk_read(struct ehci_dbgp * dbgp,unsigned int devnum,unsigned int endpoint,unsigned int size,u32 * pctrl)615 static int dbgp_bulk_read(struct ehci_dbgp *dbgp,
616 unsigned int devnum, unsigned int endpoint,
617 unsigned int size, u32 *pctrl)
618 {
619 u32 addr, pids, ctrl;
620
621 if ( size > DBGP_MAX_PACKET )
622 return -EINVAL;
623
624 addr = DBGP_EPADDR(devnum, endpoint);
625 pids = dbgp_pid_read_update(readl(&dbgp->ehci_debug->pids), USB_PID_IN);
626 ctrl = readl(&dbgp->ehci_debug->control) & ~DBGP_OUT;
627
628 writel(addr, &dbgp->ehci_debug->address);
629 writel(pids, &dbgp->ehci_debug->pids);
630 if ( likely(!pctrl) )
631 dbgp_issue_command(dbgp, ctrl, dbgp_in);
632 else
633 dbgp_issue_command(dbgp, *pctrl = ctrl, dbgp_ctrl);
634
635 return 0;
636 }
637
dbgp_control_msg(struct ehci_dbgp * dbgp,unsigned int devnum,int requesttype,int request,int value,int index,void * data,unsigned int size)638 static int dbgp_control_msg(struct ehci_dbgp *dbgp, unsigned int devnum,
639 int requesttype, int request, int value,
640 int index, void *data, unsigned int size)
641 {
642 u32 addr, pids, ctrl;
643 struct usb_ctrlrequest req;
644 bool_t read = (requesttype & USB_DIR_IN) != 0;
645 int ret;
646
647 if ( size > (read ? DBGP_MAX_PACKET : 0) )
648 return -EINVAL;
649
650 /* Compute the control message */
651 req.bRequestType = requesttype;
652 req.bRequest = request;
653 req.wValue = cpu_to_le16(value);
654 req.wIndex = cpu_to_le16(index);
655 req.wLength = cpu_to_le16(size);
656
657 pids = DBGP_PID_SET(USB_PID_DATA0, USB_PID_SETUP);
658 addr = DBGP_EPADDR(devnum, 0);
659 ctrl = dbgp_len_update(readl(&dbgp->ehci_debug->control), sizeof(req));
660
661 /* Send the setup message */
662 dbgp_set_data(dbgp->ehci_debug, &req, sizeof(req));
663 writel(addr, &dbgp->ehci_debug->address);
664 writel(pids, &dbgp->ehci_debug->pids);
665 dbgp_issue_command(dbgp, ctrl, dbgp_ctrl);
666 ret = dbgp_wait_until_done(dbgp, ctrl, DBGP_LOOPS);
667 if ( ret < 0 )
668 return ret;
669
670 /* Read the result */
671 ret = dbgp_bulk_read(dbgp, devnum, 0, size, &ctrl);
672 if ( !ret )
673 ret = dbgp_wait_until_done(dbgp, ctrl, DBGP_LOOPS);
674 if ( ret > 0 )
675 {
676 if ( size > ret )
677 size = ret;
678 dbgp_get_data(dbgp->ehci_debug, data, size);
679 }
680
681 return ret;
682 }
683
__find_dbgp(u8 bus,u8 slot,u8 func)684 static unsigned int __init __find_dbgp(u8 bus, u8 slot, u8 func)
685 {
686 uint32_t class = pci_conf_read32(PCI_SBDF(0, bus, slot, func),
687 PCI_CLASS_REVISION);
688
689 if ( (class >> 8) != PCI_CLASS_SERIAL_USB_EHCI )
690 return 0;
691
692 return pci_find_cap_offset(0, bus, slot, func, PCI_CAP_ID_EHCI_DEBUG);
693 }
694
find_dbgp(struct ehci_dbgp * dbgp,unsigned int ehci_num)695 static unsigned int __init find_dbgp(struct ehci_dbgp *dbgp,
696 unsigned int ehci_num)
697 {
698 unsigned int bus, slot, func;
699
700 for ( bus = 0; bus < 256; bus++ )
701 {
702 for ( slot = 0; slot < 32; slot++ )
703 {
704 for ( func = 0; func < 8; func++ )
705 {
706 unsigned int cap;
707
708 if ( !pci_device_detect(0, bus, slot, func) )
709 {
710 if ( !func )
711 break;
712 continue;
713 }
714
715 cap = __find_dbgp(bus, slot, func);
716 if ( !cap || ehci_num-- )
717 {
718 if ( !func && !(pci_conf_read8(PCI_SBDF(0, bus, slot, func),
719 PCI_HEADER_TYPE) & 0x80) )
720 break;
721 continue;
722 }
723
724 dbgp->bus = bus;
725 dbgp->slot = slot;
726 dbgp->func = func;
727 return cap;
728 }
729 }
730 }
731
732 return 0;
733 }
734
ehci_dbgp_startup(struct ehci_dbgp * dbgp)735 static int ehci_dbgp_startup(struct ehci_dbgp *dbgp)
736 {
737 u32 ctrl, cmd, status;
738 unsigned int loop;
739
740 /* Claim ownership, but do not enable yet */
741 ctrl = readl(&dbgp->ehci_debug->control);
742 ctrl |= DBGP_OWNER;
743 ctrl &= ~(DBGP_ENABLED | DBGP_INUSE);
744 writel(ctrl, &dbgp->ehci_debug->control);
745 udelay(1);
746
747 ehci_dbgp_status(dbgp, "EHCI startup");
748 /* Start the EHCI. */
749 cmd = readl(&dbgp->ehci_regs->command);
750 cmd &= ~(CMD_LRESET | CMD_IAAD | CMD_PSE | CMD_ASE | CMD_RESET);
751 cmd |= CMD_RUN;
752 writel(cmd, &dbgp->ehci_regs->command);
753
754 /* Ensure everything is routed to the EHCI */
755 writel(FLAG_CF, &dbgp->ehci_regs->configured_flag);
756
757 /* Wait until the controller is no longer halted. */
758 loop = 1000;
759 do {
760 status = readl(&dbgp->ehci_regs->status);
761 if ( !(status & STS_HALT) )
762 break;
763 udelay(1);
764 } while ( --loop );
765
766 if ( !loop )
767 {
768 dbgp_printk("EHCI cannot be started\n");
769 return -ENODEV;
770 }
771 dbgp_printk("EHCI started\n");
772
773 return 0;
774 }
775
ehci_dbgp_controller_reset(struct ehci_dbgp * dbgp)776 static int ehci_dbgp_controller_reset(struct ehci_dbgp *dbgp)
777 {
778 unsigned int loop = 250 * 1000;
779 u32 cmd;
780
781 /* Reset the EHCI controller */
782 cmd = readl(&dbgp->ehci_regs->command);
783 cmd |= CMD_RESET;
784 writel(cmd, &dbgp->ehci_regs->command);
785 do {
786 cmd = readl(&dbgp->ehci_regs->command);
787 } while ( (cmd & CMD_RESET) && --loop );
788
789 if ( !loop )
790 {
791 dbgp_printk("cannot reset EHCI\n");
792 return -1;
793 }
794 ehci_dbgp_status(dbgp, "ehci reset done");
795
796 return 0;
797 }
798
ehci_reset_port(struct ehci_dbgp * dbgp,unsigned int port)799 static int ehci_reset_port(struct ehci_dbgp *dbgp, unsigned int port)
800 {
801 u32 portsc, delay_time, delay;
802
803 ehci_dbgp_status(dbgp, "reset port");
804 /* Reset the USB debug port. */
805 portsc = readl(&dbgp->ehci_regs->port_status[port - 1]);
806 portsc &= ~PORT_PE;
807 portsc |= PORT_RESET;
808 writel(portsc, &dbgp->ehci_regs->port_status[port - 1]);
809
810 delay = HUB_ROOT_RESET_TIME;
811 for ( delay_time = 0; delay_time < HUB_RESET_TIMEOUT;
812 delay_time += delay )
813 {
814 dbgp_mdelay(delay);
815 portsc = readl(&dbgp->ehci_regs->port_status[port - 1]);
816 if (!(portsc & PORT_RESET))
817 break;
818 }
819
820 if ( portsc & PORT_RESET )
821 {
822 /* force reset to complete */
823 unsigned int loop = 100 * 1000;
824
825 writel(portsc & ~(PORT_RWC_BITS | PORT_RESET),
826 &dbgp->ehci_regs->port_status[port - 1]);
827 do {
828 udelay(1);
829 portsc = readl(&dbgp->ehci_regs->port_status[port-1]);
830 } while ( (portsc & PORT_RESET) && --loop );
831 }
832
833 /* Device went away? */
834 if ( !(portsc & PORT_CONNECT) )
835 return -ENOTCONN;
836
837 /* bomb out completely if something weird happened */
838 if ( portsc & PORT_CSC )
839 return -EINVAL;
840
841 /* If we've finished resetting, then break out of the loop */
842 if ( !(portsc & PORT_RESET) && (portsc & PORT_PE) )
843 return 0;
844
845 return -EBUSY;
846 }
847
ehci_wait_for_port(struct ehci_dbgp * dbgp,unsigned int port)848 static int ehci_wait_for_port(struct ehci_dbgp *dbgp, unsigned int port)
849 {
850 u32 status;
851 unsigned int reps;
852
853 for ( reps = 0; reps < 300; reps++ )
854 {
855 status = readl(&dbgp->ehci_regs->status);
856 if ( status & STS_PCD )
857 break;
858 dbgp_mdelay(1);
859 }
860
861 return ehci_reset_port(dbgp, port) == 0 ? 0 : -ENOTCONN;
862 }
863
864 /* Return 0 on success
865 * Return -ENODEV for any general failure
866 * Return -EIO if wait for port fails
867 */
ehci_dbgp_external_startup(struct ehci_dbgp * dbgp)868 static int ehci_dbgp_external_startup(struct ehci_dbgp *dbgp)
869 {
870 unsigned int devnum;
871 struct usb_debug_descriptor dbgp_desc;
872 int ret;
873 u32 ctrl, portsc, cmd;
874 unsigned int dbg_port = dbgp->phys_port;
875 unsigned int tries = 3;
876 unsigned int reset_port_tries = 1;
877 bool_t try_hard_once = 1;
878
879 try_port_reset_again:
880 ret = ehci_dbgp_startup(dbgp);
881 if ( ret )
882 return ret;
883
884 /* Wait for a device to show up in the debug port */
885 ret = ehci_wait_for_port(dbgp, dbg_port);
886 if ( ret < 0 )
887 {
888 portsc = readl(&dbgp->ehci_regs->port_status[dbg_port - 1]);
889 if ( !(portsc & PORT_CONNECT) && try_hard_once )
890 {
891 /*
892 * Last ditch effort to try to force enable the debug device by
893 * using the packet test EHCI command to try and wake it up.
894 */
895 try_hard_once = 0;
896 cmd = readl(&dbgp->ehci_regs->command);
897 cmd &= ~CMD_RUN;
898 writel(cmd, &dbgp->ehci_regs->command);
899 portsc = readl(&dbgp->ehci_regs->port_status[dbg_port - 1]);
900 portsc |= PORT_TEST_PKT;
901 writel(portsc, &dbgp->ehci_regs->port_status[dbg_port - 1]);
902 ehci_dbgp_status(dbgp, "Trying to force debug port online");
903 mdelay(50);
904 ehci_dbgp_controller_reset(dbgp);
905 goto try_port_reset_again;
906 }
907 else if ( reset_port_tries-- )
908 goto try_port_reset_again;
909 dbgp_printk("no device found in debug port\n");
910 return -EIO;
911 }
912 ehci_dbgp_status(dbgp, "wait for port done");
913
914 /* Enable the debug port */
915 ctrl = readl(&dbgp->ehci_debug->control);
916 ctrl |= DBGP_CLAIM;
917 writel(ctrl, &dbgp->ehci_debug->control);
918 ctrl = readl(&dbgp->ehci_debug->control);
919 if ( (ctrl & DBGP_CLAIM) != DBGP_CLAIM )
920 {
921 dbgp_printk("no device in debug port\n");
922 writel(ctrl & ~DBGP_CLAIM, &dbgp->ehci_debug->control);
923 return -ENODEV;
924 }
925 ehci_dbgp_status(dbgp, "debug port enabled");
926
927 /* Completely transfer the debug device to the debug controller */
928 portsc = readl(&dbgp->ehci_regs->port_status[dbg_port - 1]);
929 portsc &= ~PORT_PE;
930 writel(portsc, &dbgp->ehci_regs->port_status[dbg_port - 1]);
931
932 dbgp_mdelay(100);
933
934 try_again:
935 /* Find the debug device and make it device number 127 */
936 for ( devnum = 0; devnum <= 127; devnum++ )
937 {
938 ret = dbgp_control_msg(dbgp, devnum,
939 USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_DEVICE,
940 USB_REQ_GET_DESCRIPTOR, (USB_DT_DEBUG << 8), 0,
941 &dbgp_desc, sizeof(dbgp_desc));
942 if ( ret > 0 )
943 break;
944 }
945 if ( devnum > 127 )
946 {
947 dbgp_printk("could not find attached debug device\n");
948 goto err;
949 }
950 dbgp->out.endpoint = dbgp_desc.bDebugOutEndpoint;
951 dbgp->in.endpoint = dbgp_desc.bDebugInEndpoint;
952
953 /* Move the device to 127 if it isn't already there. */
954 if ( devnum != USB_DEBUG_DEVNUM )
955 {
956 ret = dbgp_control_msg(dbgp, devnum,
957 USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_DEVICE,
958 USB_REQ_SET_ADDRESS, USB_DEBUG_DEVNUM, 0, NULL, 0);
959 if ( ret < 0 )
960 {
961 dbgp_printk("could not move attached device to %d\n",
962 USB_DEBUG_DEVNUM);
963 goto err;
964 }
965 devnum = USB_DEBUG_DEVNUM;
966 dbgp_printk("debug device renamed to 127\n");
967 }
968
969 /* Enable the debug interface */
970 ret = dbgp_control_msg(dbgp, USB_DEBUG_DEVNUM,
971 USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_DEVICE,
972 USB_REQ_SET_FEATURE, USB_DEVICE_DEBUG_MODE,
973 0, NULL, 0);
974 if ( ret < 0 )
975 {
976 dbgp_printk("could not enable the debug device\n");
977 goto err;
978 }
979 dbgp_printk("debug interface enabled\n");
980
981 /* Perform a small write to get the even/odd data state in sync. */
982 ret = dbgp_bulk_write(dbgp, USB_DEBUG_DEVNUM, dbgp->out.endpoint,
983 "\n", 1, &ctrl);
984 if ( !ret )
985 ret = dbgp_wait_until_done(dbgp, ctrl, DBGP_LOOPS);
986 if ( ret < 0 )
987 {
988 dbgp_printk("dbgp_bulk_write failed: %d\n", ret);
989 goto err;
990 }
991 dbgp_printk("small write done\n");
992 dbgp->state = dbgp_idle;
993
994 return 0;
995 err:
996 if ( tries-- )
997 goto try_again;
998 return -ENODEV;
999 }
1000
1001 typedef void (*set_debug_port_t)(struct ehci_dbgp *, unsigned int);
1002
default_set_debug_port(struct ehci_dbgp * dbgp,unsigned int port)1003 static void default_set_debug_port(struct ehci_dbgp *dbgp, unsigned int port)
1004 {
1005 }
1006
1007 static set_debug_port_t __read_mostly set_debug_port = default_set_debug_port;
1008
nvidia_set_debug_port(struct ehci_dbgp * dbgp,unsigned int port)1009 static void nvidia_set_debug_port(struct ehci_dbgp *dbgp, unsigned int port)
1010 {
1011 uint32_t dword = pci_conf_read32(PCI_SBDF(0, dbgp->bus, dbgp->slot,
1012 dbgp->func), 0x74);
1013
1014 dword &= ~(0x0f << 12);
1015 dword |= (port & 0x0f) << 12;
1016 pci_conf_write32(PCI_SBDF(0, dbgp->bus, dbgp->slot, dbgp->func), 0x74,
1017 dword);
1018 dbgp_printk("set debug port to %u\n", port);
1019 }
1020
detect_set_debug_port(struct ehci_dbgp * dbgp)1021 static void __init detect_set_debug_port(struct ehci_dbgp *dbgp)
1022 {
1023 if ( pci_conf_read16(PCI_SBDF(0, dbgp->bus, dbgp->slot, dbgp->func),
1024 PCI_VENDOR_ID) == 0x10de )
1025 {
1026 dbgp_printk("using nvidia set_debug_port\n");
1027 set_debug_port = nvidia_set_debug_port;
1028 }
1029 }
1030
1031 /*
1032 * The code in ehci_dbgp_bios_handoff() is derived from the USB PCI
1033 * quirk initialization in Linux.
1034 */
1035 #define EHCI_USBLEGSUP_BIOS (1 << 16) /* BIOS semaphore */
1036 #define EHCI_USBLEGCTLSTS 4 /* legacy control/status */
ehci_dbgp_bios_handoff(struct ehci_dbgp * dbgp,u32 hcc_params)1037 static void ehci_dbgp_bios_handoff(struct ehci_dbgp *dbgp, u32 hcc_params)
1038 {
1039 u32 cap;
1040 unsigned int offset = HCC_EXT_CAPS(hcc_params);
1041 int msec;
1042
1043 if ( !offset )
1044 return;
1045
1046 cap = pci_conf_read32(PCI_SBDF(0, dbgp->bus, dbgp->slot, dbgp->func),
1047 offset);
1048 dbgp_printk("dbgp: EHCI BIOS state %08x\n", cap);
1049
1050 if ( (cap & 0xff) == 1 && (cap & EHCI_USBLEGSUP_BIOS) )
1051 {
1052 dbgp_printk("dbgp: BIOS handoff\n");
1053 pci_conf_write8(PCI_SBDF(0, dbgp->bus, dbgp->slot, dbgp->func),
1054 offset + 3, 1);
1055 }
1056
1057 /* if boot firmware now owns EHCI, spin till it hands it over. */
1058 msec = 1000;
1059 while ( (cap & EHCI_USBLEGSUP_BIOS) && (msec > 0) )
1060 {
1061 mdelay(10);
1062 msec -= 10;
1063 cap = pci_conf_read32(PCI_SBDF(0, dbgp->bus, dbgp->slot, dbgp->func),
1064 offset);
1065 }
1066
1067 if ( cap & EHCI_USBLEGSUP_BIOS )
1068 {
1069 /* well, possibly buggy BIOS... try to shut it down,
1070 * and hope nothing goes too wrong */
1071 dbgp_printk("dbgp: BIOS handoff failed: %08x\n", cap);
1072 pci_conf_write8(PCI_SBDF(0, dbgp->bus, dbgp->slot, dbgp->func),
1073 offset + 2, 0);
1074 }
1075
1076 /* just in case, always disable EHCI SMIs */
1077 pci_conf_write8(PCI_SBDF(0, dbgp->bus, dbgp->slot, dbgp->func),
1078 offset + EHCI_USBLEGCTLSTS, 0);
1079 }
1080
ehci_dbgp_setup(struct ehci_dbgp * dbgp)1081 static int ehci_dbgp_setup(struct ehci_dbgp *dbgp)
1082 {
1083 u32 ctrl, portsc, hcs_params;
1084 unsigned int i, debug_port, new_debug_port = 0, n_ports;
1085 unsigned int port_map_tried, playtimes = 3;
1086 int ret;
1087
1088 ehci_dbgp_bios_handoff(dbgp, readl(&dbgp->ehci_caps->hcc_params));
1089
1090 try_next_time:
1091 port_map_tried = 0;
1092
1093 try_next_port:
1094
1095 hcs_params = readl(&dbgp->ehci_caps->hcs_params);
1096 debug_port = HCS_DEBUG_PORT(hcs_params);
1097 dbgp->phys_port = debug_port;
1098 n_ports = HCS_N_PORTS(hcs_params);
1099
1100 dbgp_printk("debug_port: %u\n", debug_port);
1101 dbgp_printk("n_ports: %u\n", n_ports);
1102 ehci_dbgp_status(dbgp, "");
1103
1104 if ( n_ports == 0 )
1105 return -1;
1106
1107 for ( i = 1; i <= n_ports; i++ )
1108 {
1109 portsc = readl(&dbgp->ehci_regs->port_status[i-1]);
1110 dbgp_printk("portstatus%d: %08x\n", i, portsc);
1111 }
1112
1113 if ( port_map_tried && (new_debug_port != debug_port) )
1114 {
1115 if ( --playtimes )
1116 {
1117 set_debug_port(dbgp, new_debug_port);
1118 goto try_next_time;
1119 }
1120 return -1;
1121 }
1122
1123 /* Only reset the controller if it is not already in the
1124 * configured state */
1125 if ( readl(&dbgp->ehci_regs->configured_flag) & FLAG_CF )
1126 ehci_dbgp_status(dbgp, "ehci skip - already configured");
1127 else if ( ehci_dbgp_controller_reset(dbgp) != 0 )
1128 return -1;
1129
1130 ret = ehci_dbgp_external_startup(dbgp);
1131 if (ret == -EIO)
1132 goto next_debug_port;
1133
1134 if ( ret < 0 )
1135 {
1136 /* Things didn't work so remove my claim */
1137 ctrl = readl(&dbgp->ehci_debug->control);
1138 ctrl &= ~(DBGP_CLAIM | DBGP_OUT);
1139 writel(ctrl, &dbgp->ehci_debug->control);
1140 return -1;
1141 }
1142
1143 return 0;
1144
1145 next_debug_port:
1146 port_map_tried |= 1 << (debug_port - 1);
1147 new_debug_port = (debug_port % n_ports) + 1;
1148 if ( port_map_tried != ((1 << n_ports) - 1) )
1149 {
1150 set_debug_port(dbgp, new_debug_port);
1151 goto try_next_port;
1152 }
1153 if ( --playtimes )
1154 {
1155 set_debug_port(dbgp, new_debug_port);
1156 goto try_next_time;
1157 }
1158
1159 return -1;
1160 }
1161
_ehci_dbgp_flush(struct ehci_dbgp * dbgp)1162 static inline void _ehci_dbgp_flush(struct ehci_dbgp *dbgp)
1163 {
1164 if ( dbgp_bulk_write(dbgp, USB_DEBUG_DEVNUM, dbgp->out.endpoint,
1165 dbgp->out.buf, dbgp->out.chunk, NULL) )
1166 BUG();
1167 dbgp->out.chunk = 0;
1168 }
1169
ehci_dbgp_flush(struct serial_port * port)1170 static void ehci_dbgp_flush(struct serial_port *port)
1171 {
1172 struct ehci_dbgp *dbgp = port->uart;
1173 s_time_t goal;
1174
1175 if ( !dbgp->out.chunk || !dbgp->ehci_debug || dbgp->state == dbgp_unsafe )
1176 return;
1177
1178 if ( dbgp->state == dbgp_idle || !port->sync )
1179 dbgp_check_for_completion(dbgp, 1, NULL);
1180 else
1181 dbgp_wait_until_complete(dbgp, NULL);
1182
1183 if ( dbgp->state == dbgp_idle )
1184 {
1185 _ehci_dbgp_flush(dbgp);
1186
1187 if ( port->sync )
1188 {
1189 dbgp_wait_until_complete(dbgp, NULL);
1190 return;
1191 }
1192 }
1193
1194 goal = NOW() + MICROSECS(DBGP_CHECK_INTERVAL);
1195 if ( dbgp->timer.expires > goal )
1196 set_timer(&dbgp->timer, goal);
1197 }
1198
ehci_dbgp_putc(struct serial_port * port,char c)1199 static void ehci_dbgp_putc(struct serial_port *port, char c)
1200 {
1201 struct ehci_dbgp *dbgp = port->uart;
1202
1203 if ( unlikely(dbgp->out.chunk >= DBGP_MAX_PACKET) )
1204 return;
1205
1206 dbgp->out.buf[dbgp->out.chunk++] = c;
1207
1208 if ( dbgp->out.chunk == DBGP_MAX_PACKET )
1209 ehci_dbgp_flush(port);
1210 }
1211
ehci_dbgp_tx_ready(struct serial_port * port)1212 static int ehci_dbgp_tx_ready(struct serial_port *port)
1213 {
1214 struct ehci_dbgp *dbgp = port->uart;
1215
1216 if ( unlikely(!dbgp->ehci_debug) || unlikely(dbgp->state == dbgp_unsafe) )
1217 return port->sync || port->tx_log_everything || !port->txbuf;
1218
1219 if ( dbgp->out.chunk == DBGP_MAX_PACKET )
1220 ehci_dbgp_flush(port);
1221 else
1222 dbgp_check_for_completion(dbgp, 1, NULL);
1223
1224 if ( dbgp->state != dbgp_idle && dbgp->out.chunk >= DBGP_MAX_PACKET )
1225 return 0;
1226
1227 return DBGP_MAX_PACKET - dbgp->out.chunk +
1228 (dbgp->state == dbgp_idle) * DBGP_MAX_PACKET;
1229 }
1230
ehci_dbgp_getc(struct serial_port * port,char * pc)1231 static int ehci_dbgp_getc(struct serial_port *port, char *pc)
1232 {
1233 struct ehci_dbgp *dbgp = port->uart;
1234
1235 if ( !dbgp->in.chunk )
1236 return 0;
1237
1238 *pc = *dbgp->in.buf;
1239 if ( --dbgp->in.chunk )
1240 memmove(dbgp->in.buf, dbgp->in.buf + 1, dbgp->in.chunk);
1241
1242 return 1;
1243 }
1244
1245 /* Safe: ehci_dbgp_poll() runs as timer handler, so not reentrant. */
1246 static struct serial_port *poll_port;
1247
_ehci_dbgp_poll(struct cpu_user_regs * regs)1248 static void _ehci_dbgp_poll(struct cpu_user_regs *regs)
1249 {
1250 struct serial_port *port = poll_port;
1251 struct ehci_dbgp *dbgp = port->uart;
1252 unsigned long flags;
1253 unsigned int timeout = MICROSECS(DBGP_CHECK_INTERVAL);
1254 bool_t empty = 0;
1255
1256 if ( !dbgp->ehci_debug )
1257 return;
1258
1259 if ( spin_trylock_irqsave(&port->tx_lock, flags) )
1260 {
1261 if ( dbgp->state != dbgp_unsafe )
1262 dbgp_check_for_completion(dbgp, DBGP_CHECK_INTERVAL, NULL);
1263 if ( dbgp->state == dbgp_idle && dbgp->out.chunk )
1264 _ehci_dbgp_flush(dbgp);
1265 if ( dbgp->state == dbgp_idle || dbgp->out.chunk < DBGP_MAX_PACKET )
1266 empty = 1;
1267 spin_unlock_irqrestore(&port->tx_lock, flags);
1268 }
1269
1270 if ( dbgp->in.chunk )
1271 serial_rx_interrupt(port, regs);
1272
1273 if ( empty )
1274 serial_tx_interrupt(port, regs);
1275
1276 if ( spin_trylock_irqsave(&port->tx_lock, flags) )
1277 {
1278 if ( dbgp->state == dbgp_idle && !dbgp->in.chunk &&
1279 !dbgp->out.chunk && port->txbufp == port->txbufc )
1280 {
1281 if ( dbgp_bulk_read(dbgp, USB_DEBUG_DEVNUM, dbgp->in.endpoint,
1282 DBGP_MAX_PACKET, NULL) )
1283 BUG();
1284 timeout = MILLISECS(DBGP_IDLE_INTERVAL);
1285 }
1286 spin_unlock_irqrestore(&port->tx_lock, flags);
1287 }
1288
1289 set_timer(&dbgp->timer, NOW() + timeout);
1290 }
1291
ehci_dbgp_poll(void * data)1292 static void ehci_dbgp_poll(void *data)
1293 {
1294 poll_port = data;
1295 #ifdef run_in_exception_handler
1296 run_in_exception_handler(_ehci_dbgp_poll);
1297 #else
1298 _ehci_dbgp_poll(guest_cpu_user_regs());
1299 #endif
1300 }
1301
ehci_dbgp_setup_preirq(struct ehci_dbgp * dbgp)1302 static bool_t ehci_dbgp_setup_preirq(struct ehci_dbgp *dbgp)
1303 {
1304 if ( !ehci_dbgp_setup(dbgp) )
1305 return 1;
1306
1307 dbgp_printk("ehci_dbgp_setup failed\n");
1308 dbgp->ehci_debug = NULL;
1309 return 0;
1310 }
1311
ehci_dbgp_init_preirq(struct serial_port * port)1312 static void __init ehci_dbgp_init_preirq(struct serial_port *port)
1313 {
1314 struct ehci_dbgp *dbgp = port->uart;
1315 u32 debug_port, offset;
1316 void __iomem *ehci_bar;
1317
1318 debug_port = pci_conf_read32(PCI_SBDF(0, dbgp->bus, dbgp->slot, dbgp->func),
1319 dbgp->cap);
1320 offset = (debug_port >> 16) & 0xfff;
1321
1322 /* double check if the mem space is enabled */
1323 dbgp->pci_cr = pci_conf_read8(PCI_SBDF(0, dbgp->bus, dbgp->slot,
1324 dbgp->func),
1325 PCI_COMMAND);
1326 if ( !(dbgp->pci_cr & PCI_COMMAND_MEMORY) )
1327 {
1328 dbgp->pci_cr |= PCI_COMMAND_MEMORY;
1329 pci_conf_write16(PCI_SBDF(0, dbgp->bus, dbgp->slot, dbgp->func),
1330 PCI_COMMAND, dbgp->pci_cr);
1331 dbgp_printk("MMIO for EHCI enabled\n");
1332 }
1333
1334 /*
1335 * FIXME I don't have the bar size so just guess PAGE_SIZE is more
1336 * than enough. 1k is the biggest that was seen.
1337 */
1338 set_fixmap_nocache(FIX_EHCI_DBGP, dbgp->bar_val);
1339 ehci_bar = fix_to_virt(FIX_EHCI_DBGP);
1340 ehci_bar += dbgp->bar_val & ~PAGE_MASK;
1341 dbgp_printk("ehci_bar: %p\n", ehci_bar);
1342
1343 dbgp->ehci_caps = ehci_bar;
1344 dbgp->ehci_regs = ehci_bar +
1345 HC_LENGTH(readl(&dbgp->ehci_caps->hc_capbase));
1346 dbgp->ehci_debug = ehci_bar + offset;
1347
1348 detect_set_debug_port(dbgp);
1349
1350 if ( ehci_dbgp_setup_preirq(dbgp) )
1351 ehci_dbgp_status(dbgp, "ehci_dbgp_init_preirq complete");
1352
1353 dbgp->lock = &port->tx_lock;
1354 }
1355
ehci_dbgp_setup_postirq(struct ehci_dbgp * dbgp)1356 static void ehci_dbgp_setup_postirq(struct ehci_dbgp *dbgp)
1357 {
1358 set_timer(&dbgp->timer, NOW() + MILLISECS(1));
1359 }
1360
ehci_dbgp_init_postirq(struct serial_port * port)1361 static void __init ehci_dbgp_init_postirq(struct serial_port *port)
1362 {
1363 struct ehci_dbgp *dbgp = port->uart;
1364
1365 if ( !dbgp->ehci_debug )
1366 return;
1367
1368 serial_async_transmit(port);
1369
1370 init_timer(&dbgp->timer, ehci_dbgp_poll, port, 0);
1371
1372 ehci_dbgp_setup_postirq(dbgp);
1373
1374 pci_hide_device(0, dbgp->bus, PCI_DEVFN(dbgp->slot, dbgp->func));
1375 }
1376
ehci_dbgp_check_release(struct ehci_dbgp * dbgp)1377 static int ehci_dbgp_check_release(struct ehci_dbgp *dbgp)
1378 {
1379 struct ehci_dbg_port __iomem *ehci_debug = dbgp->ehci_debug;
1380 u32 ctrl;
1381 unsigned int i;
1382
1383 if ( !ehci_debug )
1384 return 0;
1385
1386 for ( i = 0; i < DBGP_MAX_PACKET; ++i )
1387 if ( dbgp->out.buf[i] )
1388 return 1;
1389
1390 /*
1391 * This means the console is not initialized, or should get shutdown
1392 * so as to allow for reuse of the USB device, which means it is time
1393 * to shutdown the USB debug port.
1394 */
1395 printk(XENLOG_INFO "Releasing EHCI debug port at %02x:%02x.%u\n",
1396 dbgp->bus, dbgp->slot, dbgp->func);
1397
1398 if ( dbgp->timer.function )
1399 kill_timer(&dbgp->timer);
1400 dbgp->ehci_debug = NULL;
1401
1402 ctrl = readl(&ehci_debug->control);
1403 if ( ctrl & DBGP_ENABLED )
1404 {
1405 ctrl &= ~DBGP_CLAIM;
1406 writel(ctrl, &ehci_debug->control);
1407 }
1408
1409 return 0;
1410 }
1411
ehci_dbgp_endboot(struct serial_port * port)1412 static void __init ehci_dbgp_endboot(struct serial_port *port)
1413 {
1414 ehci_dbgp_check_release(port->uart);
1415 }
1416
ehci_dbgp_suspend(struct serial_port * port)1417 static void ehci_dbgp_suspend(struct serial_port *port)
1418 {
1419 struct ehci_dbgp *dbgp = port->uart;
1420
1421 if ( !dbgp->ehci_debug )
1422 return;
1423
1424 stop_timer(&dbgp->timer);
1425 dbgp->timer.expires = 0;
1426
1427 dbgp->pci_cr = pci_conf_read16(PCI_SBDF(0, dbgp->bus, dbgp->slot,
1428 dbgp->func),
1429 PCI_COMMAND);
1430
1431 dbgp->state = dbgp_unsafe;
1432 }
1433
ehci_dbgp_resume(struct serial_port * port)1434 static void ehci_dbgp_resume(struct serial_port *port)
1435 {
1436 struct ehci_dbgp *dbgp = port->uart;
1437
1438 if ( !dbgp->ehci_debug )
1439 return;
1440
1441 pci_conf_write32(PCI_SBDF(0, dbgp->bus, dbgp->slot, dbgp->func), dbgp->bar,
1442 dbgp->bar_val);
1443 pci_conf_write16(PCI_SBDF(0, dbgp->bus, dbgp->slot, dbgp->func),
1444 PCI_COMMAND, dbgp->pci_cr);
1445
1446 ehci_dbgp_setup_preirq(dbgp);
1447 ehci_dbgp_setup_postirq(dbgp);
1448 }
1449
1450 static struct uart_driver __read_mostly ehci_dbgp_driver = {
1451 .init_preirq = ehci_dbgp_init_preirq,
1452 .init_postirq = ehci_dbgp_init_postirq,
1453 .endboot = ehci_dbgp_endboot,
1454 .suspend = ehci_dbgp_suspend,
1455 .resume = ehci_dbgp_resume,
1456 .tx_ready = ehci_dbgp_tx_ready,
1457 .putc = ehci_dbgp_putc,
1458 .flush = ehci_dbgp_flush,
1459 .getc = ehci_dbgp_getc
1460 };
1461
1462 static struct ehci_dbgp ehci_dbgp = { .state = dbgp_unsafe, .phys_port = 1 };
1463
1464 static char __initdata opt_dbgp[30];
1465 string_param("dbgp", opt_dbgp);
1466
ehci_dbgp_init(void)1467 void __init ehci_dbgp_init(void)
1468 {
1469 struct ehci_dbgp *dbgp = &ehci_dbgp;
1470 u32 debug_port, offset, bar_val;
1471 const char *e;
1472
1473 if ( strncmp(opt_dbgp, "ehci", 4) )
1474 return;
1475
1476 if ( isdigit(opt_dbgp[4]) || !opt_dbgp[4] )
1477 {
1478 unsigned int num = 0;
1479
1480 if ( opt_dbgp[4] )
1481 simple_strtoul(opt_dbgp + 4, &e, 10);
1482
1483 dbgp->cap = find_dbgp(dbgp, num);
1484 if ( !dbgp->cap )
1485 return;
1486
1487 dbgp_printk("Found EHCI debug port on %02x:%02x.%u\n",
1488 dbgp->bus, dbgp->slot, dbgp->func);
1489 }
1490 else if ( strncmp(opt_dbgp + 4, "@pci", 4) == 0 )
1491 {
1492 unsigned int bus, slot, func;
1493
1494 e = parse_pci(opt_dbgp + 8, NULL, &bus, &slot, &func);
1495 if ( !e || *e )
1496 return;
1497
1498 dbgp->bus = bus;
1499 dbgp->slot = slot;
1500 dbgp->func = func;
1501
1502 if ( !pci_device_detect(0, bus, slot, func) )
1503 return;
1504
1505 dbgp->cap = __find_dbgp(bus, slot, func);
1506 if ( !dbgp->cap )
1507 return;
1508
1509 dbgp_printk("Using EHCI debug port on %02x:%02x.%u\n",
1510 bus, slot, func);
1511 }
1512 else
1513 return;
1514
1515 debug_port = pci_conf_read32(PCI_SBDF(0, dbgp->bus, dbgp->slot, dbgp->func),
1516 dbgp->cap);
1517 dbgp->bar = (debug_port >> 29) & 0x7;
1518 dbgp->bar = ((dbgp->bar - 1) * 4) + PCI_BASE_ADDRESS_0;
1519 offset = (debug_port >> 16) & 0xfff;
1520 dbgp_printk("bar: %02x offset: %03x\n", dbgp->bar, offset);
1521 if ( dbgp->bar < PCI_BASE_ADDRESS_0 || dbgp->bar > PCI_BASE_ADDRESS_5 )
1522 {
1523 dbgp_printk("unsupported/invalid bar\n");
1524 return;
1525 }
1526
1527 dbgp->bar_val = bar_val = pci_conf_read32(PCI_SBDF(0, dbgp->bus, dbgp->slot,
1528 dbgp->func), dbgp->bar);
1529 dbgp_printk("bar_val: %08x\n", bar_val);
1530 if ( bar_val & ~PCI_BASE_ADDRESS_MEM_MASK )
1531 {
1532 dbgp_printk("only simple 32-bit MMIO BARs supported\n");
1533 return;
1534 }
1535 bar_val &= PCI_BASE_ADDRESS_MEM_MASK;
1536 if ( !bar_val || !(bar_val + (bar_val & -bar_val)) )
1537 {
1538 dbgp_printk("firmware initialization of MMIO BAR required\n");
1539 return;
1540 }
1541
1542 serial_register_uart(SERHND_DBGP, &ehci_dbgp_driver, dbgp);
1543 }
1544
dbgp_op(const struct physdev_dbgp_op * op)1545 int dbgp_op(const struct physdev_dbgp_op *op)
1546 {
1547 if ( !ehci_dbgp.ehci_debug )
1548 return 0;
1549
1550 switch ( op->bus )
1551 {
1552 case PHYSDEVOP_DBGP_BUS_UNKNOWN:
1553 break;
1554 case PHYSDEVOP_DBGP_BUS_PCI:
1555 if ( op->u.pci.seg || ehci_dbgp.bus != op->u.pci.bus ||
1556 PCI_DEVFN(ehci_dbgp.slot, ehci_dbgp.func) != op->u.pci.devfn )
1557 default:
1558 return 0;
1559 break;
1560 }
1561
1562 switch ( op->op )
1563 {
1564 case PHYSDEVOP_DBGP_RESET_PREPARE:
1565 spin_lock_irq(ehci_dbgp.lock);
1566 ehci_dbgp.state = dbgp_unsafe;
1567 dbgp_wait_until_complete(&ehci_dbgp, NULL);
1568 spin_unlock_irq(ehci_dbgp.lock);
1569
1570 return ehci_dbgp_check_release(&ehci_dbgp);
1571
1572 case PHYSDEVOP_DBGP_RESET_DONE:
1573 return ehci_dbgp_external_startup(&ehci_dbgp) ?: 1;
1574 }
1575
1576 return -ENOSYS;
1577 }
1578