1 /*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include <linux/delay.h>
27
28 #include "dc_bios_types.h"
29 #include "dcn10_stream_encoder.h"
30 #include "reg_helper.h"
31 #include "hw_shared.h"
32 #include "inc/link_dpcd.h"
33 #include "dpcd_defs.h"
34 #include "dcn30/dcn30_afmt.h"
35
36 #define DC_LOGGER \
37 enc1->base.ctx->logger
38
39
40 #define REG(reg)\
41 (enc1->regs->reg)
42
43 #undef FN
44 #define FN(reg_name, field_name) \
45 enc1->se_shift->field_name, enc1->se_mask->field_name
46
47 #define VBI_LINE_0 0
48 #define DP_BLANK_MAX_RETRY 20
49 #define HDMI_CLOCK_CHANNEL_RATE_MORE_340M 340000
50
51
52 enum {
53 DP_MST_UPDATE_MAX_RETRY = 50
54 };
55
56 #define CTX \
57 enc1->base.ctx
58
enc1_update_generic_info_packet(struct dcn10_stream_encoder * enc1,uint32_t packet_index,const struct dc_info_packet * info_packet)59 void enc1_update_generic_info_packet(
60 struct dcn10_stream_encoder *enc1,
61 uint32_t packet_index,
62 const struct dc_info_packet *info_packet)
63 {
64 uint32_t regval;
65 /* TODOFPGA Figure out a proper number for max_retries polling for lock
66 * use 50 for now.
67 */
68 uint32_t max_retries = 50;
69
70 /*we need turn on clock before programming AFMT block*/
71 REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1);
72
73 if (packet_index >= 8)
74 ASSERT(0);
75
76 /* poll dig_update_lock is not locked -> asic internal signal
77 * assume otg master lock will unlock it
78 */
79 /* REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_LOCK_STATUS,
80 0, 10, max_retries);*/
81
82 /* check if HW reading GSP memory */
83 REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT,
84 0, 10, max_retries);
85
86 /* HW does is not reading GSP memory not reading too long ->
87 * something wrong. clear GPS memory access and notify?
88 * hw SW is writing to GSP memory
89 */
90 REG_UPDATE(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT_CLR, 1);
91
92 /* choose which generic packet to use */
93 regval = REG_READ(AFMT_VBI_PACKET_CONTROL);
94 REG_UPDATE(AFMT_VBI_PACKET_CONTROL,
95 AFMT_GENERIC_INDEX, packet_index);
96
97 /* write generic packet header
98 * (4th byte is for GENERIC0 only)
99 */
100 REG_SET_4(AFMT_GENERIC_HDR, 0,
101 AFMT_GENERIC_HB0, info_packet->hb0,
102 AFMT_GENERIC_HB1, info_packet->hb1,
103 AFMT_GENERIC_HB2, info_packet->hb2,
104 AFMT_GENERIC_HB3, info_packet->hb3);
105
106 /* write generic packet contents
107 * (we never use last 4 bytes)
108 * there are 8 (0-7) mmDIG0_AFMT_GENERIC0_x registers
109 */
110 {
111 const uint32_t *content =
112 (const uint32_t *) &info_packet->sb[0];
113
114 REG_WRITE(AFMT_GENERIC_0, *content++);
115 REG_WRITE(AFMT_GENERIC_1, *content++);
116 REG_WRITE(AFMT_GENERIC_2, *content++);
117 REG_WRITE(AFMT_GENERIC_3, *content++);
118 REG_WRITE(AFMT_GENERIC_4, *content++);
119 REG_WRITE(AFMT_GENERIC_5, *content++);
120 REG_WRITE(AFMT_GENERIC_6, *content++);
121 REG_WRITE(AFMT_GENERIC_7, *content);
122 }
123
124 switch (packet_index) {
125 case 0:
126 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
127 AFMT_GENERIC0_IMMEDIATE_UPDATE, 1);
128 break;
129 case 1:
130 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
131 AFMT_GENERIC1_IMMEDIATE_UPDATE, 1);
132 break;
133 case 2:
134 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
135 AFMT_GENERIC2_IMMEDIATE_UPDATE, 1);
136 break;
137 case 3:
138 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
139 AFMT_GENERIC3_IMMEDIATE_UPDATE, 1);
140 break;
141 case 4:
142 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
143 AFMT_GENERIC4_IMMEDIATE_UPDATE, 1);
144 break;
145 case 5:
146 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
147 AFMT_GENERIC5_IMMEDIATE_UPDATE, 1);
148 break;
149 case 6:
150 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
151 AFMT_GENERIC6_IMMEDIATE_UPDATE, 1);
152 break;
153 case 7:
154 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
155 AFMT_GENERIC7_IMMEDIATE_UPDATE, 1);
156 break;
157 default:
158 break;
159 }
160 }
161
enc1_update_hdmi_info_packet(struct dcn10_stream_encoder * enc1,uint32_t packet_index,const struct dc_info_packet * info_packet)162 static void enc1_update_hdmi_info_packet(
163 struct dcn10_stream_encoder *enc1,
164 uint32_t packet_index,
165 const struct dc_info_packet *info_packet)
166 {
167 uint32_t cont, send, line;
168
169 if (info_packet->valid) {
170 enc1_update_generic_info_packet(
171 enc1,
172 packet_index,
173 info_packet);
174
175 /* enable transmission of packet(s) -
176 * packet transmission begins on the next frame
177 */
178 cont = 1;
179 /* send packet(s) every frame */
180 send = 1;
181 /* select line number to send packets on */
182 line = 2;
183 } else {
184 cont = 0;
185 send = 0;
186 line = 0;
187 }
188
189 /* choose which generic packet control to use */
190 switch (packet_index) {
191 case 0:
192 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL0,
193 HDMI_GENERIC0_CONT, cont,
194 HDMI_GENERIC0_SEND, send,
195 HDMI_GENERIC0_LINE, line);
196 break;
197 case 1:
198 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL0,
199 HDMI_GENERIC1_CONT, cont,
200 HDMI_GENERIC1_SEND, send,
201 HDMI_GENERIC1_LINE, line);
202 break;
203 case 2:
204 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL1,
205 HDMI_GENERIC0_CONT, cont,
206 HDMI_GENERIC0_SEND, send,
207 HDMI_GENERIC0_LINE, line);
208 break;
209 case 3:
210 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL1,
211 HDMI_GENERIC1_CONT, cont,
212 HDMI_GENERIC1_SEND, send,
213 HDMI_GENERIC1_LINE, line);
214 break;
215 case 4:
216 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL2,
217 HDMI_GENERIC0_CONT, cont,
218 HDMI_GENERIC0_SEND, send,
219 HDMI_GENERIC0_LINE, line);
220 break;
221 case 5:
222 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL2,
223 HDMI_GENERIC1_CONT, cont,
224 HDMI_GENERIC1_SEND, send,
225 HDMI_GENERIC1_LINE, line);
226 break;
227 case 6:
228 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL3,
229 HDMI_GENERIC0_CONT, cont,
230 HDMI_GENERIC0_SEND, send,
231 HDMI_GENERIC0_LINE, line);
232 break;
233 case 7:
234 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL3,
235 HDMI_GENERIC1_CONT, cont,
236 HDMI_GENERIC1_SEND, send,
237 HDMI_GENERIC1_LINE, line);
238 break;
239 default:
240 /* invalid HW packet index */
241 DC_LOG_WARNING(
242 "Invalid HW packet index: %s()\n",
243 __func__);
244 return;
245 }
246 }
247
248 /* setup stream encoder in dp mode */
enc1_stream_encoder_dp_set_stream_attribute(struct stream_encoder * enc,struct dc_crtc_timing * crtc_timing,enum dc_color_space output_color_space,bool use_vsc_sdp_for_colorimetry,uint32_t enable_sdp_splitting)249 void enc1_stream_encoder_dp_set_stream_attribute(
250 struct stream_encoder *enc,
251 struct dc_crtc_timing *crtc_timing,
252 enum dc_color_space output_color_space,
253 bool use_vsc_sdp_for_colorimetry,
254 uint32_t enable_sdp_splitting)
255 {
256 uint32_t h_active_start;
257 uint32_t v_active_start;
258 uint32_t misc0 = 0;
259 uint32_t misc1 = 0;
260 uint32_t h_blank;
261 uint32_t h_back_porch;
262 uint8_t synchronous_clock = 0; /* asynchronous mode */
263 uint8_t colorimetry_bpc;
264 uint8_t dynamic_range_rgb = 0; /*full range*/
265 uint8_t dynamic_range_ycbcr = 1; /*bt709*/
266 uint8_t dp_pixel_encoding = 0;
267 uint8_t dp_component_depth = 0;
268
269 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
270 struct dc_crtc_timing hw_crtc_timing = *crtc_timing;
271
272 if (hw_crtc_timing.flags.INTERLACE) {
273 /*the input timing is in VESA spec format with Interlace flag =1*/
274 hw_crtc_timing.v_total /= 2;
275 hw_crtc_timing.v_border_top /= 2;
276 hw_crtc_timing.v_addressable /= 2;
277 hw_crtc_timing.v_border_bottom /= 2;
278 hw_crtc_timing.v_front_porch /= 2;
279 hw_crtc_timing.v_sync_width /= 2;
280 }
281
282
283 /* set pixel encoding */
284 switch (hw_crtc_timing.pixel_encoding) {
285 case PIXEL_ENCODING_YCBCR422:
286 dp_pixel_encoding = DP_PIXEL_ENCODING_TYPE_YCBCR422;
287 break;
288 case PIXEL_ENCODING_YCBCR444:
289 dp_pixel_encoding = DP_PIXEL_ENCODING_TYPE_YCBCR444;
290
291 if (hw_crtc_timing.flags.Y_ONLY)
292 if (hw_crtc_timing.display_color_depth != COLOR_DEPTH_666)
293 /* HW testing only, no use case yet.
294 * Color depth of Y-only could be
295 * 8, 10, 12, 16 bits
296 */
297 dp_pixel_encoding = DP_PIXEL_ENCODING_TYPE_Y_ONLY;
298
299 /* Note: DP_MSA_MISC1 bit 7 is the indicator
300 * of Y-only mode.
301 * This bit is set in HW if register
302 * DP_PIXEL_ENCODING is programmed to 0x4
303 */
304 break;
305 case PIXEL_ENCODING_YCBCR420:
306 dp_pixel_encoding = DP_PIXEL_ENCODING_TYPE_YCBCR420;
307 break;
308 default:
309 dp_pixel_encoding = DP_PIXEL_ENCODING_TYPE_RGB444;
310 break;
311 }
312
313 misc1 = REG_READ(DP_MSA_MISC);
314 /* For YCbCr420 and BT2020 Colorimetry Formats, VSC SDP shall be used.
315 * When MISC1, bit 6, is Set to 1, a Source device uses a VSC SDP to indicate the
316 * Pixel Encoding/Colorimetry Format and that a Sink device shall ignore MISC1, bit 7,
317 * and MISC0, bits 7:1 (MISC1, bit 7, and MISC0, bits 7:1, become "don't care").
318 */
319 if (use_vsc_sdp_for_colorimetry)
320 misc1 = misc1 | 0x40;
321 else
322 misc1 = misc1 & ~0x40;
323
324 /* set color depth */
325 switch (hw_crtc_timing.display_color_depth) {
326 case COLOR_DEPTH_666:
327 dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_6BPC;
328 break;
329 case COLOR_DEPTH_888:
330 dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_8BPC;
331 break;
332 case COLOR_DEPTH_101010:
333 dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_10BPC;
334 break;
335 case COLOR_DEPTH_121212:
336 dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_12BPC;
337 break;
338 case COLOR_DEPTH_161616:
339 dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_16BPC;
340 break;
341 default:
342 dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_6BPC;
343 break;
344 }
345
346 /* Set DP pixel encoding and component depth */
347 REG_UPDATE_2(DP_PIXEL_FORMAT,
348 DP_PIXEL_ENCODING, dp_pixel_encoding,
349 DP_COMPONENT_DEPTH, dp_component_depth);
350
351 /* set dynamic range and YCbCr range */
352
353 switch (hw_crtc_timing.display_color_depth) {
354 case COLOR_DEPTH_666:
355 colorimetry_bpc = 0;
356 break;
357 case COLOR_DEPTH_888:
358 colorimetry_bpc = 1;
359 break;
360 case COLOR_DEPTH_101010:
361 colorimetry_bpc = 2;
362 break;
363 case COLOR_DEPTH_121212:
364 colorimetry_bpc = 3;
365 break;
366 default:
367 colorimetry_bpc = 0;
368 break;
369 }
370
371 misc0 = misc0 | synchronous_clock;
372 misc0 = colorimetry_bpc << 5;
373
374 switch (output_color_space) {
375 case COLOR_SPACE_SRGB:
376 misc1 = misc1 & ~0x80; /* bit7 = 0*/
377 dynamic_range_rgb = 0; /*full range*/
378 break;
379 case COLOR_SPACE_SRGB_LIMITED:
380 misc0 = misc0 | 0x8; /* bit3=1 */
381 misc1 = misc1 & ~0x80; /* bit7 = 0*/
382 dynamic_range_rgb = 1; /*limited range*/
383 break;
384 case COLOR_SPACE_YCBCR601:
385 case COLOR_SPACE_YCBCR601_LIMITED:
386 misc0 = misc0 | 0x8; /* bit3=1, bit4=0 */
387 misc1 = misc1 & ~0x80; /* bit7 = 0*/
388 dynamic_range_ycbcr = 0; /*bt601*/
389 if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
390 misc0 = misc0 | 0x2; /* bit2=0, bit1=1 */
391 else if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR444)
392 misc0 = misc0 | 0x4; /* bit2=1, bit1=0 */
393 break;
394 case COLOR_SPACE_YCBCR709:
395 case COLOR_SPACE_YCBCR709_LIMITED:
396 misc0 = misc0 | 0x18; /* bit3=1, bit4=1 */
397 misc1 = misc1 & ~0x80; /* bit7 = 0*/
398 dynamic_range_ycbcr = 1; /*bt709*/
399 if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
400 misc0 = misc0 | 0x2; /* bit2=0, bit1=1 */
401 else if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR444)
402 misc0 = misc0 | 0x4; /* bit2=1, bit1=0 */
403 break;
404 case COLOR_SPACE_2020_RGB_LIMITEDRANGE:
405 dynamic_range_rgb = 1; /*limited range*/
406 break;
407 case COLOR_SPACE_2020_RGB_FULLRANGE:
408 case COLOR_SPACE_2020_YCBCR:
409 case COLOR_SPACE_XR_RGB:
410 case COLOR_SPACE_MSREF_SCRGB:
411 case COLOR_SPACE_ADOBERGB:
412 case COLOR_SPACE_DCIP3:
413 case COLOR_SPACE_XV_YCC_709:
414 case COLOR_SPACE_XV_YCC_601:
415 case COLOR_SPACE_DISPLAYNATIVE:
416 case COLOR_SPACE_DOLBYVISION:
417 case COLOR_SPACE_APPCTRL:
418 case COLOR_SPACE_CUSTOMPOINTS:
419 case COLOR_SPACE_UNKNOWN:
420 case COLOR_SPACE_YCBCR709_BLACK:
421 /* do nothing */
422 break;
423 }
424
425 REG_SET(DP_MSA_COLORIMETRY, 0, DP_MSA_MISC0, misc0);
426 REG_WRITE(DP_MSA_MISC, misc1); /* MSA_MISC1 */
427
428 /* dcn new register
429 * dc_crtc_timing is vesa dmt struct. data from edid
430 */
431 REG_SET_2(DP_MSA_TIMING_PARAM1, 0,
432 DP_MSA_HTOTAL, hw_crtc_timing.h_total,
433 DP_MSA_VTOTAL, hw_crtc_timing.v_total);
434
435 /* calculate from vesa timing parameters
436 * h_active_start related to leading edge of sync
437 */
438
439 h_blank = hw_crtc_timing.h_total - hw_crtc_timing.h_border_left -
440 hw_crtc_timing.h_addressable - hw_crtc_timing.h_border_right;
441
442 h_back_porch = h_blank - hw_crtc_timing.h_front_porch -
443 hw_crtc_timing.h_sync_width;
444
445 /* start at beginning of left border */
446 h_active_start = hw_crtc_timing.h_sync_width + h_back_porch;
447
448
449 v_active_start = hw_crtc_timing.v_total - hw_crtc_timing.v_border_top -
450 hw_crtc_timing.v_addressable - hw_crtc_timing.v_border_bottom -
451 hw_crtc_timing.v_front_porch;
452
453
454 /* start at beginning of left border */
455 REG_SET_2(DP_MSA_TIMING_PARAM2, 0,
456 DP_MSA_HSTART, h_active_start,
457 DP_MSA_VSTART, v_active_start);
458
459 REG_SET_4(DP_MSA_TIMING_PARAM3, 0,
460 DP_MSA_HSYNCWIDTH,
461 hw_crtc_timing.h_sync_width,
462 DP_MSA_HSYNCPOLARITY,
463 !hw_crtc_timing.flags.HSYNC_POSITIVE_POLARITY,
464 DP_MSA_VSYNCWIDTH,
465 hw_crtc_timing.v_sync_width,
466 DP_MSA_VSYNCPOLARITY,
467 !hw_crtc_timing.flags.VSYNC_POSITIVE_POLARITY);
468
469 /* HWDITH include border or overscan */
470 REG_SET_2(DP_MSA_TIMING_PARAM4, 0,
471 DP_MSA_HWIDTH, hw_crtc_timing.h_border_left +
472 hw_crtc_timing.h_addressable + hw_crtc_timing.h_border_right,
473 DP_MSA_VHEIGHT, hw_crtc_timing.v_border_top +
474 hw_crtc_timing.v_addressable + hw_crtc_timing.v_border_bottom);
475 }
476
enc1_stream_encoder_set_stream_attribute_helper(struct dcn10_stream_encoder * enc1,struct dc_crtc_timing * crtc_timing)477 void enc1_stream_encoder_set_stream_attribute_helper(
478 struct dcn10_stream_encoder *enc1,
479 struct dc_crtc_timing *crtc_timing)
480 {
481 switch (crtc_timing->pixel_encoding) {
482 case PIXEL_ENCODING_YCBCR422:
483 REG_UPDATE(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, 1);
484 break;
485 default:
486 REG_UPDATE(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, 0);
487 break;
488 }
489 REG_UPDATE(DIG_FE_CNTL, TMDS_COLOR_FORMAT, 0);
490 }
491
492 /* setup stream encoder in hdmi mode */
enc1_stream_encoder_hdmi_set_stream_attribute(struct stream_encoder * enc,struct dc_crtc_timing * crtc_timing,int actual_pix_clk_khz,bool enable_audio)493 void enc1_stream_encoder_hdmi_set_stream_attribute(
494 struct stream_encoder *enc,
495 struct dc_crtc_timing *crtc_timing,
496 int actual_pix_clk_khz,
497 bool enable_audio)
498 {
499 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
500 struct bp_encoder_control cntl = {0};
501
502 cntl.action = ENCODER_CONTROL_SETUP;
503 cntl.engine_id = enc1->base.id;
504 cntl.signal = SIGNAL_TYPE_HDMI_TYPE_A;
505 cntl.enable_dp_audio = enable_audio;
506 cntl.pixel_clock = actual_pix_clk_khz;
507 cntl.lanes_number = LANE_COUNT_FOUR;
508
509 if (enc1->base.bp->funcs->encoder_control(
510 enc1->base.bp, &cntl) != BP_RESULT_OK)
511 return;
512
513 enc1_stream_encoder_set_stream_attribute_helper(enc1, crtc_timing);
514
515 /* setup HDMI engine */
516 REG_UPDATE_6(HDMI_CONTROL,
517 HDMI_PACKET_GEN_VERSION, 1,
518 HDMI_KEEPOUT_MODE, 1,
519 HDMI_DEEP_COLOR_ENABLE, 0,
520 HDMI_DATA_SCRAMBLE_EN, 0,
521 HDMI_NO_EXTRA_NULL_PACKET_FILLED, 1,
522 HDMI_CLOCK_CHANNEL_RATE, 0);
523
524
525 switch (crtc_timing->display_color_depth) {
526 case COLOR_DEPTH_888:
527 REG_UPDATE(HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);
528 DC_LOG_DEBUG("HDMI source set to 24BPP deep color depth\n");
529 break;
530 case COLOR_DEPTH_101010:
531 if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) {
532 REG_UPDATE_2(HDMI_CONTROL,
533 HDMI_DEEP_COLOR_DEPTH, 1,
534 HDMI_DEEP_COLOR_ENABLE, 0);
535 DC_LOG_DEBUG("HDMI source 30BPP deep color depth" \
536 "disabled for YCBCR422 pixel encoding\n");
537 } else {
538 REG_UPDATE_2(HDMI_CONTROL,
539 HDMI_DEEP_COLOR_DEPTH, 1,
540 HDMI_DEEP_COLOR_ENABLE, 1);
541 DC_LOG_DEBUG("HDMI source 30BPP deep color depth" \
542 "enabled for YCBCR422 non-pixel encoding\n");
543 }
544 break;
545 case COLOR_DEPTH_121212:
546 if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) {
547 REG_UPDATE_2(HDMI_CONTROL,
548 HDMI_DEEP_COLOR_DEPTH, 2,
549 HDMI_DEEP_COLOR_ENABLE, 0);
550 DC_LOG_DEBUG("HDMI source 36BPP deep color depth" \
551 "disabled for YCBCR422 pixel encoding\n");
552 } else {
553 REG_UPDATE_2(HDMI_CONTROL,
554 HDMI_DEEP_COLOR_DEPTH, 2,
555 HDMI_DEEP_COLOR_ENABLE, 1);
556 DC_LOG_DEBUG("HDMI source 36BPP deep color depth" \
557 "enabled for non-pixel YCBCR422 encoding\n");
558 }
559 break;
560 case COLOR_DEPTH_161616:
561 REG_UPDATE_2(HDMI_CONTROL,
562 HDMI_DEEP_COLOR_DEPTH, 3,
563 HDMI_DEEP_COLOR_ENABLE, 1);
564 DC_LOG_DEBUG("HDMI source deep color depth enabled in" \
565 "reserved mode\n");
566 break;
567 default:
568 break;
569 }
570
571 if (actual_pix_clk_khz >= HDMI_CLOCK_CHANNEL_RATE_MORE_340M) {
572 /* enable HDMI data scrambler
573 * HDMI_CLOCK_CHANNEL_RATE_MORE_340M
574 * Clock channel frequency is 1/4 of character rate.
575 */
576 REG_UPDATE_2(HDMI_CONTROL,
577 HDMI_DATA_SCRAMBLE_EN, 1,
578 HDMI_CLOCK_CHANNEL_RATE, 1);
579 } else if (crtc_timing->flags.LTE_340MCSC_SCRAMBLE) {
580
581 /* TODO: New feature for DCE11, still need to implement */
582
583 /* enable HDMI data scrambler
584 * HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE
585 * Clock channel frequency is the same
586 * as character rate
587 */
588 REG_UPDATE_2(HDMI_CONTROL,
589 HDMI_DATA_SCRAMBLE_EN, 1,
590 HDMI_CLOCK_CHANNEL_RATE, 0);
591 }
592
593
594 REG_UPDATE_3(HDMI_VBI_PACKET_CONTROL,
595 HDMI_GC_CONT, 1,
596 HDMI_GC_SEND, 1,
597 HDMI_NULL_SEND, 1);
598
599 /* following belongs to audio */
600 REG_UPDATE(HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);
601
602 REG_UPDATE(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
603
604 REG_UPDATE(HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE,
605 VBI_LINE_0 + 2);
606
607 REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, 0);
608 }
609
610 /* setup stream encoder in dvi mode */
enc1_stream_encoder_dvi_set_stream_attribute(struct stream_encoder * enc,struct dc_crtc_timing * crtc_timing,bool is_dual_link)611 void enc1_stream_encoder_dvi_set_stream_attribute(
612 struct stream_encoder *enc,
613 struct dc_crtc_timing *crtc_timing,
614 bool is_dual_link)
615 {
616 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
617 struct bp_encoder_control cntl = {0};
618
619 cntl.action = ENCODER_CONTROL_SETUP;
620 cntl.engine_id = enc1->base.id;
621 cntl.signal = is_dual_link ?
622 SIGNAL_TYPE_DVI_DUAL_LINK : SIGNAL_TYPE_DVI_SINGLE_LINK;
623 cntl.enable_dp_audio = false;
624 cntl.pixel_clock = crtc_timing->pix_clk_100hz / 10;
625 cntl.lanes_number = (is_dual_link) ? LANE_COUNT_EIGHT : LANE_COUNT_FOUR;
626
627 if (enc1->base.bp->funcs->encoder_control(
628 enc1->base.bp, &cntl) != BP_RESULT_OK)
629 return;
630
631 ASSERT(crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB);
632 ASSERT(crtc_timing->display_color_depth == COLOR_DEPTH_888);
633 enc1_stream_encoder_set_stream_attribute_helper(enc1, crtc_timing);
634 }
635
enc1_stream_encoder_set_throttled_vcp_size(struct stream_encoder * enc,struct fixed31_32 avg_time_slots_per_mtp)636 void enc1_stream_encoder_set_throttled_vcp_size(
637 struct stream_encoder *enc,
638 struct fixed31_32 avg_time_slots_per_mtp)
639 {
640 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
641 uint32_t x = dc_fixpt_floor(
642 avg_time_slots_per_mtp);
643 uint32_t y = dc_fixpt_ceil(
644 dc_fixpt_shl(
645 dc_fixpt_sub_int(
646 avg_time_slots_per_mtp,
647 x),
648 26));
649
650 // If y rounds up to integer, carry it over to x.
651 if (y >> 26) {
652 x += 1;
653 y = 0;
654 }
655
656 REG_SET_2(DP_MSE_RATE_CNTL, 0,
657 DP_MSE_RATE_X, x,
658 DP_MSE_RATE_Y, y);
659
660 /* wait for update to be completed on the link */
661 /* i.e. DP_MSE_RATE_UPDATE_PENDING field (read only) */
662 /* is reset to 0 (not pending) */
663 REG_WAIT(DP_MSE_RATE_UPDATE, DP_MSE_RATE_UPDATE_PENDING,
664 0,
665 10, DP_MST_UPDATE_MAX_RETRY);
666 }
667
enc1_stream_encoder_update_hdmi_info_packets(struct stream_encoder * enc,const struct encoder_info_frame * info_frame)668 static void enc1_stream_encoder_update_hdmi_info_packets(
669 struct stream_encoder *enc,
670 const struct encoder_info_frame *info_frame)
671 {
672 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
673
674 /* for bring up, disable dp double TODO */
675 REG_UPDATE(HDMI_DB_CONTROL, HDMI_DB_DISABLE, 1);
676
677 enc1_update_hdmi_info_packet(enc1, 0, &info_frame->avi);
678 enc1_update_hdmi_info_packet(enc1, 1, &info_frame->vendor);
679 enc1_update_hdmi_info_packet(enc1, 2, &info_frame->gamut);
680 enc1_update_hdmi_info_packet(enc1, 3, &info_frame->spd);
681 enc1_update_hdmi_info_packet(enc1, 4, &info_frame->hdrsmd);
682 }
683
enc1_stream_encoder_stop_hdmi_info_packets(struct stream_encoder * enc)684 static void enc1_stream_encoder_stop_hdmi_info_packets(
685 struct stream_encoder *enc)
686 {
687 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
688
689 /* stop generic packets 0 & 1 on HDMI */
690 REG_SET_6(HDMI_GENERIC_PACKET_CONTROL0, 0,
691 HDMI_GENERIC1_CONT, 0,
692 HDMI_GENERIC1_LINE, 0,
693 HDMI_GENERIC1_SEND, 0,
694 HDMI_GENERIC0_CONT, 0,
695 HDMI_GENERIC0_LINE, 0,
696 HDMI_GENERIC0_SEND, 0);
697
698 /* stop generic packets 2 & 3 on HDMI */
699 REG_SET_6(HDMI_GENERIC_PACKET_CONTROL1, 0,
700 HDMI_GENERIC0_CONT, 0,
701 HDMI_GENERIC0_LINE, 0,
702 HDMI_GENERIC0_SEND, 0,
703 HDMI_GENERIC1_CONT, 0,
704 HDMI_GENERIC1_LINE, 0,
705 HDMI_GENERIC1_SEND, 0);
706
707 /* stop generic packets 2 & 3 on HDMI */
708 REG_SET_6(HDMI_GENERIC_PACKET_CONTROL2, 0,
709 HDMI_GENERIC0_CONT, 0,
710 HDMI_GENERIC0_LINE, 0,
711 HDMI_GENERIC0_SEND, 0,
712 HDMI_GENERIC1_CONT, 0,
713 HDMI_GENERIC1_LINE, 0,
714 HDMI_GENERIC1_SEND, 0);
715
716 REG_SET_6(HDMI_GENERIC_PACKET_CONTROL3, 0,
717 HDMI_GENERIC0_CONT, 0,
718 HDMI_GENERIC0_LINE, 0,
719 HDMI_GENERIC0_SEND, 0,
720 HDMI_GENERIC1_CONT, 0,
721 HDMI_GENERIC1_LINE, 0,
722 HDMI_GENERIC1_SEND, 0);
723 }
724
enc1_stream_encoder_update_dp_info_packets(struct stream_encoder * enc,const struct encoder_info_frame * info_frame)725 void enc1_stream_encoder_update_dp_info_packets(
726 struct stream_encoder *enc,
727 const struct encoder_info_frame *info_frame)
728 {
729 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
730 uint32_t value = 0;
731
732 if (info_frame->vsc.valid)
733 enc1_update_generic_info_packet(
734 enc1,
735 0, /* packetIndex */
736 &info_frame->vsc);
737
738 /* VSC SDP at packetIndex 1 is used by PSR in DMCUB FW.
739 * Note that the enablement of GSP1 is not done below,
740 * it's done in FW.
741 */
742 if (info_frame->vsc.valid)
743 enc1_update_generic_info_packet(
744 enc1,
745 1, /* packetIndex */
746 &info_frame->vsc);
747
748 if (info_frame->spd.valid)
749 enc1_update_generic_info_packet(
750 enc1,
751 2, /* packetIndex */
752 &info_frame->spd);
753
754 if (info_frame->hdrsmd.valid)
755 enc1_update_generic_info_packet(
756 enc1,
757 3, /* packetIndex */
758 &info_frame->hdrsmd);
759
760 /* packetIndex 4 is used for send immediate sdp message, and please
761 * use other packetIndex (such as 5,6) for other info packet
762 */
763
764 /* enable/disable transmission of packet(s).
765 * If enabled, packet transmission begins on the next frame
766 */
767 REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, info_frame->vsc.valid);
768 REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, info_frame->spd.valid);
769 REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, info_frame->hdrsmd.valid);
770
771 /* This bit is the master enable bit.
772 * When enabling secondary stream engine,
773 * this master bit must also be set.
774 * This register shared with audio info frame.
775 * Therefore we need to enable master bit
776 * if at least on of the fields is not 0
777 */
778 value = REG_READ(DP_SEC_CNTL);
779 if (value)
780 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
781 }
782
enc1_stream_encoder_send_immediate_sdp_message(struct stream_encoder * enc,const uint8_t * custom_sdp_message,unsigned int sdp_message_size)783 void enc1_stream_encoder_send_immediate_sdp_message(
784 struct stream_encoder *enc,
785 const uint8_t *custom_sdp_message,
786 unsigned int sdp_message_size)
787 {
788 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
789 uint32_t value = 0;
790
791 /* TODOFPGA Figure out a proper number for max_retries polling for lock
792 * use 50 for now.
793 */
794 uint32_t max_retries = 50;
795
796 /* check if GSP4 is transmitted */
797 REG_WAIT(DP_SEC_CNTL2, DP_SEC_GSP4_SEND_PENDING,
798 0, 10, max_retries);
799
800 /* disable GSP4 transmitting */
801 REG_UPDATE(DP_SEC_CNTL2, DP_SEC_GSP4_SEND, 0);
802
803 /* transmit GSP4 at the earliest time in a frame */
804 REG_UPDATE(DP_SEC_CNTL2, DP_SEC_GSP4_SEND_ANY_LINE, 1);
805
806 /*we need turn on clock before programming AFMT block*/
807 REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1);
808
809 /* check if HW reading GSP memory */
810 REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT,
811 0, 10, max_retries);
812
813 /* HW does is not reading GSP memory not reading too long ->
814 * something wrong. clear GPS memory access and notify?
815 * hw SW is writing to GSP memory
816 */
817 REG_UPDATE(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT_CLR, 1);
818
819 /* use generic packet 4 for immediate sdp message */
820 REG_UPDATE(AFMT_VBI_PACKET_CONTROL,
821 AFMT_GENERIC_INDEX, 4);
822
823 /* write generic packet header
824 * (4th byte is for GENERIC0 only)
825 */
826 REG_SET_4(AFMT_GENERIC_HDR, 0,
827 AFMT_GENERIC_HB0, custom_sdp_message[0],
828 AFMT_GENERIC_HB1, custom_sdp_message[1],
829 AFMT_GENERIC_HB2, custom_sdp_message[2],
830 AFMT_GENERIC_HB3, custom_sdp_message[3]);
831
832 /* write generic packet contents
833 * (we never use last 4 bytes)
834 * there are 8 (0-7) mmDIG0_AFMT_GENERIC0_x registers
835 */
836 {
837 const uint32_t *content =
838 (const uint32_t *) &custom_sdp_message[4];
839
840 REG_WRITE(AFMT_GENERIC_0, *content++);
841 REG_WRITE(AFMT_GENERIC_1, *content++);
842 REG_WRITE(AFMT_GENERIC_2, *content++);
843 REG_WRITE(AFMT_GENERIC_3, *content++);
844 REG_WRITE(AFMT_GENERIC_4, *content++);
845 REG_WRITE(AFMT_GENERIC_5, *content++);
846 REG_WRITE(AFMT_GENERIC_6, *content++);
847 REG_WRITE(AFMT_GENERIC_7, *content);
848 }
849
850 /* check whether GENERIC4 registers double buffer update in immediate mode
851 * is pending
852 */
853 REG_WAIT(AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING,
854 0, 10, max_retries);
855
856 /* atomically update double-buffered GENERIC4 registers in immediate mode
857 * (update immediately)
858 */
859 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
860 AFMT_GENERIC4_IMMEDIATE_UPDATE, 1);
861
862 /* enable GSP4 transmitting */
863 REG_UPDATE(DP_SEC_CNTL2, DP_SEC_GSP4_SEND, 1);
864
865 /* This bit is the master enable bit.
866 * When enabling secondary stream engine,
867 * this master bit must also be set.
868 * This register shared with audio info frame.
869 * Therefore we need to enable master bit
870 * if at least on of the fields is not 0
871 */
872 value = REG_READ(DP_SEC_CNTL);
873 if (value)
874 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
875 }
876
enc1_stream_encoder_stop_dp_info_packets(struct stream_encoder * enc)877 void enc1_stream_encoder_stop_dp_info_packets(
878 struct stream_encoder *enc)
879 {
880 /* stop generic packets on DP */
881 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
882 uint32_t value = 0;
883
884 REG_SET_10(DP_SEC_CNTL, 0,
885 DP_SEC_GSP0_ENABLE, 0,
886 DP_SEC_GSP1_ENABLE, 0,
887 DP_SEC_GSP2_ENABLE, 0,
888 DP_SEC_GSP3_ENABLE, 0,
889 DP_SEC_GSP4_ENABLE, 0,
890 DP_SEC_GSP5_ENABLE, 0,
891 DP_SEC_GSP6_ENABLE, 0,
892 DP_SEC_GSP7_ENABLE, 0,
893 DP_SEC_MPG_ENABLE, 0,
894 DP_SEC_STREAM_ENABLE, 0);
895
896 /* this register shared with audio info frame.
897 * therefore we need to keep master enabled
898 * if at least one of the fields is not 0 */
899 value = REG_READ(DP_SEC_CNTL);
900 if (value)
901 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
902
903 }
904
enc1_stream_encoder_dp_blank(struct dc_link * link,struct stream_encoder * enc)905 void enc1_stream_encoder_dp_blank(
906 struct dc_link *link,
907 struct stream_encoder *enc)
908 {
909 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
910 uint32_t reg1 = 0;
911 uint32_t max_retries = DP_BLANK_MAX_RETRY * 10;
912
913 /* Note: For CZ, we are changing driver default to disable
914 * stream deferred to next VBLANK. If results are positive, we
915 * will make the same change to all DCE versions. There are a
916 * handful of panels that cannot handle disable stream at
917 * HBLANK and will result in a white line flash across the
918 * screen on stream disable.
919 */
920 REG_GET(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, ®1);
921 if ((reg1 & 0x1) == 0)
922 /*stream not enabled*/
923 return;
924 /* Specify the video stream disable point
925 * (2 = start of the next vertical blank)
926 */
927 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_DIS_DEFER, 2);
928 /* Larger delay to wait until VBLANK - use max retry of
929 * 10us*10200=102ms. This covers 100.0ms of minimum 10 Hz mode +
930 * a little more because we may not trust delay accuracy.
931 */
932 max_retries = DP_BLANK_MAX_RETRY * 501;
933
934 /* disable DP stream */
935 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 0);
936
937 dp_source_sequence_trace(link, DPCD_SOURCE_SEQ_AFTER_DISABLE_DP_VID_STREAM);
938
939 /* the encoder stops sending the video stream
940 * at the start of the vertical blanking.
941 * Poll for DP_VID_STREAM_STATUS == 0
942 */
943
944 REG_WAIT(DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS,
945 0,
946 10, max_retries);
947
948 /* Tell the DP encoder to ignore timing from CRTC, must be done after
949 * the polling. If we set DP_STEER_FIFO_RESET before DP stream blank is
950 * complete, stream status will be stuck in video stream enabled state,
951 * i.e. DP_VID_STREAM_STATUS stuck at 1.
952 */
953
954 REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, true);
955
956 dp_source_sequence_trace(link, DPCD_SOURCE_SEQ_AFTER_FIFO_STEER_RESET);
957 }
958
959 /* output video stream to link encoder */
enc1_stream_encoder_dp_unblank(struct dc_link * link,struct stream_encoder * enc,const struct encoder_unblank_param * param)960 void enc1_stream_encoder_dp_unblank(
961 struct dc_link *link,
962 struct stream_encoder *enc,
963 const struct encoder_unblank_param *param)
964 {
965 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
966
967 if (param->link_settings.link_rate != LINK_RATE_UNKNOWN) {
968 uint32_t n_vid = 0x8000;
969 uint32_t m_vid;
970 uint32_t n_multiply = 0;
971 uint64_t m_vid_l = n_vid;
972
973 /* YCbCr 4:2:0 : Computed VID_M will be 2X the input rate */
974 if (param->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) {
975 /*this param->pixel_clk_khz is half of 444 rate for 420 already*/
976 n_multiply = 1;
977 }
978 /* M / N = Fstream / Flink
979 * m_vid / n_vid = pixel rate / link rate
980 */
981
982 m_vid_l *= param->timing.pix_clk_100hz / 10;
983 m_vid_l = div_u64(m_vid_l,
984 param->link_settings.link_rate
985 * LINK_RATE_REF_FREQ_IN_KHZ);
986
987 m_vid = (uint32_t) m_vid_l;
988
989 /* enable auto measurement */
990
991 REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 0);
992
993 /* auto measurement need 1 full 0x8000 symbol cycle to kick in,
994 * therefore program initial value for Mvid and Nvid
995 */
996
997 REG_UPDATE(DP_VID_N, DP_VID_N, n_vid);
998
999 REG_UPDATE(DP_VID_M, DP_VID_M, m_vid);
1000
1001 REG_UPDATE_2(DP_VID_TIMING,
1002 DP_VID_M_N_GEN_EN, 1,
1003 DP_VID_N_MUL, n_multiply);
1004 }
1005
1006 /* set DIG_START to 0x1 to resync FIFO */
1007
1008 REG_UPDATE(DIG_FE_CNTL, DIG_START, 1);
1009
1010 /* switch DP encoder to CRTC data */
1011
1012 REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, 0);
1013
1014 /* wait 100us for DIG/DP logic to prime
1015 * (i.e. a few video lines)
1016 */
1017 udelay(100);
1018
1019 /* the hardware would start sending video at the start of the next DP
1020 * frame (i.e. rising edge of the vblank).
1021 * NOTE: We used to program DP_VID_STREAM_DIS_DEFER = 2 here, but this
1022 * register has no effect on enable transition! HW always guarantees
1023 * VID_STREAM enable at start of next frame, and this is not
1024 * programmable
1025 */
1026
1027 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, true);
1028
1029 dp_source_sequence_trace(link, DPCD_SOURCE_SEQ_AFTER_ENABLE_DP_VID_STREAM);
1030 }
1031
enc1_stream_encoder_set_avmute(struct stream_encoder * enc,bool enable)1032 void enc1_stream_encoder_set_avmute(
1033 struct stream_encoder *enc,
1034 bool enable)
1035 {
1036 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
1037 unsigned int value = enable ? 1 : 0;
1038
1039 REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, value);
1040 }
1041
enc1_reset_hdmi_stream_attribute(struct stream_encoder * enc)1042 void enc1_reset_hdmi_stream_attribute(
1043 struct stream_encoder *enc)
1044 {
1045 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
1046
1047 REG_UPDATE_5(HDMI_CONTROL,
1048 HDMI_PACKET_GEN_VERSION, 1,
1049 HDMI_KEEPOUT_MODE, 1,
1050 HDMI_DEEP_COLOR_ENABLE, 0,
1051 HDMI_DATA_SCRAMBLE_EN, 0,
1052 HDMI_CLOCK_CHANNEL_RATE, 0);
1053 }
1054
1055
1056 #define DP_SEC_AUD_N__DP_SEC_AUD_N__DEFAULT 0x8000
1057 #define DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUTO_CALC 1
1058
1059 #include "include/audio_types.h"
1060
1061
1062 /* 25.2MHz/1.001*/
1063 /* 25.2MHz/1.001*/
1064 /* 25.2MHz*/
1065 /* 27MHz */
1066 /* 27MHz*1.001*/
1067 /* 27MHz*1.001*/
1068 /* 54MHz*/
1069 /* 54MHz*1.001*/
1070 /* 74.25MHz/1.001*/
1071 /* 74.25MHz*/
1072 /* 148.5MHz/1.001*/
1073 /* 148.5MHz*/
1074
1075 static const struct audio_clock_info audio_clock_info_table[16] = {
1076 {2517, 4576, 28125, 7007, 31250, 6864, 28125},
1077 {2518, 4576, 28125, 7007, 31250, 6864, 28125},
1078 {2520, 4096, 25200, 6272, 28000, 6144, 25200},
1079 {2700, 4096, 27000, 6272, 30000, 6144, 27000},
1080 {2702, 4096, 27027, 6272, 30030, 6144, 27027},
1081 {2703, 4096, 27027, 6272, 30030, 6144, 27027},
1082 {5400, 4096, 54000, 6272, 60000, 6144, 54000},
1083 {5405, 4096, 54054, 6272, 60060, 6144, 54054},
1084 {7417, 11648, 210937, 17836, 234375, 11648, 140625},
1085 {7425, 4096, 74250, 6272, 82500, 6144, 74250},
1086 {14835, 11648, 421875, 8918, 234375, 5824, 140625},
1087 {14850, 4096, 148500, 6272, 165000, 6144, 148500},
1088 {29670, 5824, 421875, 4459, 234375, 5824, 281250},
1089 {29700, 3072, 222750, 4704, 247500, 5120, 247500},
1090 {59340, 5824, 843750, 8918, 937500, 5824, 562500},
1091 {59400, 3072, 445500, 9408, 990000, 6144, 594000}
1092 };
1093
1094 static const struct audio_clock_info audio_clock_info_table_36bpc[14] = {
1095 {2517, 9152, 84375, 7007, 48875, 9152, 56250},
1096 {2518, 9152, 84375, 7007, 48875, 9152, 56250},
1097 {2520, 4096, 37800, 6272, 42000, 6144, 37800},
1098 {2700, 4096, 40500, 6272, 45000, 6144, 40500},
1099 {2702, 8192, 81081, 6272, 45045, 8192, 54054},
1100 {2703, 8192, 81081, 6272, 45045, 8192, 54054},
1101 {5400, 4096, 81000, 6272, 90000, 6144, 81000},
1102 {5405, 4096, 81081, 6272, 90090, 6144, 81081},
1103 {7417, 11648, 316406, 17836, 351562, 11648, 210937},
1104 {7425, 4096, 111375, 6272, 123750, 6144, 111375},
1105 {14835, 11648, 632812, 17836, 703125, 11648, 421875},
1106 {14850, 4096, 222750, 6272, 247500, 6144, 222750},
1107 {29670, 5824, 632812, 8918, 703125, 5824, 421875},
1108 {29700, 4096, 445500, 4704, 371250, 5120, 371250}
1109 };
1110
1111 static const struct audio_clock_info audio_clock_info_table_48bpc[14] = {
1112 {2517, 4576, 56250, 7007, 62500, 6864, 56250},
1113 {2518, 4576, 56250, 7007, 62500, 6864, 56250},
1114 {2520, 4096, 50400, 6272, 56000, 6144, 50400},
1115 {2700, 4096, 54000, 6272, 60000, 6144, 54000},
1116 {2702, 4096, 54054, 6267, 60060, 8192, 54054},
1117 {2703, 4096, 54054, 6272, 60060, 8192, 54054},
1118 {5400, 4096, 108000, 6272, 120000, 6144, 108000},
1119 {5405, 4096, 108108, 6272, 120120, 6144, 108108},
1120 {7417, 11648, 421875, 17836, 468750, 11648, 281250},
1121 {7425, 4096, 148500, 6272, 165000, 6144, 148500},
1122 {14835, 11648, 843750, 8918, 468750, 11648, 281250},
1123 {14850, 4096, 297000, 6272, 330000, 6144, 297000},
1124 {29670, 5824, 843750, 4459, 468750, 5824, 562500},
1125 {29700, 3072, 445500, 4704, 495000, 5120, 495000}
1126
1127
1128 };
1129
speakers_to_channels(struct audio_speaker_flags speaker_flags)1130 static union audio_cea_channels speakers_to_channels(
1131 struct audio_speaker_flags speaker_flags)
1132 {
1133 union audio_cea_channels cea_channels = {0};
1134
1135 /* these are one to one */
1136 cea_channels.channels.FL = speaker_flags.FL_FR;
1137 cea_channels.channels.FR = speaker_flags.FL_FR;
1138 cea_channels.channels.LFE = speaker_flags.LFE;
1139 cea_channels.channels.FC = speaker_flags.FC;
1140
1141 /* if Rear Left and Right exist move RC speaker to channel 7
1142 * otherwise to channel 5
1143 */
1144 if (speaker_flags.RL_RR) {
1145 cea_channels.channels.RL_RC = speaker_flags.RL_RR;
1146 cea_channels.channels.RR = speaker_flags.RL_RR;
1147 cea_channels.channels.RC_RLC_FLC = speaker_flags.RC;
1148 } else {
1149 cea_channels.channels.RL_RC = speaker_flags.RC;
1150 }
1151
1152 /* FRONT Left Right Center and REAR Left Right Center are exclusive */
1153 if (speaker_flags.FLC_FRC) {
1154 cea_channels.channels.RC_RLC_FLC = speaker_flags.FLC_FRC;
1155 cea_channels.channels.RRC_FRC = speaker_flags.FLC_FRC;
1156 } else {
1157 cea_channels.channels.RC_RLC_FLC = speaker_flags.RLC_RRC;
1158 cea_channels.channels.RRC_FRC = speaker_flags.RLC_RRC;
1159 }
1160
1161 return cea_channels;
1162 }
1163
get_audio_clock_info(enum dc_color_depth color_depth,uint32_t crtc_pixel_clock_100Hz,uint32_t actual_pixel_clock_100Hz,struct audio_clock_info * audio_clock_info)1164 void get_audio_clock_info(
1165 enum dc_color_depth color_depth,
1166 uint32_t crtc_pixel_clock_100Hz,
1167 uint32_t actual_pixel_clock_100Hz,
1168 struct audio_clock_info *audio_clock_info)
1169 {
1170 const struct audio_clock_info *clock_info;
1171 uint32_t index;
1172 uint32_t crtc_pixel_clock_in_10khz = crtc_pixel_clock_100Hz / 100;
1173 uint32_t audio_array_size;
1174
1175 switch (color_depth) {
1176 case COLOR_DEPTH_161616:
1177 clock_info = audio_clock_info_table_48bpc;
1178 audio_array_size = ARRAY_SIZE(
1179 audio_clock_info_table_48bpc);
1180 break;
1181 case COLOR_DEPTH_121212:
1182 clock_info = audio_clock_info_table_36bpc;
1183 audio_array_size = ARRAY_SIZE(
1184 audio_clock_info_table_36bpc);
1185 break;
1186 default:
1187 clock_info = audio_clock_info_table;
1188 audio_array_size = ARRAY_SIZE(
1189 audio_clock_info_table);
1190 break;
1191 }
1192
1193 if (clock_info != NULL) {
1194 /* search for exact pixel clock in table */
1195 for (index = 0; index < audio_array_size; index++) {
1196 if (clock_info[index].pixel_clock_in_10khz >
1197 crtc_pixel_clock_in_10khz)
1198 break; /* not match */
1199 else if (clock_info[index].pixel_clock_in_10khz ==
1200 crtc_pixel_clock_in_10khz) {
1201 /* match found */
1202 *audio_clock_info = clock_info[index];
1203 return;
1204 }
1205 }
1206 }
1207
1208 /* not found */
1209 if (actual_pixel_clock_100Hz == 0)
1210 actual_pixel_clock_100Hz = crtc_pixel_clock_100Hz;
1211
1212 /* See HDMI spec the table entry under
1213 * pixel clock of "Other". */
1214 audio_clock_info->pixel_clock_in_10khz =
1215 actual_pixel_clock_100Hz / 100;
1216 audio_clock_info->cts_32khz = actual_pixel_clock_100Hz / 10;
1217 audio_clock_info->cts_44khz = actual_pixel_clock_100Hz / 10;
1218 audio_clock_info->cts_48khz = actual_pixel_clock_100Hz / 10;
1219
1220 audio_clock_info->n_32khz = 4096;
1221 audio_clock_info->n_44khz = 6272;
1222 audio_clock_info->n_48khz = 6144;
1223 }
1224
enc1_se_audio_setup(struct stream_encoder * enc,unsigned int az_inst,struct audio_info * audio_info)1225 static void enc1_se_audio_setup(
1226 struct stream_encoder *enc,
1227 unsigned int az_inst,
1228 struct audio_info *audio_info)
1229 {
1230 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
1231
1232 uint32_t channels = 0;
1233
1234 ASSERT(audio_info);
1235 if (audio_info == NULL)
1236 /* This should not happen.it does so we don't get BSOD*/
1237 return;
1238
1239 channels = speakers_to_channels(audio_info->flags.speaker_flags).all;
1240
1241 /* setup the audio stream source select (audio -> dig mapping) */
1242 REG_SET(AFMT_AUDIO_SRC_CONTROL, 0, AFMT_AUDIO_SRC_SELECT, az_inst);
1243
1244 /* Channel allocation */
1245 REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_CHANNEL_ENABLE, channels);
1246 }
1247
enc1_se_setup_hdmi_audio(struct stream_encoder * enc,const struct audio_crtc_info * crtc_info)1248 static void enc1_se_setup_hdmi_audio(
1249 struct stream_encoder *enc,
1250 const struct audio_crtc_info *crtc_info)
1251 {
1252 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
1253
1254 struct audio_clock_info audio_clock_info = {0};
1255
1256 /* HDMI_AUDIO_PACKET_CONTROL */
1257 REG_UPDATE(HDMI_AUDIO_PACKET_CONTROL,
1258 HDMI_AUDIO_DELAY_EN, 1);
1259
1260 /* AFMT_AUDIO_PACKET_CONTROL */
1261 REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
1262
1263 /* AFMT_AUDIO_PACKET_CONTROL2 */
1264 REG_UPDATE_2(AFMT_AUDIO_PACKET_CONTROL2,
1265 AFMT_AUDIO_LAYOUT_OVRD, 0,
1266 AFMT_60958_OSF_OVRD, 0);
1267
1268 /* HDMI_ACR_PACKET_CONTROL */
1269 REG_UPDATE_3(HDMI_ACR_PACKET_CONTROL,
1270 HDMI_ACR_AUTO_SEND, 1,
1271 HDMI_ACR_SOURCE, 0,
1272 HDMI_ACR_AUDIO_PRIORITY, 0);
1273
1274 /* Program audio clock sample/regeneration parameters */
1275 get_audio_clock_info(crtc_info->color_depth,
1276 crtc_info->requested_pixel_clock_100Hz,
1277 crtc_info->calculated_pixel_clock_100Hz,
1278 &audio_clock_info);
1279 DC_LOG_HW_AUDIO(
1280 "\n%s:Input::requested_pixel_clock_100Hz = %d" \
1281 "calculated_pixel_clock_100Hz = %d \n", __func__, \
1282 crtc_info->requested_pixel_clock_100Hz, \
1283 crtc_info->calculated_pixel_clock_100Hz);
1284
1285 /* HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK */
1286 REG_UPDATE(HDMI_ACR_32_0, HDMI_ACR_CTS_32, audio_clock_info.cts_32khz);
1287
1288 /* HDMI_ACR_32_1__HDMI_ACR_N_32_MASK */
1289 REG_UPDATE(HDMI_ACR_32_1, HDMI_ACR_N_32, audio_clock_info.n_32khz);
1290
1291 /* HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK */
1292 REG_UPDATE(HDMI_ACR_44_0, HDMI_ACR_CTS_44, audio_clock_info.cts_44khz);
1293
1294 /* HDMI_ACR_44_1__HDMI_ACR_N_44_MASK */
1295 REG_UPDATE(HDMI_ACR_44_1, HDMI_ACR_N_44, audio_clock_info.n_44khz);
1296
1297 /* HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK */
1298 REG_UPDATE(HDMI_ACR_48_0, HDMI_ACR_CTS_48, audio_clock_info.cts_48khz);
1299
1300 /* HDMI_ACR_48_1__HDMI_ACR_N_48_MASK */
1301 REG_UPDATE(HDMI_ACR_48_1, HDMI_ACR_N_48, audio_clock_info.n_48khz);
1302
1303 /* Video driver cannot know in advance which sample rate will
1304 * be used by HD Audio driver
1305 * HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE field is
1306 * programmed below in interruppt callback
1307 */
1308
1309 /* AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK &
1310 * AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK
1311 */
1312 REG_UPDATE_2(AFMT_60958_0,
1313 AFMT_60958_CS_CHANNEL_NUMBER_L, 1,
1314 AFMT_60958_CS_CLOCK_ACCURACY, 0);
1315
1316 /* AFMT_60958_1 AFMT_60958_CS_CHALNNEL_NUMBER_R */
1317 REG_UPDATE(AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2);
1318
1319 /* AFMT_60958_2 now keep this settings until
1320 * Programming guide comes out
1321 */
1322 REG_UPDATE_6(AFMT_60958_2,
1323 AFMT_60958_CS_CHANNEL_NUMBER_2, 3,
1324 AFMT_60958_CS_CHANNEL_NUMBER_3, 4,
1325 AFMT_60958_CS_CHANNEL_NUMBER_4, 5,
1326 AFMT_60958_CS_CHANNEL_NUMBER_5, 6,
1327 AFMT_60958_CS_CHANNEL_NUMBER_6, 7,
1328 AFMT_60958_CS_CHANNEL_NUMBER_7, 8);
1329 }
1330
enc1_se_setup_dp_audio(struct stream_encoder * enc)1331 static void enc1_se_setup_dp_audio(
1332 struct stream_encoder *enc)
1333 {
1334 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
1335
1336 /* --- DP Audio packet configurations --- */
1337
1338 /* ATP Configuration */
1339 REG_SET(DP_SEC_AUD_N, 0,
1340 DP_SEC_AUD_N, DP_SEC_AUD_N__DP_SEC_AUD_N__DEFAULT);
1341
1342 /* Async/auto-calc timestamp mode */
1343 REG_SET(DP_SEC_TIMESTAMP, 0, DP_SEC_TIMESTAMP_MODE,
1344 DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUTO_CALC);
1345
1346 /* --- The following are the registers
1347 * copied from the SetupHDMI ---
1348 */
1349
1350 /* AFMT_AUDIO_PACKET_CONTROL */
1351 REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
1352
1353 /* AFMT_AUDIO_PACKET_CONTROL2 */
1354 /* Program the ATP and AIP next */
1355 REG_UPDATE_2(AFMT_AUDIO_PACKET_CONTROL2,
1356 AFMT_AUDIO_LAYOUT_OVRD, 0,
1357 AFMT_60958_OSF_OVRD, 0);
1358
1359 /* AFMT_INFOFRAME_CONTROL0 */
1360 REG_UPDATE(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
1361
1362 /* AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK */
1363 REG_UPDATE(AFMT_60958_0, AFMT_60958_CS_CLOCK_ACCURACY, 0);
1364 }
1365
enc1_se_enable_audio_clock(struct stream_encoder * enc,bool enable)1366 void enc1_se_enable_audio_clock(
1367 struct stream_encoder *enc,
1368 bool enable)
1369 {
1370 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
1371
1372 if (REG(AFMT_CNTL) == 0)
1373 return; /* DCE8/10 does not have this register */
1374
1375 REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, !!enable);
1376
1377 /* wait for AFMT clock to turn on,
1378 * expectation: this should complete in 1-2 reads
1379 *
1380 * REG_WAIT(AFMT_CNTL, AFMT_AUDIO_CLOCK_ON, !!enable, 1, 10);
1381 *
1382 * TODO: wait for clock_on does not work well. May need HW
1383 * program sequence. But audio seems work normally even without wait
1384 * for clock_on status change
1385 */
1386 }
1387
enc1_se_enable_dp_audio(struct stream_encoder * enc)1388 void enc1_se_enable_dp_audio(
1389 struct stream_encoder *enc)
1390 {
1391 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
1392
1393 /* Enable Audio packets */
1394 REG_UPDATE(DP_SEC_CNTL, DP_SEC_ASP_ENABLE, 1);
1395
1396 /* Program the ATP and AIP next */
1397 REG_UPDATE_2(DP_SEC_CNTL,
1398 DP_SEC_ATP_ENABLE, 1,
1399 DP_SEC_AIP_ENABLE, 1);
1400
1401 /* Program STREAM_ENABLE after all the other enables. */
1402 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
1403 }
1404
enc1_se_disable_dp_audio(struct stream_encoder * enc)1405 static void enc1_se_disable_dp_audio(
1406 struct stream_encoder *enc)
1407 {
1408 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
1409 uint32_t value = 0;
1410
1411 /* Disable Audio packets */
1412 REG_UPDATE_5(DP_SEC_CNTL,
1413 DP_SEC_ASP_ENABLE, 0,
1414 DP_SEC_ATP_ENABLE, 0,
1415 DP_SEC_AIP_ENABLE, 0,
1416 DP_SEC_ACM_ENABLE, 0,
1417 DP_SEC_STREAM_ENABLE, 0);
1418
1419 /* This register shared with encoder info frame. Therefore we need to
1420 * keep master enabled if at least on of the fields is not 0
1421 */
1422 value = REG_READ(DP_SEC_CNTL);
1423 if (value != 0)
1424 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
1425
1426 }
1427
enc1_se_audio_mute_control(struct stream_encoder * enc,bool mute)1428 void enc1_se_audio_mute_control(
1429 struct stream_encoder *enc,
1430 bool mute)
1431 {
1432 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
1433
1434 REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, !mute);
1435 }
1436
enc1_se_dp_audio_setup(struct stream_encoder * enc,unsigned int az_inst,struct audio_info * info)1437 void enc1_se_dp_audio_setup(
1438 struct stream_encoder *enc,
1439 unsigned int az_inst,
1440 struct audio_info *info)
1441 {
1442 enc1_se_audio_setup(enc, az_inst, info);
1443 }
1444
enc1_se_dp_audio_enable(struct stream_encoder * enc)1445 void enc1_se_dp_audio_enable(
1446 struct stream_encoder *enc)
1447 {
1448 enc1_se_enable_audio_clock(enc, true);
1449 enc1_se_setup_dp_audio(enc);
1450 enc1_se_enable_dp_audio(enc);
1451 }
1452
enc1_se_dp_audio_disable(struct stream_encoder * enc)1453 void enc1_se_dp_audio_disable(
1454 struct stream_encoder *enc)
1455 {
1456 enc1_se_disable_dp_audio(enc);
1457 enc1_se_enable_audio_clock(enc, false);
1458 }
1459
enc1_se_hdmi_audio_setup(struct stream_encoder * enc,unsigned int az_inst,struct audio_info * info,struct audio_crtc_info * audio_crtc_info)1460 void enc1_se_hdmi_audio_setup(
1461 struct stream_encoder *enc,
1462 unsigned int az_inst,
1463 struct audio_info *info,
1464 struct audio_crtc_info *audio_crtc_info)
1465 {
1466 enc1_se_enable_audio_clock(enc, true);
1467 enc1_se_setup_hdmi_audio(enc, audio_crtc_info);
1468 enc1_se_audio_setup(enc, az_inst, info);
1469 }
1470
enc1_se_hdmi_audio_disable(struct stream_encoder * enc)1471 void enc1_se_hdmi_audio_disable(
1472 struct stream_encoder *enc)
1473 {
1474 #if defined(CONFIG_DRM_AMD_DC_DCN)
1475 if (enc->afmt && enc->afmt->funcs->afmt_powerdown)
1476 enc->afmt->funcs->afmt_powerdown(enc->afmt);
1477 #endif
1478 enc1_se_enable_audio_clock(enc, false);
1479 }
1480
1481
enc1_setup_stereo_sync(struct stream_encoder * enc,int tg_inst,bool enable)1482 void enc1_setup_stereo_sync(
1483 struct stream_encoder *enc,
1484 int tg_inst, bool enable)
1485 {
1486 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
1487 REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, tg_inst);
1488 REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, !enable);
1489 }
1490
enc1_dig_connect_to_otg(struct stream_encoder * enc,int tg_inst)1491 void enc1_dig_connect_to_otg(
1492 struct stream_encoder *enc,
1493 int tg_inst)
1494 {
1495 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
1496
1497 REG_UPDATE(DIG_FE_CNTL, DIG_SOURCE_SELECT, tg_inst);
1498 }
1499
enc1_dig_source_otg(struct stream_encoder * enc)1500 unsigned int enc1_dig_source_otg(
1501 struct stream_encoder *enc)
1502 {
1503 uint32_t tg_inst = 0;
1504 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
1505
1506 REG_GET(DIG_FE_CNTL, DIG_SOURCE_SELECT, &tg_inst);
1507
1508 return tg_inst;
1509 }
1510
enc1_stream_encoder_dp_get_pixel_format(struct stream_encoder * enc,enum dc_pixel_encoding * encoding,enum dc_color_depth * depth)1511 bool enc1_stream_encoder_dp_get_pixel_format(
1512 struct stream_encoder *enc,
1513 enum dc_pixel_encoding *encoding,
1514 enum dc_color_depth *depth)
1515 {
1516 uint32_t hw_encoding = 0;
1517 uint32_t hw_depth = 0;
1518 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
1519
1520 if (enc == NULL ||
1521 encoding == NULL ||
1522 depth == NULL)
1523 return false;
1524
1525 REG_GET_2(DP_PIXEL_FORMAT,
1526 DP_PIXEL_ENCODING, &hw_encoding,
1527 DP_COMPONENT_DEPTH, &hw_depth);
1528
1529 switch (hw_depth) {
1530 case DP_COMPONENT_PIXEL_DEPTH_6BPC:
1531 *depth = COLOR_DEPTH_666;
1532 break;
1533 case DP_COMPONENT_PIXEL_DEPTH_8BPC:
1534 *depth = COLOR_DEPTH_888;
1535 break;
1536 case DP_COMPONENT_PIXEL_DEPTH_10BPC:
1537 *depth = COLOR_DEPTH_101010;
1538 break;
1539 case DP_COMPONENT_PIXEL_DEPTH_12BPC:
1540 *depth = COLOR_DEPTH_121212;
1541 break;
1542 case DP_COMPONENT_PIXEL_DEPTH_16BPC:
1543 *depth = COLOR_DEPTH_161616;
1544 break;
1545 default:
1546 *depth = COLOR_DEPTH_UNDEFINED;
1547 break;
1548 }
1549
1550 switch (hw_encoding) {
1551 case DP_PIXEL_ENCODING_TYPE_RGB444:
1552 *encoding = PIXEL_ENCODING_RGB;
1553 break;
1554 case DP_PIXEL_ENCODING_TYPE_YCBCR422:
1555 *encoding = PIXEL_ENCODING_YCBCR422;
1556 break;
1557 case DP_PIXEL_ENCODING_TYPE_YCBCR444:
1558 case DP_PIXEL_ENCODING_TYPE_Y_ONLY:
1559 *encoding = PIXEL_ENCODING_YCBCR444;
1560 break;
1561 case DP_PIXEL_ENCODING_TYPE_YCBCR420:
1562 *encoding = PIXEL_ENCODING_YCBCR420;
1563 break;
1564 default:
1565 *encoding = PIXEL_ENCODING_UNDEFINED;
1566 break;
1567 }
1568 return true;
1569 }
1570
1571 static const struct stream_encoder_funcs dcn10_str_enc_funcs = {
1572 .dp_set_stream_attribute =
1573 enc1_stream_encoder_dp_set_stream_attribute,
1574 .hdmi_set_stream_attribute =
1575 enc1_stream_encoder_hdmi_set_stream_attribute,
1576 .dvi_set_stream_attribute =
1577 enc1_stream_encoder_dvi_set_stream_attribute,
1578 .set_throttled_vcp_size =
1579 enc1_stream_encoder_set_throttled_vcp_size,
1580 .update_hdmi_info_packets =
1581 enc1_stream_encoder_update_hdmi_info_packets,
1582 .stop_hdmi_info_packets =
1583 enc1_stream_encoder_stop_hdmi_info_packets,
1584 .update_dp_info_packets =
1585 enc1_stream_encoder_update_dp_info_packets,
1586 .send_immediate_sdp_message =
1587 enc1_stream_encoder_send_immediate_sdp_message,
1588 .stop_dp_info_packets =
1589 enc1_stream_encoder_stop_dp_info_packets,
1590 .dp_blank =
1591 enc1_stream_encoder_dp_blank,
1592 .dp_unblank =
1593 enc1_stream_encoder_dp_unblank,
1594 .audio_mute_control = enc1_se_audio_mute_control,
1595
1596 .dp_audio_setup = enc1_se_dp_audio_setup,
1597 .dp_audio_enable = enc1_se_dp_audio_enable,
1598 .dp_audio_disable = enc1_se_dp_audio_disable,
1599
1600 .hdmi_audio_setup = enc1_se_hdmi_audio_setup,
1601 .hdmi_audio_disable = enc1_se_hdmi_audio_disable,
1602 .setup_stereo_sync = enc1_setup_stereo_sync,
1603 .set_avmute = enc1_stream_encoder_set_avmute,
1604 .dig_connect_to_otg = enc1_dig_connect_to_otg,
1605 .hdmi_reset_stream_attribute = enc1_reset_hdmi_stream_attribute,
1606 .dig_source_otg = enc1_dig_source_otg,
1607
1608 .dp_get_pixel_format = enc1_stream_encoder_dp_get_pixel_format,
1609 };
1610
dcn10_stream_encoder_construct(struct dcn10_stream_encoder * enc1,struct dc_context * ctx,struct dc_bios * bp,enum engine_id eng_id,const struct dcn10_stream_enc_registers * regs,const struct dcn10_stream_encoder_shift * se_shift,const struct dcn10_stream_encoder_mask * se_mask)1611 void dcn10_stream_encoder_construct(
1612 struct dcn10_stream_encoder *enc1,
1613 struct dc_context *ctx,
1614 struct dc_bios *bp,
1615 enum engine_id eng_id,
1616 const struct dcn10_stream_enc_registers *regs,
1617 const struct dcn10_stream_encoder_shift *se_shift,
1618 const struct dcn10_stream_encoder_mask *se_mask)
1619 {
1620 enc1->base.funcs = &dcn10_str_enc_funcs;
1621 enc1->base.ctx = ctx;
1622 enc1->base.id = eng_id;
1623 enc1->base.bp = bp;
1624 enc1->regs = regs;
1625 enc1->se_shift = se_shift;
1626 enc1->se_mask = se_mask;
1627 enc1->base.stream_enc_inst = eng_id - ENGINE_ID_DIGA;
1628 }
1629
1630