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Searched defs:hart (Results 1 – 6 of 6) sorted by relevance

/u-boot/arch/riscv/lib/
A Dandes_plic.c24 #define PENDING_REG(base, hart) ((ulong)(base) + 0x1000 + ((hart) / 4) * 4) argument
26 #define ENABLE_REG(base, hart) ((ulong)(base) + 0x2000 + (hart) * 0x80) argument
28 #define CLAIM_REG(base, hart) ((ulong)(base) + 0x200004 + (hart) * 0x1000) argument
31 #define SEND_IPI_TO_HART(hart) (0x80 >> (hart)) argument
35 static int enable_ipi(int hart) in enable_ipi()
86 int riscv_send_ipi(int hart) in riscv_send_ipi()
96 int riscv_clear_ipi(int hart) in riscv_clear_ipi()
106 int riscv_get_ipi(int hart, int *pending) in riscv_get_ipi()
A Dsifive_clint.c19 #define MSIP_REG(base, hart) ((ulong)(base) + (hart) * 4) argument
40 int riscv_send_ipi(int hart) in riscv_send_ipi()
47 int riscv_clear_ipi(int hart) in riscv_clear_ipi()
54 int riscv_get_ipi(int hart, int *pending) in riscv_get_ipi()
A Dsbi_ipi.c16 int riscv_send_ipi(int hart) in riscv_send_ipi()
26 int riscv_clear_ipi(int hart) in riscv_clear_ipi()
33 int riscv_get_ipi(int hart, int *pending) in riscv_get_ipi()
A Dsmp.c85 void handle_ipi(ulong hart) in handle_ipi()
/u-boot/drivers/cache/
A Dcache-v5l2.c56 #define CCTL_CMD_REG(base, hart) ((ulong)(base) + 0x40 + (hart) * 0x10) argument
60 #define CCTL_STATUS_MSK(hart) (0xf << ((hart) * 4)) argument
61 #define CCTL_STATUS_IDLE(hart) (0 << ((hart) * 4)) argument
62 #define CCTL_STATUS_PROCESS(hart) (1 << ((hart) * 4)) argument
63 #define CCTL_STATUS_ILLEGAL(hart) (2 << ((hart) * 4)) argument
90 u8 hart = gd->arch.boot_hart; in v5l2_disable() local
/u-boot/arch/riscv/cpu/
A Dcpu.c81 static void dummy_pending_ipi_clear(ulong hart, ulong arg0, ulong arg1) in dummy_pending_ipi_clear()

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