1 // SPDX-License-Identifier: ISC
2 /* Copyright (C) 2020 MediaTek Inc.
3 *
4 * Author: Felix Fietkau <nbd@nbd.name>
5 * Lorenzo Bianconi <lorenzo@kernel.org>
6 * Sean Wang <sean.wang@mediatek.com>
7 */
8
9 #include <linux/kernel.h>
10 #include <linux/iopoll.h>
11 #include <linux/module.h>
12
13 #include <linux/mmc/host.h>
14 #include <linux/mmc/sdio_ids.h>
15 #include <linux/mmc/sdio_func.h>
16
17 #include "trace.h"
18 #include "sdio.h"
19 #include "mt76.h"
20
mt76s_refill_sched_quota(struct mt76_dev * dev,u32 * data)21 static int mt76s_refill_sched_quota(struct mt76_dev *dev, u32 *data)
22 {
23 u32 ple_ac_data_quota[] = {
24 FIELD_GET(TXQ_CNT_L, data[4]), /* VO */
25 FIELD_GET(TXQ_CNT_H, data[3]), /* VI */
26 FIELD_GET(TXQ_CNT_L, data[3]), /* BE */
27 FIELD_GET(TXQ_CNT_H, data[2]), /* BK */
28 };
29 u32 pse_ac_data_quota[] = {
30 FIELD_GET(TXQ_CNT_H, data[1]), /* VO */
31 FIELD_GET(TXQ_CNT_L, data[1]), /* VI */
32 FIELD_GET(TXQ_CNT_H, data[0]), /* BE */
33 FIELD_GET(TXQ_CNT_L, data[0]), /* BK */
34 };
35 u32 pse_mcu_quota = FIELD_GET(TXQ_CNT_L, data[2]);
36 u32 pse_data_quota = 0, ple_data_quota = 0;
37 struct mt76_sdio *sdio = &dev->sdio;
38 int i;
39
40 for (i = 0; i < ARRAY_SIZE(pse_ac_data_quota); i++) {
41 pse_data_quota += pse_ac_data_quota[i];
42 ple_data_quota += ple_ac_data_quota[i];
43 }
44
45 if (!pse_data_quota && !ple_data_quota && !pse_mcu_quota)
46 return 0;
47
48 sdio->sched.pse_mcu_quota += pse_mcu_quota;
49 sdio->sched.pse_data_quota += pse_data_quota;
50 sdio->sched.ple_data_quota += ple_data_quota;
51
52 return pse_data_quota + ple_data_quota + pse_mcu_quota;
53 }
54
55 static struct sk_buff *
mt76s_build_rx_skb(void * data,int data_len,int buf_len)56 mt76s_build_rx_skb(void *data, int data_len, int buf_len)
57 {
58 int len = min_t(int, data_len, MT_SKB_HEAD_LEN);
59 struct sk_buff *skb;
60
61 skb = alloc_skb(len, GFP_KERNEL);
62 if (!skb)
63 return NULL;
64
65 skb_put_data(skb, data, len);
66 if (data_len > len) {
67 struct page *page;
68
69 data += len;
70 page = virt_to_head_page(data);
71 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
72 page, data - page_address(page),
73 data_len - len, buf_len);
74 get_page(page);
75 }
76
77 return skb;
78 }
79
80 static int
mt76s_rx_run_queue(struct mt76_dev * dev,enum mt76_rxq_id qid,struct mt76s_intr * intr)81 mt76s_rx_run_queue(struct mt76_dev *dev, enum mt76_rxq_id qid,
82 struct mt76s_intr *intr)
83 {
84 struct mt76_queue *q = &dev->q_rx[qid];
85 struct mt76_sdio *sdio = &dev->sdio;
86 int len = 0, err, i;
87 struct page *page;
88 u8 *buf;
89
90 for (i = 0; i < intr->rx.num[qid]; i++)
91 len += round_up(intr->rx.len[qid][i] + 4, 4);
92
93 if (!len)
94 return 0;
95
96 if (len > sdio->func->cur_blksize)
97 len = roundup(len, sdio->func->cur_blksize);
98
99 page = __dev_alloc_pages(GFP_KERNEL, get_order(len));
100 if (!page)
101 return -ENOMEM;
102
103 buf = page_address(page);
104
105 err = sdio_readsb(sdio->func, buf, MCR_WRDR(qid), len);
106 if (err < 0) {
107 dev_err(dev->dev, "sdio read data failed:%d\n", err);
108 put_page(page);
109 return err;
110 }
111
112 for (i = 0; i < intr->rx.num[qid]; i++) {
113 int index = (q->head + i) % q->ndesc;
114 struct mt76_queue_entry *e = &q->entry[index];
115 __le32 *rxd = (__le32 *)buf;
116
117 /* parse rxd to get the actual packet length */
118 len = FIELD_GET(GENMASK(15, 0), le32_to_cpu(rxd[0]));
119 e->skb = mt76s_build_rx_skb(buf, len, round_up(len + 4, 4));
120 if (!e->skb)
121 break;
122
123 buf += round_up(len + 4, 4);
124 if (q->queued + i + 1 == q->ndesc)
125 break;
126 }
127 put_page(page);
128
129 spin_lock_bh(&q->lock);
130 q->head = (q->head + i) % q->ndesc;
131 q->queued += i;
132 spin_unlock_bh(&q->lock);
133
134 return i;
135 }
136
mt76s_rx_handler(struct mt76_dev * dev)137 static int mt76s_rx_handler(struct mt76_dev *dev)
138 {
139 struct mt76_sdio *sdio = &dev->sdio;
140 struct mt76s_intr intr;
141 int nframes = 0, ret;
142
143 ret = sdio->parse_irq(dev, &intr);
144 if (ret)
145 return ret;
146
147 trace_dev_irq(dev, intr.isr, 0);
148
149 if (intr.isr & WHIER_RX0_DONE_INT_EN) {
150 ret = mt76s_rx_run_queue(dev, 0, &intr);
151 if (ret > 0) {
152 mt76_worker_schedule(&sdio->net_worker);
153 nframes += ret;
154 }
155 }
156
157 if (intr.isr & WHIER_RX1_DONE_INT_EN) {
158 ret = mt76s_rx_run_queue(dev, 1, &intr);
159 if (ret > 0) {
160 mt76_worker_schedule(&sdio->net_worker);
161 nframes += ret;
162 }
163 }
164
165 nframes += !!mt76s_refill_sched_quota(dev, intr.tx.wtqcr);
166
167 return nframes;
168 }
169
170 static int
mt76s_tx_pick_quota(struct mt76_sdio * sdio,bool mcu,int buf_sz,int * pse_size,int * ple_size)171 mt76s_tx_pick_quota(struct mt76_sdio *sdio, bool mcu, int buf_sz,
172 int *pse_size, int *ple_size)
173 {
174 int pse_sz;
175
176 pse_sz = DIV_ROUND_UP(buf_sz + sdio->sched.deficit,
177 sdio->sched.pse_page_size);
178
179 if (mcu && sdio->hw_ver == MT76_CONNAC2_SDIO)
180 pse_sz = 1;
181
182 if (mcu) {
183 if (sdio->sched.pse_mcu_quota < *pse_size + pse_sz)
184 return -EBUSY;
185 } else {
186 if (sdio->sched.pse_data_quota < *pse_size + pse_sz ||
187 sdio->sched.ple_data_quota < *ple_size + 1)
188 return -EBUSY;
189
190 *ple_size = *ple_size + 1;
191 }
192 *pse_size = *pse_size + pse_sz;
193
194 return 0;
195 }
196
197 static void
mt76s_tx_update_quota(struct mt76_sdio * sdio,bool mcu,int pse_size,int ple_size)198 mt76s_tx_update_quota(struct mt76_sdio *sdio, bool mcu, int pse_size,
199 int ple_size)
200 {
201 if (mcu) {
202 sdio->sched.pse_mcu_quota -= pse_size;
203 } else {
204 sdio->sched.pse_data_quota -= pse_size;
205 sdio->sched.ple_data_quota -= ple_size;
206 }
207 }
208
__mt76s_xmit_queue(struct mt76_dev * dev,u8 * data,int len)209 static int __mt76s_xmit_queue(struct mt76_dev *dev, u8 *data, int len)
210 {
211 struct mt76_sdio *sdio = &dev->sdio;
212 int err;
213
214 if (len > sdio->func->cur_blksize)
215 len = roundup(len, sdio->func->cur_blksize);
216
217 err = sdio_writesb(sdio->func, MCR_WTDR1, data, len);
218 if (err)
219 dev_err(dev->dev, "sdio write failed: %d\n", err);
220
221 return err;
222 }
223
mt76s_tx_run_queue(struct mt76_dev * dev,struct mt76_queue * q)224 static int mt76s_tx_run_queue(struct mt76_dev *dev, struct mt76_queue *q)
225 {
226 int qid, err, nframes = 0, len = 0, pse_sz = 0, ple_sz = 0;
227 bool mcu = q == dev->q_mcu[MT_MCUQ_WM];
228 struct mt76_sdio *sdio = &dev->sdio;
229 u8 pad;
230
231 qid = mcu ? ARRAY_SIZE(sdio->xmit_buf) - 1 : q->qid;
232 while (q->first != q->head) {
233 struct mt76_queue_entry *e = &q->entry[q->first];
234 struct sk_buff *iter;
235
236 smp_rmb();
237
238 if (test_bit(MT76_MCU_RESET, &dev->phy.state))
239 goto next;
240
241 if (!test_bit(MT76_STATE_MCU_RUNNING, &dev->phy.state)) {
242 __skb_put_zero(e->skb, 4);
243 err = __mt76s_xmit_queue(dev, e->skb->data,
244 e->skb->len);
245 if (err)
246 return err;
247
248 goto next;
249 }
250
251 pad = roundup(e->skb->len, 4) - e->skb->len;
252 if (len + e->skb->len + pad + 4 > MT76S_XMIT_BUF_SZ)
253 break;
254
255 if (mt76s_tx_pick_quota(sdio, mcu, e->buf_sz, &pse_sz,
256 &ple_sz))
257 break;
258
259 memcpy(sdio->xmit_buf[qid] + len, e->skb->data,
260 skb_headlen(e->skb));
261 len += skb_headlen(e->skb);
262 nframes++;
263
264 skb_walk_frags(e->skb, iter) {
265 memcpy(sdio->xmit_buf[qid] + len, iter->data,
266 iter->len);
267 len += iter->len;
268 nframes++;
269 }
270
271 if (unlikely(pad)) {
272 memset(sdio->xmit_buf[qid] + len, 0, pad);
273 len += pad;
274 }
275 next:
276 q->first = (q->first + 1) % q->ndesc;
277 e->done = true;
278 }
279
280 if (nframes) {
281 memset(sdio->xmit_buf[qid] + len, 0, 4);
282 err = __mt76s_xmit_queue(dev, sdio->xmit_buf[qid], len + 4);
283 if (err)
284 return err;
285 }
286 mt76s_tx_update_quota(sdio, mcu, pse_sz, ple_sz);
287
288 mt76_worker_schedule(&sdio->status_worker);
289
290 return nframes;
291 }
292
mt76s_txrx_worker(struct mt76_sdio * sdio)293 void mt76s_txrx_worker(struct mt76_sdio *sdio)
294 {
295 struct mt76_dev *dev = container_of(sdio, struct mt76_dev, sdio);
296 int i, nframes, ret;
297
298 /* disable interrupt */
299 sdio_claim_host(sdio->func);
300 sdio_writel(sdio->func, WHLPCR_INT_EN_CLR, MCR_WHLPCR, NULL);
301
302 do {
303 nframes = 0;
304
305 /* tx */
306 for (i = 0; i <= MT_TXQ_PSD; i++) {
307 ret = mt76s_tx_run_queue(dev, dev->phy.q_tx[i]);
308 if (ret > 0)
309 nframes += ret;
310 }
311 ret = mt76s_tx_run_queue(dev, dev->q_mcu[MT_MCUQ_WM]);
312 if (ret > 0)
313 nframes += ret;
314
315 /* rx */
316 ret = mt76s_rx_handler(dev);
317 if (ret > 0)
318 nframes += ret;
319
320 if (test_bit(MT76_MCU_RESET, &dev->phy.state)) {
321 if (!mt76s_txqs_empty(dev))
322 continue;
323 else
324 wake_up(&sdio->wait);
325 }
326 } while (nframes > 0);
327
328 /* enable interrupt */
329 sdio_writel(sdio->func, WHLPCR_INT_EN_SET, MCR_WHLPCR, NULL);
330 sdio_release_host(sdio->func);
331 }
332 EXPORT_SYMBOL_GPL(mt76s_txrx_worker);
333
mt76s_sdio_irq(struct sdio_func * func)334 void mt76s_sdio_irq(struct sdio_func *func)
335 {
336 struct mt76_dev *dev = sdio_get_drvdata(func);
337 struct mt76_sdio *sdio = &dev->sdio;
338
339 if (!test_bit(MT76_STATE_INITIALIZED, &dev->phy.state) ||
340 test_bit(MT76_MCU_RESET, &dev->phy.state))
341 return;
342
343 mt76_worker_schedule(&sdio->txrx_worker);
344 }
345 EXPORT_SYMBOL_GPL(mt76s_sdio_irq);
346
mt76s_txqs_empty(struct mt76_dev * dev)347 bool mt76s_txqs_empty(struct mt76_dev *dev)
348 {
349 struct mt76_queue *q;
350 int i;
351
352 for (i = 0; i <= MT_TXQ_PSD + 1; i++) {
353 if (i <= MT_TXQ_PSD)
354 q = dev->phy.q_tx[i];
355 else
356 q = dev->q_mcu[MT_MCUQ_WM];
357
358 if (q->first != q->head)
359 return false;
360 }
361
362 return true;
363 }
364 EXPORT_SYMBOL_GPL(mt76s_txqs_empty);
365