1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * MediaTek High-speed UART driver
4 *
5 * Copyright (C) 2018 MediaTek Inc.
6 * Author: Weijie Gao <weijie.gao@mediatek.com>
7 */
8
9 #include <clk.h>
10 #include <common.h>
11 #include <div64.h>
12 #include <dm.h>
13 #include <errno.h>
14 #include <log.h>
15 #include <serial.h>
16 #include <watchdog.h>
17 #include <asm/global_data.h>
18 #include <asm/io.h>
19 #include <asm/types.h>
20 #include <linux/err.h>
21
22 struct mtk_serial_regs {
23 u32 rbr;
24 u32 ier;
25 u32 fcr;
26 u32 lcr;
27 u32 mcr;
28 u32 lsr;
29 u32 msr;
30 u32 spr;
31 u32 mdr1;
32 u32 highspeed;
33 u32 sample_count;
34 u32 sample_point;
35 u32 fracdiv_l;
36 u32 fracdiv_m;
37 u32 escape_en;
38 u32 guard;
39 u32 rx_sel;
40 };
41
42 #define thr rbr
43 #define iir fcr
44 #define dll rbr
45 #define dlm ier
46
47 #define UART_LCR_WLS_8 0x03 /* 8 bit character length */
48 #define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
49
50 #define UART_LSR_DR 0x01 /* Data ready */
51 #define UART_LSR_THRE 0x20 /* Xmit holding register empty */
52 #define UART_LSR_TEMT 0x40 /* Xmitter empty */
53
54 #define UART_MCR_DTR 0x01 /* DTR */
55 #define UART_MCR_RTS 0x02 /* RTS */
56
57 #define UART_FCR_FIFO_EN 0x01 /* Fifo enable */
58 #define UART_FCR_RXSR 0x02 /* Receiver soft reset */
59 #define UART_FCR_TXSR 0x04 /* Transmitter soft reset */
60
61 #define UART_MCRVAL (UART_MCR_DTR | \
62 UART_MCR_RTS)
63
64 /* Clear & enable FIFOs */
65 #define UART_FCRVAL (UART_FCR_FIFO_EN | \
66 UART_FCR_RXSR | \
67 UART_FCR_TXSR)
68
69 /* the data is correct if the real baud is within 3%. */
70 #define BAUD_ALLOW_MAX(baud) ((baud) + (baud) * 3 / 100)
71 #define BAUD_ALLOW_MIX(baud) ((baud) - (baud) * 3 / 100)
72
73 struct mtk_serial_priv {
74 struct mtk_serial_regs __iomem *regs;
75 u32 clock;
76 };
77
_mtk_serial_setbrg(struct mtk_serial_priv * priv,int baud)78 static void _mtk_serial_setbrg(struct mtk_serial_priv *priv, int baud)
79 {
80 bool support_clk12m_baud115200;
81 u32 quot, samplecount, realbaud;
82
83 if ((baud <= 115200) && (priv->clock == 12000000))
84 support_clk12m_baud115200 = true;
85 else
86 support_clk12m_baud115200 = false;
87
88 if (baud <= 115200) {
89 writel(0, &priv->regs->highspeed);
90 quot = DIV_ROUND_CLOSEST(priv->clock, 16 * baud);
91
92 if (support_clk12m_baud115200) {
93 writel(3, &priv->regs->highspeed);
94 quot = DIV_ROUND_CLOSEST(priv->clock, 256 * baud);
95 if (quot == 0)
96 quot = 1;
97
98 samplecount = DIV_ROUND_CLOSEST(priv->clock,
99 quot * baud);
100 if (samplecount != 0) {
101 realbaud = priv->clock / samplecount / quot;
102 if ((realbaud > BAUD_ALLOW_MAX(baud)) ||
103 (realbaud < BAUD_ALLOW_MIX(baud))) {
104 pr_info("baud %d can't be handled\n",
105 baud);
106 }
107 } else {
108 pr_info("samplecount is 0\n");
109 }
110 }
111 } else if (baud <= 576000) {
112 writel(2, &priv->regs->highspeed);
113
114 /* Set to next lower baudrate supported */
115 if ((baud == 500000) || (baud == 576000))
116 baud = 460800;
117 quot = DIV_ROUND_UP(priv->clock, 4 * baud);
118 } else {
119 writel(3, &priv->regs->highspeed);
120 quot = DIV_ROUND_UP(priv->clock, 256 * baud);
121 }
122
123 /* set divisor */
124 writel(UART_LCR_WLS_8 | UART_LCR_DLAB, &priv->regs->lcr);
125 writel(quot & 0xff, &priv->regs->dll);
126 writel((quot >> 8) & 0xff, &priv->regs->dlm);
127 writel(UART_LCR_WLS_8, &priv->regs->lcr);
128
129 if (baud > 460800) {
130 u32 tmp;
131
132 tmp = DIV_ROUND_CLOSEST(priv->clock, quot * baud);
133 writel(tmp - 1, &priv->regs->sample_count);
134 writel((tmp - 2) >> 1, &priv->regs->sample_point);
135 } else {
136 writel(0, &priv->regs->sample_count);
137 writel(0xff, &priv->regs->sample_point);
138 }
139
140 if (support_clk12m_baud115200) {
141 writel(samplecount - 1, &priv->regs->sample_count);
142 writel((samplecount - 2) >> 1, &priv->regs->sample_point);
143 }
144 }
145
_mtk_serial_putc(struct mtk_serial_priv * priv,const char ch)146 static int _mtk_serial_putc(struct mtk_serial_priv *priv, const char ch)
147 {
148 if (!(readl(&priv->regs->lsr) & UART_LSR_THRE))
149 return -EAGAIN;
150
151 writel(ch, &priv->regs->thr);
152
153 if (ch == '\n')
154 WATCHDOG_RESET();
155
156 return 0;
157 }
158
_mtk_serial_getc(struct mtk_serial_priv * priv)159 static int _mtk_serial_getc(struct mtk_serial_priv *priv)
160 {
161 if (!(readl(&priv->regs->lsr) & UART_LSR_DR))
162 return -EAGAIN;
163
164 return readl(&priv->regs->rbr);
165 }
166
_mtk_serial_pending(struct mtk_serial_priv * priv,bool input)167 static int _mtk_serial_pending(struct mtk_serial_priv *priv, bool input)
168 {
169 if (input)
170 return (readl(&priv->regs->lsr) & UART_LSR_DR) ? 1 : 0;
171 else
172 return (readl(&priv->regs->lsr) & UART_LSR_THRE) ? 0 : 1;
173 }
174
175 #if defined(CONFIG_DM_SERIAL) && \
176 (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_DM))
mtk_serial_setbrg(struct udevice * dev,int baudrate)177 static int mtk_serial_setbrg(struct udevice *dev, int baudrate)
178 {
179 struct mtk_serial_priv *priv = dev_get_priv(dev);
180
181 _mtk_serial_setbrg(priv, baudrate);
182
183 return 0;
184 }
185
mtk_serial_putc(struct udevice * dev,const char ch)186 static int mtk_serial_putc(struct udevice *dev, const char ch)
187 {
188 struct mtk_serial_priv *priv = dev_get_priv(dev);
189
190 return _mtk_serial_putc(priv, ch);
191 }
192
mtk_serial_getc(struct udevice * dev)193 static int mtk_serial_getc(struct udevice *dev)
194 {
195 struct mtk_serial_priv *priv = dev_get_priv(dev);
196
197 return _mtk_serial_getc(priv);
198 }
199
mtk_serial_pending(struct udevice * dev,bool input)200 static int mtk_serial_pending(struct udevice *dev, bool input)
201 {
202 struct mtk_serial_priv *priv = dev_get_priv(dev);
203
204 return _mtk_serial_pending(priv, input);
205 }
206
mtk_serial_probe(struct udevice * dev)207 static int mtk_serial_probe(struct udevice *dev)
208 {
209 struct mtk_serial_priv *priv = dev_get_priv(dev);
210
211 /* Disable interrupt */
212 writel(0, &priv->regs->ier);
213
214 writel(UART_MCRVAL, &priv->regs->mcr);
215 writel(UART_FCRVAL, &priv->regs->fcr);
216
217 return 0;
218 }
219
mtk_serial_of_to_plat(struct udevice * dev)220 static int mtk_serial_of_to_plat(struct udevice *dev)
221 {
222 struct mtk_serial_priv *priv = dev_get_priv(dev);
223 fdt_addr_t addr;
224 struct clk clk;
225 int err;
226
227 addr = dev_read_addr(dev);
228 if (addr == FDT_ADDR_T_NONE)
229 return -EINVAL;
230
231 priv->regs = map_physmem(addr, 0, MAP_NOCACHE);
232
233 err = clk_get_by_index(dev, 0, &clk);
234 if (!err) {
235 err = clk_get_rate(&clk);
236 if (!IS_ERR_VALUE(err))
237 priv->clock = err;
238 } else if (err != -ENOENT && err != -ENODEV && err != -ENOSYS) {
239 debug("mtk_serial: failed to get clock\n");
240 return err;
241 }
242
243 if (!priv->clock)
244 priv->clock = dev_read_u32_default(dev, "clock-frequency", 0);
245
246 if (!priv->clock) {
247 debug("mtk_serial: clock not defined\n");
248 return -EINVAL;
249 }
250
251 return 0;
252 }
253
254 static const struct dm_serial_ops mtk_serial_ops = {
255 .putc = mtk_serial_putc,
256 .pending = mtk_serial_pending,
257 .getc = mtk_serial_getc,
258 .setbrg = mtk_serial_setbrg,
259 };
260
261 static const struct udevice_id mtk_serial_ids[] = {
262 { .compatible = "mediatek,hsuart" },
263 { .compatible = "mediatek,mt6577-uart" },
264 { }
265 };
266
267 U_BOOT_DRIVER(serial_mtk) = {
268 .name = "serial_mtk",
269 .id = UCLASS_SERIAL,
270 .of_match = mtk_serial_ids,
271 .of_to_plat = mtk_serial_of_to_plat,
272 .priv_auto = sizeof(struct mtk_serial_priv),
273 .probe = mtk_serial_probe,
274 .ops = &mtk_serial_ops,
275 .flags = DM_FLAG_PRE_RELOC,
276 };
277 #else
278
279 DECLARE_GLOBAL_DATA_PTR;
280
281 #define DECLARE_HSUART_PRIV(port) \
282 static struct mtk_serial_priv mtk_hsuart##port = { \
283 .regs = (struct mtk_serial_regs *)CONFIG_SYS_NS16550_COM##port, \
284 .clock = CONFIG_SYS_NS16550_CLK \
285 };
286
287 #define DECLARE_HSUART_FUNCTIONS(port) \
288 static int mtk_serial##port##_init(void) \
289 { \
290 writel(0, &mtk_hsuart##port.regs->ier); \
291 writel(UART_MCRVAL, &mtk_hsuart##port.regs->mcr); \
292 writel(UART_FCRVAL, &mtk_hsuart##port.regs->fcr); \
293 _mtk_serial_setbrg(&mtk_hsuart##port, gd->baudrate); \
294 return 0 ; \
295 } \
296 static void mtk_serial##port##_setbrg(void) \
297 { \
298 _mtk_serial_setbrg(&mtk_hsuart##port, gd->baudrate); \
299 } \
300 static int mtk_serial##port##_getc(void) \
301 { \
302 int err; \
303 do { \
304 err = _mtk_serial_getc(&mtk_hsuart##port); \
305 if (err == -EAGAIN) \
306 WATCHDOG_RESET(); \
307 } while (err == -EAGAIN); \
308 return err >= 0 ? err : 0; \
309 } \
310 static int mtk_serial##port##_tstc(void) \
311 { \
312 return _mtk_serial_pending(&mtk_hsuart##port, true); \
313 } \
314 static void mtk_serial##port##_putc(const char c) \
315 { \
316 int err; \
317 if (c == '\n') \
318 mtk_serial##port##_putc('\r'); \
319 do { \
320 err = _mtk_serial_putc(&mtk_hsuart##port, c); \
321 } while (err == -EAGAIN); \
322 } \
323 static void mtk_serial##port##_puts(const char *s) \
324 { \
325 while (*s) { \
326 mtk_serial##port##_putc(*s++); \
327 } \
328 }
329
330 /* Serial device descriptor */
331 #define INIT_HSUART_STRUCTURE(port, __name) { \
332 .name = __name, \
333 .start = mtk_serial##port##_init, \
334 .stop = NULL, \
335 .setbrg = mtk_serial##port##_setbrg, \
336 .getc = mtk_serial##port##_getc, \
337 .tstc = mtk_serial##port##_tstc, \
338 .putc = mtk_serial##port##_putc, \
339 .puts = mtk_serial##port##_puts, \
340 }
341
342 #define DECLARE_HSUART(port, __name) \
343 DECLARE_HSUART_PRIV(port); \
344 DECLARE_HSUART_FUNCTIONS(port); \
345 struct serial_device mtk_hsuart##port##_device = \
346 INIT_HSUART_STRUCTURE(port, __name);
347
348 #if !defined(CONFIG_CONS_INDEX)
349 #elif (CONFIG_CONS_INDEX < 1) || (CONFIG_CONS_INDEX > 6)
350 #error "Invalid console index value."
351 #endif
352
353 #if CONFIG_CONS_INDEX == 1 && !defined(CONFIG_SYS_NS16550_COM1)
354 #error "Console port 1 defined but not configured."
355 #elif CONFIG_CONS_INDEX == 2 && !defined(CONFIG_SYS_NS16550_COM2)
356 #error "Console port 2 defined but not configured."
357 #elif CONFIG_CONS_INDEX == 3 && !defined(CONFIG_SYS_NS16550_COM3)
358 #error "Console port 3 defined but not configured."
359 #elif CONFIG_CONS_INDEX == 4 && !defined(CONFIG_SYS_NS16550_COM4)
360 #error "Console port 4 defined but not configured."
361 #elif CONFIG_CONS_INDEX == 5 && !defined(CONFIG_SYS_NS16550_COM5)
362 #error "Console port 5 defined but not configured."
363 #elif CONFIG_CONS_INDEX == 6 && !defined(CONFIG_SYS_NS16550_COM6)
364 #error "Console port 6 defined but not configured."
365 #endif
366
367 #if defined(CONFIG_SYS_NS16550_COM1)
368 DECLARE_HSUART(1, "mtk-hsuart0");
369 #endif
370 #if defined(CONFIG_SYS_NS16550_COM2)
371 DECLARE_HSUART(2, "mtk-hsuart1");
372 #endif
373 #if defined(CONFIG_SYS_NS16550_COM3)
374 DECLARE_HSUART(3, "mtk-hsuart2");
375 #endif
376 #if defined(CONFIG_SYS_NS16550_COM4)
377 DECLARE_HSUART(4, "mtk-hsuart3");
378 #endif
379 #if defined(CONFIG_SYS_NS16550_COM5)
380 DECLARE_HSUART(5, "mtk-hsuart4");
381 #endif
382 #if defined(CONFIG_SYS_NS16550_COM6)
383 DECLARE_HSUART(6, "mtk-hsuart5");
384 #endif
385
default_serial_console(void)386 __weak struct serial_device *default_serial_console(void)
387 {
388 #if CONFIG_CONS_INDEX == 1
389 return &mtk_hsuart1_device;
390 #elif CONFIG_CONS_INDEX == 2
391 return &mtk_hsuart2_device;
392 #elif CONFIG_CONS_INDEX == 3
393 return &mtk_hsuart3_device;
394 #elif CONFIG_CONS_INDEX == 4
395 return &mtk_hsuart4_device;
396 #elif CONFIG_CONS_INDEX == 5
397 return &mtk_hsuart5_device;
398 #elif CONFIG_CONS_INDEX == 6
399 return &mtk_hsuart6_device;
400 #else
401 #error "Bad CONFIG_CONS_INDEX."
402 #endif
403 }
404
mtk_serial_initialize(void)405 void mtk_serial_initialize(void)
406 {
407 #if defined(CONFIG_SYS_NS16550_COM1)
408 serial_register(&mtk_hsuart1_device);
409 #endif
410 #if defined(CONFIG_SYS_NS16550_COM2)
411 serial_register(&mtk_hsuart2_device);
412 #endif
413 #if defined(CONFIG_SYS_NS16550_COM3)
414 serial_register(&mtk_hsuart3_device);
415 #endif
416 #if defined(CONFIG_SYS_NS16550_COM4)
417 serial_register(&mtk_hsuart4_device);
418 #endif
419 #if defined(CONFIG_SYS_NS16550_COM5)
420 serial_register(&mtk_hsuart5_device);
421 #endif
422 #if defined(CONFIG_SYS_NS16550_COM6)
423 serial_register(&mtk_hsuart6_device);
424 #endif
425 }
426
427 #endif
428
429 #ifdef CONFIG_DEBUG_UART_MTK
430
431 #include <debug_uart.h>
432
_debug_uart_init(void)433 static inline void _debug_uart_init(void)
434 {
435 struct mtk_serial_priv priv;
436
437 priv.regs = (void *) CONFIG_DEBUG_UART_BASE;
438 priv.clock = CONFIG_DEBUG_UART_CLOCK;
439
440 writel(0, &priv.regs->ier);
441 writel(UART_MCRVAL, &priv.regs->mcr);
442 writel(UART_FCRVAL, &priv.regs->fcr);
443
444 _mtk_serial_setbrg(&priv, CONFIG_BAUDRATE);
445 }
446
_debug_uart_putc(int ch)447 static inline void _debug_uart_putc(int ch)
448 {
449 struct mtk_serial_regs __iomem *regs =
450 (void *) CONFIG_DEBUG_UART_BASE;
451
452 while (!(readl(®s->lsr) & UART_LSR_THRE))
453 ;
454
455 writel(ch, ®s->thr);
456 }
457
458 DEBUG_UART_FUNCS
459
460 #endif
461