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Searched defs:parent_rate (Results 1 – 25 of 33) sorted by relevance

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/u-boot/drivers/clk/imx/
A Dclk-pllv3.c48 unsigned long parent_rate = clk_get_parent_rate(clk); in clk_pllv3_generic_get_rate() local
58 unsigned long parent_rate = clk_get_parent_rate(clk); in clk_pllv3_generic_set_rate() local
126 unsigned long parent_rate = clk_get_parent_rate(clk); in clk_pllv3_sys_get_rate() local
135 unsigned long parent_rate = clk_get_parent_rate(clk); in clk_pllv3_sys_set_rate() local
172 unsigned long parent_rate = clk_get_parent_rate(clk); in clk_pllv3_av_get_rate() local
190 unsigned long parent_rate = clk_get_parent_rate(clk); in clk_pllv3_av_set_rate() local
A Dclk-composite-8m.c37 ulong parent_rate = clk_get_parent_rate(&composite->clk); in imx8m_clk_composite_divider_recalc_rate() local
59 unsigned long parent_rate, in imx8m_clk_composite_compute_dividers()
93 ulong parent_rate = clk_get_parent_rate(&composite->clk); in imx8m_clk_composite_divider_set_rate() local
A Dclk-pfd.c47 unsigned long parent_rate = clk_get_parent_rate(clk); in clk_pfd_recalc_rate() local
60 unsigned long parent_rate = clk_get_parent_rate(clk); in clk_pfd_set_rate() local
/u-boot/drivers/clk/ti/
A Dclk-divider.c71 static int _div_round_up(const struct clk_div_table *table, ulong parent_rate, in _div_round_up()
91 static int _div_round(const struct clk_div_table *table, ulong parent_rate, in _div_round()
104 ulong parent_rate, parent_round_rate, max_div; in clk_ti_divider_best_div() local
174 ulong parent_rate; in clk_ti_divider_round_rate() local
187 ulong parent_rate; in clk_ti_divider_set_rate() local
215 ulong rate, parent_rate; in clk_ti_divider_get_rate() local
/u-boot/drivers/clk/analogbits/
A Dwrpll-cln28hpc.c184 unsigned long parent_rate) in __wrpll_update_parent_rate()
222 unsigned long parent_rate) in wrpll_configure_for_rate()
331 unsigned long parent_rate) in wrpll_calc_output_rate()
/u-boot/drivers/clk/rockchip/
A Dclk_rv1108.c312 ulong parent_rate = rkclk_pll_get_rate(cru, CLK_GENERAL); in rv1108_aclk_bus_get_clk() local
324 ulong parent_rate = rkclk_pll_get_rate(cru, CLK_GENERAL); in rv1108_aclk_bus_set_clk() local
340 ulong parent_rate = rkclk_pll_get_rate(cru, CLK_GENERAL); in rv1108_aclk_peri_get_clk() local
352 ulong parent_rate = rkclk_pll_get_rate(cru, CLK_GENERAL); in rv1108_hclk_peri_get_clk() local
364 ulong parent_rate = rkclk_pll_get_rate(cru, CLK_GENERAL); in rv1108_pclk_peri_get_clk() local
376 ulong parent_rate = rkclk_pll_get_rate(cru, CLK_GENERAL); in rv1108_aclk_peri_set_clk() local
392 ulong parent_rate = rkclk_pll_get_rate(cru, CLK_GENERAL); in rv1108_hclk_peri_set_clk() local
407 ulong parent_rate = rkclk_pll_get_rate(cru, CLK_GENERAL); in rv1108_pclk_peri_set_clk() local
/u-boot/drivers/clk/
A Dclk-divider.c56 unsigned long divider_recalc_rate(struct clk *hw, unsigned long parent_rate, in divider_recalc_rate()
77 unsigned long parent_rate = clk_get_parent_rate(clk); in clk_divider_recalc_rate() local
137 int divider_get_val(unsigned long rate, unsigned long parent_rate, in divider_get_val()
156 unsigned long parent_rate = clk_get_parent_rate(clk); in clk_divider_set_rate() local
A Dclk-cdce9xx.c172 u32 parent_rate; in cdce9xx_clk_get_rate() local
184 u32 parent_rate; in cdce9xx_clk_set_rate() local
A Dclk_sandbox_ccf.c46 unsigned long parent_rate = clk_get_parent_rate(clk); in clk_pllv3_get_rate() local
154 ulong parent_rate = clk_get_parent_rate(&composite->clk); in sandbox_clk_composite_divider_recalc_rate() local
A Dclk-fixed-factor.c24 unsigned long parent_rate = clk_get_parent_rate(clk); in clk_factor_recalc_rate() local
A Dclk-hsdk-cgu.c258 const u32 parent_rate; member
429 u32 parent_rate = clk->curr_domain.pll->parent_rate; in pll_get() local
564 ulong parent_rate = pll_get(sclk); in idiv_get() local
654 ulong parent_rate = pll_get(sclk); in idiv_set() local
A Dclk_pic32.c174 int parent_rate, int rate, int parent_id) in pic32_set_refclk()
235 u32 rodiv, rotrim, rosel, v, parent_rate; in pic32_get_refclk() local
/u-boot/drivers/clk/meson/
A Daxg.c86 unsigned long parent_rate; in meson_clk81_get_rate() local
120 static long mpll_rate_from_params(unsigned long parent_rate, in mpll_rate_from_params()
158 unsigned long parent_rate; in meson_mpll_get_rate() local
A Dgxbb.c274 unsigned int rate, parent_rate; in meson_div_get_rate() local
323 unsigned long parent_rate; in meson_div_set_rate() local
573 unsigned long parent_rate; in meson_clk81_get_rate() local
608 static long mpll_rate_from_params(unsigned long parent_rate, in mpll_rate_from_params()
646 unsigned long parent_rate; in meson_mpll_get_rate() local
A Dg12a.c239 unsigned int rate, parent_rate; in meson_div_get_rate() local
292 unsigned long parent_rate; in meson_div_set_rate() local
571 unsigned long parent_rate; in meson_clk81_get_rate() local
602 static long mpll_rate_from_params(unsigned long parent_rate, in mpll_rate_from_params()
640 unsigned long parent_rate; in meson_mpll_get_rate() local
/u-boot/drivers/clk/at91/
A Dclk-sam9x60-pll.c60 ulong parent_rate) in sam9x60_frac_pll_compute_mul_frac()
99 ulong parent_rate = clk_get_parent_rate(clk); in sam9x60_frac_pll_set_rate() local
144 ulong parent_rate = clk_get_parent_rate(clk); in sam9x60_frac_pll_get_rate() local
308 ulong parent_rate = clk_get_parent_rate(clk); in sam9x60_div_pll_set_rate() local
347 ulong parent_rate = clk_get_parent_rate(clk); in sam9x60_div_pll_get_rate() local
A Dclk-utmi.c55 ulong parent_rate = clk_get_parent_rate(clk); in clk_utmi_enable() local
171 ulong parent_rate = clk_get_parent_rate(clk); in clk_utmi_sama7g5_enable() local
A Dclk-generic.c91 ulong parent_rate = clk_get_parent_rate(clk); in clk_gck_set_rate() local
117 ulong parent_rate = clk_get_parent_rate(clk); in clk_gck_get_rate() local
A Dclk-programmable.c43 ulong rate, parent_rate = clk_get_parent_rate(clk); in clk_programmable_get_rate() local
92 ulong parent_rate = clk_get_parent_rate(clk); in clk_programmable_set_rate() local
A Dclk-peripheral.c158 ulong parent_rate = clk_get_parent_rate(clk); in clk_sam9x5_peripheral_get_rate() local
175 ulong parent_rate = clk_get_parent_rate(clk); in clk_sam9x5_peripheral_set_rate() local
A Dclk-master.c210 ulong parent_rate = clk_get_parent_rate(clk); in clk_sama7g5_master_set_rate() local
239 ulong parent_rate = clk_get_parent_rate(clk); in clk_sama7g5_master_get_rate() local
/u-boot/arch/arm/mach-tegra/
A Dclock.c248 static int clk_get_divider(unsigned divider_bits, unsigned long parent_rate, in clk_get_divider()
302 static unsigned long get_rate_from_divider(unsigned long parent_rate, in get_rate_from_divider()
316 unsigned parent_rate = pll_rate[parent]; in clock_get_periph_rate() local
371 static int find_best_divider(unsigned divider_bits, unsigned long parent_rate, in find_best_divider()
531 unsigned int __weak clk_m_get_rate(unsigned int parent_rate) in clk_m_get_rate()
540 u64 parent_rate, rate; in clock_get_rate() local
/u-boot/drivers/clk/sifive/
A Dfu540-prci.c436 unsigned long parent_rate) in sifive_fu540_prci_wrpll_recalc_rate()
446 unsigned long *parent_rate) in sifive_fu540_prci_wrpll_round_rate()
460 unsigned long parent_rate) in sifive_fu540_prci_wrpll_set_rate()
516 unsigned long parent_rate) in sifive_fu540_prci_tlclksel_recalc_rate()
671 ulong parent_rate; in sifive_fu540_prci_parent_rate() local
/u-boot/include/linux/clk/
A Danalogbits-wrpll-cln28hpc.h66 unsigned long parent_rate; member
/u-boot/drivers/clk/uniphier/
A Dclk-uniphier-core.c185 unsigned long parent_rate; in __uniphier_clk_set_rate() local

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