1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (C) 2018 MediaTek Inc. 4 * Author: Ryder Lee <ryder.lee@mediatek.com> 5 */ 6 7 #ifndef __DRV_CLK_MTK_H 8 #define __DRV_CLK_MTK_H 9 10 #include <linux/bitops.h> 11 #define CLK_XTAL 0 12 #define MHZ (1000 * 1000) 13 14 #define HAVE_RST_BAR BIT(0) 15 #define CLK_DOMAIN_SCPSYS BIT(0) 16 #define CLK_MUX_SETCLR_UPD BIT(1) 17 18 #define CLK_GATE_SETCLR BIT(0) 19 #define CLK_GATE_SETCLR_INV BIT(1) 20 #define CLK_GATE_NO_SETCLR BIT(2) 21 #define CLK_GATE_NO_SETCLR_INV BIT(3) 22 #define CLK_GATE_MASK GENMASK(3, 0) 23 24 #define CLK_PARENT_APMIXED BIT(4) 25 #define CLK_PARENT_TOPCKGEN BIT(5) 26 #define CLK_PARENT_MASK GENMASK(5, 4) 27 28 #define ETHSYS_HIFSYS_RST_CTRL_OFS 0x34 29 30 /* struct mtk_pll_data - hardware-specific PLLs data */ 31 struct mtk_pll_data { 32 const int id; 33 u32 reg; 34 u32 pwr_reg; 35 u32 en_mask; 36 u32 pd_reg; 37 int pd_shift; 38 u32 flags; 39 u32 rst_bar_mask; 40 u64 fmax; 41 u64 fmin; 42 int pcwbits; 43 int pcwibits; 44 u32 pcw_reg; 45 int pcw_shift; 46 u32 pcw_chg_reg; 47 }; 48 49 /** 50 * struct mtk_fixed_clk - fixed clocks 51 * 52 * @id: index of clocks 53 * @parent: index of parnet clocks 54 * @rate: fixed rate 55 */ 56 struct mtk_fixed_clk { 57 const int id; 58 const int parent; 59 unsigned long rate; 60 }; 61 62 #define FIXED_CLK(_id, _parent, _rate) { \ 63 .id = _id, \ 64 .parent = _parent, \ 65 .rate = _rate, \ 66 } 67 68 /** 69 * struct mtk_fixed_factor - fixed multiplier and divider clocks 70 * 71 * @id: index of clocks 72 * @parent: index of parnet clocks 73 * @mult: multiplier 74 * @div: divider 75 * @flag: hardware-specific flags 76 */ 77 struct mtk_fixed_factor { 78 const int id; 79 const int parent; 80 u32 mult; 81 u32 div; 82 u32 flags; 83 }; 84 85 #define FACTOR(_id, _parent, _mult, _div, _flags) { \ 86 .id = _id, \ 87 .parent = _parent, \ 88 .mult = _mult, \ 89 .div = _div, \ 90 .flags = _flags, \ 91 } 92 93 /** 94 * struct mtk_composite - aggregate clock of mux, divider and gate clocks 95 * 96 * @id: index of clocks 97 * @parent: index of parnet clocks 98 * @mux_reg: hardware-specific mux register 99 * @gate_reg: hardware-specific gate register 100 * @mux_mask: mask to the mux bit field 101 * @mux_shift: shift to the mux bit field 102 * @gate_shift: shift to the gate bit field 103 * @num_parents: number of parent clocks 104 * @flags: hardware-specific flags 105 */ 106 struct mtk_composite { 107 const int id; 108 const int *parent; 109 u32 mux_reg; 110 u32 mux_set_reg; 111 u32 mux_clr_reg; 112 u32 upd_reg; 113 u32 gate_reg; 114 u32 mux_mask; 115 signed char mux_shift; 116 signed char upd_shift; 117 signed char gate_shift; 118 signed char num_parents; 119 u16 flags; 120 }; 121 122 #define MUX_GATE_FLAGS(_id, _parents, _reg, _shift, _width, _gate, \ 123 _flags) { \ 124 .id = _id, \ 125 .mux_reg = _reg, \ 126 .mux_shift = _shift, \ 127 .mux_mask = BIT(_width) - 1, \ 128 .gate_reg = _reg, \ 129 .gate_shift = _gate, \ 130 .parent = _parents, \ 131 .num_parents = ARRAY_SIZE(_parents), \ 132 .flags = _flags, \ 133 } 134 135 #define MUX_GATE(_id, _parents, _reg, _shift, _width, _gate) \ 136 MUX_GATE_FLAGS(_id, _parents, _reg, _shift, _width, _gate, 0) 137 138 #define MUX(_id, _parents, _reg, _shift, _width) { \ 139 .id = _id, \ 140 .mux_reg = _reg, \ 141 .mux_shift = _shift, \ 142 .mux_mask = BIT(_width) - 1, \ 143 .gate_shift = -1, \ 144 .parent = _parents, \ 145 .num_parents = ARRAY_SIZE(_parents), \ 146 .flags = 0, \ 147 } 148 149 #define MUX_CLR_SET_UPD_FLAGS(_id, _parents, _mux_ofs, _mux_set_ofs,\ 150 _mux_clr_ofs, _shift, _width, _gate, \ 151 _upd_ofs, _upd, _flags) { \ 152 .id = _id, \ 153 .mux_reg = _mux_ofs, \ 154 .mux_set_reg = _mux_set_ofs, \ 155 .mux_clr_reg = _mux_clr_ofs, \ 156 .upd_reg = _upd_ofs, \ 157 .upd_shift = _upd, \ 158 .mux_shift = _shift, \ 159 .mux_mask = BIT(_width) - 1, \ 160 .gate_reg = _mux_ofs, \ 161 .gate_shift = _gate, \ 162 .parent = _parents, \ 163 .num_parents = ARRAY_SIZE(_parents), \ 164 .flags = _flags, \ 165 } 166 167 struct mtk_gate_regs { 168 u32 sta_ofs; 169 u32 clr_ofs; 170 u32 set_ofs; 171 }; 172 173 /** 174 * struct mtk_gate - gate clocks 175 * 176 * @id: index of gate clocks 177 * @parent: index of parnet clocks 178 * @regs: hardware-specific mux register 179 * @shift: shift to the gate bit field 180 * @flags: hardware-specific flags 181 */ 182 struct mtk_gate { 183 const int id; 184 const int parent; 185 const struct mtk_gate_regs *regs; 186 int shift; 187 u32 flags; 188 }; 189 190 /* struct mtk_clk_tree - clock tree */ 191 struct mtk_clk_tree { 192 unsigned long xtal_rate; 193 unsigned long xtal2_rate; 194 const int fdivs_offs; 195 const int muxes_offs; 196 const struct mtk_pll_data *plls; 197 const struct mtk_fixed_clk *fclks; 198 const struct mtk_fixed_factor *fdivs; 199 const struct mtk_composite *muxes; 200 }; 201 202 struct mtk_clk_priv { 203 void __iomem *base; 204 const struct mtk_clk_tree *tree; 205 }; 206 207 struct mtk_cg_priv { 208 void __iomem *base; 209 const struct mtk_clk_tree *tree; 210 const struct mtk_gate *gates; 211 }; 212 213 extern const struct clk_ops mtk_clk_apmixedsys_ops; 214 extern const struct clk_ops mtk_clk_topckgen_ops; 215 extern const struct clk_ops mtk_clk_gate_ops; 216 217 int mtk_common_clk_init(struct udevice *dev, 218 const struct mtk_clk_tree *tree); 219 int mtk_common_clk_gate_init(struct udevice *dev, 220 const struct mtk_clk_tree *tree, 221 const struct mtk_gate *gates); 222 223 #endif /* __DRV_CLK_MTK_H */ 224