1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */
2 /*
3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
4 */
5
6 #ifndef ATH11K_HW_H
7 #define ATH11K_HW_H
8
9 #include "hal.h"
10 #include "wmi.h"
11
12 /* Target configuration defines */
13
14 /* Num VDEVS per radio */
15 #define TARGET_NUM_VDEVS (16 + 1)
16
17 #define TARGET_NUM_PEERS_PDEV (512 + TARGET_NUM_VDEVS)
18
19 /* Num of peers for Single Radio mode */
20 #define TARGET_NUM_PEERS_SINGLE (TARGET_NUM_PEERS_PDEV)
21
22 /* Num of peers for DBS */
23 #define TARGET_NUM_PEERS_DBS (2 * TARGET_NUM_PEERS_PDEV)
24
25 /* Num of peers for DBS_SBS */
26 #define TARGET_NUM_PEERS_DBS_SBS (3 * TARGET_NUM_PEERS_PDEV)
27
28 /* Max num of stations (per radio) */
29 #define TARGET_NUM_STATIONS 512
30
31 #define TARGET_NUM_PEERS(x) TARGET_NUM_PEERS_##x
32 #define TARGET_NUM_PEER_KEYS 2
33 #define TARGET_NUM_TIDS(x) (2 * TARGET_NUM_PEERS(x) + \
34 4 * TARGET_NUM_VDEVS + 8)
35
36 #define TARGET_AST_SKID_LIMIT 16
37 #define TARGET_NUM_OFFLD_PEERS 4
38 #define TARGET_NUM_OFFLD_REORDER_BUFFS 4
39
40 #define TARGET_TX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2) | BIT(4))
41 #define TARGET_RX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2) | BIT(4))
42 #define TARGET_RX_TIMEOUT_LO_PRI 100
43 #define TARGET_RX_TIMEOUT_HI_PRI 40
44
45 #define TARGET_DECAP_MODE_RAW 0
46 #define TARGET_DECAP_MODE_NATIVE_WIFI 1
47 #define TARGET_DECAP_MODE_ETH 2
48
49 #define TARGET_SCAN_MAX_PENDING_REQS 4
50 #define TARGET_BMISS_OFFLOAD_MAX_VDEV 3
51 #define TARGET_ROAM_OFFLOAD_MAX_VDEV 3
52 #define TARGET_ROAM_OFFLOAD_MAX_AP_PROFILES 8
53 #define TARGET_GTK_OFFLOAD_MAX_VDEV 3
54 #define TARGET_NUM_MCAST_GROUPS 12
55 #define TARGET_NUM_MCAST_TABLE_ELEMS 64
56 #define TARGET_MCAST2UCAST_MODE 2
57 #define TARGET_TX_DBG_LOG_SIZE 1024
58 #define TARGET_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 1
59 #define TARGET_VOW_CONFIG 0
60 #define TARGET_NUM_MSDU_DESC (2500)
61 #define TARGET_MAX_FRAG_ENTRIES 6
62 #define TARGET_MAX_BCN_OFFLD 16
63 #define TARGET_NUM_WDS_ENTRIES 32
64 #define TARGET_DMA_BURST_SIZE 1
65 #define TARGET_RX_BATCHMODE 1
66
67 #define ATH11K_HW_MAX_QUEUES 4
68 #define ATH11K_QUEUE_LEN 4096
69
70 #define ATH11k_HW_RATECODE_CCK_SHORT_PREAM_MASK 0x4
71
72 #define ATH11K_FW_DIR "ath11k"
73
74 #define ATH11K_BOARD_MAGIC "QCA-ATH11K-BOARD"
75 #define ATH11K_BOARD_API2_FILE "board-2.bin"
76 #define ATH11K_DEFAULT_BOARD_FILE "board.bin"
77 #define ATH11K_DEFAULT_CAL_FILE "caldata.bin"
78 #define ATH11K_AMSS_FILE "amss.bin"
79 #define ATH11K_M3_FILE "m3.bin"
80
81 enum ath11k_hw_rate_cck {
82 ATH11K_HW_RATE_CCK_LP_11M = 0,
83 ATH11K_HW_RATE_CCK_LP_5_5M,
84 ATH11K_HW_RATE_CCK_LP_2M,
85 ATH11K_HW_RATE_CCK_LP_1M,
86 ATH11K_HW_RATE_CCK_SP_11M,
87 ATH11K_HW_RATE_CCK_SP_5_5M,
88 ATH11K_HW_RATE_CCK_SP_2M,
89 };
90
91 enum ath11k_hw_rate_ofdm {
92 ATH11K_HW_RATE_OFDM_48M = 0,
93 ATH11K_HW_RATE_OFDM_24M,
94 ATH11K_HW_RATE_OFDM_12M,
95 ATH11K_HW_RATE_OFDM_6M,
96 ATH11K_HW_RATE_OFDM_54M,
97 ATH11K_HW_RATE_OFDM_36M,
98 ATH11K_HW_RATE_OFDM_18M,
99 ATH11K_HW_RATE_OFDM_9M,
100 };
101
102 enum ath11k_bus {
103 ATH11K_BUS_AHB,
104 ATH11K_BUS_PCI,
105 };
106
107 #define ATH11K_EXT_IRQ_GRP_NUM_MAX 11
108
109 struct hal_rx_desc;
110 struct hal_tcl_data_cmd;
111
112 struct ath11k_hw_ring_mask {
113 u8 tx[ATH11K_EXT_IRQ_GRP_NUM_MAX];
114 u8 rx_mon_status[ATH11K_EXT_IRQ_GRP_NUM_MAX];
115 u8 rx[ATH11K_EXT_IRQ_GRP_NUM_MAX];
116 u8 rx_err[ATH11K_EXT_IRQ_GRP_NUM_MAX];
117 u8 rx_wbm_rel[ATH11K_EXT_IRQ_GRP_NUM_MAX];
118 u8 reo_status[ATH11K_EXT_IRQ_GRP_NUM_MAX];
119 u8 rxdma2host[ATH11K_EXT_IRQ_GRP_NUM_MAX];
120 u8 host2rxdma[ATH11K_EXT_IRQ_GRP_NUM_MAX];
121 };
122
123 struct ath11k_hw_hal_params {
124 enum hal_rx_buf_return_buf_manager rx_buf_rbm;
125 };
126
127 struct ath11k_hw_params {
128 const char *name;
129 u16 hw_rev;
130 u8 max_radios;
131 u32 bdf_addr;
132
133 struct {
134 const char *dir;
135 size_t board_size;
136 size_t cal_offset;
137 } fw;
138
139 const struct ath11k_hw_ops *hw_ops;
140 const struct ath11k_hw_ring_mask *ring_mask;
141
142 bool internal_sleep_clock;
143
144 const struct ath11k_hw_regs *regs;
145 u32 qmi_service_ins_id;
146 const struct ce_attr *host_ce_config;
147 u32 ce_count;
148 const struct ce_pipe_config *target_ce_config;
149 u32 target_ce_count;
150 const struct service_to_pipe *svc_to_ce_map;
151 u32 svc_to_ce_map_len;
152
153 bool single_pdev_only;
154
155 bool rxdma1_enable;
156 int num_rxmda_per_pdev;
157 bool rx_mac_buf_ring;
158 bool vdev_start_delay;
159 bool htt_peer_map_v2;
160
161 struct {
162 u8 fft_sz;
163 u8 fft_pad_sz;
164 u8 summary_pad_sz;
165 u8 fft_hdr_len;
166 u16 max_fft_bins;
167 } spectral;
168
169 u16 interface_modes;
170 bool supports_monitor;
171 bool supports_shadow_regs;
172 bool idle_ps;
173 bool cold_boot_calib;
174 bool supports_suspend;
175 u32 hal_desc_sz;
176 bool fix_l1ss;
177 u8 max_tx_ring;
178 const struct ath11k_hw_hal_params *hal_params;
179 };
180
181 struct ath11k_hw_ops {
182 u8 (*get_hw_mac_from_pdev_id)(int pdev_id);
183 void (*wmi_init_config)(struct ath11k_base *ab,
184 struct target_resource_config *config);
185 int (*mac_id_to_pdev_id)(struct ath11k_hw_params *hw, int mac_id);
186 int (*mac_id_to_srng_id)(struct ath11k_hw_params *hw, int mac_id);
187 void (*tx_mesh_enable)(struct ath11k_base *ab,
188 struct hal_tcl_data_cmd *tcl_cmd);
189 bool (*rx_desc_get_first_msdu)(struct hal_rx_desc *desc);
190 bool (*rx_desc_get_last_msdu)(struct hal_rx_desc *desc);
191 u8 (*rx_desc_get_l3_pad_bytes)(struct hal_rx_desc *desc);
192 u8 *(*rx_desc_get_hdr_status)(struct hal_rx_desc *desc);
193 bool (*rx_desc_encrypt_valid)(struct hal_rx_desc *desc);
194 u32 (*rx_desc_get_encrypt_type)(struct hal_rx_desc *desc);
195 u8 (*rx_desc_get_decap_type)(struct hal_rx_desc *desc);
196 u8 (*rx_desc_get_mesh_ctl)(struct hal_rx_desc *desc);
197 bool (*rx_desc_get_mpdu_seq_ctl_vld)(struct hal_rx_desc *desc);
198 bool (*rx_desc_get_mpdu_fc_valid)(struct hal_rx_desc *desc);
199 u16 (*rx_desc_get_mpdu_start_seq_no)(struct hal_rx_desc *desc);
200 u16 (*rx_desc_get_msdu_len)(struct hal_rx_desc *desc);
201 u8 (*rx_desc_get_msdu_sgi)(struct hal_rx_desc *desc);
202 u8 (*rx_desc_get_msdu_rate_mcs)(struct hal_rx_desc *desc);
203 u8 (*rx_desc_get_msdu_rx_bw)(struct hal_rx_desc *desc);
204 u32 (*rx_desc_get_msdu_freq)(struct hal_rx_desc *desc);
205 u8 (*rx_desc_get_msdu_pkt_type)(struct hal_rx_desc *desc);
206 u8 (*rx_desc_get_msdu_nss)(struct hal_rx_desc *desc);
207 u8 (*rx_desc_get_mpdu_tid)(struct hal_rx_desc *desc);
208 u16 (*rx_desc_get_mpdu_peer_id)(struct hal_rx_desc *desc);
209 void (*rx_desc_copy_attn_end_tlv)(struct hal_rx_desc *fdesc,
210 struct hal_rx_desc *ldesc);
211 u32 (*rx_desc_get_mpdu_start_tag)(struct hal_rx_desc *desc);
212 u32 (*rx_desc_get_mpdu_ppdu_id)(struct hal_rx_desc *desc);
213 void (*rx_desc_set_msdu_len)(struct hal_rx_desc *desc, u16 len);
214 struct rx_attention *(*rx_desc_get_attention)(struct hal_rx_desc *desc);
215 u8 *(*rx_desc_get_msdu_payload)(struct hal_rx_desc *desc);
216 void (*reo_setup)(struct ath11k_base *ab);
217 u16 (*mpdu_info_get_peerid)(u8 *tlv_data);
218 bool (*rx_desc_mac_addr2_valid)(struct hal_rx_desc *desc);
219 u8* (*rx_desc_mpdu_start_addr2)(struct hal_rx_desc *desc);
220 };
221
222 extern const struct ath11k_hw_ops ipq8074_ops;
223 extern const struct ath11k_hw_ops ipq6018_ops;
224 extern const struct ath11k_hw_ops qca6390_ops;
225 extern const struct ath11k_hw_ops qcn9074_ops;
226 extern const struct ath11k_hw_ops wcn6855_ops;
227
228 extern const struct ath11k_hw_ring_mask ath11k_hw_ring_mask_ipq8074;
229 extern const struct ath11k_hw_ring_mask ath11k_hw_ring_mask_qca6390;
230 extern const struct ath11k_hw_ring_mask ath11k_hw_ring_mask_qcn9074;
231
232 extern const struct ath11k_hw_hal_params ath11k_hw_hal_params_ipq8074;
233 extern const struct ath11k_hw_hal_params ath11k_hw_hal_params_qca6390;
234
235 static inline
ath11k_hw_get_mac_from_pdev_id(struct ath11k_hw_params * hw,int pdev_idx)236 int ath11k_hw_get_mac_from_pdev_id(struct ath11k_hw_params *hw,
237 int pdev_idx)
238 {
239 if (hw->hw_ops->get_hw_mac_from_pdev_id)
240 return hw->hw_ops->get_hw_mac_from_pdev_id(pdev_idx);
241
242 return 0;
243 }
244
ath11k_hw_mac_id_to_pdev_id(struct ath11k_hw_params * hw,int mac_id)245 static inline int ath11k_hw_mac_id_to_pdev_id(struct ath11k_hw_params *hw,
246 int mac_id)
247 {
248 if (hw->hw_ops->mac_id_to_pdev_id)
249 return hw->hw_ops->mac_id_to_pdev_id(hw, mac_id);
250
251 return 0;
252 }
253
ath11k_hw_mac_id_to_srng_id(struct ath11k_hw_params * hw,int mac_id)254 static inline int ath11k_hw_mac_id_to_srng_id(struct ath11k_hw_params *hw,
255 int mac_id)
256 {
257 if (hw->hw_ops->mac_id_to_srng_id)
258 return hw->hw_ops->mac_id_to_srng_id(hw, mac_id);
259
260 return 0;
261 }
262
263 struct ath11k_fw_ie {
264 __le32 id;
265 __le32 len;
266 u8 data[];
267 };
268
269 enum ath11k_bd_ie_board_type {
270 ATH11K_BD_IE_BOARD_NAME = 0,
271 ATH11K_BD_IE_BOARD_DATA = 1,
272 };
273
274 enum ath11k_bd_ie_type {
275 /* contains sub IEs of enum ath11k_bd_ie_board_type */
276 ATH11K_BD_IE_BOARD = 0,
277 ATH11K_BD_IE_BOARD_EXT = 1,
278 };
279
280 struct ath11k_hw_regs {
281 u32 hal_tcl1_ring_base_lsb;
282 u32 hal_tcl1_ring_base_msb;
283 u32 hal_tcl1_ring_id;
284 u32 hal_tcl1_ring_misc;
285 u32 hal_tcl1_ring_tp_addr_lsb;
286 u32 hal_tcl1_ring_tp_addr_msb;
287 u32 hal_tcl1_ring_consumer_int_setup_ix0;
288 u32 hal_tcl1_ring_consumer_int_setup_ix1;
289 u32 hal_tcl1_ring_msi1_base_lsb;
290 u32 hal_tcl1_ring_msi1_base_msb;
291 u32 hal_tcl1_ring_msi1_data;
292 u32 hal_tcl2_ring_base_lsb;
293 u32 hal_tcl_ring_base_lsb;
294
295 u32 hal_tcl_status_ring_base_lsb;
296
297 u32 hal_reo1_ring_base_lsb;
298 u32 hal_reo1_ring_base_msb;
299 u32 hal_reo1_ring_id;
300 u32 hal_reo1_ring_misc;
301 u32 hal_reo1_ring_hp_addr_lsb;
302 u32 hal_reo1_ring_hp_addr_msb;
303 u32 hal_reo1_ring_producer_int_setup;
304 u32 hal_reo1_ring_msi1_base_lsb;
305 u32 hal_reo1_ring_msi1_base_msb;
306 u32 hal_reo1_ring_msi1_data;
307 u32 hal_reo2_ring_base_lsb;
308 u32 hal_reo1_aging_thresh_ix_0;
309 u32 hal_reo1_aging_thresh_ix_1;
310 u32 hal_reo1_aging_thresh_ix_2;
311 u32 hal_reo1_aging_thresh_ix_3;
312
313 u32 hal_reo1_ring_hp;
314 u32 hal_reo1_ring_tp;
315 u32 hal_reo2_ring_hp;
316
317 u32 hal_reo_tcl_ring_base_lsb;
318 u32 hal_reo_tcl_ring_hp;
319
320 u32 hal_reo_status_ring_base_lsb;
321 u32 hal_reo_status_hp;
322
323 u32 hal_seq_wcss_umac_ce0_src_reg;
324 u32 hal_seq_wcss_umac_ce0_dst_reg;
325 u32 hal_seq_wcss_umac_ce1_src_reg;
326 u32 hal_seq_wcss_umac_ce1_dst_reg;
327
328 u32 hal_wbm_idle_link_ring_base_lsb;
329 u32 hal_wbm_idle_link_ring_misc;
330
331 u32 hal_wbm_release_ring_base_lsb;
332
333 u32 hal_wbm0_release_ring_base_lsb;
334 u32 hal_wbm1_release_ring_base_lsb;
335
336 u32 pcie_qserdes_sysclk_en_sel;
337 u32 pcie_pcs_osc_dtct_config_base;
338 };
339
340 extern const struct ath11k_hw_regs ipq8074_regs;
341 extern const struct ath11k_hw_regs qca6390_regs;
342 extern const struct ath11k_hw_regs qcn9074_regs;
343 extern const struct ath11k_hw_regs wcn6855_regs;
344
345 #endif
346