1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Marvell RVU Ethernet driver
3 *
4 * Copyright (C) 2020 Marvell.
5 *
6 */
7
8 #ifndef OTX2_COMMON_H
9 #define OTX2_COMMON_H
10
11 #include <linux/ethtool.h>
12 #include <linux/pci.h>
13 #include <linux/iommu.h>
14 #include <linux/net_tstamp.h>
15 #include <linux/ptp_clock_kernel.h>
16 #include <linux/timecounter.h>
17 #include <linux/soc/marvell/octeontx2/asm.h>
18 #include <net/pkt_cls.h>
19 #include <net/devlink.h>
20
21 #include <mbox.h>
22 #include <npc.h>
23 #include "otx2_reg.h"
24 #include "otx2_txrx.h"
25 #include "otx2_devlink.h"
26 #include <rvu_trace.h>
27
28 /* PCI device IDs */
29 #define PCI_DEVID_OCTEONTX2_RVU_PF 0xA063
30 #define PCI_DEVID_OCTEONTX2_RVU_VF 0xA064
31 #define PCI_DEVID_OCTEONTX2_RVU_AFVF 0xA0F8
32
33 #define PCI_SUBSYS_DEVID_96XX_RVU_PFVF 0xB200
34
35 /* PCI BAR nos */
36 #define PCI_CFG_REG_BAR_NUM 2
37 #define PCI_MBOX_BAR_NUM 4
38
39 #define NAME_SIZE 32
40
41 enum arua_mapped_qtypes {
42 AURA_NIX_RQ,
43 AURA_NIX_SQ,
44 };
45
46 /* NIX LF interrupts range*/
47 #define NIX_LF_QINT_VEC_START 0x00
48 #define NIX_LF_CINT_VEC_START 0x40
49 #define NIX_LF_GINT_VEC 0x80
50 #define NIX_LF_ERR_VEC 0x81
51 #define NIX_LF_POISON_VEC 0x82
52
53 /* Send skid of 2000 packets required for CQ size of 4K CQEs. */
54 #define SEND_CQ_SKID 2000
55
56 struct otx2_lmt_info {
57 u64 lmt_addr;
58 u16 lmt_id;
59 };
60 /* RSS configuration */
61 struct otx2_rss_ctx {
62 u8 ind_tbl[MAX_RSS_INDIR_TBL_SIZE];
63 };
64
65 struct otx2_rss_info {
66 u8 enable;
67 u32 flowkey_cfg;
68 u16 rss_size;
69 #define RSS_HASH_KEY_SIZE 44 /* 352 bit key */
70 u8 key[RSS_HASH_KEY_SIZE];
71 struct otx2_rss_ctx *rss_ctx[MAX_RSS_GROUPS];
72 };
73
74 /* NIX (or NPC) RX errors */
75 enum otx2_errlvl {
76 NPC_ERRLVL_RE,
77 NPC_ERRLVL_LID_LA,
78 NPC_ERRLVL_LID_LB,
79 NPC_ERRLVL_LID_LC,
80 NPC_ERRLVL_LID_LD,
81 NPC_ERRLVL_LID_LE,
82 NPC_ERRLVL_LID_LF,
83 NPC_ERRLVL_LID_LG,
84 NPC_ERRLVL_LID_LH,
85 NPC_ERRLVL_NIX = 0x0F,
86 };
87
88 enum otx2_errcodes_re {
89 /* NPC_ERRLVL_RE errcodes */
90 ERRCODE_FCS = 0x7,
91 ERRCODE_FCS_RCV = 0x8,
92 ERRCODE_UNDERSIZE = 0x10,
93 ERRCODE_OVERSIZE = 0x11,
94 ERRCODE_OL2_LEN_MISMATCH = 0x12,
95 /* NPC_ERRLVL_NIX errcodes */
96 ERRCODE_OL3_LEN = 0x10,
97 ERRCODE_OL4_LEN = 0x11,
98 ERRCODE_OL4_CSUM = 0x12,
99 ERRCODE_IL3_LEN = 0x20,
100 ERRCODE_IL4_LEN = 0x21,
101 ERRCODE_IL4_CSUM = 0x22,
102 };
103
104 /* NIX TX stats */
105 enum nix_stat_lf_tx {
106 TX_UCAST = 0x0,
107 TX_BCAST = 0x1,
108 TX_MCAST = 0x2,
109 TX_DROP = 0x3,
110 TX_OCTS = 0x4,
111 TX_STATS_ENUM_LAST,
112 };
113
114 /* NIX RX stats */
115 enum nix_stat_lf_rx {
116 RX_OCTS = 0x0,
117 RX_UCAST = 0x1,
118 RX_BCAST = 0x2,
119 RX_MCAST = 0x3,
120 RX_DROP = 0x4,
121 RX_DROP_OCTS = 0x5,
122 RX_FCS = 0x6,
123 RX_ERR = 0x7,
124 RX_DRP_BCAST = 0x8,
125 RX_DRP_MCAST = 0x9,
126 RX_DRP_L3BCAST = 0xa,
127 RX_DRP_L3MCAST = 0xb,
128 RX_STATS_ENUM_LAST,
129 };
130
131 struct otx2_dev_stats {
132 u64 rx_bytes;
133 u64 rx_frames;
134 u64 rx_ucast_frames;
135 u64 rx_bcast_frames;
136 u64 rx_mcast_frames;
137 u64 rx_drops;
138
139 u64 tx_bytes;
140 u64 tx_frames;
141 u64 tx_ucast_frames;
142 u64 tx_bcast_frames;
143 u64 tx_mcast_frames;
144 u64 tx_drops;
145 };
146
147 /* Driver counted stats */
148 struct otx2_drv_stats {
149 atomic_t rx_fcs_errs;
150 atomic_t rx_oversize_errs;
151 atomic_t rx_undersize_errs;
152 atomic_t rx_csum_errs;
153 atomic_t rx_len_errs;
154 atomic_t rx_other_errs;
155 };
156
157 struct mbox {
158 struct otx2_mbox mbox;
159 struct work_struct mbox_wrk;
160 struct otx2_mbox mbox_up;
161 struct work_struct mbox_up_wrk;
162 struct otx2_nic *pfvf;
163 void *bbuf_base; /* Bounce buffer for mbox memory */
164 struct mutex lock; /* serialize mailbox access */
165 int num_msgs; /* mbox number of messages */
166 int up_num_msgs; /* mbox_up number of messages */
167 };
168
169 struct otx2_hw {
170 struct pci_dev *pdev;
171 struct otx2_rss_info rss_info;
172 u16 rx_queues;
173 u16 tx_queues;
174 u16 xdp_queues;
175 u16 tot_tx_queues;
176 u16 max_queues;
177 u16 pool_cnt;
178 u16 rqpool_cnt;
179 u16 sqpool_cnt;
180
181 /* NPA */
182 u32 stack_pg_ptrs; /* No of ptrs per stack page */
183 u32 stack_pg_bytes; /* Size of stack page */
184 u16 sqb_size;
185
186 /* NIX */
187 u16 txschq_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC];
188 u16 matchall_ipolicer;
189 u32 dwrr_mtu;
190
191 /* HW settings, coalescing etc */
192 u16 rx_chan_base;
193 u16 tx_chan_base;
194 u16 cq_qcount_wait;
195 u16 cq_ecount_wait;
196 u16 rq_skid;
197 u8 cq_time_wait;
198
199 /* Segmentation */
200 u8 lso_tsov4_idx;
201 u8 lso_tsov6_idx;
202 u8 lso_udpv4_idx;
203 u8 lso_udpv6_idx;
204
205 /* RSS */
206 u8 flowkey_alg_idx;
207
208 /* MSI-X */
209 u8 cint_cnt; /* CQ interrupt count */
210 u16 npa_msixoff; /* Offset of NPA vectors */
211 u16 nix_msixoff; /* Offset of NIX vectors */
212 char *irq_name;
213 cpumask_var_t *affinity_mask;
214
215 /* Stats */
216 struct otx2_dev_stats dev_stats;
217 struct otx2_drv_stats drv_stats;
218 u64 cgx_rx_stats[CGX_RX_STATS_COUNT];
219 u64 cgx_tx_stats[CGX_TX_STATS_COUNT];
220 u64 cgx_fec_corr_blks;
221 u64 cgx_fec_uncorr_blks;
222 u8 cgx_links; /* No. of CGX links present in HW */
223 u8 lbk_links; /* No. of LBK links present in HW */
224 u8 tx_link; /* Transmit channel link number */
225 #define HW_TSO 0
226 #define CN10K_MBOX 1
227 #define CN10K_LMTST 2
228 #define CN10K_RPM 3
229 unsigned long cap_flag;
230
231 #define LMT_LINE_SIZE 128
232 #define LMT_BURST_SIZE 32 /* 32 LMTST lines for burst SQE flush */
233 u64 *lmt_base;
234 struct otx2_lmt_info __percpu *lmt_info;
235 };
236
237 enum vfperm {
238 OTX2_RESET_VF_PERM,
239 OTX2_TRUSTED_VF,
240 };
241
242 struct otx2_vf_config {
243 struct otx2_nic *pf;
244 struct delayed_work link_event_work;
245 bool intf_down; /* interface was either configured or not */
246 u8 mac[ETH_ALEN];
247 u16 vlan;
248 int tx_vtag_idx;
249 bool trusted;
250 };
251
252 struct flr_work {
253 struct work_struct work;
254 struct otx2_nic *pf;
255 };
256
257 struct refill_work {
258 struct delayed_work pool_refill_work;
259 struct otx2_nic *pf;
260 };
261
262 struct otx2_ptp {
263 struct ptp_clock_info ptp_info;
264 struct ptp_clock *ptp_clock;
265 struct otx2_nic *nic;
266
267 struct cyclecounter cycle_counter;
268 struct timecounter time_counter;
269
270 struct delayed_work extts_work;
271 u64 last_extts;
272 u64 thresh;
273
274 struct ptp_pin_desc extts_config;
275 };
276
277 #define OTX2_HW_TIMESTAMP_LEN 8
278
279 struct otx2_mac_table {
280 u8 addr[ETH_ALEN];
281 u16 mcam_entry;
282 bool inuse;
283 };
284
285 struct otx2_flow_config {
286 u16 *flow_ent;
287 u16 *def_ent;
288 u16 nr_flows;
289 #define OTX2_DEFAULT_FLOWCOUNT 16
290 #define OTX2_MAX_UNICAST_FLOWS 8
291 #define OTX2_MAX_VLAN_FLOWS 1
292 #define OTX2_MAX_TC_FLOWS OTX2_DEFAULT_FLOWCOUNT
293 #define OTX2_MCAM_COUNT (OTX2_DEFAULT_FLOWCOUNT + \
294 OTX2_MAX_UNICAST_FLOWS + \
295 OTX2_MAX_VLAN_FLOWS)
296 u16 unicast_offset;
297 u16 rx_vlan_offset;
298 u16 vf_vlan_offset;
299 #define OTX2_PER_VF_VLAN_FLOWS 2 /* Rx + Tx per VF */
300 #define OTX2_VF_VLAN_RX_INDEX 0
301 #define OTX2_VF_VLAN_TX_INDEX 1
302 u16 max_flows;
303 u8 dmacflt_max_flows;
304 u8 *bmap_to_dmacindex;
305 unsigned long dmacflt_bmap;
306 struct list_head flow_list;
307 };
308
309 struct otx2_tc_info {
310 /* hash table to store TC offloaded flows */
311 struct rhashtable flow_table;
312 struct rhashtable_params flow_ht_params;
313 unsigned long *tc_entries_bitmap;
314 };
315
316 struct dev_hw_ops {
317 int (*sq_aq_init)(void *dev, u16 qidx, u16 sqb_aura);
318 void (*sqe_flush)(void *dev, struct otx2_snd_queue *sq,
319 int size, int qidx);
320 void (*refill_pool_ptrs)(void *dev, struct otx2_cq_queue *cq);
321 void (*aura_freeptr)(void *dev, int aura, u64 buf);
322 };
323
324 struct otx2_nic {
325 void __iomem *reg_base;
326 struct net_device *netdev;
327 struct dev_hw_ops *hw_ops;
328 void *iommu_domain;
329 u16 tx_max_pktlen;
330 u16 rbsize; /* Receive buffer size */
331
332 #define OTX2_FLAG_RX_TSTAMP_ENABLED BIT_ULL(0)
333 #define OTX2_FLAG_TX_TSTAMP_ENABLED BIT_ULL(1)
334 #define OTX2_FLAG_INTF_DOWN BIT_ULL(2)
335 #define OTX2_FLAG_MCAM_ENTRIES_ALLOC BIT_ULL(3)
336 #define OTX2_FLAG_NTUPLE_SUPPORT BIT_ULL(4)
337 #define OTX2_FLAG_UCAST_FLTR_SUPPORT BIT_ULL(5)
338 #define OTX2_FLAG_RX_VLAN_SUPPORT BIT_ULL(6)
339 #define OTX2_FLAG_VF_VLAN_SUPPORT BIT_ULL(7)
340 #define OTX2_FLAG_PF_SHUTDOWN BIT_ULL(8)
341 #define OTX2_FLAG_RX_PAUSE_ENABLED BIT_ULL(9)
342 #define OTX2_FLAG_TX_PAUSE_ENABLED BIT_ULL(10)
343 #define OTX2_FLAG_TC_FLOWER_SUPPORT BIT_ULL(11)
344 #define OTX2_FLAG_TC_MATCHALL_EGRESS_ENABLED BIT_ULL(12)
345 #define OTX2_FLAG_TC_MATCHALL_INGRESS_ENABLED BIT_ULL(13)
346 #define OTX2_FLAG_DMACFLTR_SUPPORT BIT_ULL(14)
347 u64 flags;
348 u64 *cq_op_addr;
349
350 struct bpf_prog *xdp_prog;
351 struct otx2_qset qset;
352 struct otx2_hw hw;
353 struct pci_dev *pdev;
354 struct device *dev;
355
356 /* Mbox */
357 struct mbox mbox;
358 struct mbox *mbox_pfvf;
359 struct workqueue_struct *mbox_wq;
360 struct workqueue_struct *mbox_pfvf_wq;
361
362 u8 total_vfs;
363 u16 pcifunc; /* RVU PF_FUNC */
364 u16 bpid[NIX_MAX_BPID_CHAN];
365 struct otx2_vf_config *vf_configs;
366 struct cgx_link_user_info linfo;
367
368 /* NPC MCAM */
369 struct otx2_flow_config *flow_cfg;
370 struct otx2_mac_table *mac_table;
371 struct otx2_tc_info tc_info;
372
373 u64 reset_count;
374 struct work_struct reset_task;
375 struct workqueue_struct *flr_wq;
376 struct flr_work *flr_wrk;
377 struct refill_work *refill_wrk;
378 struct workqueue_struct *otx2_wq;
379 struct work_struct rx_mode_work;
380
381 /* Ethtool stuff */
382 u32 msg_enable;
383
384 /* Block address of NIX either BLKADDR_NIX0 or BLKADDR_NIX1 */
385 int nix_blkaddr;
386 /* LMTST Lines info */
387 struct qmem *dync_lmt;
388 u16 tot_lmt_lines;
389 u16 npa_lmt_lines;
390 u32 nix_lmt_size;
391
392 struct otx2_ptp *ptp;
393 struct hwtstamp_config tstamp;
394
395 unsigned long rq_bmap;
396
397 /* Devlink */
398 struct otx2_devlink *dl;
399 };
400
is_otx2_lbkvf(struct pci_dev * pdev)401 static inline bool is_otx2_lbkvf(struct pci_dev *pdev)
402 {
403 return pdev->device == PCI_DEVID_OCTEONTX2_RVU_AFVF;
404 }
405
is_96xx_A0(struct pci_dev * pdev)406 static inline bool is_96xx_A0(struct pci_dev *pdev)
407 {
408 return (pdev->revision == 0x00) &&
409 (pdev->subsystem_device == PCI_SUBSYS_DEVID_96XX_RVU_PFVF);
410 }
411
is_96xx_B0(struct pci_dev * pdev)412 static inline bool is_96xx_B0(struct pci_dev *pdev)
413 {
414 return (pdev->revision == 0x01) &&
415 (pdev->subsystem_device == PCI_SUBSYS_DEVID_96XX_RVU_PFVF);
416 }
417
418 /* REVID for PCIe devices.
419 * Bits 0..1: minor pass, bit 3..2: major pass
420 * bits 7..4: midr id
421 */
422 #define PCI_REVISION_ID_96XX 0x00
423 #define PCI_REVISION_ID_95XX 0x10
424 #define PCI_REVISION_ID_95XXN 0x20
425 #define PCI_REVISION_ID_98XX 0x30
426 #define PCI_REVISION_ID_95XXMM 0x40
427 #define PCI_REVISION_ID_95XXO 0xE0
428
is_dev_otx2(struct pci_dev * pdev)429 static inline bool is_dev_otx2(struct pci_dev *pdev)
430 {
431 u8 midr = pdev->revision & 0xF0;
432
433 return (midr == PCI_REVISION_ID_96XX || midr == PCI_REVISION_ID_95XX ||
434 midr == PCI_REVISION_ID_95XXN || midr == PCI_REVISION_ID_98XX ||
435 midr == PCI_REVISION_ID_95XXMM || midr == PCI_REVISION_ID_95XXO);
436 }
437
otx2_setup_dev_hw_settings(struct otx2_nic * pfvf)438 static inline void otx2_setup_dev_hw_settings(struct otx2_nic *pfvf)
439 {
440 struct otx2_hw *hw = &pfvf->hw;
441
442 pfvf->hw.cq_time_wait = CQ_TIMER_THRESH_DEFAULT;
443 pfvf->hw.cq_ecount_wait = CQ_CQE_THRESH_DEFAULT;
444 pfvf->hw.cq_qcount_wait = CQ_QCOUNT_DEFAULT;
445
446 __set_bit(HW_TSO, &hw->cap_flag);
447
448 if (is_96xx_A0(pfvf->pdev)) {
449 __clear_bit(HW_TSO, &hw->cap_flag);
450
451 /* Time based irq coalescing is not supported */
452 pfvf->hw.cq_qcount_wait = 0x0;
453
454 /* Due to HW issue previous silicons required minimum
455 * 600 unused CQE to avoid CQ overflow.
456 */
457 pfvf->hw.rq_skid = 600;
458 pfvf->qset.rqe_cnt = Q_COUNT(Q_SIZE_1K);
459 }
460 if (is_96xx_B0(pfvf->pdev))
461 __clear_bit(HW_TSO, &hw->cap_flag);
462
463 if (!is_dev_otx2(pfvf->pdev)) {
464 __set_bit(CN10K_MBOX, &hw->cap_flag);
465 __set_bit(CN10K_LMTST, &hw->cap_flag);
466 __set_bit(CN10K_RPM, &hw->cap_flag);
467 }
468 }
469
470 /* Register read/write APIs */
otx2_get_regaddr(struct otx2_nic * nic,u64 offset)471 static inline void __iomem *otx2_get_regaddr(struct otx2_nic *nic, u64 offset)
472 {
473 u64 blkaddr;
474
475 switch ((offset >> RVU_FUNC_BLKADDR_SHIFT) & RVU_FUNC_BLKADDR_MASK) {
476 case BLKTYPE_NIX:
477 blkaddr = nic->nix_blkaddr;
478 break;
479 case BLKTYPE_NPA:
480 blkaddr = BLKADDR_NPA;
481 break;
482 default:
483 blkaddr = BLKADDR_RVUM;
484 break;
485 }
486
487 offset &= ~(RVU_FUNC_BLKADDR_MASK << RVU_FUNC_BLKADDR_SHIFT);
488 offset |= (blkaddr << RVU_FUNC_BLKADDR_SHIFT);
489
490 return nic->reg_base + offset;
491 }
492
otx2_write64(struct otx2_nic * nic,u64 offset,u64 val)493 static inline void otx2_write64(struct otx2_nic *nic, u64 offset, u64 val)
494 {
495 void __iomem *addr = otx2_get_regaddr(nic, offset);
496
497 writeq(val, addr);
498 }
499
otx2_read64(struct otx2_nic * nic,u64 offset)500 static inline u64 otx2_read64(struct otx2_nic *nic, u64 offset)
501 {
502 void __iomem *addr = otx2_get_regaddr(nic, offset);
503
504 return readq(addr);
505 }
506
507 /* Mbox bounce buffer APIs */
otx2_mbox_bbuf_init(struct mbox * mbox,struct pci_dev * pdev)508 static inline int otx2_mbox_bbuf_init(struct mbox *mbox, struct pci_dev *pdev)
509 {
510 struct otx2_mbox *otx2_mbox;
511 struct otx2_mbox_dev *mdev;
512
513 mbox->bbuf_base = devm_kmalloc(&pdev->dev, MBOX_SIZE, GFP_KERNEL);
514 if (!mbox->bbuf_base)
515 return -ENOMEM;
516
517 /* Overwrite mbox mbase to point to bounce buffer, so that PF/VF
518 * prepare all mbox messages in bounce buffer instead of directly
519 * in hw mbox memory.
520 */
521 otx2_mbox = &mbox->mbox;
522 mdev = &otx2_mbox->dev[0];
523 mdev->mbase = mbox->bbuf_base;
524
525 otx2_mbox = &mbox->mbox_up;
526 mdev = &otx2_mbox->dev[0];
527 mdev->mbase = mbox->bbuf_base;
528 return 0;
529 }
530
otx2_sync_mbox_bbuf(struct otx2_mbox * mbox,int devid)531 static inline void otx2_sync_mbox_bbuf(struct otx2_mbox *mbox, int devid)
532 {
533 u16 msgs_offset = ALIGN(sizeof(struct mbox_hdr), MBOX_MSG_ALIGN);
534 void *hw_mbase = mbox->hwbase + (devid * MBOX_SIZE);
535 struct otx2_mbox_dev *mdev = &mbox->dev[devid];
536 struct mbox_hdr *hdr;
537 u64 msg_size;
538
539 if (mdev->mbase == hw_mbase)
540 return;
541
542 hdr = hw_mbase + mbox->rx_start;
543 msg_size = hdr->msg_size;
544
545 if (msg_size > mbox->rx_size - msgs_offset)
546 msg_size = mbox->rx_size - msgs_offset;
547
548 /* Copy mbox messages from mbox memory to bounce buffer */
549 memcpy(mdev->mbase + mbox->rx_start,
550 hw_mbase + mbox->rx_start, msg_size + msgs_offset);
551 }
552
553 /* With the absence of API for 128-bit IO memory access for arm64,
554 * implement required operations at place.
555 */
556 #if defined(CONFIG_ARM64)
otx2_write128(u64 lo,u64 hi,void __iomem * addr)557 static inline void otx2_write128(u64 lo, u64 hi, void __iomem *addr)
558 {
559 __asm__ volatile("stp %x[x0], %x[x1], [%x[p1],#0]!"
560 ::[x0]"r"(lo), [x1]"r"(hi), [p1]"r"(addr));
561 }
562
otx2_atomic64_add(u64 incr,u64 * ptr)563 static inline u64 otx2_atomic64_add(u64 incr, u64 *ptr)
564 {
565 u64 result;
566
567 __asm__ volatile(".cpu generic+lse\n"
568 "ldadd %x[i], %x[r], [%[b]]"
569 : [r]"=r"(result), "+m"(*ptr)
570 : [i]"r"(incr), [b]"r"(ptr)
571 : "memory");
572 return result;
573 }
574
575 #else
576 #define otx2_write128(lo, hi, addr) writeq((hi) | (lo), addr)
577 #define otx2_atomic64_add(incr, ptr) ({ *ptr += incr; })
578 #endif
579
__cn10k_aura_freeptr(struct otx2_nic * pfvf,u64 aura,u64 * ptrs,u64 num_ptrs)580 static inline void __cn10k_aura_freeptr(struct otx2_nic *pfvf, u64 aura,
581 u64 *ptrs, u64 num_ptrs)
582 {
583 struct otx2_lmt_info *lmt_info;
584 u64 size = 0, count_eot = 0;
585 u64 tar_addr, val = 0;
586
587 lmt_info = per_cpu_ptr(pfvf->hw.lmt_info, smp_processor_id());
588 tar_addr = (__force u64)otx2_get_regaddr(pfvf, NPA_LF_AURA_BATCH_FREE0);
589 /* LMTID is same as AURA Id */
590 val = (lmt_info->lmt_id & 0x7FF) | BIT_ULL(63);
591 /* Set if [127:64] of last 128bit word has a valid pointer */
592 count_eot = (num_ptrs % 2) ? 0ULL : 1ULL;
593 /* Set AURA ID to free pointer */
594 ptrs[0] = (count_eot << 32) | (aura & 0xFFFFF);
595 /* Target address for LMTST flush tells HW how many 128bit
596 * words are valid from NPA_LF_AURA_BATCH_FREE0.
597 *
598 * tar_addr[6:4] is LMTST size-1 in units of 128b.
599 */
600 if (num_ptrs > 2) {
601 size = (sizeof(u64) * num_ptrs) / 16;
602 if (!count_eot)
603 size++;
604 tar_addr |= ((size - 1) & 0x7) << 4;
605 }
606 memcpy((u64 *)lmt_info->lmt_addr, ptrs, sizeof(u64) * num_ptrs);
607 /* Perform LMTST flush */
608 cn10k_lmt_flush(val, tar_addr);
609 }
610
cn10k_aura_freeptr(void * dev,int aura,u64 buf)611 static inline void cn10k_aura_freeptr(void *dev, int aura, u64 buf)
612 {
613 struct otx2_nic *pfvf = dev;
614 u64 ptrs[2];
615
616 ptrs[1] = buf;
617 /* Free only one buffer at time during init and teardown */
618 __cn10k_aura_freeptr(pfvf, aura, ptrs, 2);
619 }
620
621 /* Alloc pointer from pool/aura */
otx2_aura_allocptr(struct otx2_nic * pfvf,int aura)622 static inline u64 otx2_aura_allocptr(struct otx2_nic *pfvf, int aura)
623 {
624 u64 *ptr = (u64 *)otx2_get_regaddr(pfvf,
625 NPA_LF_AURA_OP_ALLOCX(0));
626 u64 incr = (u64)aura | BIT_ULL(63);
627
628 return otx2_atomic64_add(incr, ptr);
629 }
630
631 /* Free pointer to a pool/aura */
otx2_aura_freeptr(void * dev,int aura,u64 buf)632 static inline void otx2_aura_freeptr(void *dev, int aura, u64 buf)
633 {
634 struct otx2_nic *pfvf = dev;
635 void __iomem *addr = otx2_get_regaddr(pfvf, NPA_LF_AURA_OP_FREE0);
636
637 otx2_write128(buf, (u64)aura | BIT_ULL(63), addr);
638 }
639
otx2_get_pool_idx(struct otx2_nic * pfvf,int type,int idx)640 static inline int otx2_get_pool_idx(struct otx2_nic *pfvf, int type, int idx)
641 {
642 if (type == AURA_NIX_SQ)
643 return pfvf->hw.rqpool_cnt + idx;
644
645 /* AURA_NIX_RQ */
646 return idx;
647 }
648
649 /* Mbox APIs */
otx2_sync_mbox_msg(struct mbox * mbox)650 static inline int otx2_sync_mbox_msg(struct mbox *mbox)
651 {
652 int err;
653
654 if (!otx2_mbox_nonempty(&mbox->mbox, 0))
655 return 0;
656 otx2_mbox_msg_send(&mbox->mbox, 0);
657 err = otx2_mbox_wait_for_rsp(&mbox->mbox, 0);
658 if (err)
659 return err;
660
661 return otx2_mbox_check_rsp_msgs(&mbox->mbox, 0);
662 }
663
otx2_sync_mbox_up_msg(struct mbox * mbox,int devid)664 static inline int otx2_sync_mbox_up_msg(struct mbox *mbox, int devid)
665 {
666 int err;
667
668 if (!otx2_mbox_nonempty(&mbox->mbox_up, devid))
669 return 0;
670 otx2_mbox_msg_send(&mbox->mbox_up, devid);
671 err = otx2_mbox_wait_for_rsp(&mbox->mbox_up, devid);
672 if (err)
673 return err;
674
675 return otx2_mbox_check_rsp_msgs(&mbox->mbox_up, devid);
676 }
677
678 /* Use this API to send mbox msgs in atomic context
679 * where sleeping is not allowed
680 */
otx2_sync_mbox_msg_busy_poll(struct mbox * mbox)681 static inline int otx2_sync_mbox_msg_busy_poll(struct mbox *mbox)
682 {
683 int err;
684
685 if (!otx2_mbox_nonempty(&mbox->mbox, 0))
686 return 0;
687 otx2_mbox_msg_send(&mbox->mbox, 0);
688 err = otx2_mbox_busy_poll_for_rsp(&mbox->mbox, 0);
689 if (err)
690 return err;
691
692 return otx2_mbox_check_rsp_msgs(&mbox->mbox, 0);
693 }
694
695 #define M(_name, _id, _fn_name, _req_type, _rsp_type) \
696 static struct _req_type __maybe_unused \
697 *otx2_mbox_alloc_msg_ ## _fn_name(struct mbox *mbox) \
698 { \
699 struct _req_type *req; \
700 \
701 req = (struct _req_type *)otx2_mbox_alloc_msg_rsp( \
702 &mbox->mbox, 0, sizeof(struct _req_type), \
703 sizeof(struct _rsp_type)); \
704 if (!req) \
705 return NULL; \
706 req->hdr.sig = OTX2_MBOX_REQ_SIG; \
707 req->hdr.id = _id; \
708 trace_otx2_msg_alloc(mbox->mbox.pdev, _id, sizeof(*req)); \
709 return req; \
710 }
711
712 MBOX_MESSAGES
713 #undef M
714
715 #define M(_name, _id, _fn_name, _req_type, _rsp_type) \
716 int \
717 otx2_mbox_up_handler_ ## _fn_name(struct otx2_nic *pfvf, \
718 struct _req_type *req, \
719 struct _rsp_type *rsp); \
720
721 MBOX_UP_CGX_MESSAGES
722 #undef M
723
724 /* Time to wait before watchdog kicks off */
725 #define OTX2_TX_TIMEOUT (100 * HZ)
726
727 #define RVU_PFVF_PF_SHIFT 10
728 #define RVU_PFVF_PF_MASK 0x3F
729 #define RVU_PFVF_FUNC_SHIFT 0
730 #define RVU_PFVF_FUNC_MASK 0x3FF
731
is_otx2_vf(u16 pcifunc)732 static inline bool is_otx2_vf(u16 pcifunc)
733 {
734 return !!(pcifunc & RVU_PFVF_FUNC_MASK);
735 }
736
rvu_get_pf(u16 pcifunc)737 static inline int rvu_get_pf(u16 pcifunc)
738 {
739 return (pcifunc >> RVU_PFVF_PF_SHIFT) & RVU_PFVF_PF_MASK;
740 }
741
otx2_dma_map_page(struct otx2_nic * pfvf,struct page * page,size_t offset,size_t size,enum dma_data_direction dir)742 static inline dma_addr_t otx2_dma_map_page(struct otx2_nic *pfvf,
743 struct page *page,
744 size_t offset, size_t size,
745 enum dma_data_direction dir)
746 {
747 dma_addr_t iova;
748
749 iova = dma_map_page_attrs(pfvf->dev, page,
750 offset, size, dir, DMA_ATTR_SKIP_CPU_SYNC);
751 if (unlikely(dma_mapping_error(pfvf->dev, iova)))
752 return (dma_addr_t)NULL;
753 return iova;
754 }
755
otx2_dma_unmap_page(struct otx2_nic * pfvf,dma_addr_t addr,size_t size,enum dma_data_direction dir)756 static inline void otx2_dma_unmap_page(struct otx2_nic *pfvf,
757 dma_addr_t addr, size_t size,
758 enum dma_data_direction dir)
759 {
760 dma_unmap_page_attrs(pfvf->dev, addr, size,
761 dir, DMA_ATTR_SKIP_CPU_SYNC);
762 }
763
764 /* MSI-X APIs */
765 void otx2_free_cints(struct otx2_nic *pfvf, int n);
766 void otx2_set_cints_affinity(struct otx2_nic *pfvf);
767 int otx2_set_mac_address(struct net_device *netdev, void *p);
768 int otx2_hw_set_mtu(struct otx2_nic *pfvf, int mtu);
769 void otx2_tx_timeout(struct net_device *netdev, unsigned int txq);
770 void otx2_get_mac_from_af(struct net_device *netdev);
771 void otx2_config_irq_coalescing(struct otx2_nic *pfvf, int qidx);
772 int otx2_config_pause_frm(struct otx2_nic *pfvf);
773 void otx2_setup_segmentation(struct otx2_nic *pfvf);
774
775 /* RVU block related APIs */
776 int otx2_attach_npa_nix(struct otx2_nic *pfvf);
777 int otx2_detach_resources(struct mbox *mbox);
778 int otx2_config_npa(struct otx2_nic *pfvf);
779 int otx2_sq_aura_pool_init(struct otx2_nic *pfvf);
780 int otx2_rq_aura_pool_init(struct otx2_nic *pfvf);
781 void otx2_aura_pool_free(struct otx2_nic *pfvf);
782 void otx2_free_aura_ptr(struct otx2_nic *pfvf, int type);
783 void otx2_sq_free_sqbs(struct otx2_nic *pfvf);
784 int otx2_config_nix(struct otx2_nic *pfvf);
785 int otx2_config_nix_queues(struct otx2_nic *pfvf);
786 int otx2_txschq_config(struct otx2_nic *pfvf, int lvl);
787 int otx2_txsch_alloc(struct otx2_nic *pfvf);
788 int otx2_txschq_stop(struct otx2_nic *pfvf);
789 void otx2_sqb_flush(struct otx2_nic *pfvf);
790 int __otx2_alloc_rbuf(struct otx2_nic *pfvf, struct otx2_pool *pool,
791 dma_addr_t *dma);
792 int otx2_rxtx_enable(struct otx2_nic *pfvf, bool enable);
793 void otx2_ctx_disable(struct mbox *mbox, int type, bool npa);
794 int otx2_nix_config_bp(struct otx2_nic *pfvf, bool enable);
795 void otx2_cleanup_rx_cqes(struct otx2_nic *pfvf, struct otx2_cq_queue *cq);
796 void otx2_cleanup_tx_cqes(struct otx2_nic *pfvf, struct otx2_cq_queue *cq);
797 int otx2_sq_aq_init(void *dev, u16 qidx, u16 sqb_aura);
798 int cn10k_sq_aq_init(void *dev, u16 qidx, u16 sqb_aura);
799 int otx2_alloc_buffer(struct otx2_nic *pfvf, struct otx2_cq_queue *cq,
800 dma_addr_t *dma);
801
802 /* RSS configuration APIs*/
803 int otx2_rss_init(struct otx2_nic *pfvf);
804 int otx2_set_flowkey_cfg(struct otx2_nic *pfvf);
805 void otx2_set_rss_key(struct otx2_nic *pfvf);
806 int otx2_set_rss_table(struct otx2_nic *pfvf, int ctx_id);
807
808 /* Mbox handlers */
809 void mbox_handler_msix_offset(struct otx2_nic *pfvf,
810 struct msix_offset_rsp *rsp);
811 void mbox_handler_npa_lf_alloc(struct otx2_nic *pfvf,
812 struct npa_lf_alloc_rsp *rsp);
813 void mbox_handler_nix_lf_alloc(struct otx2_nic *pfvf,
814 struct nix_lf_alloc_rsp *rsp);
815 void mbox_handler_nix_txsch_alloc(struct otx2_nic *pf,
816 struct nix_txsch_alloc_rsp *rsp);
817 void mbox_handler_cgx_stats(struct otx2_nic *pfvf,
818 struct cgx_stats_rsp *rsp);
819 void mbox_handler_cgx_fec_stats(struct otx2_nic *pfvf,
820 struct cgx_fec_stats_rsp *rsp);
821 void otx2_set_fec_stats_count(struct otx2_nic *pfvf);
822 void mbox_handler_nix_bp_enable(struct otx2_nic *pfvf,
823 struct nix_bp_cfg_rsp *rsp);
824
825 /* Device stats APIs */
826 void otx2_get_dev_stats(struct otx2_nic *pfvf);
827 void otx2_get_stats64(struct net_device *netdev,
828 struct rtnl_link_stats64 *stats);
829 void otx2_update_lmac_stats(struct otx2_nic *pfvf);
830 void otx2_update_lmac_fec_stats(struct otx2_nic *pfvf);
831 int otx2_update_rq_stats(struct otx2_nic *pfvf, int qidx);
832 int otx2_update_sq_stats(struct otx2_nic *pfvf, int qidx);
833 void otx2_set_ethtool_ops(struct net_device *netdev);
834 void otx2vf_set_ethtool_ops(struct net_device *netdev);
835
836 int otx2_open(struct net_device *netdev);
837 int otx2_stop(struct net_device *netdev);
838 int otx2_set_real_num_queues(struct net_device *netdev,
839 int tx_queues, int rx_queues);
840 int otx2_ioctl(struct net_device *netdev, struct ifreq *req, int cmd);
841 int otx2_config_hwtstamp(struct net_device *netdev, struct ifreq *ifr);
842
843 /* MCAM filter related APIs */
844 int otx2_mcam_flow_init(struct otx2_nic *pf);
845 int otx2vf_mcam_flow_init(struct otx2_nic *pfvf);
846 int otx2_alloc_mcam_entries(struct otx2_nic *pfvf, u16 count);
847 void otx2_mcam_flow_del(struct otx2_nic *pf);
848 int otx2_destroy_ntuple_flows(struct otx2_nic *pf);
849 int otx2_destroy_mcam_flows(struct otx2_nic *pfvf);
850 int otx2_get_flow(struct otx2_nic *pfvf,
851 struct ethtool_rxnfc *nfc, u32 location);
852 int otx2_get_all_flows(struct otx2_nic *pfvf,
853 struct ethtool_rxnfc *nfc, u32 *rule_locs);
854 int otx2_add_flow(struct otx2_nic *pfvf,
855 struct ethtool_rxnfc *nfc);
856 int otx2_remove_flow(struct otx2_nic *pfvf, u32 location);
857 int otx2_get_maxflows(struct otx2_flow_config *flow_cfg);
858 void otx2_rss_ctx_flow_del(struct otx2_nic *pfvf, int ctx_id);
859 int otx2_del_macfilter(struct net_device *netdev, const u8 *mac);
860 int otx2_add_macfilter(struct net_device *netdev, const u8 *mac);
861 int otx2_enable_rxvlan(struct otx2_nic *pf, bool enable);
862 int otx2_install_rxvlan_offload_flow(struct otx2_nic *pfvf);
863 bool otx2_xdp_sq_append_pkt(struct otx2_nic *pfvf, u64 iova, int len, u16 qidx);
864 u16 otx2_get_max_mtu(struct otx2_nic *pfvf);
865 /* tc support */
866 int otx2_init_tc(struct otx2_nic *nic);
867 void otx2_shutdown_tc(struct otx2_nic *nic);
868 int otx2_setup_tc(struct net_device *netdev, enum tc_setup_type type,
869 void *type_data);
870 int otx2_tc_alloc_ent_bitmap(struct otx2_nic *nic);
871 /* CGX/RPM DMAC filters support */
872 int otx2_dmacflt_get_max_cnt(struct otx2_nic *pf);
873 int otx2_dmacflt_add(struct otx2_nic *pf, const u8 *mac, u8 bit_pos);
874 int otx2_dmacflt_remove(struct otx2_nic *pf, const u8 *mac, u8 bit_pos);
875 int otx2_dmacflt_update(struct otx2_nic *pf, u8 *mac, u8 bit_pos);
876 void otx2_dmacflt_reinstall_flows(struct otx2_nic *pf);
877 void otx2_dmacflt_update_pfmac_flow(struct otx2_nic *pfvf);
878 #endif /* OTX2_COMMON_H */
879