1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * drivers/soc/tegra/pmc.c
4 *
5 * Copyright (c) 2010 Google, Inc
6 * Copyright (c) 2018-2020, NVIDIA CORPORATION. All rights reserved.
7 *
8 * Author:
9 * Colin Cross <ccross@google.com>
10 */
11
12 #define pr_fmt(fmt) "tegra-pmc: " fmt
13
14 #include <linux/arm-smccc.h>
15 #include <linux/clk.h>
16 #include <linux/clk-provider.h>
17 #include <linux/clkdev.h>
18 #include <linux/clk/clk-conf.h>
19 #include <linux/clk/tegra.h>
20 #include <linux/debugfs.h>
21 #include <linux/delay.h>
22 #include <linux/device.h>
23 #include <linux/err.h>
24 #include <linux/export.h>
25 #include <linux/init.h>
26 #include <linux/io.h>
27 #include <linux/iopoll.h>
28 #include <linux/irqdomain.h>
29 #include <linux/irq.h>
30 #include <linux/kernel.h>
31 #include <linux/of_address.h>
32 #include <linux/of_clk.h>
33 #include <linux/of.h>
34 #include <linux/of_irq.h>
35 #include <linux/of_platform.h>
36 #include <linux/pinctrl/pinconf-generic.h>
37 #include <linux/pinctrl/pinconf.h>
38 #include <linux/pinctrl/pinctrl.h>
39 #include <linux/platform_device.h>
40 #include <linux/pm_domain.h>
41 #include <linux/pm_opp.h>
42 #include <linux/reboot.h>
43 #include <linux/regmap.h>
44 #include <linux/reset.h>
45 #include <linux/seq_file.h>
46 #include <linux/slab.h>
47 #include <linux/spinlock.h>
48
49 #include <soc/tegra/common.h>
50 #include <soc/tegra/fuse.h>
51 #include <soc/tegra/pmc.h>
52
53 #include <dt-bindings/interrupt-controller/arm-gic.h>
54 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
55 #include <dt-bindings/gpio/tegra186-gpio.h>
56 #include <dt-bindings/gpio/tegra194-gpio.h>
57 #include <dt-bindings/soc/tegra-pmc.h>
58
59 #define PMC_CNTRL 0x0
60 #define PMC_CNTRL_INTR_POLARITY BIT(17) /* inverts INTR polarity */
61 #define PMC_CNTRL_CPU_PWRREQ_OE BIT(16) /* CPU pwr req enable */
62 #define PMC_CNTRL_CPU_PWRREQ_POLARITY BIT(15) /* CPU pwr req polarity */
63 #define PMC_CNTRL_SIDE_EFFECT_LP0 BIT(14) /* LP0 when CPU pwr gated */
64 #define PMC_CNTRL_SYSCLK_OE BIT(11) /* system clock enable */
65 #define PMC_CNTRL_SYSCLK_POLARITY BIT(10) /* sys clk polarity */
66 #define PMC_CNTRL_PWRREQ_POLARITY BIT(8)
67 #define PMC_CNTRL_BLINK_EN 7
68 #define PMC_CNTRL_MAIN_RST BIT(4)
69
70 #define PMC_WAKE_MASK 0x0c
71 #define PMC_WAKE_LEVEL 0x10
72 #define PMC_WAKE_STATUS 0x14
73 #define PMC_SW_WAKE_STATUS 0x18
74 #define PMC_DPD_PADS_ORIDE 0x1c
75 #define PMC_DPD_PADS_ORIDE_BLINK 20
76
77 #define DPD_SAMPLE 0x020
78 #define DPD_SAMPLE_ENABLE BIT(0)
79 #define DPD_SAMPLE_DISABLE (0 << 0)
80
81 #define PWRGATE_TOGGLE 0x30
82 #define PWRGATE_TOGGLE_START BIT(8)
83
84 #define REMOVE_CLAMPING 0x34
85
86 #define PWRGATE_STATUS 0x38
87
88 #define PMC_BLINK_TIMER 0x40
89 #define PMC_IMPL_E_33V_PWR 0x40
90
91 #define PMC_PWR_DET 0x48
92
93 #define PMC_SCRATCH0_MODE_RECOVERY BIT(31)
94 #define PMC_SCRATCH0_MODE_BOOTLOADER BIT(30)
95 #define PMC_SCRATCH0_MODE_RCM BIT(1)
96 #define PMC_SCRATCH0_MODE_MASK (PMC_SCRATCH0_MODE_RECOVERY | \
97 PMC_SCRATCH0_MODE_BOOTLOADER | \
98 PMC_SCRATCH0_MODE_RCM)
99
100 #define PMC_CPUPWRGOOD_TIMER 0xc8
101 #define PMC_CPUPWROFF_TIMER 0xcc
102 #define PMC_COREPWRGOOD_TIMER 0x3c
103 #define PMC_COREPWROFF_TIMER 0xe0
104
105 #define PMC_PWR_DET_VALUE 0xe4
106
107 #define PMC_USB_DEBOUNCE_DEL 0xec
108 #define PMC_USB_AO 0xf0
109
110 #define PMC_SCRATCH41 0x140
111
112 #define PMC_WAKE2_MASK 0x160
113 #define PMC_WAKE2_LEVEL 0x164
114 #define PMC_WAKE2_STATUS 0x168
115 #define PMC_SW_WAKE2_STATUS 0x16c
116
117 #define PMC_CLK_OUT_CNTRL 0x1a8
118 #define PMC_CLK_OUT_MUX_MASK GENMASK(1, 0)
119 #define PMC_SENSOR_CTRL 0x1b0
120 #define PMC_SENSOR_CTRL_SCRATCH_WRITE BIT(2)
121 #define PMC_SENSOR_CTRL_ENABLE_RST BIT(1)
122
123 #define PMC_RST_STATUS_POR 0
124 #define PMC_RST_STATUS_WATCHDOG 1
125 #define PMC_RST_STATUS_SENSOR 2
126 #define PMC_RST_STATUS_SW_MAIN 3
127 #define PMC_RST_STATUS_LP0 4
128 #define PMC_RST_STATUS_AOTAG 5
129
130 #define IO_DPD_REQ 0x1b8
131 #define IO_DPD_REQ_CODE_IDLE (0U << 30)
132 #define IO_DPD_REQ_CODE_OFF (1U << 30)
133 #define IO_DPD_REQ_CODE_ON (2U << 30)
134 #define IO_DPD_REQ_CODE_MASK (3U << 30)
135
136 #define IO_DPD_STATUS 0x1bc
137 #define IO_DPD2_REQ 0x1c0
138 #define IO_DPD2_STATUS 0x1c4
139 #define SEL_DPD_TIM 0x1c8
140
141 #define PMC_UTMIP_UHSIC_TRIGGERS 0x1ec
142 #define PMC_UTMIP_UHSIC_SAVED_STATE 0x1f0
143
144 #define PMC_UTMIP_TERM_PAD_CFG 0x1f8
145 #define PMC_UTMIP_UHSIC_SLEEP_CFG 0x1fc
146 #define PMC_UTMIP_UHSIC_FAKE 0x218
147
148 #define PMC_SCRATCH54 0x258
149 #define PMC_SCRATCH54_DATA_SHIFT 8
150 #define PMC_SCRATCH54_ADDR_SHIFT 0
151
152 #define PMC_SCRATCH55 0x25c
153 #define PMC_SCRATCH55_RESET_TEGRA BIT(31)
154 #define PMC_SCRATCH55_CNTRL_ID_SHIFT 27
155 #define PMC_SCRATCH55_PINMUX_SHIFT 24
156 #define PMC_SCRATCH55_16BITOP BIT(15)
157 #define PMC_SCRATCH55_CHECKSUM_SHIFT 16
158 #define PMC_SCRATCH55_I2CSLV1_SHIFT 0
159
160 #define PMC_UTMIP_UHSIC_LINE_WAKEUP 0x26c
161
162 #define PMC_UTMIP_BIAS_MASTER_CNTRL 0x270
163 #define PMC_UTMIP_MASTER_CONFIG 0x274
164 #define PMC_UTMIP_UHSIC2_TRIGGERS 0x27c
165 #define PMC_UTMIP_MASTER2_CONFIG 0x29c
166
167 #define GPU_RG_CNTRL 0x2d4
168
169 #define PMC_UTMIP_PAD_CFG0 0x4c0
170 #define PMC_UTMIP_UHSIC_SLEEP_CFG1 0x4d0
171 #define PMC_UTMIP_SLEEPWALK_P3 0x4e0
172 /* Tegra186 and later */
173 #define WAKE_AOWAKE_CNTRL(x) (0x000 + ((x) << 2))
174 #define WAKE_AOWAKE_CNTRL_LEVEL (1 << 3)
175 #define WAKE_AOWAKE_MASK_W(x) (0x180 + ((x) << 2))
176 #define WAKE_AOWAKE_MASK_R(x) (0x300 + ((x) << 2))
177 #define WAKE_AOWAKE_STATUS_W(x) (0x30c + ((x) << 2))
178 #define WAKE_AOWAKE_STATUS_R(x) (0x48c + ((x) << 2))
179 #define WAKE_AOWAKE_TIER0_ROUTING(x) (0x4b4 + ((x) << 2))
180 #define WAKE_AOWAKE_TIER1_ROUTING(x) (0x4c0 + ((x) << 2))
181 #define WAKE_AOWAKE_TIER2_ROUTING(x) (0x4cc + ((x) << 2))
182
183 #define WAKE_AOWAKE_CTRL 0x4f4
184 #define WAKE_AOWAKE_CTRL_INTR_POLARITY BIT(0)
185
186 /* for secure PMC */
187 #define TEGRA_SMC_PMC 0xc2fffe00
188 #define TEGRA_SMC_PMC_READ 0xaa
189 #define TEGRA_SMC_PMC_WRITE 0xbb
190
191 struct pmc_clk {
192 struct clk_hw hw;
193 unsigned long offs;
194 u32 mux_shift;
195 u32 force_en_shift;
196 };
197
198 #define to_pmc_clk(_hw) container_of(_hw, struct pmc_clk, hw)
199
200 struct pmc_clk_gate {
201 struct clk_hw hw;
202 unsigned long offs;
203 u32 shift;
204 };
205
206 #define to_pmc_clk_gate(_hw) container_of(_hw, struct pmc_clk_gate, hw)
207
208 struct pmc_clk_init_data {
209 char *name;
210 const char *const *parents;
211 int num_parents;
212 int clk_id;
213 u8 mux_shift;
214 u8 force_en_shift;
215 };
216
217 static const char * const clk_out1_parents[] = { "osc", "osc_div2",
218 "osc_div4", "extern1",
219 };
220
221 static const char * const clk_out2_parents[] = { "osc", "osc_div2",
222 "osc_div4", "extern2",
223 };
224
225 static const char * const clk_out3_parents[] = { "osc", "osc_div2",
226 "osc_div4", "extern3",
227 };
228
229 static const struct pmc_clk_init_data tegra_pmc_clks_data[] = {
230 {
231 .name = "pmc_clk_out_1",
232 .parents = clk_out1_parents,
233 .num_parents = ARRAY_SIZE(clk_out1_parents),
234 .clk_id = TEGRA_PMC_CLK_OUT_1,
235 .mux_shift = 6,
236 .force_en_shift = 2,
237 },
238 {
239 .name = "pmc_clk_out_2",
240 .parents = clk_out2_parents,
241 .num_parents = ARRAY_SIZE(clk_out2_parents),
242 .clk_id = TEGRA_PMC_CLK_OUT_2,
243 .mux_shift = 14,
244 .force_en_shift = 10,
245 },
246 {
247 .name = "pmc_clk_out_3",
248 .parents = clk_out3_parents,
249 .num_parents = ARRAY_SIZE(clk_out3_parents),
250 .clk_id = TEGRA_PMC_CLK_OUT_3,
251 .mux_shift = 22,
252 .force_en_shift = 18,
253 },
254 };
255
256 struct tegra_powergate {
257 struct generic_pm_domain genpd;
258 struct tegra_pmc *pmc;
259 unsigned int id;
260 struct clk **clks;
261 unsigned int num_clks;
262 unsigned long *clk_rates;
263 struct reset_control *reset;
264 };
265
266 struct tegra_io_pad_soc {
267 enum tegra_io_pad id;
268 unsigned int dpd;
269 unsigned int voltage;
270 const char *name;
271 };
272
273 struct tegra_pmc_regs {
274 unsigned int scratch0;
275 unsigned int dpd_req;
276 unsigned int dpd_status;
277 unsigned int dpd2_req;
278 unsigned int dpd2_status;
279 unsigned int rst_status;
280 unsigned int rst_source_shift;
281 unsigned int rst_source_mask;
282 unsigned int rst_level_shift;
283 unsigned int rst_level_mask;
284 };
285
286 struct tegra_wake_event {
287 const char *name;
288 unsigned int id;
289 unsigned int irq;
290 struct {
291 unsigned int instance;
292 unsigned int pin;
293 } gpio;
294 };
295
296 #define TEGRA_WAKE_IRQ(_name, _id, _irq) \
297 { \
298 .name = _name, \
299 .id = _id, \
300 .irq = _irq, \
301 .gpio = { \
302 .instance = UINT_MAX, \
303 .pin = UINT_MAX, \
304 }, \
305 }
306
307 #define TEGRA_WAKE_GPIO(_name, _id, _instance, _pin) \
308 { \
309 .name = _name, \
310 .id = _id, \
311 .irq = 0, \
312 .gpio = { \
313 .instance = _instance, \
314 .pin = _pin, \
315 }, \
316 }
317
318 struct tegra_pmc_soc {
319 unsigned int num_powergates;
320 const char *const *powergates;
321 unsigned int num_cpu_powergates;
322 const u8 *cpu_powergates;
323
324 bool has_tsense_reset;
325 bool has_gpu_clamps;
326 bool needs_mbist_war;
327 bool has_impl_33v_pwr;
328 bool maybe_tz_only;
329
330 const struct tegra_io_pad_soc *io_pads;
331 unsigned int num_io_pads;
332
333 const struct pinctrl_pin_desc *pin_descs;
334 unsigned int num_pin_descs;
335
336 const struct tegra_pmc_regs *regs;
337 void (*init)(struct tegra_pmc *pmc);
338 void (*setup_irq_polarity)(struct tegra_pmc *pmc,
339 struct device_node *np,
340 bool invert);
341 int (*irq_set_wake)(struct irq_data *data, unsigned int on);
342 int (*irq_set_type)(struct irq_data *data, unsigned int type);
343 int (*powergate_set)(struct tegra_pmc *pmc, unsigned int id,
344 bool new_state);
345
346 const char * const *reset_sources;
347 unsigned int num_reset_sources;
348 const char * const *reset_levels;
349 unsigned int num_reset_levels;
350
351 /*
352 * These describe events that can wake the system from sleep (i.e.
353 * LP0 or SC7). Wakeup from other sleep states (such as LP1 or LP2)
354 * are dealt with in the LIC.
355 */
356 const struct tegra_wake_event *wake_events;
357 unsigned int num_wake_events;
358
359 const struct pmc_clk_init_data *pmc_clks_data;
360 unsigned int num_pmc_clks;
361 bool has_blink_output;
362 bool has_usb_sleepwalk;
363 bool supports_core_domain;
364 };
365
366 /**
367 * struct tegra_pmc - NVIDIA Tegra PMC
368 * @dev: pointer to PMC device structure
369 * @base: pointer to I/O remapped register region
370 * @wake: pointer to I/O remapped region for WAKE registers
371 * @aotag: pointer to I/O remapped region for AOTAG registers
372 * @scratch: pointer to I/O remapped region for scratch registers
373 * @clk: pointer to pclk clock
374 * @soc: pointer to SoC data structure
375 * @tz_only: flag specifying if the PMC can only be accessed via TrustZone
376 * @debugfs: pointer to debugfs entry
377 * @rate: currently configured rate of pclk
378 * @suspend_mode: lowest suspend mode available
379 * @cpu_good_time: CPU power good time (in microseconds)
380 * @cpu_off_time: CPU power off time (in microsecends)
381 * @core_osc_time: core power good OSC time (in microseconds)
382 * @core_pmu_time: core power good PMU time (in microseconds)
383 * @core_off_time: core power off time (in microseconds)
384 * @corereq_high: core power request is active-high
385 * @sysclkreq_high: system clock request is active-high
386 * @combined_req: combined power request for CPU & core
387 * @cpu_pwr_good_en: CPU power good signal is enabled
388 * @lp0_vec_phys: physical base address of the LP0 warm boot code
389 * @lp0_vec_size: size of the LP0 warm boot code
390 * @powergates_available: Bitmap of available power gates
391 * @powergates_lock: mutex for power gate register access
392 * @pctl_dev: pin controller exposed by the PMC
393 * @domain: IRQ domain provided by the PMC
394 * @irq: chip implementation for the IRQ domain
395 * @clk_nb: pclk clock changes handler
396 */
397 struct tegra_pmc {
398 struct device *dev;
399 void __iomem *base;
400 void __iomem *wake;
401 void __iomem *aotag;
402 void __iomem *scratch;
403 struct clk *clk;
404 struct dentry *debugfs;
405
406 const struct tegra_pmc_soc *soc;
407 bool tz_only;
408
409 unsigned long rate;
410
411 enum tegra_suspend_mode suspend_mode;
412 u32 cpu_good_time;
413 u32 cpu_off_time;
414 u32 core_osc_time;
415 u32 core_pmu_time;
416 u32 core_off_time;
417 bool corereq_high;
418 bool sysclkreq_high;
419 bool combined_req;
420 bool cpu_pwr_good_en;
421 u32 lp0_vec_phys;
422 u32 lp0_vec_size;
423 DECLARE_BITMAP(powergates_available, TEGRA_POWERGATE_MAX);
424
425 struct mutex powergates_lock;
426
427 struct pinctrl_dev *pctl_dev;
428
429 struct irq_domain *domain;
430 struct irq_chip irq;
431
432 struct notifier_block clk_nb;
433
434 bool core_domain_state_synced;
435 bool core_domain_registered;
436 };
437
438 static struct tegra_pmc *pmc = &(struct tegra_pmc) {
439 .base = NULL,
440 .suspend_mode = TEGRA_SUSPEND_NOT_READY,
441 };
442
443 static inline struct tegra_powergate *
to_powergate(struct generic_pm_domain * domain)444 to_powergate(struct generic_pm_domain *domain)
445 {
446 return container_of(domain, struct tegra_powergate, genpd);
447 }
448
tegra_pmc_readl(struct tegra_pmc * pmc,unsigned long offset)449 static u32 tegra_pmc_readl(struct tegra_pmc *pmc, unsigned long offset)
450 {
451 struct arm_smccc_res res;
452
453 if (pmc->tz_only) {
454 arm_smccc_smc(TEGRA_SMC_PMC, TEGRA_SMC_PMC_READ, offset, 0, 0,
455 0, 0, 0, &res);
456 if (res.a0) {
457 if (pmc->dev)
458 dev_warn(pmc->dev, "%s(): SMC failed: %lu\n",
459 __func__, res.a0);
460 else
461 pr_warn("%s(): SMC failed: %lu\n", __func__,
462 res.a0);
463 }
464
465 return res.a1;
466 }
467
468 return readl(pmc->base + offset);
469 }
470
tegra_pmc_writel(struct tegra_pmc * pmc,u32 value,unsigned long offset)471 static void tegra_pmc_writel(struct tegra_pmc *pmc, u32 value,
472 unsigned long offset)
473 {
474 struct arm_smccc_res res;
475
476 if (pmc->tz_only) {
477 arm_smccc_smc(TEGRA_SMC_PMC, TEGRA_SMC_PMC_WRITE, offset,
478 value, 0, 0, 0, 0, &res);
479 if (res.a0) {
480 if (pmc->dev)
481 dev_warn(pmc->dev, "%s(): SMC failed: %lu\n",
482 __func__, res.a0);
483 else
484 pr_warn("%s(): SMC failed: %lu\n", __func__,
485 res.a0);
486 }
487 } else {
488 writel(value, pmc->base + offset);
489 }
490 }
491
tegra_pmc_scratch_readl(struct tegra_pmc * pmc,unsigned long offset)492 static u32 tegra_pmc_scratch_readl(struct tegra_pmc *pmc, unsigned long offset)
493 {
494 if (pmc->tz_only)
495 return tegra_pmc_readl(pmc, offset);
496
497 return readl(pmc->scratch + offset);
498 }
499
tegra_pmc_scratch_writel(struct tegra_pmc * pmc,u32 value,unsigned long offset)500 static void tegra_pmc_scratch_writel(struct tegra_pmc *pmc, u32 value,
501 unsigned long offset)
502 {
503 if (pmc->tz_only)
504 tegra_pmc_writel(pmc, value, offset);
505 else
506 writel(value, pmc->scratch + offset);
507 }
508
509 /*
510 * TODO Figure out a way to call this with the struct tegra_pmc * passed in.
511 * This currently doesn't work because readx_poll_timeout() can only operate
512 * on functions that take a single argument.
513 */
tegra_powergate_state(int id)514 static inline bool tegra_powergate_state(int id)
515 {
516 if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps)
517 return (tegra_pmc_readl(pmc, GPU_RG_CNTRL) & 0x1) == 0;
518 else
519 return (tegra_pmc_readl(pmc, PWRGATE_STATUS) & BIT(id)) != 0;
520 }
521
tegra_powergate_is_valid(struct tegra_pmc * pmc,int id)522 static inline bool tegra_powergate_is_valid(struct tegra_pmc *pmc, int id)
523 {
524 return (pmc->soc && pmc->soc->powergates[id]);
525 }
526
tegra_powergate_is_available(struct tegra_pmc * pmc,int id)527 static inline bool tegra_powergate_is_available(struct tegra_pmc *pmc, int id)
528 {
529 return test_bit(id, pmc->powergates_available);
530 }
531
tegra_powergate_lookup(struct tegra_pmc * pmc,const char * name)532 static int tegra_powergate_lookup(struct tegra_pmc *pmc, const char *name)
533 {
534 unsigned int i;
535
536 if (!pmc || !pmc->soc || !name)
537 return -EINVAL;
538
539 for (i = 0; i < pmc->soc->num_powergates; i++) {
540 if (!tegra_powergate_is_valid(pmc, i))
541 continue;
542
543 if (!strcmp(name, pmc->soc->powergates[i]))
544 return i;
545 }
546
547 return -ENODEV;
548 }
549
tegra20_powergate_set(struct tegra_pmc * pmc,unsigned int id,bool new_state)550 static int tegra20_powergate_set(struct tegra_pmc *pmc, unsigned int id,
551 bool new_state)
552 {
553 unsigned int retries = 100;
554 bool status;
555 int ret;
556
557 /*
558 * As per TRM documentation, the toggle command will be dropped by PMC
559 * if there is contention with a HW-initiated toggling (i.e. CPU core
560 * power-gated), the command should be retried in that case.
561 */
562 do {
563 tegra_pmc_writel(pmc, PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE);
564
565 /* wait for PMC to execute the command */
566 ret = readx_poll_timeout(tegra_powergate_state, id, status,
567 status == new_state, 1, 10);
568 } while (ret == -ETIMEDOUT && retries--);
569
570 return ret;
571 }
572
tegra_powergate_toggle_ready(struct tegra_pmc * pmc)573 static inline bool tegra_powergate_toggle_ready(struct tegra_pmc *pmc)
574 {
575 return !(tegra_pmc_readl(pmc, PWRGATE_TOGGLE) & PWRGATE_TOGGLE_START);
576 }
577
tegra114_powergate_set(struct tegra_pmc * pmc,unsigned int id,bool new_state)578 static int tegra114_powergate_set(struct tegra_pmc *pmc, unsigned int id,
579 bool new_state)
580 {
581 bool status;
582 int err;
583
584 /* wait while PMC power gating is contended */
585 err = readx_poll_timeout(tegra_powergate_toggle_ready, pmc, status,
586 status == true, 1, 100);
587 if (err)
588 return err;
589
590 tegra_pmc_writel(pmc, PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE);
591
592 /* wait for PMC to accept the command */
593 err = readx_poll_timeout(tegra_powergate_toggle_ready, pmc, status,
594 status == true, 1, 100);
595 if (err)
596 return err;
597
598 /* wait for PMC to execute the command */
599 err = readx_poll_timeout(tegra_powergate_state, id, status,
600 status == new_state, 10, 100000);
601 if (err)
602 return err;
603
604 return 0;
605 }
606
607 /**
608 * tegra_powergate_set() - set the state of a partition
609 * @pmc: power management controller
610 * @id: partition ID
611 * @new_state: new state of the partition
612 */
tegra_powergate_set(struct tegra_pmc * pmc,unsigned int id,bool new_state)613 static int tegra_powergate_set(struct tegra_pmc *pmc, unsigned int id,
614 bool new_state)
615 {
616 int err;
617
618 if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps)
619 return -EINVAL;
620
621 mutex_lock(&pmc->powergates_lock);
622
623 if (tegra_powergate_state(id) == new_state) {
624 mutex_unlock(&pmc->powergates_lock);
625 return 0;
626 }
627
628 err = pmc->soc->powergate_set(pmc, id, new_state);
629
630 mutex_unlock(&pmc->powergates_lock);
631
632 return err;
633 }
634
__tegra_powergate_remove_clamping(struct tegra_pmc * pmc,unsigned int id)635 static int __tegra_powergate_remove_clamping(struct tegra_pmc *pmc,
636 unsigned int id)
637 {
638 u32 mask;
639
640 mutex_lock(&pmc->powergates_lock);
641
642 /*
643 * On Tegra124 and later, the clamps for the GPU are controlled by a
644 * separate register (with different semantics).
645 */
646 if (id == TEGRA_POWERGATE_3D) {
647 if (pmc->soc->has_gpu_clamps) {
648 tegra_pmc_writel(pmc, 0, GPU_RG_CNTRL);
649 goto out;
650 }
651 }
652
653 /*
654 * Tegra 2 has a bug where PCIE and VDE clamping masks are
655 * swapped relatively to the partition ids
656 */
657 if (id == TEGRA_POWERGATE_VDEC)
658 mask = (1 << TEGRA_POWERGATE_PCIE);
659 else if (id == TEGRA_POWERGATE_PCIE)
660 mask = (1 << TEGRA_POWERGATE_VDEC);
661 else
662 mask = (1 << id);
663
664 tegra_pmc_writel(pmc, mask, REMOVE_CLAMPING);
665
666 out:
667 mutex_unlock(&pmc->powergates_lock);
668
669 return 0;
670 }
671
tegra_powergate_prepare_clocks(struct tegra_powergate * pg)672 static int tegra_powergate_prepare_clocks(struct tegra_powergate *pg)
673 {
674 unsigned long safe_rate = 100 * 1000 * 1000;
675 unsigned int i;
676 int err;
677
678 for (i = 0; i < pg->num_clks; i++) {
679 pg->clk_rates[i] = clk_get_rate(pg->clks[i]);
680
681 if (!pg->clk_rates[i]) {
682 err = -EINVAL;
683 goto out;
684 }
685
686 if (pg->clk_rates[i] <= safe_rate)
687 continue;
688
689 /*
690 * We don't know whether voltage state is okay for the
691 * current clock rate, hence it's better to temporally
692 * switch clock to a safe rate which is suitable for
693 * all voltages, before enabling the clock.
694 */
695 err = clk_set_rate(pg->clks[i], safe_rate);
696 if (err)
697 goto out;
698 }
699
700 return 0;
701
702 out:
703 while (i--)
704 clk_set_rate(pg->clks[i], pg->clk_rates[i]);
705
706 return err;
707 }
708
tegra_powergate_unprepare_clocks(struct tegra_powergate * pg)709 static int tegra_powergate_unprepare_clocks(struct tegra_powergate *pg)
710 {
711 unsigned int i;
712 int err;
713
714 for (i = 0; i < pg->num_clks; i++) {
715 err = clk_set_rate(pg->clks[i], pg->clk_rates[i]);
716 if (err)
717 return err;
718 }
719
720 return 0;
721 }
722
tegra_powergate_disable_clocks(struct tegra_powergate * pg)723 static void tegra_powergate_disable_clocks(struct tegra_powergate *pg)
724 {
725 unsigned int i;
726
727 for (i = 0; i < pg->num_clks; i++)
728 clk_disable_unprepare(pg->clks[i]);
729 }
730
tegra_powergate_enable_clocks(struct tegra_powergate * pg)731 static int tegra_powergate_enable_clocks(struct tegra_powergate *pg)
732 {
733 unsigned int i;
734 int err;
735
736 for (i = 0; i < pg->num_clks; i++) {
737 err = clk_prepare_enable(pg->clks[i]);
738 if (err)
739 goto out;
740 }
741
742 return 0;
743
744 out:
745 while (i--)
746 clk_disable_unprepare(pg->clks[i]);
747
748 return err;
749 }
750
tegra_powergate_power_up(struct tegra_powergate * pg,bool disable_clocks)751 static int tegra_powergate_power_up(struct tegra_powergate *pg,
752 bool disable_clocks)
753 {
754 int err;
755
756 err = reset_control_assert(pg->reset);
757 if (err)
758 return err;
759
760 usleep_range(10, 20);
761
762 err = tegra_powergate_set(pg->pmc, pg->id, true);
763 if (err < 0)
764 return err;
765
766 usleep_range(10, 20);
767
768 err = tegra_powergate_prepare_clocks(pg);
769 if (err)
770 goto powergate_off;
771
772 err = tegra_powergate_enable_clocks(pg);
773 if (err)
774 goto unprepare_clks;
775
776 usleep_range(10, 20);
777
778 err = __tegra_powergate_remove_clamping(pg->pmc, pg->id);
779 if (err)
780 goto disable_clks;
781
782 usleep_range(10, 20);
783
784 err = reset_control_deassert(pg->reset);
785 if (err)
786 goto disable_clks;
787
788 usleep_range(10, 20);
789
790 if (pg->pmc->soc->needs_mbist_war)
791 err = tegra210_clk_handle_mbist_war(pg->id);
792 if (err)
793 goto disable_clks;
794
795 if (disable_clocks)
796 tegra_powergate_disable_clocks(pg);
797
798 err = tegra_powergate_unprepare_clocks(pg);
799 if (err)
800 return err;
801
802 return 0;
803
804 disable_clks:
805 tegra_powergate_disable_clocks(pg);
806 usleep_range(10, 20);
807
808 unprepare_clks:
809 tegra_powergate_unprepare_clocks(pg);
810
811 powergate_off:
812 tegra_powergate_set(pg->pmc, pg->id, false);
813
814 return err;
815 }
816
tegra_powergate_power_down(struct tegra_powergate * pg)817 static int tegra_powergate_power_down(struct tegra_powergate *pg)
818 {
819 int err;
820
821 err = tegra_powergate_prepare_clocks(pg);
822 if (err)
823 return err;
824
825 err = tegra_powergate_enable_clocks(pg);
826 if (err)
827 goto unprepare_clks;
828
829 usleep_range(10, 20);
830
831 err = reset_control_assert(pg->reset);
832 if (err)
833 goto disable_clks;
834
835 usleep_range(10, 20);
836
837 tegra_powergate_disable_clocks(pg);
838
839 usleep_range(10, 20);
840
841 err = tegra_powergate_set(pg->pmc, pg->id, false);
842 if (err)
843 goto assert_resets;
844
845 err = tegra_powergate_unprepare_clocks(pg);
846 if (err)
847 return err;
848
849 return 0;
850
851 assert_resets:
852 tegra_powergate_enable_clocks(pg);
853 usleep_range(10, 20);
854 reset_control_deassert(pg->reset);
855 usleep_range(10, 20);
856
857 disable_clks:
858 tegra_powergate_disable_clocks(pg);
859
860 unprepare_clks:
861 tegra_powergate_unprepare_clocks(pg);
862
863 return err;
864 }
865
tegra_genpd_power_on(struct generic_pm_domain * domain)866 static int tegra_genpd_power_on(struct generic_pm_domain *domain)
867 {
868 struct tegra_powergate *pg = to_powergate(domain);
869 struct device *dev = pg->pmc->dev;
870 int err;
871
872 err = tegra_powergate_power_up(pg, true);
873 if (err) {
874 dev_err(dev, "failed to turn on PM domain %s: %d\n",
875 pg->genpd.name, err);
876 goto out;
877 }
878
879 reset_control_release(pg->reset);
880
881 out:
882 return err;
883 }
884
tegra_genpd_power_off(struct generic_pm_domain * domain)885 static int tegra_genpd_power_off(struct generic_pm_domain *domain)
886 {
887 struct tegra_powergate *pg = to_powergate(domain);
888 struct device *dev = pg->pmc->dev;
889 int err;
890
891 err = reset_control_acquire(pg->reset);
892 if (err < 0) {
893 dev_err(dev, "failed to acquire resets for PM domain %s: %d\n",
894 pg->genpd.name, err);
895 return err;
896 }
897
898 err = tegra_powergate_power_down(pg);
899 if (err) {
900 dev_err(dev, "failed to turn off PM domain %s: %d\n",
901 pg->genpd.name, err);
902 reset_control_release(pg->reset);
903 }
904
905 return err;
906 }
907
908 /**
909 * tegra_powergate_power_on() - power on partition
910 * @id: partition ID
911 */
tegra_powergate_power_on(unsigned int id)912 int tegra_powergate_power_on(unsigned int id)
913 {
914 if (!tegra_powergate_is_available(pmc, id))
915 return -EINVAL;
916
917 return tegra_powergate_set(pmc, id, true);
918 }
919 EXPORT_SYMBOL(tegra_powergate_power_on);
920
921 /**
922 * tegra_powergate_power_off() - power off partition
923 * @id: partition ID
924 */
tegra_powergate_power_off(unsigned int id)925 int tegra_powergate_power_off(unsigned int id)
926 {
927 if (!tegra_powergate_is_available(pmc, id))
928 return -EINVAL;
929
930 return tegra_powergate_set(pmc, id, false);
931 }
932 EXPORT_SYMBOL(tegra_powergate_power_off);
933
934 /**
935 * tegra_powergate_is_powered() - check if partition is powered
936 * @pmc: power management controller
937 * @id: partition ID
938 */
tegra_powergate_is_powered(struct tegra_pmc * pmc,unsigned int id)939 static int tegra_powergate_is_powered(struct tegra_pmc *pmc, unsigned int id)
940 {
941 if (!tegra_powergate_is_valid(pmc, id))
942 return -EINVAL;
943
944 return tegra_powergate_state(id);
945 }
946
947 /**
948 * tegra_powergate_remove_clamping() - remove power clamps for partition
949 * @id: partition ID
950 */
tegra_powergate_remove_clamping(unsigned int id)951 int tegra_powergate_remove_clamping(unsigned int id)
952 {
953 if (!tegra_powergate_is_available(pmc, id))
954 return -EINVAL;
955
956 return __tegra_powergate_remove_clamping(pmc, id);
957 }
958 EXPORT_SYMBOL(tegra_powergate_remove_clamping);
959
960 /**
961 * tegra_powergate_sequence_power_up() - power up partition
962 * @id: partition ID
963 * @clk: clock for partition
964 * @rst: reset for partition
965 *
966 * Must be called with clk disabled, and returns with clk enabled.
967 */
tegra_powergate_sequence_power_up(unsigned int id,struct clk * clk,struct reset_control * rst)968 int tegra_powergate_sequence_power_up(unsigned int id, struct clk *clk,
969 struct reset_control *rst)
970 {
971 struct tegra_powergate *pg;
972 int err;
973
974 if (!tegra_powergate_is_available(pmc, id))
975 return -EINVAL;
976
977 pg = kzalloc(sizeof(*pg), GFP_KERNEL);
978 if (!pg)
979 return -ENOMEM;
980
981 pg->clk_rates = kzalloc(sizeof(*pg->clk_rates), GFP_KERNEL);
982 if (!pg->clk_rates) {
983 kfree(pg->clks);
984 return -ENOMEM;
985 }
986
987 pg->id = id;
988 pg->clks = &clk;
989 pg->num_clks = 1;
990 pg->reset = rst;
991 pg->pmc = pmc;
992
993 err = tegra_powergate_power_up(pg, false);
994 if (err)
995 dev_err(pmc->dev, "failed to turn on partition %d: %d\n", id,
996 err);
997
998 kfree(pg->clk_rates);
999 kfree(pg);
1000
1001 return err;
1002 }
1003 EXPORT_SYMBOL(tegra_powergate_sequence_power_up);
1004
1005 /**
1006 * tegra_get_cpu_powergate_id() - convert from CPU ID to partition ID
1007 * @pmc: power management controller
1008 * @cpuid: CPU partition ID
1009 *
1010 * Returns the partition ID corresponding to the CPU partition ID or a
1011 * negative error code on failure.
1012 */
tegra_get_cpu_powergate_id(struct tegra_pmc * pmc,unsigned int cpuid)1013 static int tegra_get_cpu_powergate_id(struct tegra_pmc *pmc,
1014 unsigned int cpuid)
1015 {
1016 if (pmc->soc && cpuid < pmc->soc->num_cpu_powergates)
1017 return pmc->soc->cpu_powergates[cpuid];
1018
1019 return -EINVAL;
1020 }
1021
1022 /**
1023 * tegra_pmc_cpu_is_powered() - check if CPU partition is powered
1024 * @cpuid: CPU partition ID
1025 */
tegra_pmc_cpu_is_powered(unsigned int cpuid)1026 bool tegra_pmc_cpu_is_powered(unsigned int cpuid)
1027 {
1028 int id;
1029
1030 id = tegra_get_cpu_powergate_id(pmc, cpuid);
1031 if (id < 0)
1032 return false;
1033
1034 return tegra_powergate_is_powered(pmc, id);
1035 }
1036
1037 /**
1038 * tegra_pmc_cpu_power_on() - power on CPU partition
1039 * @cpuid: CPU partition ID
1040 */
tegra_pmc_cpu_power_on(unsigned int cpuid)1041 int tegra_pmc_cpu_power_on(unsigned int cpuid)
1042 {
1043 int id;
1044
1045 id = tegra_get_cpu_powergate_id(pmc, cpuid);
1046 if (id < 0)
1047 return id;
1048
1049 return tegra_powergate_set(pmc, id, true);
1050 }
1051
1052 /**
1053 * tegra_pmc_cpu_remove_clamping() - remove power clamps for CPU partition
1054 * @cpuid: CPU partition ID
1055 */
tegra_pmc_cpu_remove_clamping(unsigned int cpuid)1056 int tegra_pmc_cpu_remove_clamping(unsigned int cpuid)
1057 {
1058 int id;
1059
1060 id = tegra_get_cpu_powergate_id(pmc, cpuid);
1061 if (id < 0)
1062 return id;
1063
1064 return tegra_powergate_remove_clamping(id);
1065 }
1066
tegra_pmc_restart_notify(struct notifier_block * this,unsigned long action,void * data)1067 static int tegra_pmc_restart_notify(struct notifier_block *this,
1068 unsigned long action, void *data)
1069 {
1070 const char *cmd = data;
1071 u32 value;
1072
1073 value = tegra_pmc_scratch_readl(pmc, pmc->soc->regs->scratch0);
1074 value &= ~PMC_SCRATCH0_MODE_MASK;
1075
1076 if (cmd) {
1077 if (strcmp(cmd, "recovery") == 0)
1078 value |= PMC_SCRATCH0_MODE_RECOVERY;
1079
1080 if (strcmp(cmd, "bootloader") == 0)
1081 value |= PMC_SCRATCH0_MODE_BOOTLOADER;
1082
1083 if (strcmp(cmd, "forced-recovery") == 0)
1084 value |= PMC_SCRATCH0_MODE_RCM;
1085 }
1086
1087 tegra_pmc_scratch_writel(pmc, value, pmc->soc->regs->scratch0);
1088
1089 /* reset everything but PMC_SCRATCH0 and PMC_RST_STATUS */
1090 value = tegra_pmc_readl(pmc, PMC_CNTRL);
1091 value |= PMC_CNTRL_MAIN_RST;
1092 tegra_pmc_writel(pmc, value, PMC_CNTRL);
1093
1094 return NOTIFY_DONE;
1095 }
1096
1097 static struct notifier_block tegra_pmc_restart_handler = {
1098 .notifier_call = tegra_pmc_restart_notify,
1099 .priority = 128,
1100 };
1101
powergate_show(struct seq_file * s,void * data)1102 static int powergate_show(struct seq_file *s, void *data)
1103 {
1104 unsigned int i;
1105 int status;
1106
1107 seq_printf(s, " powergate powered\n");
1108 seq_printf(s, "------------------\n");
1109
1110 for (i = 0; i < pmc->soc->num_powergates; i++) {
1111 status = tegra_powergate_is_powered(pmc, i);
1112 if (status < 0)
1113 continue;
1114
1115 seq_printf(s, " %9s %7s\n", pmc->soc->powergates[i],
1116 status ? "yes" : "no");
1117 }
1118
1119 return 0;
1120 }
1121
1122 DEFINE_SHOW_ATTRIBUTE(powergate);
1123
tegra_powergate_debugfs_init(void)1124 static int tegra_powergate_debugfs_init(void)
1125 {
1126 pmc->debugfs = debugfs_create_file("powergate", S_IRUGO, NULL, NULL,
1127 &powergate_fops);
1128 if (!pmc->debugfs)
1129 return -ENOMEM;
1130
1131 return 0;
1132 }
1133
tegra_powergate_of_get_clks(struct tegra_powergate * pg,struct device_node * np)1134 static int tegra_powergate_of_get_clks(struct tegra_powergate *pg,
1135 struct device_node *np)
1136 {
1137 struct clk *clk;
1138 unsigned int i, count;
1139 int err;
1140
1141 count = of_clk_get_parent_count(np);
1142 if (count == 0)
1143 return -ENODEV;
1144
1145 pg->clks = kcalloc(count, sizeof(clk), GFP_KERNEL);
1146 if (!pg->clks)
1147 return -ENOMEM;
1148
1149 pg->clk_rates = kcalloc(count, sizeof(*pg->clk_rates), GFP_KERNEL);
1150 if (!pg->clk_rates) {
1151 kfree(pg->clks);
1152 return -ENOMEM;
1153 }
1154
1155 for (i = 0; i < count; i++) {
1156 pg->clks[i] = of_clk_get(np, i);
1157 if (IS_ERR(pg->clks[i])) {
1158 err = PTR_ERR(pg->clks[i]);
1159 goto err;
1160 }
1161 }
1162
1163 pg->num_clks = count;
1164
1165 return 0;
1166
1167 err:
1168 while (i--)
1169 clk_put(pg->clks[i]);
1170
1171 kfree(pg->clk_rates);
1172 kfree(pg->clks);
1173
1174 return err;
1175 }
1176
tegra_powergate_of_get_resets(struct tegra_powergate * pg,struct device_node * np,bool off)1177 static int tegra_powergate_of_get_resets(struct tegra_powergate *pg,
1178 struct device_node *np, bool off)
1179 {
1180 struct device *dev = pg->pmc->dev;
1181 int err;
1182
1183 pg->reset = of_reset_control_array_get_exclusive_released(np);
1184 if (IS_ERR(pg->reset)) {
1185 err = PTR_ERR(pg->reset);
1186 dev_err(dev, "failed to get device resets: %d\n", err);
1187 return err;
1188 }
1189
1190 err = reset_control_acquire(pg->reset);
1191 if (err < 0) {
1192 pr_err("failed to acquire resets: %d\n", err);
1193 goto out;
1194 }
1195
1196 if (off) {
1197 err = reset_control_assert(pg->reset);
1198 } else {
1199 err = reset_control_deassert(pg->reset);
1200 if (err < 0)
1201 goto out;
1202
1203 reset_control_release(pg->reset);
1204 }
1205
1206 out:
1207 if (err) {
1208 reset_control_release(pg->reset);
1209 reset_control_put(pg->reset);
1210 }
1211
1212 return err;
1213 }
1214
tegra_powergate_add(struct tegra_pmc * pmc,struct device_node * np)1215 static int tegra_powergate_add(struct tegra_pmc *pmc, struct device_node *np)
1216 {
1217 struct device *dev = pmc->dev;
1218 struct tegra_powergate *pg;
1219 int id, err = 0;
1220 bool off;
1221
1222 pg = kzalloc(sizeof(*pg), GFP_KERNEL);
1223 if (!pg)
1224 return -ENOMEM;
1225
1226 id = tegra_powergate_lookup(pmc, np->name);
1227 if (id < 0) {
1228 dev_err(dev, "powergate lookup failed for %pOFn: %d\n", np, id);
1229 err = -ENODEV;
1230 goto free_mem;
1231 }
1232
1233 /*
1234 * Clear the bit for this powergate so it cannot be managed
1235 * directly via the legacy APIs for controlling powergates.
1236 */
1237 clear_bit(id, pmc->powergates_available);
1238
1239 pg->id = id;
1240 pg->genpd.name = np->name;
1241 pg->genpd.power_off = tegra_genpd_power_off;
1242 pg->genpd.power_on = tegra_genpd_power_on;
1243 pg->pmc = pmc;
1244
1245 off = !tegra_powergate_is_powered(pmc, pg->id);
1246
1247 err = tegra_powergate_of_get_clks(pg, np);
1248 if (err < 0) {
1249 dev_err(dev, "failed to get clocks for %pOFn: %d\n", np, err);
1250 goto set_available;
1251 }
1252
1253 err = tegra_powergate_of_get_resets(pg, np, off);
1254 if (err < 0) {
1255 dev_err(dev, "failed to get resets for %pOFn: %d\n", np, err);
1256 goto remove_clks;
1257 }
1258
1259 if (!IS_ENABLED(CONFIG_PM_GENERIC_DOMAINS)) {
1260 if (off)
1261 WARN_ON(tegra_powergate_power_up(pg, true));
1262
1263 goto remove_resets;
1264 }
1265
1266 err = pm_genpd_init(&pg->genpd, NULL, off);
1267 if (err < 0) {
1268 dev_err(dev, "failed to initialise PM domain %pOFn: %d\n", np,
1269 err);
1270 goto remove_resets;
1271 }
1272
1273 err = of_genpd_add_provider_simple(np, &pg->genpd);
1274 if (err < 0) {
1275 dev_err(dev, "failed to add PM domain provider for %pOFn: %d\n",
1276 np, err);
1277 goto remove_genpd;
1278 }
1279
1280 dev_dbg(dev, "added PM domain %s\n", pg->genpd.name);
1281
1282 return 0;
1283
1284 remove_genpd:
1285 pm_genpd_remove(&pg->genpd);
1286
1287 remove_resets:
1288 reset_control_put(pg->reset);
1289
1290 remove_clks:
1291 while (pg->num_clks--)
1292 clk_put(pg->clks[pg->num_clks]);
1293
1294 kfree(pg->clks);
1295
1296 set_available:
1297 set_bit(id, pmc->powergates_available);
1298
1299 free_mem:
1300 kfree(pg);
1301
1302 return err;
1303 }
1304
tegra_pmc_core_domain_state_synced(void)1305 bool tegra_pmc_core_domain_state_synced(void)
1306 {
1307 return pmc->core_domain_state_synced;
1308 }
1309
1310 static int
tegra_pmc_core_pd_set_performance_state(struct generic_pm_domain * genpd,unsigned int level)1311 tegra_pmc_core_pd_set_performance_state(struct generic_pm_domain *genpd,
1312 unsigned int level)
1313 {
1314 struct dev_pm_opp *opp;
1315 int err;
1316
1317 opp = dev_pm_opp_find_level_ceil(&genpd->dev, &level);
1318 if (IS_ERR(opp)) {
1319 dev_err(&genpd->dev, "failed to find OPP for level %u: %pe\n",
1320 level, opp);
1321 return PTR_ERR(opp);
1322 }
1323
1324 mutex_lock(&pmc->powergates_lock);
1325 err = dev_pm_opp_set_opp(pmc->dev, opp);
1326 mutex_unlock(&pmc->powergates_lock);
1327
1328 dev_pm_opp_put(opp);
1329
1330 if (err) {
1331 dev_err(&genpd->dev, "failed to set voltage to %duV: %d\n",
1332 level, err);
1333 return err;
1334 }
1335
1336 return 0;
1337 }
1338
1339 static unsigned int
tegra_pmc_core_pd_opp_to_performance_state(struct generic_pm_domain * genpd,struct dev_pm_opp * opp)1340 tegra_pmc_core_pd_opp_to_performance_state(struct generic_pm_domain *genpd,
1341 struct dev_pm_opp *opp)
1342 {
1343 return dev_pm_opp_get_level(opp);
1344 }
1345
tegra_pmc_core_pd_add(struct tegra_pmc * pmc,struct device_node * np)1346 static int tegra_pmc_core_pd_add(struct tegra_pmc *pmc, struct device_node *np)
1347 {
1348 struct generic_pm_domain *genpd;
1349 const char *rname = "core";
1350 int err;
1351
1352 genpd = devm_kzalloc(pmc->dev, sizeof(*genpd), GFP_KERNEL);
1353 if (!genpd)
1354 return -ENOMEM;
1355
1356 genpd->name = np->name;
1357 genpd->set_performance_state = tegra_pmc_core_pd_set_performance_state;
1358 genpd->opp_to_performance_state = tegra_pmc_core_pd_opp_to_performance_state;
1359
1360 err = devm_pm_opp_set_regulators(pmc->dev, &rname, 1);
1361 if (err)
1362 return dev_err_probe(pmc->dev, err,
1363 "failed to set core OPP regulator\n");
1364
1365 err = pm_genpd_init(genpd, NULL, false);
1366 if (err) {
1367 dev_err(pmc->dev, "failed to init core genpd: %d\n", err);
1368 return err;
1369 }
1370
1371 err = of_genpd_add_provider_simple(np, genpd);
1372 if (err) {
1373 dev_err(pmc->dev, "failed to add core genpd: %d\n", err);
1374 goto remove_genpd;
1375 }
1376
1377 pmc->core_domain_registered = true;
1378
1379 return 0;
1380
1381 remove_genpd:
1382 pm_genpd_remove(genpd);
1383
1384 return err;
1385 }
1386
tegra_powergate_init(struct tegra_pmc * pmc,struct device_node * parent)1387 static int tegra_powergate_init(struct tegra_pmc *pmc,
1388 struct device_node *parent)
1389 {
1390 struct of_phandle_args child_args, parent_args;
1391 struct device_node *np, *child;
1392 int err = 0;
1393
1394 /*
1395 * Core power domain is the parent of powergate domains, hence it
1396 * should be registered first.
1397 */
1398 np = of_get_child_by_name(parent, "core-domain");
1399 if (np) {
1400 err = tegra_pmc_core_pd_add(pmc, np);
1401 of_node_put(np);
1402 if (err)
1403 return err;
1404 }
1405
1406 np = of_get_child_by_name(parent, "powergates");
1407 if (!np)
1408 return 0;
1409
1410 for_each_child_of_node(np, child) {
1411 err = tegra_powergate_add(pmc, child);
1412 if (err < 0) {
1413 of_node_put(child);
1414 break;
1415 }
1416
1417 if (of_parse_phandle_with_args(child, "power-domains",
1418 "#power-domain-cells",
1419 0, &parent_args))
1420 continue;
1421
1422 child_args.np = child;
1423 child_args.args_count = 0;
1424
1425 err = of_genpd_add_subdomain(&parent_args, &child_args);
1426 of_node_put(parent_args.np);
1427 if (err) {
1428 of_node_put(child);
1429 break;
1430 }
1431 }
1432
1433 of_node_put(np);
1434
1435 return err;
1436 }
1437
tegra_powergate_remove(struct generic_pm_domain * genpd)1438 static void tegra_powergate_remove(struct generic_pm_domain *genpd)
1439 {
1440 struct tegra_powergate *pg = to_powergate(genpd);
1441
1442 reset_control_put(pg->reset);
1443
1444 while (pg->num_clks--)
1445 clk_put(pg->clks[pg->num_clks]);
1446
1447 kfree(pg->clks);
1448
1449 set_bit(pg->id, pmc->powergates_available);
1450
1451 kfree(pg);
1452 }
1453
tegra_powergate_remove_all(struct device_node * parent)1454 static void tegra_powergate_remove_all(struct device_node *parent)
1455 {
1456 struct generic_pm_domain *genpd;
1457 struct device_node *np, *child;
1458
1459 np = of_get_child_by_name(parent, "powergates");
1460 if (!np)
1461 return;
1462
1463 for_each_child_of_node(np, child) {
1464 of_genpd_del_provider(child);
1465
1466 genpd = of_genpd_remove_last(child);
1467 if (IS_ERR(genpd))
1468 continue;
1469
1470 tegra_powergate_remove(genpd);
1471 }
1472
1473 of_node_put(np);
1474
1475 np = of_get_child_by_name(parent, "core-domain");
1476 if (np) {
1477 of_genpd_del_provider(np);
1478 of_genpd_remove_last(np);
1479 }
1480 }
1481
1482 static const struct tegra_io_pad_soc *
tegra_io_pad_find(struct tegra_pmc * pmc,enum tegra_io_pad id)1483 tegra_io_pad_find(struct tegra_pmc *pmc, enum tegra_io_pad id)
1484 {
1485 unsigned int i;
1486
1487 for (i = 0; i < pmc->soc->num_io_pads; i++)
1488 if (pmc->soc->io_pads[i].id == id)
1489 return &pmc->soc->io_pads[i];
1490
1491 return NULL;
1492 }
1493
tegra_io_pad_get_dpd_register_bit(struct tegra_pmc * pmc,enum tegra_io_pad id,unsigned long * request,unsigned long * status,u32 * mask)1494 static int tegra_io_pad_get_dpd_register_bit(struct tegra_pmc *pmc,
1495 enum tegra_io_pad id,
1496 unsigned long *request,
1497 unsigned long *status,
1498 u32 *mask)
1499 {
1500 const struct tegra_io_pad_soc *pad;
1501
1502 pad = tegra_io_pad_find(pmc, id);
1503 if (!pad) {
1504 dev_err(pmc->dev, "invalid I/O pad ID %u\n", id);
1505 return -ENOENT;
1506 }
1507
1508 if (pad->dpd == UINT_MAX)
1509 return -ENOTSUPP;
1510
1511 *mask = BIT(pad->dpd % 32);
1512
1513 if (pad->dpd < 32) {
1514 *status = pmc->soc->regs->dpd_status;
1515 *request = pmc->soc->regs->dpd_req;
1516 } else {
1517 *status = pmc->soc->regs->dpd2_status;
1518 *request = pmc->soc->regs->dpd2_req;
1519 }
1520
1521 return 0;
1522 }
1523
tegra_io_pad_prepare(struct tegra_pmc * pmc,enum tegra_io_pad id,unsigned long * request,unsigned long * status,u32 * mask)1524 static int tegra_io_pad_prepare(struct tegra_pmc *pmc, enum tegra_io_pad id,
1525 unsigned long *request, unsigned long *status,
1526 u32 *mask)
1527 {
1528 unsigned long rate, value;
1529 int err;
1530
1531 err = tegra_io_pad_get_dpd_register_bit(pmc, id, request, status, mask);
1532 if (err)
1533 return err;
1534
1535 if (pmc->clk) {
1536 rate = pmc->rate;
1537 if (!rate) {
1538 dev_err(pmc->dev, "failed to get clock rate\n");
1539 return -ENODEV;
1540 }
1541
1542 tegra_pmc_writel(pmc, DPD_SAMPLE_ENABLE, DPD_SAMPLE);
1543
1544 /* must be at least 200 ns, in APB (PCLK) clock cycles */
1545 value = DIV_ROUND_UP(1000000000, rate);
1546 value = DIV_ROUND_UP(200, value);
1547 tegra_pmc_writel(pmc, value, SEL_DPD_TIM);
1548 }
1549
1550 return 0;
1551 }
1552
tegra_io_pad_poll(struct tegra_pmc * pmc,unsigned long offset,u32 mask,u32 val,unsigned long timeout)1553 static int tegra_io_pad_poll(struct tegra_pmc *pmc, unsigned long offset,
1554 u32 mask, u32 val, unsigned long timeout)
1555 {
1556 u32 value;
1557
1558 timeout = jiffies + msecs_to_jiffies(timeout);
1559
1560 while (time_after(timeout, jiffies)) {
1561 value = tegra_pmc_readl(pmc, offset);
1562 if ((value & mask) == val)
1563 return 0;
1564
1565 usleep_range(250, 1000);
1566 }
1567
1568 return -ETIMEDOUT;
1569 }
1570
tegra_io_pad_unprepare(struct tegra_pmc * pmc)1571 static void tegra_io_pad_unprepare(struct tegra_pmc *pmc)
1572 {
1573 if (pmc->clk)
1574 tegra_pmc_writel(pmc, DPD_SAMPLE_DISABLE, DPD_SAMPLE);
1575 }
1576
1577 /**
1578 * tegra_io_pad_power_enable() - enable power to I/O pad
1579 * @id: Tegra I/O pad ID for which to enable power
1580 *
1581 * Returns: 0 on success or a negative error code on failure.
1582 */
tegra_io_pad_power_enable(enum tegra_io_pad id)1583 int tegra_io_pad_power_enable(enum tegra_io_pad id)
1584 {
1585 unsigned long request, status;
1586 u32 mask;
1587 int err;
1588
1589 mutex_lock(&pmc->powergates_lock);
1590
1591 err = tegra_io_pad_prepare(pmc, id, &request, &status, &mask);
1592 if (err < 0) {
1593 dev_err(pmc->dev, "failed to prepare I/O pad: %d\n", err);
1594 goto unlock;
1595 }
1596
1597 tegra_pmc_writel(pmc, IO_DPD_REQ_CODE_OFF | mask, request);
1598
1599 err = tegra_io_pad_poll(pmc, status, mask, 0, 250);
1600 if (err < 0) {
1601 dev_err(pmc->dev, "failed to enable I/O pad: %d\n", err);
1602 goto unlock;
1603 }
1604
1605 tegra_io_pad_unprepare(pmc);
1606
1607 unlock:
1608 mutex_unlock(&pmc->powergates_lock);
1609 return err;
1610 }
1611 EXPORT_SYMBOL(tegra_io_pad_power_enable);
1612
1613 /**
1614 * tegra_io_pad_power_disable() - disable power to I/O pad
1615 * @id: Tegra I/O pad ID for which to disable power
1616 *
1617 * Returns: 0 on success or a negative error code on failure.
1618 */
tegra_io_pad_power_disable(enum tegra_io_pad id)1619 int tegra_io_pad_power_disable(enum tegra_io_pad id)
1620 {
1621 unsigned long request, status;
1622 u32 mask;
1623 int err;
1624
1625 mutex_lock(&pmc->powergates_lock);
1626
1627 err = tegra_io_pad_prepare(pmc, id, &request, &status, &mask);
1628 if (err < 0) {
1629 dev_err(pmc->dev, "failed to prepare I/O pad: %d\n", err);
1630 goto unlock;
1631 }
1632
1633 tegra_pmc_writel(pmc, IO_DPD_REQ_CODE_ON | mask, request);
1634
1635 err = tegra_io_pad_poll(pmc, status, mask, mask, 250);
1636 if (err < 0) {
1637 dev_err(pmc->dev, "failed to disable I/O pad: %d\n", err);
1638 goto unlock;
1639 }
1640
1641 tegra_io_pad_unprepare(pmc);
1642
1643 unlock:
1644 mutex_unlock(&pmc->powergates_lock);
1645 return err;
1646 }
1647 EXPORT_SYMBOL(tegra_io_pad_power_disable);
1648
tegra_io_pad_is_powered(struct tegra_pmc * pmc,enum tegra_io_pad id)1649 static int tegra_io_pad_is_powered(struct tegra_pmc *pmc, enum tegra_io_pad id)
1650 {
1651 unsigned long request, status;
1652 u32 mask, value;
1653 int err;
1654
1655 err = tegra_io_pad_get_dpd_register_bit(pmc, id, &request, &status,
1656 &mask);
1657 if (err)
1658 return err;
1659
1660 value = tegra_pmc_readl(pmc, status);
1661
1662 return !(value & mask);
1663 }
1664
tegra_io_pad_set_voltage(struct tegra_pmc * pmc,enum tegra_io_pad id,int voltage)1665 static int tegra_io_pad_set_voltage(struct tegra_pmc *pmc, enum tegra_io_pad id,
1666 int voltage)
1667 {
1668 const struct tegra_io_pad_soc *pad;
1669 u32 value;
1670
1671 pad = tegra_io_pad_find(pmc, id);
1672 if (!pad)
1673 return -ENOENT;
1674
1675 if (pad->voltage == UINT_MAX)
1676 return -ENOTSUPP;
1677
1678 mutex_lock(&pmc->powergates_lock);
1679
1680 if (pmc->soc->has_impl_33v_pwr) {
1681 value = tegra_pmc_readl(pmc, PMC_IMPL_E_33V_PWR);
1682
1683 if (voltage == TEGRA_IO_PAD_VOLTAGE_1V8)
1684 value &= ~BIT(pad->voltage);
1685 else
1686 value |= BIT(pad->voltage);
1687
1688 tegra_pmc_writel(pmc, value, PMC_IMPL_E_33V_PWR);
1689 } else {
1690 /* write-enable PMC_PWR_DET_VALUE[pad->voltage] */
1691 value = tegra_pmc_readl(pmc, PMC_PWR_DET);
1692 value |= BIT(pad->voltage);
1693 tegra_pmc_writel(pmc, value, PMC_PWR_DET);
1694
1695 /* update I/O voltage */
1696 value = tegra_pmc_readl(pmc, PMC_PWR_DET_VALUE);
1697
1698 if (voltage == TEGRA_IO_PAD_VOLTAGE_1V8)
1699 value &= ~BIT(pad->voltage);
1700 else
1701 value |= BIT(pad->voltage);
1702
1703 tegra_pmc_writel(pmc, value, PMC_PWR_DET_VALUE);
1704 }
1705
1706 mutex_unlock(&pmc->powergates_lock);
1707
1708 usleep_range(100, 250);
1709
1710 return 0;
1711 }
1712
tegra_io_pad_get_voltage(struct tegra_pmc * pmc,enum tegra_io_pad id)1713 static int tegra_io_pad_get_voltage(struct tegra_pmc *pmc, enum tegra_io_pad id)
1714 {
1715 const struct tegra_io_pad_soc *pad;
1716 u32 value;
1717
1718 pad = tegra_io_pad_find(pmc, id);
1719 if (!pad)
1720 return -ENOENT;
1721
1722 if (pad->voltage == UINT_MAX)
1723 return -ENOTSUPP;
1724
1725 if (pmc->soc->has_impl_33v_pwr)
1726 value = tegra_pmc_readl(pmc, PMC_IMPL_E_33V_PWR);
1727 else
1728 value = tegra_pmc_readl(pmc, PMC_PWR_DET_VALUE);
1729
1730 if ((value & BIT(pad->voltage)) == 0)
1731 return TEGRA_IO_PAD_VOLTAGE_1V8;
1732
1733 return TEGRA_IO_PAD_VOLTAGE_3V3;
1734 }
1735
1736 /**
1737 * tegra_io_rail_power_on() - enable power to I/O rail
1738 * @id: Tegra I/O pad ID for which to enable power
1739 *
1740 * See also: tegra_io_pad_power_enable()
1741 */
tegra_io_rail_power_on(unsigned int id)1742 int tegra_io_rail_power_on(unsigned int id)
1743 {
1744 return tegra_io_pad_power_enable(id);
1745 }
1746 EXPORT_SYMBOL(tegra_io_rail_power_on);
1747
1748 /**
1749 * tegra_io_rail_power_off() - disable power to I/O rail
1750 * @id: Tegra I/O pad ID for which to disable power
1751 *
1752 * See also: tegra_io_pad_power_disable()
1753 */
tegra_io_rail_power_off(unsigned int id)1754 int tegra_io_rail_power_off(unsigned int id)
1755 {
1756 return tegra_io_pad_power_disable(id);
1757 }
1758 EXPORT_SYMBOL(tegra_io_rail_power_off);
1759
1760 #ifdef CONFIG_PM_SLEEP
tegra_pmc_get_suspend_mode(void)1761 enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void)
1762 {
1763 return pmc->suspend_mode;
1764 }
1765
tegra_pmc_set_suspend_mode(enum tegra_suspend_mode mode)1766 void tegra_pmc_set_suspend_mode(enum tegra_suspend_mode mode)
1767 {
1768 if (mode < TEGRA_SUSPEND_NONE || mode >= TEGRA_MAX_SUSPEND_MODE)
1769 return;
1770
1771 pmc->suspend_mode = mode;
1772 }
1773
tegra_pmc_enter_suspend_mode(enum tegra_suspend_mode mode)1774 void tegra_pmc_enter_suspend_mode(enum tegra_suspend_mode mode)
1775 {
1776 unsigned long long rate = 0;
1777 u64 ticks;
1778 u32 value;
1779
1780 switch (mode) {
1781 case TEGRA_SUSPEND_LP1:
1782 rate = 32768;
1783 break;
1784
1785 case TEGRA_SUSPEND_LP2:
1786 rate = pmc->rate;
1787 break;
1788
1789 default:
1790 break;
1791 }
1792
1793 if (WARN_ON_ONCE(rate == 0))
1794 rate = 100000000;
1795
1796 ticks = pmc->cpu_good_time * rate + USEC_PER_SEC - 1;
1797 do_div(ticks, USEC_PER_SEC);
1798 tegra_pmc_writel(pmc, ticks, PMC_CPUPWRGOOD_TIMER);
1799
1800 ticks = pmc->cpu_off_time * rate + USEC_PER_SEC - 1;
1801 do_div(ticks, USEC_PER_SEC);
1802 tegra_pmc_writel(pmc, ticks, PMC_CPUPWROFF_TIMER);
1803
1804 value = tegra_pmc_readl(pmc, PMC_CNTRL);
1805 value &= ~PMC_CNTRL_SIDE_EFFECT_LP0;
1806 value |= PMC_CNTRL_CPU_PWRREQ_OE;
1807 tegra_pmc_writel(pmc, value, PMC_CNTRL);
1808 }
1809 #endif
1810
tegra_pmc_parse_dt(struct tegra_pmc * pmc,struct device_node * np)1811 static int tegra_pmc_parse_dt(struct tegra_pmc *pmc, struct device_node *np)
1812 {
1813 u32 value, values[2];
1814
1815 if (of_property_read_u32(np, "nvidia,suspend-mode", &value)) {
1816 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1817 } else {
1818 switch (value) {
1819 case 0:
1820 pmc->suspend_mode = TEGRA_SUSPEND_LP0;
1821 break;
1822
1823 case 1:
1824 pmc->suspend_mode = TEGRA_SUSPEND_LP1;
1825 break;
1826
1827 case 2:
1828 pmc->suspend_mode = TEGRA_SUSPEND_LP2;
1829 break;
1830
1831 default:
1832 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1833 break;
1834 }
1835 }
1836
1837 pmc->suspend_mode = tegra_pm_validate_suspend_mode(pmc->suspend_mode);
1838
1839 if (of_property_read_u32(np, "nvidia,cpu-pwr-good-time", &value))
1840 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1841
1842 pmc->cpu_good_time = value;
1843
1844 if (of_property_read_u32(np, "nvidia,cpu-pwr-off-time", &value))
1845 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1846
1847 pmc->cpu_off_time = value;
1848
1849 if (of_property_read_u32_array(np, "nvidia,core-pwr-good-time",
1850 values, ARRAY_SIZE(values)))
1851 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1852
1853 pmc->core_osc_time = values[0];
1854 pmc->core_pmu_time = values[1];
1855
1856 if (of_property_read_u32(np, "nvidia,core-pwr-off-time", &value))
1857 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1858
1859 pmc->core_off_time = value;
1860
1861 pmc->corereq_high = of_property_read_bool(np,
1862 "nvidia,core-power-req-active-high");
1863
1864 pmc->sysclkreq_high = of_property_read_bool(np,
1865 "nvidia,sys-clock-req-active-high");
1866
1867 pmc->combined_req = of_property_read_bool(np,
1868 "nvidia,combined-power-req");
1869
1870 pmc->cpu_pwr_good_en = of_property_read_bool(np,
1871 "nvidia,cpu-pwr-good-en");
1872
1873 if (of_property_read_u32_array(np, "nvidia,lp0-vec", values,
1874 ARRAY_SIZE(values)))
1875 if (pmc->suspend_mode == TEGRA_SUSPEND_LP0)
1876 pmc->suspend_mode = TEGRA_SUSPEND_LP1;
1877
1878 pmc->lp0_vec_phys = values[0];
1879 pmc->lp0_vec_size = values[1];
1880
1881 return 0;
1882 }
1883
tegra_pmc_init(struct tegra_pmc * pmc)1884 static void tegra_pmc_init(struct tegra_pmc *pmc)
1885 {
1886 if (pmc->soc->init)
1887 pmc->soc->init(pmc);
1888 }
1889
tegra_pmc_init_tsense_reset(struct tegra_pmc * pmc)1890 static void tegra_pmc_init_tsense_reset(struct tegra_pmc *pmc)
1891 {
1892 static const char disabled[] = "emergency thermal reset disabled";
1893 u32 pmu_addr, ctrl_id, reg_addr, reg_data, pinmux;
1894 struct device *dev = pmc->dev;
1895 struct device_node *np;
1896 u32 value, checksum;
1897
1898 if (!pmc->soc->has_tsense_reset)
1899 return;
1900
1901 np = of_get_child_by_name(pmc->dev->of_node, "i2c-thermtrip");
1902 if (!np) {
1903 dev_warn(dev, "i2c-thermtrip node not found, %s.\n", disabled);
1904 return;
1905 }
1906
1907 if (of_property_read_u32(np, "nvidia,i2c-controller-id", &ctrl_id)) {
1908 dev_err(dev, "I2C controller ID missing, %s.\n", disabled);
1909 goto out;
1910 }
1911
1912 if (of_property_read_u32(np, "nvidia,bus-addr", &pmu_addr)) {
1913 dev_err(dev, "nvidia,bus-addr missing, %s.\n", disabled);
1914 goto out;
1915 }
1916
1917 if (of_property_read_u32(np, "nvidia,reg-addr", ®_addr)) {
1918 dev_err(dev, "nvidia,reg-addr missing, %s.\n", disabled);
1919 goto out;
1920 }
1921
1922 if (of_property_read_u32(np, "nvidia,reg-data", ®_data)) {
1923 dev_err(dev, "nvidia,reg-data missing, %s.\n", disabled);
1924 goto out;
1925 }
1926
1927 if (of_property_read_u32(np, "nvidia,pinmux-id", &pinmux))
1928 pinmux = 0;
1929
1930 value = tegra_pmc_readl(pmc, PMC_SENSOR_CTRL);
1931 value |= PMC_SENSOR_CTRL_SCRATCH_WRITE;
1932 tegra_pmc_writel(pmc, value, PMC_SENSOR_CTRL);
1933
1934 value = (reg_data << PMC_SCRATCH54_DATA_SHIFT) |
1935 (reg_addr << PMC_SCRATCH54_ADDR_SHIFT);
1936 tegra_pmc_writel(pmc, value, PMC_SCRATCH54);
1937
1938 value = PMC_SCRATCH55_RESET_TEGRA;
1939 value |= ctrl_id << PMC_SCRATCH55_CNTRL_ID_SHIFT;
1940 value |= pinmux << PMC_SCRATCH55_PINMUX_SHIFT;
1941 value |= pmu_addr << PMC_SCRATCH55_I2CSLV1_SHIFT;
1942
1943 /*
1944 * Calculate checksum of SCRATCH54, SCRATCH55 fields. Bits 23:16 will
1945 * contain the checksum and are currently zero, so they are not added.
1946 */
1947 checksum = reg_addr + reg_data + (value & 0xff) + ((value >> 8) & 0xff)
1948 + ((value >> 24) & 0xff);
1949 checksum &= 0xff;
1950 checksum = 0x100 - checksum;
1951
1952 value |= checksum << PMC_SCRATCH55_CHECKSUM_SHIFT;
1953
1954 tegra_pmc_writel(pmc, value, PMC_SCRATCH55);
1955
1956 value = tegra_pmc_readl(pmc, PMC_SENSOR_CTRL);
1957 value |= PMC_SENSOR_CTRL_ENABLE_RST;
1958 tegra_pmc_writel(pmc, value, PMC_SENSOR_CTRL);
1959
1960 dev_info(pmc->dev, "emergency thermal reset enabled\n");
1961
1962 out:
1963 of_node_put(np);
1964 }
1965
tegra_io_pad_pinctrl_get_groups_count(struct pinctrl_dev * pctl_dev)1966 static int tegra_io_pad_pinctrl_get_groups_count(struct pinctrl_dev *pctl_dev)
1967 {
1968 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev);
1969
1970 return pmc->soc->num_io_pads;
1971 }
1972
tegra_io_pad_pinctrl_get_group_name(struct pinctrl_dev * pctl,unsigned int group)1973 static const char *tegra_io_pad_pinctrl_get_group_name(struct pinctrl_dev *pctl,
1974 unsigned int group)
1975 {
1976 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl);
1977
1978 return pmc->soc->io_pads[group].name;
1979 }
1980
tegra_io_pad_pinctrl_get_group_pins(struct pinctrl_dev * pctl_dev,unsigned int group,const unsigned int ** pins,unsigned int * num_pins)1981 static int tegra_io_pad_pinctrl_get_group_pins(struct pinctrl_dev *pctl_dev,
1982 unsigned int group,
1983 const unsigned int **pins,
1984 unsigned int *num_pins)
1985 {
1986 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev);
1987
1988 *pins = &pmc->soc->io_pads[group].id;
1989 *num_pins = 1;
1990
1991 return 0;
1992 }
1993
1994 static const struct pinctrl_ops tegra_io_pad_pinctrl_ops = {
1995 .get_groups_count = tegra_io_pad_pinctrl_get_groups_count,
1996 .get_group_name = tegra_io_pad_pinctrl_get_group_name,
1997 .get_group_pins = tegra_io_pad_pinctrl_get_group_pins,
1998 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
1999 .dt_free_map = pinconf_generic_dt_free_map,
2000 };
2001
tegra_io_pad_pinconf_get(struct pinctrl_dev * pctl_dev,unsigned int pin,unsigned long * config)2002 static int tegra_io_pad_pinconf_get(struct pinctrl_dev *pctl_dev,
2003 unsigned int pin, unsigned long *config)
2004 {
2005 enum pin_config_param param = pinconf_to_config_param(*config);
2006 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev);
2007 const struct tegra_io_pad_soc *pad;
2008 int ret;
2009 u32 arg;
2010
2011 pad = tegra_io_pad_find(pmc, pin);
2012 if (!pad)
2013 return -EINVAL;
2014
2015 switch (param) {
2016 case PIN_CONFIG_POWER_SOURCE:
2017 ret = tegra_io_pad_get_voltage(pmc, pad->id);
2018 if (ret < 0)
2019 return ret;
2020
2021 arg = ret;
2022 break;
2023
2024 case PIN_CONFIG_MODE_LOW_POWER:
2025 ret = tegra_io_pad_is_powered(pmc, pad->id);
2026 if (ret < 0)
2027 return ret;
2028
2029 arg = !ret;
2030 break;
2031
2032 default:
2033 return -EINVAL;
2034 }
2035
2036 *config = pinconf_to_config_packed(param, arg);
2037
2038 return 0;
2039 }
2040
tegra_io_pad_pinconf_set(struct pinctrl_dev * pctl_dev,unsigned int pin,unsigned long * configs,unsigned int num_configs)2041 static int tegra_io_pad_pinconf_set(struct pinctrl_dev *pctl_dev,
2042 unsigned int pin, unsigned long *configs,
2043 unsigned int num_configs)
2044 {
2045 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev);
2046 const struct tegra_io_pad_soc *pad;
2047 enum pin_config_param param;
2048 unsigned int i;
2049 int err;
2050 u32 arg;
2051
2052 pad = tegra_io_pad_find(pmc, pin);
2053 if (!pad)
2054 return -EINVAL;
2055
2056 for (i = 0; i < num_configs; ++i) {
2057 param = pinconf_to_config_param(configs[i]);
2058 arg = pinconf_to_config_argument(configs[i]);
2059
2060 switch (param) {
2061 case PIN_CONFIG_MODE_LOW_POWER:
2062 if (arg)
2063 err = tegra_io_pad_power_disable(pad->id);
2064 else
2065 err = tegra_io_pad_power_enable(pad->id);
2066 if (err)
2067 return err;
2068 break;
2069 case PIN_CONFIG_POWER_SOURCE:
2070 if (arg != TEGRA_IO_PAD_VOLTAGE_1V8 &&
2071 arg != TEGRA_IO_PAD_VOLTAGE_3V3)
2072 return -EINVAL;
2073 err = tegra_io_pad_set_voltage(pmc, pad->id, arg);
2074 if (err)
2075 return err;
2076 break;
2077 default:
2078 return -EINVAL;
2079 }
2080 }
2081
2082 return 0;
2083 }
2084
2085 static const struct pinconf_ops tegra_io_pad_pinconf_ops = {
2086 .pin_config_get = tegra_io_pad_pinconf_get,
2087 .pin_config_set = tegra_io_pad_pinconf_set,
2088 .is_generic = true,
2089 };
2090
2091 static struct pinctrl_desc tegra_pmc_pctl_desc = {
2092 .pctlops = &tegra_io_pad_pinctrl_ops,
2093 .confops = &tegra_io_pad_pinconf_ops,
2094 };
2095
tegra_pmc_pinctrl_init(struct tegra_pmc * pmc)2096 static int tegra_pmc_pinctrl_init(struct tegra_pmc *pmc)
2097 {
2098 int err;
2099
2100 if (!pmc->soc->num_pin_descs)
2101 return 0;
2102
2103 tegra_pmc_pctl_desc.name = dev_name(pmc->dev);
2104 tegra_pmc_pctl_desc.pins = pmc->soc->pin_descs;
2105 tegra_pmc_pctl_desc.npins = pmc->soc->num_pin_descs;
2106
2107 pmc->pctl_dev = devm_pinctrl_register(pmc->dev, &tegra_pmc_pctl_desc,
2108 pmc);
2109 if (IS_ERR(pmc->pctl_dev)) {
2110 err = PTR_ERR(pmc->pctl_dev);
2111 dev_err(pmc->dev, "failed to register pin controller: %d\n",
2112 err);
2113 return err;
2114 }
2115
2116 return 0;
2117 }
2118
reset_reason_show(struct device * dev,struct device_attribute * attr,char * buf)2119 static ssize_t reset_reason_show(struct device *dev,
2120 struct device_attribute *attr, char *buf)
2121 {
2122 u32 value;
2123
2124 value = tegra_pmc_readl(pmc, pmc->soc->regs->rst_status);
2125 value &= pmc->soc->regs->rst_source_mask;
2126 value >>= pmc->soc->regs->rst_source_shift;
2127
2128 if (WARN_ON(value >= pmc->soc->num_reset_sources))
2129 return sprintf(buf, "%s\n", "UNKNOWN");
2130
2131 return sprintf(buf, "%s\n", pmc->soc->reset_sources[value]);
2132 }
2133
2134 static DEVICE_ATTR_RO(reset_reason);
2135
reset_level_show(struct device * dev,struct device_attribute * attr,char * buf)2136 static ssize_t reset_level_show(struct device *dev,
2137 struct device_attribute *attr, char *buf)
2138 {
2139 u32 value;
2140
2141 value = tegra_pmc_readl(pmc, pmc->soc->regs->rst_status);
2142 value &= pmc->soc->regs->rst_level_mask;
2143 value >>= pmc->soc->regs->rst_level_shift;
2144
2145 if (WARN_ON(value >= pmc->soc->num_reset_levels))
2146 return sprintf(buf, "%s\n", "UNKNOWN");
2147
2148 return sprintf(buf, "%s\n", pmc->soc->reset_levels[value]);
2149 }
2150
2151 static DEVICE_ATTR_RO(reset_level);
2152
tegra_pmc_reset_sysfs_init(struct tegra_pmc * pmc)2153 static void tegra_pmc_reset_sysfs_init(struct tegra_pmc *pmc)
2154 {
2155 struct device *dev = pmc->dev;
2156 int err = 0;
2157
2158 if (pmc->soc->reset_sources) {
2159 err = device_create_file(dev, &dev_attr_reset_reason);
2160 if (err < 0)
2161 dev_warn(dev,
2162 "failed to create attr \"reset_reason\": %d\n",
2163 err);
2164 }
2165
2166 if (pmc->soc->reset_levels) {
2167 err = device_create_file(dev, &dev_attr_reset_level);
2168 if (err < 0)
2169 dev_warn(dev,
2170 "failed to create attr \"reset_level\": %d\n",
2171 err);
2172 }
2173 }
2174
tegra_pmc_irq_translate(struct irq_domain * domain,struct irq_fwspec * fwspec,unsigned long * hwirq,unsigned int * type)2175 static int tegra_pmc_irq_translate(struct irq_domain *domain,
2176 struct irq_fwspec *fwspec,
2177 unsigned long *hwirq,
2178 unsigned int *type)
2179 {
2180 if (WARN_ON(fwspec->param_count < 2))
2181 return -EINVAL;
2182
2183 *hwirq = fwspec->param[0];
2184 *type = fwspec->param[1];
2185
2186 return 0;
2187 }
2188
tegra_pmc_irq_alloc(struct irq_domain * domain,unsigned int virq,unsigned int num_irqs,void * data)2189 static int tegra_pmc_irq_alloc(struct irq_domain *domain, unsigned int virq,
2190 unsigned int num_irqs, void *data)
2191 {
2192 struct tegra_pmc *pmc = domain->host_data;
2193 const struct tegra_pmc_soc *soc = pmc->soc;
2194 struct irq_fwspec *fwspec = data;
2195 unsigned int i;
2196 int err = 0;
2197
2198 if (WARN_ON(num_irqs > 1))
2199 return -EINVAL;
2200
2201 for (i = 0; i < soc->num_wake_events; i++) {
2202 const struct tegra_wake_event *event = &soc->wake_events[i];
2203
2204 if (fwspec->param_count == 2) {
2205 struct irq_fwspec spec;
2206
2207 if (event->id != fwspec->param[0])
2208 continue;
2209
2210 err = irq_domain_set_hwirq_and_chip(domain, virq,
2211 event->id,
2212 &pmc->irq, pmc);
2213 if (err < 0)
2214 break;
2215
2216 spec.fwnode = &pmc->dev->of_node->fwnode;
2217 spec.param_count = 3;
2218 spec.param[0] = GIC_SPI;
2219 spec.param[1] = event->irq;
2220 spec.param[2] = fwspec->param[1];
2221
2222 err = irq_domain_alloc_irqs_parent(domain, virq,
2223 num_irqs, &spec);
2224
2225 break;
2226 }
2227
2228 if (fwspec->param_count == 3) {
2229 if (event->gpio.instance != fwspec->param[0] ||
2230 event->gpio.pin != fwspec->param[1])
2231 continue;
2232
2233 err = irq_domain_set_hwirq_and_chip(domain, virq,
2234 event->id,
2235 &pmc->irq, pmc);
2236
2237 /* GPIO hierarchies stop at the PMC level */
2238 if (!err && domain->parent)
2239 err = irq_domain_disconnect_hierarchy(domain->parent,
2240 virq);
2241 break;
2242 }
2243 }
2244
2245 /* If there is no wake-up event, there is no PMC mapping */
2246 if (i == soc->num_wake_events)
2247 err = irq_domain_disconnect_hierarchy(domain, virq);
2248
2249 return err;
2250 }
2251
2252 static const struct irq_domain_ops tegra_pmc_irq_domain_ops = {
2253 .translate = tegra_pmc_irq_translate,
2254 .alloc = tegra_pmc_irq_alloc,
2255 };
2256
tegra210_pmc_irq_set_wake(struct irq_data * data,unsigned int on)2257 static int tegra210_pmc_irq_set_wake(struct irq_data *data, unsigned int on)
2258 {
2259 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data);
2260 unsigned int offset, bit;
2261 u32 value;
2262
2263 offset = data->hwirq / 32;
2264 bit = data->hwirq % 32;
2265
2266 /* clear wake status */
2267 tegra_pmc_writel(pmc, 0, PMC_SW_WAKE_STATUS);
2268 tegra_pmc_writel(pmc, 0, PMC_SW_WAKE2_STATUS);
2269
2270 tegra_pmc_writel(pmc, 0, PMC_WAKE_STATUS);
2271 tegra_pmc_writel(pmc, 0, PMC_WAKE2_STATUS);
2272
2273 /* enable PMC wake */
2274 if (data->hwirq >= 32)
2275 offset = PMC_WAKE2_MASK;
2276 else
2277 offset = PMC_WAKE_MASK;
2278
2279 value = tegra_pmc_readl(pmc, offset);
2280
2281 if (on)
2282 value |= BIT(bit);
2283 else
2284 value &= ~BIT(bit);
2285
2286 tegra_pmc_writel(pmc, value, offset);
2287
2288 return 0;
2289 }
2290
tegra210_pmc_irq_set_type(struct irq_data * data,unsigned int type)2291 static int tegra210_pmc_irq_set_type(struct irq_data *data, unsigned int type)
2292 {
2293 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data);
2294 unsigned int offset, bit;
2295 u32 value;
2296
2297 offset = data->hwirq / 32;
2298 bit = data->hwirq % 32;
2299
2300 if (data->hwirq >= 32)
2301 offset = PMC_WAKE2_LEVEL;
2302 else
2303 offset = PMC_WAKE_LEVEL;
2304
2305 value = tegra_pmc_readl(pmc, offset);
2306
2307 switch (type) {
2308 case IRQ_TYPE_EDGE_RISING:
2309 case IRQ_TYPE_LEVEL_HIGH:
2310 value |= BIT(bit);
2311 break;
2312
2313 case IRQ_TYPE_EDGE_FALLING:
2314 case IRQ_TYPE_LEVEL_LOW:
2315 value &= ~BIT(bit);
2316 break;
2317
2318 case IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING:
2319 value ^= BIT(bit);
2320 break;
2321
2322 default:
2323 return -EINVAL;
2324 }
2325
2326 tegra_pmc_writel(pmc, value, offset);
2327
2328 return 0;
2329 }
2330
tegra186_pmc_irq_set_wake(struct irq_data * data,unsigned int on)2331 static int tegra186_pmc_irq_set_wake(struct irq_data *data, unsigned int on)
2332 {
2333 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data);
2334 unsigned int offset, bit;
2335 u32 value;
2336
2337 offset = data->hwirq / 32;
2338 bit = data->hwirq % 32;
2339
2340 /* clear wake status */
2341 writel(0x1, pmc->wake + WAKE_AOWAKE_STATUS_W(data->hwirq));
2342
2343 /* route wake to tier 2 */
2344 value = readl(pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(offset));
2345
2346 if (!on)
2347 value &= ~(1 << bit);
2348 else
2349 value |= 1 << bit;
2350
2351 writel(value, pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(offset));
2352
2353 /* enable wakeup event */
2354 writel(!!on, pmc->wake + WAKE_AOWAKE_MASK_W(data->hwirq));
2355
2356 return 0;
2357 }
2358
tegra186_pmc_irq_set_type(struct irq_data * data,unsigned int type)2359 static int tegra186_pmc_irq_set_type(struct irq_data *data, unsigned int type)
2360 {
2361 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data);
2362 u32 value;
2363
2364 value = readl(pmc->wake + WAKE_AOWAKE_CNTRL(data->hwirq));
2365
2366 switch (type) {
2367 case IRQ_TYPE_EDGE_RISING:
2368 case IRQ_TYPE_LEVEL_HIGH:
2369 value |= WAKE_AOWAKE_CNTRL_LEVEL;
2370 break;
2371
2372 case IRQ_TYPE_EDGE_FALLING:
2373 case IRQ_TYPE_LEVEL_LOW:
2374 value &= ~WAKE_AOWAKE_CNTRL_LEVEL;
2375 break;
2376
2377 case IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING:
2378 value ^= WAKE_AOWAKE_CNTRL_LEVEL;
2379 break;
2380
2381 default:
2382 return -EINVAL;
2383 }
2384
2385 writel(value, pmc->wake + WAKE_AOWAKE_CNTRL(data->hwirq));
2386
2387 return 0;
2388 }
2389
tegra_irq_mask_parent(struct irq_data * data)2390 static void tegra_irq_mask_parent(struct irq_data *data)
2391 {
2392 if (data->parent_data)
2393 irq_chip_mask_parent(data);
2394 }
2395
tegra_irq_unmask_parent(struct irq_data * data)2396 static void tegra_irq_unmask_parent(struct irq_data *data)
2397 {
2398 if (data->parent_data)
2399 irq_chip_unmask_parent(data);
2400 }
2401
tegra_irq_eoi_parent(struct irq_data * data)2402 static void tegra_irq_eoi_parent(struct irq_data *data)
2403 {
2404 if (data->parent_data)
2405 irq_chip_eoi_parent(data);
2406 }
2407
tegra_irq_set_affinity_parent(struct irq_data * data,const struct cpumask * dest,bool force)2408 static int tegra_irq_set_affinity_parent(struct irq_data *data,
2409 const struct cpumask *dest,
2410 bool force)
2411 {
2412 if (data->parent_data)
2413 return irq_chip_set_affinity_parent(data, dest, force);
2414
2415 return -EINVAL;
2416 }
2417
tegra_pmc_irq_init(struct tegra_pmc * pmc)2418 static int tegra_pmc_irq_init(struct tegra_pmc *pmc)
2419 {
2420 struct irq_domain *parent = NULL;
2421 struct device_node *np;
2422
2423 np = of_irq_find_parent(pmc->dev->of_node);
2424 if (np) {
2425 parent = irq_find_host(np);
2426 of_node_put(np);
2427 }
2428
2429 if (!parent)
2430 return 0;
2431
2432 pmc->irq.name = dev_name(pmc->dev);
2433 pmc->irq.irq_mask = tegra_irq_mask_parent;
2434 pmc->irq.irq_unmask = tegra_irq_unmask_parent;
2435 pmc->irq.irq_eoi = tegra_irq_eoi_parent;
2436 pmc->irq.irq_set_affinity = tegra_irq_set_affinity_parent;
2437 pmc->irq.irq_set_type = pmc->soc->irq_set_type;
2438 pmc->irq.irq_set_wake = pmc->soc->irq_set_wake;
2439
2440 pmc->domain = irq_domain_add_hierarchy(parent, 0, 96, pmc->dev->of_node,
2441 &tegra_pmc_irq_domain_ops, pmc);
2442 if (!pmc->domain) {
2443 dev_err(pmc->dev, "failed to allocate domain\n");
2444 return -ENOMEM;
2445 }
2446
2447 return 0;
2448 }
2449
tegra_pmc_clk_notify_cb(struct notifier_block * nb,unsigned long action,void * ptr)2450 static int tegra_pmc_clk_notify_cb(struct notifier_block *nb,
2451 unsigned long action, void *ptr)
2452 {
2453 struct tegra_pmc *pmc = container_of(nb, struct tegra_pmc, clk_nb);
2454 struct clk_notifier_data *data = ptr;
2455
2456 switch (action) {
2457 case PRE_RATE_CHANGE:
2458 mutex_lock(&pmc->powergates_lock);
2459 break;
2460
2461 case POST_RATE_CHANGE:
2462 pmc->rate = data->new_rate;
2463 fallthrough;
2464
2465 case ABORT_RATE_CHANGE:
2466 mutex_unlock(&pmc->powergates_lock);
2467 break;
2468
2469 default:
2470 WARN_ON_ONCE(1);
2471 return notifier_from_errno(-EINVAL);
2472 }
2473
2474 return NOTIFY_OK;
2475 }
2476
pmc_clk_fence_udelay(u32 offset)2477 static void pmc_clk_fence_udelay(u32 offset)
2478 {
2479 tegra_pmc_readl(pmc, offset);
2480 /* pmc clk propagation delay 2 us */
2481 udelay(2);
2482 }
2483
pmc_clk_mux_get_parent(struct clk_hw * hw)2484 static u8 pmc_clk_mux_get_parent(struct clk_hw *hw)
2485 {
2486 struct pmc_clk *clk = to_pmc_clk(hw);
2487 u32 val;
2488
2489 val = tegra_pmc_readl(pmc, clk->offs) >> clk->mux_shift;
2490 val &= PMC_CLK_OUT_MUX_MASK;
2491
2492 return val;
2493 }
2494
pmc_clk_mux_set_parent(struct clk_hw * hw,u8 index)2495 static int pmc_clk_mux_set_parent(struct clk_hw *hw, u8 index)
2496 {
2497 struct pmc_clk *clk = to_pmc_clk(hw);
2498 u32 val;
2499
2500 val = tegra_pmc_readl(pmc, clk->offs);
2501 val &= ~(PMC_CLK_OUT_MUX_MASK << clk->mux_shift);
2502 val |= index << clk->mux_shift;
2503 tegra_pmc_writel(pmc, val, clk->offs);
2504 pmc_clk_fence_udelay(clk->offs);
2505
2506 return 0;
2507 }
2508
pmc_clk_is_enabled(struct clk_hw * hw)2509 static int pmc_clk_is_enabled(struct clk_hw *hw)
2510 {
2511 struct pmc_clk *clk = to_pmc_clk(hw);
2512 u32 val;
2513
2514 val = tegra_pmc_readl(pmc, clk->offs) & BIT(clk->force_en_shift);
2515
2516 return val ? 1 : 0;
2517 }
2518
pmc_clk_set_state(unsigned long offs,u32 shift,int state)2519 static void pmc_clk_set_state(unsigned long offs, u32 shift, int state)
2520 {
2521 u32 val;
2522
2523 val = tegra_pmc_readl(pmc, offs);
2524 val = state ? (val | BIT(shift)) : (val & ~BIT(shift));
2525 tegra_pmc_writel(pmc, val, offs);
2526 pmc_clk_fence_udelay(offs);
2527 }
2528
pmc_clk_enable(struct clk_hw * hw)2529 static int pmc_clk_enable(struct clk_hw *hw)
2530 {
2531 struct pmc_clk *clk = to_pmc_clk(hw);
2532
2533 pmc_clk_set_state(clk->offs, clk->force_en_shift, 1);
2534
2535 return 0;
2536 }
2537
pmc_clk_disable(struct clk_hw * hw)2538 static void pmc_clk_disable(struct clk_hw *hw)
2539 {
2540 struct pmc_clk *clk = to_pmc_clk(hw);
2541
2542 pmc_clk_set_state(clk->offs, clk->force_en_shift, 0);
2543 }
2544
2545 static const struct clk_ops pmc_clk_ops = {
2546 .get_parent = pmc_clk_mux_get_parent,
2547 .set_parent = pmc_clk_mux_set_parent,
2548 .determine_rate = __clk_mux_determine_rate,
2549 .is_enabled = pmc_clk_is_enabled,
2550 .enable = pmc_clk_enable,
2551 .disable = pmc_clk_disable,
2552 };
2553
2554 static struct clk *
tegra_pmc_clk_out_register(struct tegra_pmc * pmc,const struct pmc_clk_init_data * data,unsigned long offset)2555 tegra_pmc_clk_out_register(struct tegra_pmc *pmc,
2556 const struct pmc_clk_init_data *data,
2557 unsigned long offset)
2558 {
2559 struct clk_init_data init;
2560 struct pmc_clk *pmc_clk;
2561
2562 pmc_clk = devm_kzalloc(pmc->dev, sizeof(*pmc_clk), GFP_KERNEL);
2563 if (!pmc_clk)
2564 return ERR_PTR(-ENOMEM);
2565
2566 init.name = data->name;
2567 init.ops = &pmc_clk_ops;
2568 init.parent_names = data->parents;
2569 init.num_parents = data->num_parents;
2570 init.flags = CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT |
2571 CLK_SET_PARENT_GATE;
2572
2573 pmc_clk->hw.init = &init;
2574 pmc_clk->offs = offset;
2575 pmc_clk->mux_shift = data->mux_shift;
2576 pmc_clk->force_en_shift = data->force_en_shift;
2577
2578 return clk_register(NULL, &pmc_clk->hw);
2579 }
2580
pmc_clk_gate_is_enabled(struct clk_hw * hw)2581 static int pmc_clk_gate_is_enabled(struct clk_hw *hw)
2582 {
2583 struct pmc_clk_gate *gate = to_pmc_clk_gate(hw);
2584
2585 return tegra_pmc_readl(pmc, gate->offs) & BIT(gate->shift) ? 1 : 0;
2586 }
2587
pmc_clk_gate_enable(struct clk_hw * hw)2588 static int pmc_clk_gate_enable(struct clk_hw *hw)
2589 {
2590 struct pmc_clk_gate *gate = to_pmc_clk_gate(hw);
2591
2592 pmc_clk_set_state(gate->offs, gate->shift, 1);
2593
2594 return 0;
2595 }
2596
pmc_clk_gate_disable(struct clk_hw * hw)2597 static void pmc_clk_gate_disable(struct clk_hw *hw)
2598 {
2599 struct pmc_clk_gate *gate = to_pmc_clk_gate(hw);
2600
2601 pmc_clk_set_state(gate->offs, gate->shift, 0);
2602 }
2603
2604 static const struct clk_ops pmc_clk_gate_ops = {
2605 .is_enabled = pmc_clk_gate_is_enabled,
2606 .enable = pmc_clk_gate_enable,
2607 .disable = pmc_clk_gate_disable,
2608 };
2609
2610 static struct clk *
tegra_pmc_clk_gate_register(struct tegra_pmc * pmc,const char * name,const char * parent_name,unsigned long offset,u32 shift)2611 tegra_pmc_clk_gate_register(struct tegra_pmc *pmc, const char *name,
2612 const char *parent_name, unsigned long offset,
2613 u32 shift)
2614 {
2615 struct clk_init_data init;
2616 struct pmc_clk_gate *gate;
2617
2618 gate = devm_kzalloc(pmc->dev, sizeof(*gate), GFP_KERNEL);
2619 if (!gate)
2620 return ERR_PTR(-ENOMEM);
2621
2622 init.name = name;
2623 init.ops = &pmc_clk_gate_ops;
2624 init.parent_names = &parent_name;
2625 init.num_parents = 1;
2626 init.flags = 0;
2627
2628 gate->hw.init = &init;
2629 gate->offs = offset;
2630 gate->shift = shift;
2631
2632 return clk_register(NULL, &gate->hw);
2633 }
2634
tegra_pmc_clock_register(struct tegra_pmc * pmc,struct device_node * np)2635 static void tegra_pmc_clock_register(struct tegra_pmc *pmc,
2636 struct device_node *np)
2637 {
2638 struct clk *clk;
2639 struct clk_onecell_data *clk_data;
2640 unsigned int num_clks;
2641 int i, err;
2642
2643 num_clks = pmc->soc->num_pmc_clks;
2644 if (pmc->soc->has_blink_output)
2645 num_clks += 1;
2646
2647 if (!num_clks)
2648 return;
2649
2650 clk_data = devm_kmalloc(pmc->dev, sizeof(*clk_data), GFP_KERNEL);
2651 if (!clk_data)
2652 return;
2653
2654 clk_data->clks = devm_kcalloc(pmc->dev, TEGRA_PMC_CLK_MAX,
2655 sizeof(*clk_data->clks), GFP_KERNEL);
2656 if (!clk_data->clks)
2657 return;
2658
2659 clk_data->clk_num = TEGRA_PMC_CLK_MAX;
2660
2661 for (i = 0; i < TEGRA_PMC_CLK_MAX; i++)
2662 clk_data->clks[i] = ERR_PTR(-ENOENT);
2663
2664 for (i = 0; i < pmc->soc->num_pmc_clks; i++) {
2665 const struct pmc_clk_init_data *data;
2666
2667 data = pmc->soc->pmc_clks_data + i;
2668
2669 clk = tegra_pmc_clk_out_register(pmc, data, PMC_CLK_OUT_CNTRL);
2670 if (IS_ERR(clk)) {
2671 dev_warn(pmc->dev, "unable to register clock %s: %d\n",
2672 data->name, PTR_ERR_OR_ZERO(clk));
2673 return;
2674 }
2675
2676 err = clk_register_clkdev(clk, data->name, NULL);
2677 if (err) {
2678 dev_warn(pmc->dev,
2679 "unable to register %s clock lookup: %d\n",
2680 data->name, err);
2681 return;
2682 }
2683
2684 clk_data->clks[data->clk_id] = clk;
2685 }
2686
2687 if (pmc->soc->has_blink_output) {
2688 tegra_pmc_writel(pmc, 0x0, PMC_BLINK_TIMER);
2689 clk = tegra_pmc_clk_gate_register(pmc,
2690 "pmc_blink_override",
2691 "clk_32k",
2692 PMC_DPD_PADS_ORIDE,
2693 PMC_DPD_PADS_ORIDE_BLINK);
2694 if (IS_ERR(clk)) {
2695 dev_warn(pmc->dev,
2696 "unable to register pmc_blink_override: %d\n",
2697 PTR_ERR_OR_ZERO(clk));
2698 return;
2699 }
2700
2701 clk = tegra_pmc_clk_gate_register(pmc, "pmc_blink",
2702 "pmc_blink_override",
2703 PMC_CNTRL,
2704 PMC_CNTRL_BLINK_EN);
2705 if (IS_ERR(clk)) {
2706 dev_warn(pmc->dev,
2707 "unable to register pmc_blink: %d\n",
2708 PTR_ERR_OR_ZERO(clk));
2709 return;
2710 }
2711
2712 err = clk_register_clkdev(clk, "pmc_blink", NULL);
2713 if (err) {
2714 dev_warn(pmc->dev,
2715 "unable to register pmc_blink lookup: %d\n",
2716 err);
2717 return;
2718 }
2719
2720 clk_data->clks[TEGRA_PMC_CLK_BLINK] = clk;
2721 }
2722
2723 err = of_clk_add_provider(np, of_clk_src_onecell_get, clk_data);
2724 if (err)
2725 dev_warn(pmc->dev, "failed to add pmc clock provider: %d\n",
2726 err);
2727 }
2728
2729 static const struct regmap_range pmc_usb_sleepwalk_ranges[] = {
2730 regmap_reg_range(PMC_USB_DEBOUNCE_DEL, PMC_USB_AO),
2731 regmap_reg_range(PMC_UTMIP_UHSIC_TRIGGERS, PMC_UTMIP_UHSIC_SAVED_STATE),
2732 regmap_reg_range(PMC_UTMIP_TERM_PAD_CFG, PMC_UTMIP_UHSIC_FAKE),
2733 regmap_reg_range(PMC_UTMIP_UHSIC_LINE_WAKEUP, PMC_UTMIP_UHSIC_LINE_WAKEUP),
2734 regmap_reg_range(PMC_UTMIP_BIAS_MASTER_CNTRL, PMC_UTMIP_MASTER_CONFIG),
2735 regmap_reg_range(PMC_UTMIP_UHSIC2_TRIGGERS, PMC_UTMIP_MASTER2_CONFIG),
2736 regmap_reg_range(PMC_UTMIP_PAD_CFG0, PMC_UTMIP_UHSIC_SLEEP_CFG1),
2737 regmap_reg_range(PMC_UTMIP_SLEEPWALK_P3, PMC_UTMIP_SLEEPWALK_P3),
2738 };
2739
2740 static const struct regmap_access_table pmc_usb_sleepwalk_table = {
2741 .yes_ranges = pmc_usb_sleepwalk_ranges,
2742 .n_yes_ranges = ARRAY_SIZE(pmc_usb_sleepwalk_ranges),
2743 };
2744
tegra_pmc_regmap_readl(void * context,unsigned int offset,unsigned int * value)2745 static int tegra_pmc_regmap_readl(void *context, unsigned int offset, unsigned int *value)
2746 {
2747 struct tegra_pmc *pmc = context;
2748
2749 *value = tegra_pmc_readl(pmc, offset);
2750 return 0;
2751 }
2752
tegra_pmc_regmap_writel(void * context,unsigned int offset,unsigned int value)2753 static int tegra_pmc_regmap_writel(void *context, unsigned int offset, unsigned int value)
2754 {
2755 struct tegra_pmc *pmc = context;
2756
2757 tegra_pmc_writel(pmc, value, offset);
2758 return 0;
2759 }
2760
2761 static const struct regmap_config usb_sleepwalk_regmap_config = {
2762 .name = "usb_sleepwalk",
2763 .reg_bits = 32,
2764 .val_bits = 32,
2765 .reg_stride = 4,
2766 .fast_io = true,
2767 .rd_table = &pmc_usb_sleepwalk_table,
2768 .wr_table = &pmc_usb_sleepwalk_table,
2769 .reg_read = tegra_pmc_regmap_readl,
2770 .reg_write = tegra_pmc_regmap_writel,
2771 };
2772
tegra_pmc_regmap_init(struct tegra_pmc * pmc)2773 static int tegra_pmc_regmap_init(struct tegra_pmc *pmc)
2774 {
2775 struct regmap *regmap;
2776 int err;
2777
2778 if (pmc->soc->has_usb_sleepwalk) {
2779 regmap = devm_regmap_init(pmc->dev, NULL, pmc, &usb_sleepwalk_regmap_config);
2780 if (IS_ERR(regmap)) {
2781 err = PTR_ERR(regmap);
2782 dev_err(pmc->dev, "failed to allocate register map (%d)\n", err);
2783 return err;
2784 }
2785 }
2786
2787 return 0;
2788 }
2789
tegra_pmc_reset_suspend_mode(void * data)2790 static void tegra_pmc_reset_suspend_mode(void *data)
2791 {
2792 pmc->suspend_mode = TEGRA_SUSPEND_NOT_READY;
2793 }
2794
tegra_pmc_probe(struct platform_device * pdev)2795 static int tegra_pmc_probe(struct platform_device *pdev)
2796 {
2797 void __iomem *base;
2798 struct resource *res;
2799 int err;
2800
2801 /*
2802 * Early initialisation should have configured an initial
2803 * register mapping and setup the soc data pointer. If these
2804 * are not valid then something went badly wrong!
2805 */
2806 if (WARN_ON(!pmc->base || !pmc->soc))
2807 return -ENODEV;
2808
2809 err = tegra_pmc_parse_dt(pmc, pdev->dev.of_node);
2810 if (err < 0)
2811 return err;
2812
2813 err = devm_add_action_or_reset(&pdev->dev, tegra_pmc_reset_suspend_mode,
2814 NULL);
2815 if (err)
2816 return err;
2817
2818 /* take over the memory region from the early initialization */
2819 base = devm_platform_ioremap_resource(pdev, 0);
2820 if (IS_ERR(base))
2821 return PTR_ERR(base);
2822
2823 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "wake");
2824 if (res) {
2825 pmc->wake = devm_ioremap_resource(&pdev->dev, res);
2826 if (IS_ERR(pmc->wake))
2827 return PTR_ERR(pmc->wake);
2828 } else {
2829 pmc->wake = base;
2830 }
2831
2832 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "aotag");
2833 if (res) {
2834 pmc->aotag = devm_ioremap_resource(&pdev->dev, res);
2835 if (IS_ERR(pmc->aotag))
2836 return PTR_ERR(pmc->aotag);
2837 } else {
2838 pmc->aotag = base;
2839 }
2840
2841 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "scratch");
2842 if (res) {
2843 pmc->scratch = devm_ioremap_resource(&pdev->dev, res);
2844 if (IS_ERR(pmc->scratch))
2845 return PTR_ERR(pmc->scratch);
2846 } else {
2847 pmc->scratch = base;
2848 }
2849
2850 pmc->clk = devm_clk_get(&pdev->dev, "pclk");
2851 if (IS_ERR(pmc->clk)) {
2852 err = PTR_ERR(pmc->clk);
2853
2854 if (err != -ENOENT) {
2855 dev_err(&pdev->dev, "failed to get pclk: %d\n", err);
2856 return err;
2857 }
2858
2859 pmc->clk = NULL;
2860 }
2861
2862 /*
2863 * PCLK clock rate can't be retrieved using CLK API because it
2864 * causes lockup if CPU enters LP2 idle state from some other
2865 * CLK notifier, hence we're caching the rate's value locally.
2866 */
2867 if (pmc->clk) {
2868 pmc->clk_nb.notifier_call = tegra_pmc_clk_notify_cb;
2869 err = clk_notifier_register(pmc->clk, &pmc->clk_nb);
2870 if (err) {
2871 dev_err(&pdev->dev,
2872 "failed to register clk notifier\n");
2873 return err;
2874 }
2875
2876 pmc->rate = clk_get_rate(pmc->clk);
2877 }
2878
2879 pmc->dev = &pdev->dev;
2880
2881 tegra_pmc_init(pmc);
2882
2883 tegra_pmc_init_tsense_reset(pmc);
2884
2885 tegra_pmc_reset_sysfs_init(pmc);
2886
2887 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
2888 err = tegra_powergate_debugfs_init();
2889 if (err < 0)
2890 goto cleanup_sysfs;
2891 }
2892
2893 err = register_restart_handler(&tegra_pmc_restart_handler);
2894 if (err) {
2895 dev_err(&pdev->dev, "unable to register restart handler, %d\n",
2896 err);
2897 goto cleanup_debugfs;
2898 }
2899
2900 err = tegra_pmc_pinctrl_init(pmc);
2901 if (err)
2902 goto cleanup_restart_handler;
2903
2904 err = tegra_pmc_regmap_init(pmc);
2905 if (err < 0)
2906 goto cleanup_restart_handler;
2907
2908 err = tegra_powergate_init(pmc, pdev->dev.of_node);
2909 if (err < 0)
2910 goto cleanup_powergates;
2911
2912 err = tegra_pmc_irq_init(pmc);
2913 if (err < 0)
2914 goto cleanup_powergates;
2915
2916 mutex_lock(&pmc->powergates_lock);
2917 iounmap(pmc->base);
2918 pmc->base = base;
2919 mutex_unlock(&pmc->powergates_lock);
2920
2921 tegra_pmc_clock_register(pmc, pdev->dev.of_node);
2922 platform_set_drvdata(pdev, pmc);
2923 tegra_pm_init_suspend();
2924
2925 return 0;
2926
2927 cleanup_powergates:
2928 tegra_powergate_remove_all(pdev->dev.of_node);
2929 cleanup_restart_handler:
2930 unregister_restart_handler(&tegra_pmc_restart_handler);
2931 cleanup_debugfs:
2932 debugfs_remove(pmc->debugfs);
2933 cleanup_sysfs:
2934 device_remove_file(&pdev->dev, &dev_attr_reset_reason);
2935 device_remove_file(&pdev->dev, &dev_attr_reset_level);
2936 clk_notifier_unregister(pmc->clk, &pmc->clk_nb);
2937
2938 return err;
2939 }
2940
2941 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM)
tegra_pmc_suspend(struct device * dev)2942 static int tegra_pmc_suspend(struct device *dev)
2943 {
2944 struct tegra_pmc *pmc = dev_get_drvdata(dev);
2945
2946 tegra_pmc_writel(pmc, virt_to_phys(tegra_resume), PMC_SCRATCH41);
2947
2948 return 0;
2949 }
2950
tegra_pmc_resume(struct device * dev)2951 static int tegra_pmc_resume(struct device *dev)
2952 {
2953 struct tegra_pmc *pmc = dev_get_drvdata(dev);
2954
2955 tegra_pmc_writel(pmc, 0x0, PMC_SCRATCH41);
2956
2957 return 0;
2958 }
2959
2960 static SIMPLE_DEV_PM_OPS(tegra_pmc_pm_ops, tegra_pmc_suspend, tegra_pmc_resume);
2961
2962 #endif
2963
2964 static const char * const tegra20_powergates[] = {
2965 [TEGRA_POWERGATE_CPU] = "cpu",
2966 [TEGRA_POWERGATE_3D] = "3d",
2967 [TEGRA_POWERGATE_VENC] = "venc",
2968 [TEGRA_POWERGATE_VDEC] = "vdec",
2969 [TEGRA_POWERGATE_PCIE] = "pcie",
2970 [TEGRA_POWERGATE_L2] = "l2",
2971 [TEGRA_POWERGATE_MPE] = "mpe",
2972 };
2973
2974 static const struct tegra_pmc_regs tegra20_pmc_regs = {
2975 .scratch0 = 0x50,
2976 .dpd_req = 0x1b8,
2977 .dpd_status = 0x1bc,
2978 .dpd2_req = 0x1c0,
2979 .dpd2_status = 0x1c4,
2980 .rst_status = 0x1b4,
2981 .rst_source_shift = 0x0,
2982 .rst_source_mask = 0x7,
2983 .rst_level_shift = 0x0,
2984 .rst_level_mask = 0x0,
2985 };
2986
tegra20_pmc_init(struct tegra_pmc * pmc)2987 static void tegra20_pmc_init(struct tegra_pmc *pmc)
2988 {
2989 u32 value, osc, pmu, off;
2990
2991 /* Always enable CPU power request */
2992 value = tegra_pmc_readl(pmc, PMC_CNTRL);
2993 value |= PMC_CNTRL_CPU_PWRREQ_OE;
2994 tegra_pmc_writel(pmc, value, PMC_CNTRL);
2995
2996 value = tegra_pmc_readl(pmc, PMC_CNTRL);
2997
2998 if (pmc->sysclkreq_high)
2999 value &= ~PMC_CNTRL_SYSCLK_POLARITY;
3000 else
3001 value |= PMC_CNTRL_SYSCLK_POLARITY;
3002
3003 if (pmc->corereq_high)
3004 value &= ~PMC_CNTRL_PWRREQ_POLARITY;
3005 else
3006 value |= PMC_CNTRL_PWRREQ_POLARITY;
3007
3008 /* configure the output polarity while the request is tristated */
3009 tegra_pmc_writel(pmc, value, PMC_CNTRL);
3010
3011 /* now enable the request */
3012 value = tegra_pmc_readl(pmc, PMC_CNTRL);
3013 value |= PMC_CNTRL_SYSCLK_OE;
3014 tegra_pmc_writel(pmc, value, PMC_CNTRL);
3015
3016 /* program core timings which are applicable only for suspend state */
3017 if (pmc->suspend_mode != TEGRA_SUSPEND_NONE) {
3018 osc = DIV_ROUND_UP(pmc->core_osc_time * 8192, 1000000);
3019 pmu = DIV_ROUND_UP(pmc->core_pmu_time * 32768, 1000000);
3020 off = DIV_ROUND_UP(pmc->core_off_time * 32768, 1000000);
3021 tegra_pmc_writel(pmc, ((osc << 8) & 0xff00) | (pmu & 0xff),
3022 PMC_COREPWRGOOD_TIMER);
3023 tegra_pmc_writel(pmc, off, PMC_COREPWROFF_TIMER);
3024 }
3025 }
3026
tegra20_pmc_setup_irq_polarity(struct tegra_pmc * pmc,struct device_node * np,bool invert)3027 static void tegra20_pmc_setup_irq_polarity(struct tegra_pmc *pmc,
3028 struct device_node *np,
3029 bool invert)
3030 {
3031 u32 value;
3032
3033 value = tegra_pmc_readl(pmc, PMC_CNTRL);
3034
3035 if (invert)
3036 value |= PMC_CNTRL_INTR_POLARITY;
3037 else
3038 value &= ~PMC_CNTRL_INTR_POLARITY;
3039
3040 tegra_pmc_writel(pmc, value, PMC_CNTRL);
3041 }
3042
3043 static const struct tegra_pmc_soc tegra20_pmc_soc = {
3044 .supports_core_domain = false,
3045 .num_powergates = ARRAY_SIZE(tegra20_powergates),
3046 .powergates = tegra20_powergates,
3047 .num_cpu_powergates = 0,
3048 .cpu_powergates = NULL,
3049 .has_tsense_reset = false,
3050 .has_gpu_clamps = false,
3051 .needs_mbist_war = false,
3052 .has_impl_33v_pwr = false,
3053 .maybe_tz_only = false,
3054 .num_io_pads = 0,
3055 .io_pads = NULL,
3056 .num_pin_descs = 0,
3057 .pin_descs = NULL,
3058 .regs = &tegra20_pmc_regs,
3059 .init = tegra20_pmc_init,
3060 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
3061 .powergate_set = tegra20_powergate_set,
3062 .reset_sources = NULL,
3063 .num_reset_sources = 0,
3064 .reset_levels = NULL,
3065 .num_reset_levels = 0,
3066 .pmc_clks_data = NULL,
3067 .num_pmc_clks = 0,
3068 .has_blink_output = true,
3069 .has_usb_sleepwalk = true,
3070 };
3071
3072 static const char * const tegra30_powergates[] = {
3073 [TEGRA_POWERGATE_CPU] = "cpu0",
3074 [TEGRA_POWERGATE_3D] = "3d0",
3075 [TEGRA_POWERGATE_VENC] = "venc",
3076 [TEGRA_POWERGATE_VDEC] = "vdec",
3077 [TEGRA_POWERGATE_PCIE] = "pcie",
3078 [TEGRA_POWERGATE_L2] = "l2",
3079 [TEGRA_POWERGATE_MPE] = "mpe",
3080 [TEGRA_POWERGATE_HEG] = "heg",
3081 [TEGRA_POWERGATE_SATA] = "sata",
3082 [TEGRA_POWERGATE_CPU1] = "cpu1",
3083 [TEGRA_POWERGATE_CPU2] = "cpu2",
3084 [TEGRA_POWERGATE_CPU3] = "cpu3",
3085 [TEGRA_POWERGATE_CELP] = "celp",
3086 [TEGRA_POWERGATE_3D1] = "3d1",
3087 };
3088
3089 static const u8 tegra30_cpu_powergates[] = {
3090 TEGRA_POWERGATE_CPU,
3091 TEGRA_POWERGATE_CPU1,
3092 TEGRA_POWERGATE_CPU2,
3093 TEGRA_POWERGATE_CPU3,
3094 };
3095
3096 static const char * const tegra30_reset_sources[] = {
3097 "POWER_ON_RESET",
3098 "WATCHDOG",
3099 "SENSOR",
3100 "SW_MAIN",
3101 "LP0"
3102 };
3103
3104 static const struct tegra_pmc_soc tegra30_pmc_soc = {
3105 .supports_core_domain = false,
3106 .num_powergates = ARRAY_SIZE(tegra30_powergates),
3107 .powergates = tegra30_powergates,
3108 .num_cpu_powergates = ARRAY_SIZE(tegra30_cpu_powergates),
3109 .cpu_powergates = tegra30_cpu_powergates,
3110 .has_tsense_reset = true,
3111 .has_gpu_clamps = false,
3112 .needs_mbist_war = false,
3113 .has_impl_33v_pwr = false,
3114 .maybe_tz_only = false,
3115 .num_io_pads = 0,
3116 .io_pads = NULL,
3117 .num_pin_descs = 0,
3118 .pin_descs = NULL,
3119 .regs = &tegra20_pmc_regs,
3120 .init = tegra20_pmc_init,
3121 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
3122 .powergate_set = tegra20_powergate_set,
3123 .reset_sources = tegra30_reset_sources,
3124 .num_reset_sources = ARRAY_SIZE(tegra30_reset_sources),
3125 .reset_levels = NULL,
3126 .num_reset_levels = 0,
3127 .pmc_clks_data = tegra_pmc_clks_data,
3128 .num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data),
3129 .has_blink_output = true,
3130 .has_usb_sleepwalk = true,
3131 };
3132
3133 static const char * const tegra114_powergates[] = {
3134 [TEGRA_POWERGATE_CPU] = "crail",
3135 [TEGRA_POWERGATE_3D] = "3d",
3136 [TEGRA_POWERGATE_VENC] = "venc",
3137 [TEGRA_POWERGATE_VDEC] = "vdec",
3138 [TEGRA_POWERGATE_MPE] = "mpe",
3139 [TEGRA_POWERGATE_HEG] = "heg",
3140 [TEGRA_POWERGATE_CPU1] = "cpu1",
3141 [TEGRA_POWERGATE_CPU2] = "cpu2",
3142 [TEGRA_POWERGATE_CPU3] = "cpu3",
3143 [TEGRA_POWERGATE_CELP] = "celp",
3144 [TEGRA_POWERGATE_CPU0] = "cpu0",
3145 [TEGRA_POWERGATE_C0NC] = "c0nc",
3146 [TEGRA_POWERGATE_C1NC] = "c1nc",
3147 [TEGRA_POWERGATE_DIS] = "dis",
3148 [TEGRA_POWERGATE_DISB] = "disb",
3149 [TEGRA_POWERGATE_XUSBA] = "xusba",
3150 [TEGRA_POWERGATE_XUSBB] = "xusbb",
3151 [TEGRA_POWERGATE_XUSBC] = "xusbc",
3152 };
3153
3154 static const u8 tegra114_cpu_powergates[] = {
3155 TEGRA_POWERGATE_CPU0,
3156 TEGRA_POWERGATE_CPU1,
3157 TEGRA_POWERGATE_CPU2,
3158 TEGRA_POWERGATE_CPU3,
3159 };
3160
3161 static const struct tegra_pmc_soc tegra114_pmc_soc = {
3162 .supports_core_domain = false,
3163 .num_powergates = ARRAY_SIZE(tegra114_powergates),
3164 .powergates = tegra114_powergates,
3165 .num_cpu_powergates = ARRAY_SIZE(tegra114_cpu_powergates),
3166 .cpu_powergates = tegra114_cpu_powergates,
3167 .has_tsense_reset = true,
3168 .has_gpu_clamps = false,
3169 .needs_mbist_war = false,
3170 .has_impl_33v_pwr = false,
3171 .maybe_tz_only = false,
3172 .num_io_pads = 0,
3173 .io_pads = NULL,
3174 .num_pin_descs = 0,
3175 .pin_descs = NULL,
3176 .regs = &tegra20_pmc_regs,
3177 .init = tegra20_pmc_init,
3178 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
3179 .powergate_set = tegra114_powergate_set,
3180 .reset_sources = tegra30_reset_sources,
3181 .num_reset_sources = ARRAY_SIZE(tegra30_reset_sources),
3182 .reset_levels = NULL,
3183 .num_reset_levels = 0,
3184 .pmc_clks_data = tegra_pmc_clks_data,
3185 .num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data),
3186 .has_blink_output = true,
3187 .has_usb_sleepwalk = true,
3188 };
3189
3190 static const char * const tegra124_powergates[] = {
3191 [TEGRA_POWERGATE_CPU] = "crail",
3192 [TEGRA_POWERGATE_3D] = "3d",
3193 [TEGRA_POWERGATE_VENC] = "venc",
3194 [TEGRA_POWERGATE_PCIE] = "pcie",
3195 [TEGRA_POWERGATE_VDEC] = "vdec",
3196 [TEGRA_POWERGATE_MPE] = "mpe",
3197 [TEGRA_POWERGATE_HEG] = "heg",
3198 [TEGRA_POWERGATE_SATA] = "sata",
3199 [TEGRA_POWERGATE_CPU1] = "cpu1",
3200 [TEGRA_POWERGATE_CPU2] = "cpu2",
3201 [TEGRA_POWERGATE_CPU3] = "cpu3",
3202 [TEGRA_POWERGATE_CELP] = "celp",
3203 [TEGRA_POWERGATE_CPU0] = "cpu0",
3204 [TEGRA_POWERGATE_C0NC] = "c0nc",
3205 [TEGRA_POWERGATE_C1NC] = "c1nc",
3206 [TEGRA_POWERGATE_SOR] = "sor",
3207 [TEGRA_POWERGATE_DIS] = "dis",
3208 [TEGRA_POWERGATE_DISB] = "disb",
3209 [TEGRA_POWERGATE_XUSBA] = "xusba",
3210 [TEGRA_POWERGATE_XUSBB] = "xusbb",
3211 [TEGRA_POWERGATE_XUSBC] = "xusbc",
3212 [TEGRA_POWERGATE_VIC] = "vic",
3213 [TEGRA_POWERGATE_IRAM] = "iram",
3214 };
3215
3216 static const u8 tegra124_cpu_powergates[] = {
3217 TEGRA_POWERGATE_CPU0,
3218 TEGRA_POWERGATE_CPU1,
3219 TEGRA_POWERGATE_CPU2,
3220 TEGRA_POWERGATE_CPU3,
3221 };
3222
3223 #define TEGRA_IO_PAD(_id, _dpd, _voltage, _name) \
3224 ((struct tegra_io_pad_soc) { \
3225 .id = (_id), \
3226 .dpd = (_dpd), \
3227 .voltage = (_voltage), \
3228 .name = (_name), \
3229 })
3230
3231 #define TEGRA_IO_PIN_DESC(_id, _dpd, _voltage, _name) \
3232 ((struct pinctrl_pin_desc) { \
3233 .number = (_id), \
3234 .name = (_name) \
3235 })
3236
3237 #define TEGRA124_IO_PAD_TABLE(_pad) \
3238 /* .id .dpd .voltage .name */ \
3239 _pad(TEGRA_IO_PAD_AUDIO, 17, UINT_MAX, "audio"), \
3240 _pad(TEGRA_IO_PAD_BB, 15, UINT_MAX, "bb"), \
3241 _pad(TEGRA_IO_PAD_CAM, 36, UINT_MAX, "cam"), \
3242 _pad(TEGRA_IO_PAD_COMP, 22, UINT_MAX, "comp"), \
3243 _pad(TEGRA_IO_PAD_CSIA, 0, UINT_MAX, "csia"), \
3244 _pad(TEGRA_IO_PAD_CSIB, 1, UINT_MAX, "csb"), \
3245 _pad(TEGRA_IO_PAD_CSIE, 44, UINT_MAX, "cse"), \
3246 _pad(TEGRA_IO_PAD_DSI, 2, UINT_MAX, "dsi"), \
3247 _pad(TEGRA_IO_PAD_DSIB, 39, UINT_MAX, "dsib"), \
3248 _pad(TEGRA_IO_PAD_DSIC, 40, UINT_MAX, "dsic"), \
3249 _pad(TEGRA_IO_PAD_DSID, 41, UINT_MAX, "dsid"), \
3250 _pad(TEGRA_IO_PAD_HDMI, 28, UINT_MAX, "hdmi"), \
3251 _pad(TEGRA_IO_PAD_HSIC, 19, UINT_MAX, "hsic"), \
3252 _pad(TEGRA_IO_PAD_HV, 38, UINT_MAX, "hv"), \
3253 _pad(TEGRA_IO_PAD_LVDS, 57, UINT_MAX, "lvds"), \
3254 _pad(TEGRA_IO_PAD_MIPI_BIAS, 3, UINT_MAX, "mipi-bias"), \
3255 _pad(TEGRA_IO_PAD_NAND, 13, UINT_MAX, "nand"), \
3256 _pad(TEGRA_IO_PAD_PEX_BIAS, 4, UINT_MAX, "pex-bias"), \
3257 _pad(TEGRA_IO_PAD_PEX_CLK1, 5, UINT_MAX, "pex-clk1"), \
3258 _pad(TEGRA_IO_PAD_PEX_CLK2, 6, UINT_MAX, "pex-clk2"), \
3259 _pad(TEGRA_IO_PAD_PEX_CNTRL, 32, UINT_MAX, "pex-cntrl"), \
3260 _pad(TEGRA_IO_PAD_SDMMC1, 33, UINT_MAX, "sdmmc1"), \
3261 _pad(TEGRA_IO_PAD_SDMMC3, 34, UINT_MAX, "sdmmc3"), \
3262 _pad(TEGRA_IO_PAD_SDMMC4, 35, UINT_MAX, "sdmmc4"), \
3263 _pad(TEGRA_IO_PAD_SYS_DDC, 58, UINT_MAX, "sys_ddc"), \
3264 _pad(TEGRA_IO_PAD_UART, 14, UINT_MAX, "uart"), \
3265 _pad(TEGRA_IO_PAD_USB0, 9, UINT_MAX, "usb0"), \
3266 _pad(TEGRA_IO_PAD_USB1, 10, UINT_MAX, "usb1"), \
3267 _pad(TEGRA_IO_PAD_USB2, 11, UINT_MAX, "usb2"), \
3268 _pad(TEGRA_IO_PAD_USB_BIAS, 12, UINT_MAX, "usb_bias")
3269
3270 static const struct tegra_io_pad_soc tegra124_io_pads[] = {
3271 TEGRA124_IO_PAD_TABLE(TEGRA_IO_PAD)
3272 };
3273
3274 static const struct pinctrl_pin_desc tegra124_pin_descs[] = {
3275 TEGRA124_IO_PAD_TABLE(TEGRA_IO_PIN_DESC)
3276 };
3277
3278 static const struct tegra_pmc_soc tegra124_pmc_soc = {
3279 .supports_core_domain = false,
3280 .num_powergates = ARRAY_SIZE(tegra124_powergates),
3281 .powergates = tegra124_powergates,
3282 .num_cpu_powergates = ARRAY_SIZE(tegra124_cpu_powergates),
3283 .cpu_powergates = tegra124_cpu_powergates,
3284 .has_tsense_reset = true,
3285 .has_gpu_clamps = true,
3286 .needs_mbist_war = false,
3287 .has_impl_33v_pwr = false,
3288 .maybe_tz_only = false,
3289 .num_io_pads = ARRAY_SIZE(tegra124_io_pads),
3290 .io_pads = tegra124_io_pads,
3291 .num_pin_descs = ARRAY_SIZE(tegra124_pin_descs),
3292 .pin_descs = tegra124_pin_descs,
3293 .regs = &tegra20_pmc_regs,
3294 .init = tegra20_pmc_init,
3295 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
3296 .powergate_set = tegra114_powergate_set,
3297 .reset_sources = tegra30_reset_sources,
3298 .num_reset_sources = ARRAY_SIZE(tegra30_reset_sources),
3299 .reset_levels = NULL,
3300 .num_reset_levels = 0,
3301 .pmc_clks_data = tegra_pmc_clks_data,
3302 .num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data),
3303 .has_blink_output = true,
3304 .has_usb_sleepwalk = true,
3305 };
3306
3307 static const char * const tegra210_powergates[] = {
3308 [TEGRA_POWERGATE_CPU] = "crail",
3309 [TEGRA_POWERGATE_3D] = "3d",
3310 [TEGRA_POWERGATE_VENC] = "venc",
3311 [TEGRA_POWERGATE_PCIE] = "pcie",
3312 [TEGRA_POWERGATE_MPE] = "mpe",
3313 [TEGRA_POWERGATE_SATA] = "sata",
3314 [TEGRA_POWERGATE_CPU1] = "cpu1",
3315 [TEGRA_POWERGATE_CPU2] = "cpu2",
3316 [TEGRA_POWERGATE_CPU3] = "cpu3",
3317 [TEGRA_POWERGATE_CPU0] = "cpu0",
3318 [TEGRA_POWERGATE_C0NC] = "c0nc",
3319 [TEGRA_POWERGATE_SOR] = "sor",
3320 [TEGRA_POWERGATE_DIS] = "dis",
3321 [TEGRA_POWERGATE_DISB] = "disb",
3322 [TEGRA_POWERGATE_XUSBA] = "xusba",
3323 [TEGRA_POWERGATE_XUSBB] = "xusbb",
3324 [TEGRA_POWERGATE_XUSBC] = "xusbc",
3325 [TEGRA_POWERGATE_VIC] = "vic",
3326 [TEGRA_POWERGATE_IRAM] = "iram",
3327 [TEGRA_POWERGATE_NVDEC] = "nvdec",
3328 [TEGRA_POWERGATE_NVJPG] = "nvjpg",
3329 [TEGRA_POWERGATE_AUD] = "aud",
3330 [TEGRA_POWERGATE_DFD] = "dfd",
3331 [TEGRA_POWERGATE_VE2] = "ve2",
3332 };
3333
3334 static const u8 tegra210_cpu_powergates[] = {
3335 TEGRA_POWERGATE_CPU0,
3336 TEGRA_POWERGATE_CPU1,
3337 TEGRA_POWERGATE_CPU2,
3338 TEGRA_POWERGATE_CPU3,
3339 };
3340
3341 #define TEGRA210_IO_PAD_TABLE(_pad) \
3342 /* .id .dpd .voltage .name */ \
3343 _pad(TEGRA_IO_PAD_AUDIO, 17, 5, "audio"), \
3344 _pad(TEGRA_IO_PAD_AUDIO_HV, 61, 18, "audio-hv"), \
3345 _pad(TEGRA_IO_PAD_CAM, 36, 10, "cam"), \
3346 _pad(TEGRA_IO_PAD_CSIA, 0, UINT_MAX, "csia"), \
3347 _pad(TEGRA_IO_PAD_CSIB, 1, UINT_MAX, "csib"), \
3348 _pad(TEGRA_IO_PAD_CSIC, 42, UINT_MAX, "csic"), \
3349 _pad(TEGRA_IO_PAD_CSID, 43, UINT_MAX, "csid"), \
3350 _pad(TEGRA_IO_PAD_CSIE, 44, UINT_MAX, "csie"), \
3351 _pad(TEGRA_IO_PAD_CSIF, 45, UINT_MAX, "csif"), \
3352 _pad(TEGRA_IO_PAD_DBG, 25, 19, "dbg"), \
3353 _pad(TEGRA_IO_PAD_DEBUG_NONAO, 26, UINT_MAX, "debug-nonao"), \
3354 _pad(TEGRA_IO_PAD_DMIC, 50, 20, "dmic"), \
3355 _pad(TEGRA_IO_PAD_DP, 51, UINT_MAX, "dp"), \
3356 _pad(TEGRA_IO_PAD_DSI, 2, UINT_MAX, "dsi"), \
3357 _pad(TEGRA_IO_PAD_DSIB, 39, UINT_MAX, "dsib"), \
3358 _pad(TEGRA_IO_PAD_DSIC, 40, UINT_MAX, "dsic"), \
3359 _pad(TEGRA_IO_PAD_DSID, 41, UINT_MAX, "dsid"), \
3360 _pad(TEGRA_IO_PAD_EMMC, 35, UINT_MAX, "emmc"), \
3361 _pad(TEGRA_IO_PAD_EMMC2, 37, UINT_MAX, "emmc2"), \
3362 _pad(TEGRA_IO_PAD_GPIO, 27, 21, "gpio"), \
3363 _pad(TEGRA_IO_PAD_HDMI, 28, UINT_MAX, "hdmi"), \
3364 _pad(TEGRA_IO_PAD_HSIC, 19, UINT_MAX, "hsic"), \
3365 _pad(TEGRA_IO_PAD_LVDS, 57, UINT_MAX, "lvds"), \
3366 _pad(TEGRA_IO_PAD_MIPI_BIAS, 3, UINT_MAX, "mipi-bias"), \
3367 _pad(TEGRA_IO_PAD_PEX_BIAS, 4, UINT_MAX, "pex-bias"), \
3368 _pad(TEGRA_IO_PAD_PEX_CLK1, 5, UINT_MAX, "pex-clk1"), \
3369 _pad(TEGRA_IO_PAD_PEX_CLK2, 6, UINT_MAX, "pex-clk2"), \
3370 _pad(TEGRA_IO_PAD_PEX_CNTRL, UINT_MAX, 11, "pex-cntrl"), \
3371 _pad(TEGRA_IO_PAD_SDMMC1, 33, 12, "sdmmc1"), \
3372 _pad(TEGRA_IO_PAD_SDMMC3, 34, 13, "sdmmc3"), \
3373 _pad(TEGRA_IO_PAD_SPI, 46, 22, "spi"), \
3374 _pad(TEGRA_IO_PAD_SPI_HV, 47, 23, "spi-hv"), \
3375 _pad(TEGRA_IO_PAD_UART, 14, 2, "uart"), \
3376 _pad(TEGRA_IO_PAD_USB0, 9, UINT_MAX, "usb0"), \
3377 _pad(TEGRA_IO_PAD_USB1, 10, UINT_MAX, "usb1"), \
3378 _pad(TEGRA_IO_PAD_USB2, 11, UINT_MAX, "usb2"), \
3379 _pad(TEGRA_IO_PAD_USB3, 18, UINT_MAX, "usb3"), \
3380 _pad(TEGRA_IO_PAD_USB_BIAS, 12, UINT_MAX, "usb-bias")
3381
3382 static const struct tegra_io_pad_soc tegra210_io_pads[] = {
3383 TEGRA210_IO_PAD_TABLE(TEGRA_IO_PAD)
3384 };
3385
3386 static const struct pinctrl_pin_desc tegra210_pin_descs[] = {
3387 TEGRA210_IO_PAD_TABLE(TEGRA_IO_PIN_DESC)
3388 };
3389
3390 static const char * const tegra210_reset_sources[] = {
3391 "POWER_ON_RESET",
3392 "WATCHDOG",
3393 "SENSOR",
3394 "SW_MAIN",
3395 "LP0",
3396 "AOTAG"
3397 };
3398
3399 static const struct tegra_wake_event tegra210_wake_events[] = {
3400 TEGRA_WAKE_IRQ("rtc", 16, 2),
3401 TEGRA_WAKE_IRQ("pmu", 51, 86),
3402 };
3403
3404 static const struct tegra_pmc_soc tegra210_pmc_soc = {
3405 .supports_core_domain = false,
3406 .num_powergates = ARRAY_SIZE(tegra210_powergates),
3407 .powergates = tegra210_powergates,
3408 .num_cpu_powergates = ARRAY_SIZE(tegra210_cpu_powergates),
3409 .cpu_powergates = tegra210_cpu_powergates,
3410 .has_tsense_reset = true,
3411 .has_gpu_clamps = true,
3412 .needs_mbist_war = true,
3413 .has_impl_33v_pwr = false,
3414 .maybe_tz_only = true,
3415 .num_io_pads = ARRAY_SIZE(tegra210_io_pads),
3416 .io_pads = tegra210_io_pads,
3417 .num_pin_descs = ARRAY_SIZE(tegra210_pin_descs),
3418 .pin_descs = tegra210_pin_descs,
3419 .regs = &tegra20_pmc_regs,
3420 .init = tegra20_pmc_init,
3421 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
3422 .powergate_set = tegra114_powergate_set,
3423 .irq_set_wake = tegra210_pmc_irq_set_wake,
3424 .irq_set_type = tegra210_pmc_irq_set_type,
3425 .reset_sources = tegra210_reset_sources,
3426 .num_reset_sources = ARRAY_SIZE(tegra210_reset_sources),
3427 .reset_levels = NULL,
3428 .num_reset_levels = 0,
3429 .num_wake_events = ARRAY_SIZE(tegra210_wake_events),
3430 .wake_events = tegra210_wake_events,
3431 .pmc_clks_data = tegra_pmc_clks_data,
3432 .num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data),
3433 .has_blink_output = true,
3434 .has_usb_sleepwalk = true,
3435 };
3436
3437 #define TEGRA186_IO_PAD_TABLE(_pad) \
3438 /* .id .dpd .voltage .name */ \
3439 _pad(TEGRA_IO_PAD_CSIA, 0, UINT_MAX, "csia"), \
3440 _pad(TEGRA_IO_PAD_CSIB, 1, UINT_MAX, "csib"), \
3441 _pad(TEGRA_IO_PAD_DSI, 2, UINT_MAX, "dsi"), \
3442 _pad(TEGRA_IO_PAD_MIPI_BIAS, 3, UINT_MAX, "mipi-bias"), \
3443 _pad(TEGRA_IO_PAD_PEX_CLK_BIAS, 4, UINT_MAX, "pex-clk-bias"), \
3444 _pad(TEGRA_IO_PAD_PEX_CLK3, 5, UINT_MAX, "pex-clk3"), \
3445 _pad(TEGRA_IO_PAD_PEX_CLK2, 6, UINT_MAX, "pex-clk2"), \
3446 _pad(TEGRA_IO_PAD_PEX_CLK1, 7, UINT_MAX, "pex-clk1"), \
3447 _pad(TEGRA_IO_PAD_USB0, 9, UINT_MAX, "usb0"), \
3448 _pad(TEGRA_IO_PAD_USB1, 10, UINT_MAX, "usb1"), \
3449 _pad(TEGRA_IO_PAD_USB2, 11, UINT_MAX, "usb2"), \
3450 _pad(TEGRA_IO_PAD_USB_BIAS, 12, UINT_MAX, "usb-bias"), \
3451 _pad(TEGRA_IO_PAD_UART, 14, UINT_MAX, "uart"), \
3452 _pad(TEGRA_IO_PAD_AUDIO, 17, UINT_MAX, "audio"), \
3453 _pad(TEGRA_IO_PAD_HSIC, 19, UINT_MAX, "hsic"), \
3454 _pad(TEGRA_IO_PAD_DBG, 25, UINT_MAX, "dbg"), \
3455 _pad(TEGRA_IO_PAD_HDMI_DP0, 28, UINT_MAX, "hdmi-dp0"), \
3456 _pad(TEGRA_IO_PAD_HDMI_DP1, 29, UINT_MAX, "hdmi-dp1"), \
3457 _pad(TEGRA_IO_PAD_PEX_CNTRL, 32, UINT_MAX, "pex-cntrl"), \
3458 _pad(TEGRA_IO_PAD_SDMMC2_HV, 34, 5, "sdmmc2-hv"), \
3459 _pad(TEGRA_IO_PAD_SDMMC4, 36, UINT_MAX, "sdmmc4"), \
3460 _pad(TEGRA_IO_PAD_CAM, 38, UINT_MAX, "cam"), \
3461 _pad(TEGRA_IO_PAD_DSIB, 40, UINT_MAX, "dsib"), \
3462 _pad(TEGRA_IO_PAD_DSIC, 41, UINT_MAX, "dsic"), \
3463 _pad(TEGRA_IO_PAD_DSID, 42, UINT_MAX, "dsid"), \
3464 _pad(TEGRA_IO_PAD_CSIC, 43, UINT_MAX, "csic"), \
3465 _pad(TEGRA_IO_PAD_CSID, 44, UINT_MAX, "csid"), \
3466 _pad(TEGRA_IO_PAD_CSIE, 45, UINT_MAX, "csie"), \
3467 _pad(TEGRA_IO_PAD_CSIF, 46, UINT_MAX, "csif"), \
3468 _pad(TEGRA_IO_PAD_SPI, 47, UINT_MAX, "spi"), \
3469 _pad(TEGRA_IO_PAD_UFS, 49, UINT_MAX, "ufs"), \
3470 _pad(TEGRA_IO_PAD_DMIC_HV, 52, 2, "dmic-hv"), \
3471 _pad(TEGRA_IO_PAD_EDP, 53, UINT_MAX, "edp"), \
3472 _pad(TEGRA_IO_PAD_SDMMC1_HV, 55, 4, "sdmmc1-hv"), \
3473 _pad(TEGRA_IO_PAD_SDMMC3_HV, 56, 6, "sdmmc3-hv"), \
3474 _pad(TEGRA_IO_PAD_CONN, 60, UINT_MAX, "conn"), \
3475 _pad(TEGRA_IO_PAD_AUDIO_HV, 61, 1, "audio-hv"), \
3476 _pad(TEGRA_IO_PAD_AO_HV, UINT_MAX, 0, "ao-hv")
3477
3478 static const struct tegra_io_pad_soc tegra186_io_pads[] = {
3479 TEGRA186_IO_PAD_TABLE(TEGRA_IO_PAD)
3480 };
3481
3482 static const struct pinctrl_pin_desc tegra186_pin_descs[] = {
3483 TEGRA186_IO_PAD_TABLE(TEGRA_IO_PIN_DESC)
3484 };
3485
3486 static const struct tegra_pmc_regs tegra186_pmc_regs = {
3487 .scratch0 = 0x2000,
3488 .dpd_req = 0x74,
3489 .dpd_status = 0x78,
3490 .dpd2_req = 0x7c,
3491 .dpd2_status = 0x80,
3492 .rst_status = 0x70,
3493 .rst_source_shift = 0x2,
3494 .rst_source_mask = 0x3c,
3495 .rst_level_shift = 0x0,
3496 .rst_level_mask = 0x3,
3497 };
3498
tegra186_pmc_setup_irq_polarity(struct tegra_pmc * pmc,struct device_node * np,bool invert)3499 static void tegra186_pmc_setup_irq_polarity(struct tegra_pmc *pmc,
3500 struct device_node *np,
3501 bool invert)
3502 {
3503 struct resource regs;
3504 void __iomem *wake;
3505 u32 value;
3506 int index;
3507
3508 index = of_property_match_string(np, "reg-names", "wake");
3509 if (index < 0) {
3510 dev_err(pmc->dev, "failed to find PMC wake registers\n");
3511 return;
3512 }
3513
3514 of_address_to_resource(np, index, ®s);
3515
3516 wake = ioremap(regs.start, resource_size(®s));
3517 if (!wake) {
3518 dev_err(pmc->dev, "failed to map PMC wake registers\n");
3519 return;
3520 }
3521
3522 value = readl(wake + WAKE_AOWAKE_CTRL);
3523
3524 if (invert)
3525 value |= WAKE_AOWAKE_CTRL_INTR_POLARITY;
3526 else
3527 value &= ~WAKE_AOWAKE_CTRL_INTR_POLARITY;
3528
3529 writel(value, wake + WAKE_AOWAKE_CTRL);
3530
3531 iounmap(wake);
3532 }
3533
3534 static const char * const tegra186_reset_sources[] = {
3535 "SYS_RESET",
3536 "AOWDT",
3537 "MCCPLEXWDT",
3538 "BPMPWDT",
3539 "SCEWDT",
3540 "SPEWDT",
3541 "APEWDT",
3542 "BCCPLEXWDT",
3543 "SENSOR",
3544 "AOTAG",
3545 "VFSENSOR",
3546 "SWREST",
3547 "SC7",
3548 "HSM",
3549 "CORESIGHT"
3550 };
3551
3552 static const char * const tegra186_reset_levels[] = {
3553 "L0", "L1", "L2", "WARM"
3554 };
3555
3556 static const struct tegra_wake_event tegra186_wake_events[] = {
3557 TEGRA_WAKE_IRQ("pmu", 24, 209),
3558 TEGRA_WAKE_GPIO("power", 29, 1, TEGRA186_AON_GPIO(FF, 0)),
3559 TEGRA_WAKE_IRQ("rtc", 73, 10),
3560 };
3561
3562 static const struct tegra_pmc_soc tegra186_pmc_soc = {
3563 .supports_core_domain = false,
3564 .num_powergates = 0,
3565 .powergates = NULL,
3566 .num_cpu_powergates = 0,
3567 .cpu_powergates = NULL,
3568 .has_tsense_reset = false,
3569 .has_gpu_clamps = false,
3570 .needs_mbist_war = false,
3571 .has_impl_33v_pwr = true,
3572 .maybe_tz_only = false,
3573 .num_io_pads = ARRAY_SIZE(tegra186_io_pads),
3574 .io_pads = tegra186_io_pads,
3575 .num_pin_descs = ARRAY_SIZE(tegra186_pin_descs),
3576 .pin_descs = tegra186_pin_descs,
3577 .regs = &tegra186_pmc_regs,
3578 .init = NULL,
3579 .setup_irq_polarity = tegra186_pmc_setup_irq_polarity,
3580 .irq_set_wake = tegra186_pmc_irq_set_wake,
3581 .irq_set_type = tegra186_pmc_irq_set_type,
3582 .reset_sources = tegra186_reset_sources,
3583 .num_reset_sources = ARRAY_SIZE(tegra186_reset_sources),
3584 .reset_levels = tegra186_reset_levels,
3585 .num_reset_levels = ARRAY_SIZE(tegra186_reset_levels),
3586 .num_wake_events = ARRAY_SIZE(tegra186_wake_events),
3587 .wake_events = tegra186_wake_events,
3588 .pmc_clks_data = NULL,
3589 .num_pmc_clks = 0,
3590 .has_blink_output = false,
3591 .has_usb_sleepwalk = false,
3592 };
3593
3594 #define TEGRA194_IO_PAD_TABLE(_pad) \
3595 /* .id .dpd .voltage .name */ \
3596 _pad(TEGRA_IO_PAD_CSIA, 0, UINT_MAX, "csia"), \
3597 _pad(TEGRA_IO_PAD_CSIB, 1, UINT_MAX, "csib"), \
3598 _pad(TEGRA_IO_PAD_MIPI_BIAS, 3, UINT_MAX, "mipi-bias"), \
3599 _pad(TEGRA_IO_PAD_PEX_CLK_BIAS, 4, UINT_MAX, "pex-clk-bias"), \
3600 _pad(TEGRA_IO_PAD_PEX_CLK3, 5, UINT_MAX, "pex-clk3"), \
3601 _pad(TEGRA_IO_PAD_PEX_CLK2, 6, UINT_MAX, "pex-clk2"), \
3602 _pad(TEGRA_IO_PAD_PEX_CLK1, 7, UINT_MAX, "pex-clk1"), \
3603 _pad(TEGRA_IO_PAD_EQOS, 8, UINT_MAX, "eqos"), \
3604 _pad(TEGRA_IO_PAD_PEX_CLK_2_BIAS, 9, UINT_MAX, "pex-clk-2-bias"), \
3605 _pad(TEGRA_IO_PAD_PEX_CLK_2, 10, UINT_MAX, "pex-clk-2"), \
3606 _pad(TEGRA_IO_PAD_DAP3, 11, UINT_MAX, "dap3"), \
3607 _pad(TEGRA_IO_PAD_DAP5, 12, UINT_MAX, "dap5"), \
3608 _pad(TEGRA_IO_PAD_UART, 14, UINT_MAX, "uart"), \
3609 _pad(TEGRA_IO_PAD_PWR_CTL, 15, UINT_MAX, "pwr-ctl"), \
3610 _pad(TEGRA_IO_PAD_SOC_GPIO53, 16, UINT_MAX, "soc-gpio53"), \
3611 _pad(TEGRA_IO_PAD_AUDIO, 17, UINT_MAX, "audio"), \
3612 _pad(TEGRA_IO_PAD_GP_PWM2, 18, UINT_MAX, "gp-pwm2"), \
3613 _pad(TEGRA_IO_PAD_GP_PWM3, 19, UINT_MAX, "gp-pwm3"), \
3614 _pad(TEGRA_IO_PAD_SOC_GPIO12, 20, UINT_MAX, "soc-gpio12"), \
3615 _pad(TEGRA_IO_PAD_SOC_GPIO13, 21, UINT_MAX, "soc-gpio13"), \
3616 _pad(TEGRA_IO_PAD_SOC_GPIO10, 22, UINT_MAX, "soc-gpio10"), \
3617 _pad(TEGRA_IO_PAD_UART4, 23, UINT_MAX, "uart4"), \
3618 _pad(TEGRA_IO_PAD_UART5, 24, UINT_MAX, "uart5"), \
3619 _pad(TEGRA_IO_PAD_DBG, 25, UINT_MAX, "dbg"), \
3620 _pad(TEGRA_IO_PAD_HDMI_DP3, 26, UINT_MAX, "hdmi-dp3"), \
3621 _pad(TEGRA_IO_PAD_HDMI_DP2, 27, UINT_MAX, "hdmi-dp2"), \
3622 _pad(TEGRA_IO_PAD_HDMI_DP0, 28, UINT_MAX, "hdmi-dp0"), \
3623 _pad(TEGRA_IO_PAD_HDMI_DP1, 29, UINT_MAX, "hdmi-dp1"), \
3624 _pad(TEGRA_IO_PAD_PEX_CNTRL, 32, UINT_MAX, "pex-cntrl"), \
3625 _pad(TEGRA_IO_PAD_PEX_CTL2, 33, UINT_MAX, "pex-ctl2"), \
3626 _pad(TEGRA_IO_PAD_PEX_L0_RST_N, 34, UINT_MAX, "pex-l0-rst"), \
3627 _pad(TEGRA_IO_PAD_PEX_L1_RST_N, 35, UINT_MAX, "pex-l1-rst"), \
3628 _pad(TEGRA_IO_PAD_SDMMC4, 36, UINT_MAX, "sdmmc4"), \
3629 _pad(TEGRA_IO_PAD_PEX_L5_RST_N, 37, UINT_MAX, "pex-l5-rst"), \
3630 _pad(TEGRA_IO_PAD_CAM, 38, UINT_MAX, "cam"), \
3631 _pad(TEGRA_IO_PAD_CSIC, 43, UINT_MAX, "csic"), \
3632 _pad(TEGRA_IO_PAD_CSID, 44, UINT_MAX, "csid"), \
3633 _pad(TEGRA_IO_PAD_CSIE, 45, UINT_MAX, "csie"), \
3634 _pad(TEGRA_IO_PAD_CSIF, 46, UINT_MAX, "csif"), \
3635 _pad(TEGRA_IO_PAD_SPI, 47, UINT_MAX, "spi"), \
3636 _pad(TEGRA_IO_PAD_UFS, 49, UINT_MAX, "ufs"), \
3637 _pad(TEGRA_IO_PAD_CSIG, 50, UINT_MAX, "csig"), \
3638 _pad(TEGRA_IO_PAD_CSIH, 51, UINT_MAX, "csih"), \
3639 _pad(TEGRA_IO_PAD_EDP, 53, UINT_MAX, "edp"), \
3640 _pad(TEGRA_IO_PAD_SDMMC1_HV, 55, 4, "sdmmc1-hv"), \
3641 _pad(TEGRA_IO_PAD_SDMMC3_HV, 56, 6, "sdmmc3-hv"), \
3642 _pad(TEGRA_IO_PAD_CONN, 60, UINT_MAX, "conn"), \
3643 _pad(TEGRA_IO_PAD_AUDIO_HV, 61, 1, "audio-hv"), \
3644 _pad(TEGRA_IO_PAD_AO_HV, UINT_MAX, 0, "ao-hv")
3645
3646 static const struct tegra_io_pad_soc tegra194_io_pads[] = {
3647 TEGRA194_IO_PAD_TABLE(TEGRA_IO_PAD)
3648 };
3649
3650 static const struct pinctrl_pin_desc tegra194_pin_descs[] = {
3651 TEGRA194_IO_PAD_TABLE(TEGRA_IO_PIN_DESC)
3652 };
3653
3654 static const struct tegra_pmc_regs tegra194_pmc_regs = {
3655 .scratch0 = 0x2000,
3656 .dpd_req = 0x74,
3657 .dpd_status = 0x78,
3658 .dpd2_req = 0x7c,
3659 .dpd2_status = 0x80,
3660 .rst_status = 0x70,
3661 .rst_source_shift = 0x2,
3662 .rst_source_mask = 0x7c,
3663 .rst_level_shift = 0x0,
3664 .rst_level_mask = 0x3,
3665 };
3666
3667 static const char * const tegra194_reset_sources[] = {
3668 "SYS_RESET_N",
3669 "AOWDT",
3670 "BCCPLEXWDT",
3671 "BPMPWDT",
3672 "SCEWDT",
3673 "SPEWDT",
3674 "APEWDT",
3675 "LCCPLEXWDT",
3676 "SENSOR",
3677 "AOTAG",
3678 "VFSENSOR",
3679 "MAINSWRST",
3680 "SC7",
3681 "HSM",
3682 "CSITE",
3683 "RCEWDT",
3684 "PVA0WDT",
3685 "PVA1WDT",
3686 "L1A_ASYNC",
3687 "BPMPBOOT",
3688 "FUSECRC",
3689 };
3690
3691 static const struct tegra_wake_event tegra194_wake_events[] = {
3692 TEGRA_WAKE_IRQ("pmu", 24, 209),
3693 TEGRA_WAKE_GPIO("power", 29, 1, TEGRA194_AON_GPIO(EE, 4)),
3694 TEGRA_WAKE_IRQ("rtc", 73, 10),
3695 };
3696
3697 static const struct tegra_pmc_soc tegra194_pmc_soc = {
3698 .supports_core_domain = false,
3699 .num_powergates = 0,
3700 .powergates = NULL,
3701 .num_cpu_powergates = 0,
3702 .cpu_powergates = NULL,
3703 .has_tsense_reset = false,
3704 .has_gpu_clamps = false,
3705 .needs_mbist_war = false,
3706 .has_impl_33v_pwr = true,
3707 .maybe_tz_only = false,
3708 .num_io_pads = ARRAY_SIZE(tegra194_io_pads),
3709 .io_pads = tegra194_io_pads,
3710 .num_pin_descs = ARRAY_SIZE(tegra194_pin_descs),
3711 .pin_descs = tegra194_pin_descs,
3712 .regs = &tegra194_pmc_regs,
3713 .init = NULL,
3714 .setup_irq_polarity = tegra186_pmc_setup_irq_polarity,
3715 .irq_set_wake = tegra186_pmc_irq_set_wake,
3716 .irq_set_type = tegra186_pmc_irq_set_type,
3717 .reset_sources = tegra194_reset_sources,
3718 .num_reset_sources = ARRAY_SIZE(tegra194_reset_sources),
3719 .reset_levels = tegra186_reset_levels,
3720 .num_reset_levels = ARRAY_SIZE(tegra186_reset_levels),
3721 .num_wake_events = ARRAY_SIZE(tegra194_wake_events),
3722 .wake_events = tegra194_wake_events,
3723 .pmc_clks_data = NULL,
3724 .num_pmc_clks = 0,
3725 .has_blink_output = false,
3726 .has_usb_sleepwalk = false,
3727 };
3728
3729 static const struct tegra_pmc_regs tegra234_pmc_regs = {
3730 .scratch0 = 0x2000,
3731 .dpd_req = 0,
3732 .dpd_status = 0,
3733 .dpd2_req = 0,
3734 .dpd2_status = 0,
3735 .rst_status = 0x70,
3736 .rst_source_shift = 0x2,
3737 .rst_source_mask = 0xfc,
3738 .rst_level_shift = 0x0,
3739 .rst_level_mask = 0x3,
3740 };
3741
3742 static const char * const tegra234_reset_sources[] = {
3743 "SYS_RESET_N",
3744 "AOWDT",
3745 "BCCPLEXWDT",
3746 "BPMPWDT",
3747 "SCEWDT",
3748 "SPEWDT",
3749 "APEWDT",
3750 "LCCPLEXWDT",
3751 "SENSOR",
3752 "AOTAG",
3753 "VFSENSOR",
3754 "MAINSWRST",
3755 "SC7",
3756 "HSM",
3757 "CSITE",
3758 "RCEWDT",
3759 "PVA0WDT",
3760 "PVA1WDT",
3761 "L1A_ASYNC",
3762 "BPMPBOOT",
3763 "FUSECRC",
3764 };
3765
3766 static const struct tegra_pmc_soc tegra234_pmc_soc = {
3767 .supports_core_domain = false,
3768 .num_powergates = 0,
3769 .powergates = NULL,
3770 .num_cpu_powergates = 0,
3771 .cpu_powergates = NULL,
3772 .has_tsense_reset = false,
3773 .has_gpu_clamps = false,
3774 .needs_mbist_war = false,
3775 .has_impl_33v_pwr = true,
3776 .maybe_tz_only = false,
3777 .num_io_pads = 0,
3778 .io_pads = NULL,
3779 .num_pin_descs = 0,
3780 .pin_descs = NULL,
3781 .regs = &tegra234_pmc_regs,
3782 .init = NULL,
3783 .setup_irq_polarity = tegra186_pmc_setup_irq_polarity,
3784 .irq_set_wake = tegra186_pmc_irq_set_wake,
3785 .irq_set_type = tegra186_pmc_irq_set_type,
3786 .reset_sources = tegra234_reset_sources,
3787 .num_reset_sources = ARRAY_SIZE(tegra234_reset_sources),
3788 .reset_levels = tegra186_reset_levels,
3789 .num_reset_levels = ARRAY_SIZE(tegra186_reset_levels),
3790 .num_wake_events = 0,
3791 .wake_events = NULL,
3792 .pmc_clks_data = NULL,
3793 .num_pmc_clks = 0,
3794 .has_blink_output = false,
3795 };
3796
3797 static const struct of_device_id tegra_pmc_match[] = {
3798 { .compatible = "nvidia,tegra234-pmc", .data = &tegra234_pmc_soc },
3799 { .compatible = "nvidia,tegra194-pmc", .data = &tegra194_pmc_soc },
3800 { .compatible = "nvidia,tegra186-pmc", .data = &tegra186_pmc_soc },
3801 { .compatible = "nvidia,tegra210-pmc", .data = &tegra210_pmc_soc },
3802 { .compatible = "nvidia,tegra132-pmc", .data = &tegra124_pmc_soc },
3803 { .compatible = "nvidia,tegra124-pmc", .data = &tegra124_pmc_soc },
3804 { .compatible = "nvidia,tegra114-pmc", .data = &tegra114_pmc_soc },
3805 { .compatible = "nvidia,tegra30-pmc", .data = &tegra30_pmc_soc },
3806 { .compatible = "nvidia,tegra20-pmc", .data = &tegra20_pmc_soc },
3807 { }
3808 };
3809
tegra_pmc_sync_state(struct device * dev)3810 static void tegra_pmc_sync_state(struct device *dev)
3811 {
3812 int err;
3813
3814 /*
3815 * Newer device-trees have power domains, but we need to prepare all
3816 * device drivers with runtime PM and OPP support first, otherwise
3817 * state syncing is unsafe.
3818 */
3819 if (!pmc->soc->supports_core_domain)
3820 return;
3821
3822 /*
3823 * Older device-trees don't have core PD, and thus, there are
3824 * no dependencies that will block the state syncing. We shouldn't
3825 * mark the domain as synced in this case.
3826 */
3827 if (!pmc->core_domain_registered)
3828 return;
3829
3830 pmc->core_domain_state_synced = true;
3831
3832 /* this is a no-op if core regulator isn't used */
3833 mutex_lock(&pmc->powergates_lock);
3834 err = dev_pm_opp_sync_regulators(dev);
3835 mutex_unlock(&pmc->powergates_lock);
3836
3837 if (err)
3838 dev_err(dev, "failed to sync regulators: %d\n", err);
3839 }
3840
3841 static struct platform_driver tegra_pmc_driver = {
3842 .driver = {
3843 .name = "tegra-pmc",
3844 .suppress_bind_attrs = true,
3845 .of_match_table = tegra_pmc_match,
3846 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM)
3847 .pm = &tegra_pmc_pm_ops,
3848 #endif
3849 .sync_state = tegra_pmc_sync_state,
3850 },
3851 .probe = tegra_pmc_probe,
3852 };
3853 builtin_platform_driver(tegra_pmc_driver);
3854
tegra_pmc_detect_tz_only(struct tegra_pmc * pmc)3855 static bool __init tegra_pmc_detect_tz_only(struct tegra_pmc *pmc)
3856 {
3857 u32 value, saved;
3858
3859 saved = readl(pmc->base + pmc->soc->regs->scratch0);
3860 value = saved ^ 0xffffffff;
3861
3862 if (value == 0xffffffff)
3863 value = 0xdeadbeef;
3864
3865 /* write pattern and read it back */
3866 writel(value, pmc->base + pmc->soc->regs->scratch0);
3867 value = readl(pmc->base + pmc->soc->regs->scratch0);
3868
3869 /* if we read all-zeroes, access is restricted to TZ only */
3870 if (value == 0) {
3871 pr_info("access to PMC is restricted to TZ\n");
3872 return true;
3873 }
3874
3875 /* restore original value */
3876 writel(saved, pmc->base + pmc->soc->regs->scratch0);
3877
3878 return false;
3879 }
3880
3881 /*
3882 * Early initialization to allow access to registers in the very early boot
3883 * process.
3884 */
tegra_pmc_early_init(void)3885 static int __init tegra_pmc_early_init(void)
3886 {
3887 const struct of_device_id *match;
3888 struct device_node *np;
3889 struct resource regs;
3890 unsigned int i;
3891 bool invert;
3892
3893 mutex_init(&pmc->powergates_lock);
3894
3895 np = of_find_matching_node_and_match(NULL, tegra_pmc_match, &match);
3896 if (!np) {
3897 /*
3898 * Fall back to legacy initialization for 32-bit ARM only. All
3899 * 64-bit ARM device tree files for Tegra are required to have
3900 * a PMC node.
3901 *
3902 * This is for backwards-compatibility with old device trees
3903 * that didn't contain a PMC node. Note that in this case the
3904 * SoC data can't be matched and therefore powergating is
3905 * disabled.
3906 */
3907 if (IS_ENABLED(CONFIG_ARM) && soc_is_tegra()) {
3908 pr_warn("DT node not found, powergating disabled\n");
3909
3910 regs.start = 0x7000e400;
3911 regs.end = 0x7000e7ff;
3912 regs.flags = IORESOURCE_MEM;
3913
3914 pr_warn("Using memory region %pR\n", ®s);
3915 } else {
3916 /*
3917 * At this point we're not running on Tegra, so play
3918 * nice with multi-platform kernels.
3919 */
3920 return 0;
3921 }
3922 } else {
3923 /*
3924 * Extract information from the device tree if we've found a
3925 * matching node.
3926 */
3927 if (of_address_to_resource(np, 0, ®s) < 0) {
3928 pr_err("failed to get PMC registers\n");
3929 of_node_put(np);
3930 return -ENXIO;
3931 }
3932 }
3933
3934 pmc->base = ioremap(regs.start, resource_size(®s));
3935 if (!pmc->base) {
3936 pr_err("failed to map PMC registers\n");
3937 of_node_put(np);
3938 return -ENXIO;
3939 }
3940
3941 if (np) {
3942 pmc->soc = match->data;
3943
3944 if (pmc->soc->maybe_tz_only)
3945 pmc->tz_only = tegra_pmc_detect_tz_only(pmc);
3946
3947 /* Create a bitmap of the available and valid partitions */
3948 for (i = 0; i < pmc->soc->num_powergates; i++)
3949 if (pmc->soc->powergates[i])
3950 set_bit(i, pmc->powergates_available);
3951
3952 /*
3953 * Invert the interrupt polarity if a PMC device tree node
3954 * exists and contains the nvidia,invert-interrupt property.
3955 */
3956 invert = of_property_read_bool(np, "nvidia,invert-interrupt");
3957
3958 pmc->soc->setup_irq_polarity(pmc, np, invert);
3959
3960 of_node_put(np);
3961 }
3962
3963 return 0;
3964 }
3965 early_initcall(tegra_pmc_early_init);
3966