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42<li class="toctree-l1"><a class="reference internal" href="../index.html">Home</a></li>
43<li class="toctree-l1"><a class="reference internal" href="../about/index.html">About</a><ul>
44<li class="toctree-l2"><a class="reference internal" href="../about/features.html">1. Feature Overview</a><ul>
45<li class="toctree-l3"><a class="reference internal" href="../about/features.html#current-features">1.1. Current features</a></li>
46<li class="toctree-l3"><a class="reference internal" href="../about/features.html#still-to-come">1.2. Still to come</a></li>
47</ul>
48</li>
49<li class="toctree-l2"><a class="reference internal" href="../about/release-information.html">2. Release Processes</a><ul>
50<li class="toctree-l3"><a class="reference internal" href="../about/release-information.html#project-release-cadence">2.1. Project Release Cadence</a><ul>
51<li class="toctree-l4"><a class="reference internal" href="../about/release-information.html#upcoming-releases">2.1.1. Upcoming Releases</a></li>
52</ul>
53</li>
54<li class="toctree-l3"><a class="reference internal" href="../about/release-information.html#removal-of-deprecated-interfaces">2.2. Removal of Deprecated Interfaces</a></li>
55</ul>
56</li>
57<li class="toctree-l2"><a class="reference internal" href="../about/maintainers.html">3. Project Maintenance</a><ul>
58<li class="toctree-l3"><a class="reference internal" href="../about/maintainers.html#maintainers">3.1. Maintainers</a></li>
59<li class="toctree-l3"><a class="reference internal" href="../about/maintainers.html#code-owners">3.2. Code owners</a><ul>
60<li class="toctree-l4"><a class="reference internal" href="../about/maintainers.html#common-code">3.2.1. Common Code</a></li>
61<li class="toctree-l4"><a class="reference internal" href="../about/maintainers.html#drivers-libraries-and-framework-code">3.2.2. Drivers, Libraries and Framework Code</a></li>
62<li class="toctree-l4"><a class="reference internal" href="../about/maintainers.html#platform-ports">3.2.3. Platform Ports</a></li>
63<li class="toctree-l4"><a class="reference internal" href="../about/maintainers.html#secure-payloads-and-dispatchers">3.2.4. Secure Payloads and Dispatchers</a></li>
64<li class="toctree-l4"><a class="reference internal" href="../about/maintainers.html#tools">3.2.5. Tools</a></li>
65<li class="toctree-l4"><a class="reference internal" href="../about/maintainers.html#threat-model">3.2.6. Threat Model</a></li>
66<li class="toctree-l4"><a class="reference internal" href="../about/maintainers.html#conventional-changelog-extensions">3.2.7. Conventional Changelog Extensions</a></li>
67</ul>
68</li>
69</ul>
70</li>
71<li class="toctree-l2"><a class="reference internal" href="../about/contact.html">4. Support &amp; Contact</a><ul>
72<li class="toctree-l3"><a class="reference internal" href="../about/contact.html#mailing-lists">4.1. Mailing Lists</a></li>
73<li class="toctree-l3"><a class="reference internal" href="../about/contact.html#open-tech-forum-call">4.2. Open Tech Forum Call</a></li>
74<li class="toctree-l3"><a class="reference internal" href="../about/contact.html#issue-tracker">4.3. Issue Tracker</a></li>
75<li class="toctree-l3"><a class="reference internal" href="../about/contact.html#arm-licensees">4.4. Arm Licensees</a></li>
76</ul>
77</li>
78<li class="toctree-l2"><a class="reference internal" href="../about/acknowledgements.html">5. Contributor Acknowledgements</a></li>
79</ul>
80</li>
81<li class="toctree-l1"><a class="reference internal" href="../getting_started/index.html">Getting Started</a><ul>
82<li class="toctree-l2"><a class="reference internal" href="../getting_started/prerequisites.html">1. Prerequisites</a><ul>
83<li class="toctree-l3"><a class="reference internal" href="../getting_started/prerequisites.html#build-host">1.1. Build Host</a></li>
84<li class="toctree-l3"><a class="reference internal" href="../getting_started/prerequisites.html#toolchain">1.2. Toolchain</a></li>
85<li class="toctree-l3"><a class="reference internal" href="../getting_started/prerequisites.html#software-and-libraries">1.3. Software and Libraries</a><ul>
86<li class="toctree-l4"><a class="reference internal" href="../getting_started/prerequisites.html#package-installation-linux">1.3.1. Package Installation (Linux)</a></li>
87</ul>
88</li>
89<li class="toctree-l3"><a class="reference internal" href="../getting_started/prerequisites.html#supporting-files">1.4. Supporting Files</a></li>
90<li class="toctree-l3"><a class="reference internal" href="../getting_started/prerequisites.html#getting-the-tf-a-source">1.5. Getting the TF-A Source</a><ul>
91<li class="toctree-l4"><a class="reference internal" href="../getting_started/prerequisites.html#additional-steps-for-contributors">1.5.1. Additional Steps for Contributors</a></li>
92</ul>
93</li>
94</ul>
95</li>
96<li class="toctree-l2"><a class="reference internal" href="../getting_started/docs-build.html">2. Building Documentation</a><ul>
97<li class="toctree-l3"><a class="reference internal" href="../getting_started/docs-build.html#prerequisites">2.1. Prerequisites</a></li>
98<li class="toctree-l3"><a class="reference internal" href="../getting_started/docs-build.html#building-rendered-documentation">2.2. Building rendered documentation</a></li>
99<li class="toctree-l3"><a class="reference internal" href="../getting_started/docs-build.html#building-rendered-documentation-from-a-container">2.3. Building rendered documentation from a container</a></li>
100</ul>
101</li>
102<li class="toctree-l2"><a class="reference internal" href="../getting_started/tools-build.html">3. Building Supporting Tools</a><ul>
103<li class="toctree-l3"><a class="reference internal" href="../getting_started/tools-build.html#building-and-using-the-fip-tool">3.1. Building and using the FIP tool</a></li>
104<li class="toctree-l3"><a class="reference internal" href="../getting_started/tools-build.html#building-the-certificate-generation-tool">3.2. Building the Certificate Generation Tool</a><ul>
105<li class="toctree-l4"><a class="reference internal" href="../getting_started/tools-build.html#building-the-firmware-encryption-tool">3.2.1. Building the Firmware Encryption Tool</a></li>
106</ul>
107</li>
108</ul>
109</li>
110<li class="toctree-l2"><a class="reference internal" href="../getting_started/initial-build.html">4. Performing an Initial Build</a></li>
111<li class="toctree-l2"><a class="reference internal" href="../getting_started/build-options.html">5. Build Options</a><ul>
112<li class="toctree-l3"><a class="reference internal" href="../getting_started/build-options.html#common-build-options">5.1. Common build options</a></li>
113<li class="toctree-l3"><a class="reference internal" href="../getting_started/build-options.html#gicv3-driver-options">5.2. GICv3 driver options</a></li>
114<li class="toctree-l3"><a class="reference internal" href="../getting_started/build-options.html#debugging-options">5.3. Debugging options</a></li>
115<li class="toctree-l3"><a class="reference internal" href="../getting_started/build-options.html#firmware-update-options">5.4. Firmware update options</a></li>
116</ul>
117</li>
118<li class="toctree-l2"><a class="reference internal" href="../getting_started/image-terminology.html">6. Image Terminology</a><ul>
119<li class="toctree-l3"><a class="reference internal" href="../getting_started/image-terminology.html#general-notes">6.1. General Notes</a></li>
120<li class="toctree-l3"><a class="reference internal" href="../getting_started/image-terminology.html#trusted-firmware-images">6.2. Trusted Firmware Images</a><ul>
121<li class="toctree-l4"><a class="reference internal" href="../getting_started/image-terminology.html#ap-boot-rom-ap-bl1">6.2.1. AP Boot ROM: <code class="docutils literal notranslate"><span class="pre">AP_BL1</span></code></a></li>
122<li class="toctree-l4"><a class="reference internal" href="../getting_started/image-terminology.html#ap-ram-firmware-ap-bl2">6.2.2. AP RAM Firmware: <code class="docutils literal notranslate"><span class="pre">AP_BL2</span></code></a></li>
123<li class="toctree-l4"><a class="reference internal" href="../getting_started/image-terminology.html#el3-runtime-firmware-ap-bl31">6.2.3. EL3 Runtime Firmware: <code class="docutils literal notranslate"><span class="pre">AP_BL31</span></code></a></li>
124<li class="toctree-l4"><a class="reference internal" href="../getting_started/image-terminology.html#secure-el1-payload-sp-ap-bl32">6.2.4. Secure-EL1 Payload (SP): <code class="docutils literal notranslate"><span class="pre">AP_BL32</span></code></a></li>
125<li class="toctree-l4"><a class="reference internal" href="../getting_started/image-terminology.html#ap-normal-world-firmware-ap-bl33">6.2.5. AP Normal World Firmware: <code class="docutils literal notranslate"><span class="pre">AP_BL33</span></code></a></li>
126<li class="toctree-l4"><a class="reference internal" href="../getting_started/image-terminology.html#other-ap-3rd-level-images-ap-bl3-xxx">6.2.6. Other AP 3rd level images: <code class="docutils literal notranslate"><span class="pre">AP_BL3_XXX</span></code></a></li>
127<li class="toctree-l4"><a class="reference internal" href="../getting_started/image-terminology.html#realm-monitor-management-firmware-rmm">6.2.7. Realm Monitor Management Firmware: <code class="docutils literal notranslate"><span class="pre">RMM</span></code></a></li>
128<li class="toctree-l4"><a class="reference internal" href="../getting_started/image-terminology.html#scp-boot-rom-scp-bl1-previously-bl0">6.2.8. SCP Boot ROM: <code class="docutils literal notranslate"><span class="pre">SCP_BL1</span></code> (previously <code class="docutils literal notranslate"><span class="pre">BL0</span></code>)</a></li>
129<li class="toctree-l4"><a class="reference internal" href="../getting_started/image-terminology.html#scp-ram-firmware-scp-bl2-previously-bl3-0">6.2.9. SCP RAM Firmware: <code class="docutils literal notranslate"><span class="pre">SCP_BL2</span></code> (previously <code class="docutils literal notranslate"><span class="pre">BL3-0</span></code>)</a></li>
130</ul>
131</li>
132<li class="toctree-l3"><a class="reference internal" href="../getting_started/image-terminology.html#firmware-update-fwu-images">6.3. Firmware Update (FWU) Images</a><ul>
133<li class="toctree-l4"><a class="reference internal" href="../getting_started/image-terminology.html#ap-firmware-update-boot-rom-ap-ns-bl1u">6.3.1. AP Firmware Update Boot ROM: <code class="docutils literal notranslate"><span class="pre">AP_NS_BL1U</span></code></a></li>
134<li class="toctree-l4"><a class="reference internal" href="../getting_started/image-terminology.html#ap-firmware-update-config-ap-bl2u">6.3.2. AP Firmware Update Config: <code class="docutils literal notranslate"><span class="pre">AP_BL2U</span></code></a></li>
135<li class="toctree-l4"><a class="reference internal" href="../getting_started/image-terminology.html#scp-firmware-update-config-scp-bl2u-previously-bl2-u0">6.3.3. SCP Firmware Update Config: <code class="docutils literal notranslate"><span class="pre">SCP_BL2U</span></code> (previously <code class="docutils literal notranslate"><span class="pre">BL2-U0</span></code>)</a></li>
136<li class="toctree-l4"><a class="reference internal" href="../getting_started/image-terminology.html#ap-firmware-updater-ap-ns-bl2u-previously-bl3-u">6.3.4. AP Firmware Updater: <code class="docutils literal notranslate"><span class="pre">AP_NS_BL2U</span></code> (previously <code class="docutils literal notranslate"><span class="pre">BL3-U</span></code>)</a></li>
137</ul>
138</li>
139<li class="toctree-l3"><a class="reference internal" href="../getting_started/image-terminology.html#other-processor-firmware-images">6.4. Other Processor Firmware Images</a><ul>
140<li class="toctree-l4"><a class="reference internal" href="../getting_started/image-terminology.html#mcp-boot-rom-mcp-bl1">6.4.1. MCP Boot ROM: <code class="docutils literal notranslate"><span class="pre">MCP_BL1</span></code></a></li>
141<li class="toctree-l4"><a class="reference internal" href="../getting_started/image-terminology.html#mcp-ram-firmware-mcp-bl2">6.4.2. MCP RAM Firmware: <code class="docutils literal notranslate"><span class="pre">MCP_BL2</span></code></a></li>
142</ul>
143</li>
144</ul>
145</li>
146<li class="toctree-l2"><a class="reference internal" href="../getting_started/porting-guide.html">7. Porting Guide</a><ul>
147<li class="toctree-l3"><a class="reference internal" href="../getting_started/porting-guide.html#introduction">7.1. Introduction</a></li>
148<li class="toctree-l3"><a class="reference internal" href="../getting_started/porting-guide.html#common-modifications">7.2. Common modifications</a></li>
149<li class="toctree-l3"><a class="reference internal" href="../getting_started/porting-guide.html#common-mandatory-modifications">7.3. Common mandatory modifications</a><ul>
150<li class="toctree-l4"><a class="reference internal" href="../getting_started/porting-guide.html#file-platform-def-h-mandatory">7.3.1. File : platform_def.h [mandatory]</a></li>
151<li class="toctree-l4"><a class="reference internal" href="../getting_started/porting-guide.html#file-plat-macros-s-mandatory">7.3.2. File : plat_macros.S [mandatory]</a></li>
152</ul>
153</li>
154<li class="toctree-l3"><a class="reference internal" href="../getting_started/porting-guide.html#handling-reset">7.4. Handling Reset</a><ul>
155<li class="toctree-l4"><a class="reference internal" href="../getting_started/porting-guide.html#function-plat-get-my-entrypoint-mandatory-when-programmable-reset-address-0">7.4.1. Function : plat_get_my_entrypoint() [mandatory when PROGRAMMABLE_RESET_ADDRESS == 0]</a></li>
156<li class="toctree-l4"><a class="reference internal" href="../getting_started/porting-guide.html#function-plat-secondary-cold-boot-setup-mandatory-when-cold-boot-single-cpu-0">7.4.2. Function : plat_secondary_cold_boot_setup() [mandatory when COLD_BOOT_SINGLE_CPU == 0]</a></li>
157<li class="toctree-l4"><a class="reference internal" href="../getting_started/porting-guide.html#function-plat-is-my-cpu-primary-mandatory-when-cold-boot-single-cpu-0">7.4.3. Function : plat_is_my_cpu_primary() [mandatory when COLD_BOOT_SINGLE_CPU == 0]</a></li>
158<li class="toctree-l4"><a class="reference internal" href="../getting_started/porting-guide.html#function-platform-mem-init-mandatory">7.4.4. Function : platform_mem_init() [mandatory]</a></li>
159<li class="toctree-l4"><a class="reference internal" href="../getting_started/porting-guide.html#function-plat-get-rotpk-info">7.4.5. Function: plat_get_rotpk_info()</a></li>
160<li class="toctree-l4"><a class="reference internal" href="../getting_started/porting-guide.html#function-plat-get-nv-ctr">7.4.6. Function: plat_get_nv_ctr()</a></li>
161<li class="toctree-l4"><a class="reference internal" href="../getting_started/porting-guide.html#function-plat-set-nv-ctr">7.4.7. Function: plat_set_nv_ctr()</a></li>
162<li class="toctree-l4"><a class="reference internal" href="../getting_started/porting-guide.html#function-plat-set-nv-ctr2">7.4.8. Function: plat_set_nv_ctr2()</a></li>
163</ul>
164</li>
165<li class="toctree-l3"><a class="reference internal" href="../getting_started/porting-guide.html#common-mandatory-function-modifications">7.5. Common mandatory function modifications</a><ul>
166<li class="toctree-l4"><a class="reference internal" href="../getting_started/porting-guide.html#function-plat-my-core-pos">7.5.1. Function : plat_my_core_pos()</a></li>
167<li class="toctree-l4"><a class="reference internal" href="../getting_started/porting-guide.html#function-plat-core-pos-by-mpidr">7.5.2. Function : plat_core_pos_by_mpidr()</a></li>
168<li class="toctree-l4"><a class="reference internal" href="../getting_started/porting-guide.html#function-plat-get-mbedtls-heap-when-trusted-board-boot-1">7.5.3. Function : plat_get_mbedtls_heap() [when TRUSTED_BOARD_BOOT == 1]</a></li>
169<li class="toctree-l4"><a class="reference internal" href="../getting_started/porting-guide.html#function-plat-get-enc-key-info-when-fw-enc-status-0-or-1">7.5.4. Function : plat_get_enc_key_info() [when FW_ENC_STATUS == 0 or 1]</a></li>
170<li class="toctree-l4"><a class="reference internal" href="../getting_started/porting-guide.html#function-plat-fwu-set-images-source-when-psa-fwu-support-1">7.5.5. Function : plat_fwu_set_images_source() [when PSA_FWU_SUPPORT == 1]</a></li>
171<li class="toctree-l4"><a class="reference internal" href="../getting_started/porting-guide.html#function-plat-fwu-set-metadata-image-source-when-psa-fwu-support-1">7.5.6. Function : plat_fwu_set_metadata_image_source() [when PSA_FWU_SUPPORT == 1]</a></li>
172</ul>
173</li>
174<li class="toctree-l3"><a class="reference internal" href="../getting_started/porting-guide.html#common-optional-modifications">7.6. Common optional modifications</a><ul>
175<li class="toctree-l4"><a class="reference internal" href="../getting_started/porting-guide.html#function-plat-set-my-stack">7.6.1. Function : plat_set_my_stack()</a></li>
176<li class="toctree-l4"><a class="reference internal" href="../getting_started/porting-guide.html#function-plat-get-my-stack">7.6.2. Function : plat_get_my_stack()</a></li>
177<li class="toctree-l4"><a class="reference internal" href="../getting_started/porting-guide.html#function-plat-report-exception">7.6.3. Function : plat_report_exception()</a></li>
178<li class="toctree-l4"><a class="reference internal" href="../getting_started/porting-guide.html#function-plat-reset-handler">7.6.4. Function : plat_reset_handler()</a></li>
179<li class="toctree-l4"><a class="reference internal" href="../getting_started/porting-guide.html#function-plat-disable-acp">7.6.5. Function : plat_disable_acp()</a></li>
180<li class="toctree-l4"><a class="reference internal" href="../getting_started/porting-guide.html#function-plat-error-handler">7.6.6. Function : plat_error_handler()</a></li>
181<li class="toctree-l4"><a class="reference internal" href="../getting_started/porting-guide.html#function-plat-panic-handler">7.6.7. Function : plat_panic_handler()</a></li>
182<li class="toctree-l4"><a class="reference internal" href="../getting_started/porting-guide.html#function-plat-get-bl-image-load-info">7.6.8. Function : plat_get_bl_image_load_info()</a></li>
183<li class="toctree-l4"><a class="reference internal" href="../getting_started/porting-guide.html#function-plat-get-next-bl-params">7.6.9. Function : plat_get_next_bl_params()</a></li>
184<li class="toctree-l4"><a class="reference internal" href="../getting_started/porting-guide.html#function-plat-get-stack-protector-canary">7.6.10. Function : plat_get_stack_protector_canary()</a></li>
185<li class="toctree-l4"><a class="reference internal" href="../getting_started/porting-guide.html#function-plat-flush-next-bl-params">7.6.11. Function : plat_flush_next_bl_params()</a></li>
186<li class="toctree-l4"><a class="reference internal" href="../getting_started/porting-guide.html#function-plat-log-get-prefix">7.6.12. Function : plat_log_get_prefix()</a></li>
187<li class="toctree-l4"><a class="reference internal" href="../getting_started/porting-guide.html#function-plat-get-soc-version">7.6.13. Function : plat_get_soc_version()</a></li>
188<li class="toctree-l4"><a class="reference internal" href="../getting_started/porting-guide.html#function-plat-get-soc-revision">7.6.14. Function : plat_get_soc_revision()</a></li>
189<li class="toctree-l4"><a class="reference internal" href="../getting_started/porting-guide.html#function-plat-is-smccc-feature-available">7.6.15. Function : plat_is_smccc_feature_available()</a></li>
190<li class="toctree-l4"><a class="reference internal" href="../getting_started/porting-guide.html#function-plat-mboot-measure-image">7.6.16. Function : plat_mboot_measure_image()</a></li>
191</ul>
192</li>
193<li class="toctree-l3"><a class="reference internal" href="../getting_started/porting-guide.html#modifications-specific-to-a-boot-loader-stage">7.7. Modifications specific to a Boot Loader stage</a></li>
194<li class="toctree-l3"><a class="reference internal" href="../getting_started/porting-guide.html#boot-loader-stage-1-bl1">7.8. Boot Loader Stage 1 (BL1)</a><ul>
195<li class="toctree-l4"><a class="reference internal" href="../getting_started/porting-guide.html#function-bl1-early-platform-setup-mandatory">7.8.1. Function : bl1_early_platform_setup() [mandatory]</a></li>
196<li class="toctree-l4"><a class="reference internal" href="../getting_started/porting-guide.html#function-bl1-plat-arch-setup-mandatory">7.8.2. Function : bl1_plat_arch_setup() [mandatory]</a></li>
197<li class="toctree-l4"><a class="reference internal" href="../getting_started/porting-guide.html#function-bl1-platform-setup-mandatory">7.8.3. Function : bl1_platform_setup() [mandatory]</a></li>
198<li class="toctree-l4"><a class="reference internal" href="../getting_started/porting-guide.html#function-bl1-plat-sec-mem-layout-mandatory">7.8.4. Function : bl1_plat_sec_mem_layout() [mandatory]</a></li>
199<li class="toctree-l4"><a class="reference internal" href="../getting_started/porting-guide.html#function-bl1-plat-prepare-exit-optional">7.8.5. Function : bl1_plat_prepare_exit() [optional]</a></li>
200<li class="toctree-l4"><a class="reference internal" href="../getting_started/porting-guide.html#function-bl1-plat-set-ep-info-optional">7.8.6. Function : bl1_plat_set_ep_info() [optional]</a></li>
201<li class="toctree-l4"><a class="reference internal" href="../getting_started/porting-guide.html#function-bl1-plat-get-next-image-id-optional">7.8.7. Function : bl1_plat_get_next_image_id() [optional]</a></li>
202<li class="toctree-l4"><a class="reference internal" href="../getting_started/porting-guide.html#function-bl1-plat-get-image-desc-optional">7.8.8. Function : bl1_plat_get_image_desc() [optional]</a></li>
203<li class="toctree-l4"><a class="reference internal" href="../getting_started/porting-guide.html#function-bl1-plat-handle-pre-image-load-optional">7.8.9. Function : bl1_plat_handle_pre_image_load() [optional]</a></li>
204<li class="toctree-l4"><a class="reference internal" href="../getting_started/porting-guide.html#function-bl1-plat-handle-post-image-load-optional">7.8.10. Function : bl1_plat_handle_post_image_load() [optional]</a></li>
205<li class="toctree-l4"><a class="reference internal" href="../getting_started/porting-guide.html#function-bl1-plat-fwu-done-optional">7.8.11. Function : bl1_plat_fwu_done() [optional]</a></li>
206<li class="toctree-l4"><a class="reference internal" href="../getting_started/porting-guide.html#function-bl1-plat-mem-check-mandatory">7.8.12. Function : bl1_plat_mem_check() [mandatory]</a></li>
207<li class="toctree-l4"><a class="reference internal" href="../getting_started/porting-guide.html#function-bl1-plat-mboot-init-optional">7.8.13. Function : bl1_plat_mboot_init() [optional]</a></li>
208<li class="toctree-l4"><a class="reference internal" href="../getting_started/porting-guide.html#function-bl1-plat-mboot-finish-optional">7.8.14. Function : bl1_plat_mboot_finish() [optional]</a></li>
209</ul>
210</li>
211<li class="toctree-l3"><a class="reference internal" href="../getting_started/porting-guide.html#boot-loader-stage-2-bl2">7.9. Boot Loader Stage 2 (BL2)</a><ul>
212<li class="toctree-l4"><a class="reference internal" href="../getting_started/porting-guide.html#function-bl2-early-platform-setup2-mandatory">7.9.1. Function : bl2_early_platform_setup2() [mandatory]</a></li>
213<li class="toctree-l4"><a class="reference internal" href="../getting_started/porting-guide.html#function-bl2-plat-arch-setup-mandatory">7.9.2. Function : bl2_plat_arch_setup() [mandatory]</a></li>
214<li class="toctree-l4"><a class="reference internal" href="../getting_started/porting-guide.html#function-bl2-platform-setup-mandatory">7.9.3. Function : bl2_platform_setup() [mandatory]</a></li>
215<li class="toctree-l4"><a class="reference internal" href="../getting_started/porting-guide.html#function-bl2-plat-handle-pre-image-load-optional">7.9.4. Function : bl2_plat_handle_pre_image_load() [optional]</a></li>
216<li class="toctree-l4"><a class="reference internal" href="../getting_started/porting-guide.html#function-bl2-plat-handle-post-image-load-optional">7.9.5. Function : bl2_plat_handle_post_image_load() [optional]</a></li>
217<li class="toctree-l4"><a class="reference internal" href="../getting_started/porting-guide.html#function-bl2-plat-preload-setup-optional">7.9.6. Function : bl2_plat_preload_setup [optional]</a></li>
218<li class="toctree-l4"><a class="reference internal" href="../getting_started/porting-guide.html#function-plat-try-next-boot-source-optional">7.9.7. Function : plat_try_next_boot_source() [optional]</a></li>
219</ul>
220</li>
221<li class="toctree-l3"><a class="reference internal" href="../getting_started/porting-guide.html#boot-loader-stage-2-bl2-at-el3">7.10. Boot Loader Stage 2 (BL2) at EL3</a><ul>
222<li class="toctree-l4"><a class="reference internal" href="../getting_started/porting-guide.html#function-bl2-el3-early-platform-setup-mandatory">7.10.1. Function : bl2_el3_early_platform_setup() [mandatory]</a></li>
223<li class="toctree-l4"><a class="reference internal" href="../getting_started/porting-guide.html#function-bl2-el3-plat-arch-setup-mandatory">7.10.2. Function : bl2_el3_plat_arch_setup() [mandatory]</a></li>
224<li class="toctree-l4"><a class="reference internal" href="../getting_started/porting-guide.html#function-bl2-el3-plat-prepare-exit-optional">7.10.3. Function : bl2_el3_plat_prepare_exit() [optional]</a></li>
225</ul>
226</li>
227<li class="toctree-l3"><a class="reference internal" href="../getting_started/porting-guide.html#fwu-boot-loader-stage-2-bl2u">7.11. FWU Boot Loader Stage 2 (BL2U)</a><ul>
228<li class="toctree-l4"><a class="reference internal" href="../getting_started/porting-guide.html#function-bl2u-early-platform-setup-mandatory">7.11.1. Function : bl2u_early_platform_setup() [mandatory]</a></li>
229<li class="toctree-l4"><a class="reference internal" href="../getting_started/porting-guide.html#function-bl2u-plat-arch-setup-mandatory">7.11.2. Function : bl2u_plat_arch_setup() [mandatory]</a></li>
230<li class="toctree-l4"><a class="reference internal" href="../getting_started/porting-guide.html#function-bl2u-platform-setup-mandatory">7.11.3. Function : bl2u_platform_setup() [mandatory]</a></li>
231<li class="toctree-l4"><a class="reference internal" href="../getting_started/porting-guide.html#function-bl2u-plat-handle-scp-bl2u-optional">7.11.4. Function : bl2u_plat_handle_scp_bl2u() [optional]</a></li>
232<li class="toctree-l4"><a class="reference internal" href="../getting_started/porting-guide.html#function-bl2-plat-mboot-init-optional">7.11.5. Function : bl2_plat_mboot_init() [optional]</a></li>
233<li class="toctree-l4"><a class="reference internal" href="../getting_started/porting-guide.html#function-bl2-plat-mboot-finish-optional">7.11.6. Function : bl2_plat_mboot_finish() [optional]</a></li>
234</ul>
235</li>
236<li class="toctree-l3"><a class="reference internal" href="../getting_started/porting-guide.html#boot-loader-stage-3-1-bl31">7.12. Boot Loader Stage 3-1 (BL31)</a><ul>
237<li class="toctree-l4"><a class="reference internal" href="../getting_started/porting-guide.html#function-bl31-early-platform-setup2-mandatory">7.12.1. Function : bl31_early_platform_setup2() [mandatory]</a></li>
238<li class="toctree-l4"><a class="reference internal" href="../getting_started/porting-guide.html#function-bl31-plat-arch-setup-mandatory">7.12.2. Function : bl31_plat_arch_setup() [mandatory]</a></li>
239<li class="toctree-l4"><a class="reference internal" href="../getting_started/porting-guide.html#function-bl31-platform-setup-mandatory">7.12.3. Function : bl31_platform_setup() [mandatory]</a></li>
240<li class="toctree-l4"><a class="reference internal" href="../getting_started/porting-guide.html#function-bl31-plat-runtime-setup-optional">7.12.4. Function : bl31_plat_runtime_setup() [optional]</a></li>
241<li class="toctree-l4"><a class="reference internal" href="../getting_started/porting-guide.html#function-bl31-plat-get-next-image-ep-info-mandatory">7.12.5. Function : bl31_plat_get_next_image_ep_info() [mandatory]</a></li>
242<li class="toctree-l4"><a class="reference internal" href="../getting_started/porting-guide.html#function-bl31-plat-enable-mmu-optional">7.12.6. Function : bl31_plat_enable_mmu [optional]</a></li>
243<li class="toctree-l4"><a class="reference internal" href="../getting_started/porting-guide.html#function-plat-init-apkey-optional">7.12.7. Function : plat_init_apkey [optional]</a></li>
244<li class="toctree-l4"><a class="reference internal" href="../getting_started/porting-guide.html#function-plat-get-syscnt-freq2-mandatory">7.12.8. Function : plat_get_syscnt_freq2() [mandatory]</a></li>
245<li class="toctree-l4"><a class="reference internal" href="../getting_started/porting-guide.html#function-plat-arm-set-twedel-scr-el3-optional">7.12.9. Function : plat_arm_set_twedel_scr_el3() [optional]</a></li>
246<li class="toctree-l4"><a class="reference internal" href="../getting_started/porting-guide.html#define-plat-percpu-bakery-lock-size-optional">7.12.10. #define : PLAT_PERCPU_BAKERY_LOCK_SIZE [optional]</a></li>
247<li class="toctree-l4"><a class="reference internal" href="../getting_started/porting-guide.html#sdei-porting-requirements">7.12.11. SDEI porting requirements</a></li>
248<li class="toctree-l4"><a class="reference internal" href="../getting_started/porting-guide.html#trng-porting-requirements">7.12.12. TRNG porting requirements</a></li>
249</ul>
250</li>
251<li class="toctree-l3"><a class="reference internal" href="../getting_started/porting-guide.html#power-state-coordination-interface-in-bl31">7.13. Power State Coordination Interface (in BL31)</a><ul>
252<li class="toctree-l4"><a class="reference internal" href="../getting_started/porting-guide.html#function-plat-psci-stat-accounting-start-optional">7.13.1. Function : plat_psci_stat_accounting_start() [optional]</a></li>
253<li class="toctree-l4"><a class="reference internal" href="../getting_started/porting-guide.html#function-plat-psci-stat-accounting-stop-optional">7.13.2. Function : plat_psci_stat_accounting_stop() [optional]</a></li>
254<li class="toctree-l4"><a class="reference internal" href="../getting_started/porting-guide.html#function-plat-psci-stat-get-residency-optional">7.13.3. Function : plat_psci_stat_get_residency() [optional]</a></li>
255<li class="toctree-l4"><a class="reference internal" href="../getting_started/porting-guide.html#function-plat-get-target-pwr-state-optional">7.13.4. Function : plat_get_target_pwr_state() [optional]</a></li>
256<li class="toctree-l4"><a class="reference internal" href="../getting_started/porting-guide.html#function-plat-get-power-domain-tree-desc-mandatory">7.13.5. Function : plat_get_power_domain_tree_desc() [mandatory]</a></li>
257<li class="toctree-l4"><a class="reference internal" href="../getting_started/porting-guide.html#function-plat-setup-psci-ops-mandatory">7.13.6. Function : plat_setup_psci_ops() [mandatory]</a></li>
258</ul>
259</li>
260<li class="toctree-l3"><a class="reference internal" href="../getting_started/porting-guide.html#interrupt-management-framework-in-bl31">7.14. Interrupt Management framework (in BL31)</a><ul>
261<li class="toctree-l4"><a class="reference internal" href="../getting_started/porting-guide.html#function-plat-interrupt-type-to-line-mandatory">7.14.1. Function : plat_interrupt_type_to_line() [mandatory]</a></li>
262<li class="toctree-l4"><a class="reference internal" href="../getting_started/porting-guide.html#function-plat-ic-get-pending-interrupt-type-mandatory">7.14.2. Function : plat_ic_get_pending_interrupt_type() [mandatory]</a></li>
263<li class="toctree-l4"><a class="reference internal" href="../getting_started/porting-guide.html#function-plat-ic-get-pending-interrupt-id-mandatory">7.14.3. Function : plat_ic_get_pending_interrupt_id() [mandatory]</a></li>
264<li class="toctree-l4"><a class="reference internal" href="../getting_started/porting-guide.html#function-plat-ic-acknowledge-interrupt-mandatory">7.14.4. Function : plat_ic_acknowledge_interrupt() [mandatory]</a></li>
265<li class="toctree-l4"><a class="reference internal" href="../getting_started/porting-guide.html#function-plat-ic-end-of-interrupt-mandatory">7.14.5. Function : plat_ic_end_of_interrupt() [mandatory]</a></li>
266<li class="toctree-l4"><a class="reference internal" href="../getting_started/porting-guide.html#function-plat-ic-get-interrupt-type-mandatory">7.14.6. Function : plat_ic_get_interrupt_type() [mandatory]</a></li>
267</ul>
268</li>
269<li class="toctree-l3"><a class="reference internal" href="../getting_started/porting-guide.html#crash-reporting-mechanism-in-bl31">7.15. Crash Reporting mechanism (in BL31)</a><ul>
270<li class="toctree-l4"><a class="reference internal" href="../getting_started/porting-guide.html#function-plat-crash-console-init-mandatory">7.15.1. Function : plat_crash_console_init [mandatory]</a></li>
271<li class="toctree-l4"><a class="reference internal" href="../getting_started/porting-guide.html#function-plat-crash-console-putc-mandatory">7.15.2. Function : plat_crash_console_putc [mandatory]</a></li>
272<li class="toctree-l4"><a class="reference internal" href="../getting_started/porting-guide.html#function-plat-crash-console-flush-mandatory">7.15.3. Function : plat_crash_console_flush [mandatory]</a></li>
273</ul>
274</li>
275<li class="toctree-l3"><a class="reference internal" href="../getting_started/porting-guide.html#external-abort-handling-and-ras-support">7.16. External Abort handling and RAS Support</a><ul>
276<li class="toctree-l4"><a class="reference internal" href="../getting_started/porting-guide.html#function-plat-ea-handler">7.16.1. Function : plat_ea_handler</a></li>
277<li class="toctree-l4"><a class="reference internal" href="../getting_started/porting-guide.html#function-plat-handle-uncontainable-ea">7.16.2. Function : plat_handle_uncontainable_ea</a></li>
278<li class="toctree-l4"><a class="reference internal" href="../getting_started/porting-guide.html#function-plat-handle-double-fault">7.16.3. Function : plat_handle_double_fault</a></li>
279<li class="toctree-l4"><a class="reference internal" href="../getting_started/porting-guide.html#function-plat-handle-el3-ea">7.16.4. Function : plat_handle_el3_ea</a></li>
280</ul>
281</li>
282<li class="toctree-l3"><a class="reference internal" href="../getting_started/porting-guide.html#build-flags">7.17. Build flags</a></li>
283<li class="toctree-l3"><a class="reference internal" href="../getting_started/porting-guide.html#platform-include-paths">7.18. Platform include paths</a></li>
284<li class="toctree-l3"><a class="reference internal" href="../getting_started/porting-guide.html#c-library">7.19. C Library</a></li>
285<li class="toctree-l3"><a class="reference internal" href="../getting_started/porting-guide.html#storage-abstraction-layer">7.20. Storage abstraction layer</a></li>
286</ul>
287</li>
288<li class="toctree-l2"><a class="reference internal" href="../getting_started/psci-lib-integration-guide.html">8. PSCI Library Integration guide for Armv8-A AArch32 systems</a><ul>
289<li class="toctree-l3"><a class="reference internal" href="../getting_started/psci-lib-integration-guide.html#generic-call-sequence-for-psci-library-interface-aarch32">8.1. Generic call sequence for PSCI Library interface (AArch32)</a></li>
290<li class="toctree-l3"><a class="reference internal" href="../getting_started/psci-lib-integration-guide.html#psci-cpu-context-management">8.2. PSCI CPU context management</a></li>
291<li class="toctree-l3"><a class="reference internal" href="../getting_started/psci-lib-integration-guide.html#psci-library-interface">8.3. PSCI Library Interface</a><ul>
292<li class="toctree-l4"><a class="reference internal" href="../getting_started/psci-lib-integration-guide.html#interface-psci-setup">8.3.1. Interface : psci_setup()</a></li>
293<li class="toctree-l4"><a class="reference internal" href="../getting_started/psci-lib-integration-guide.html#interface-psci-prepare-next-non-secure-ctx">8.3.2. Interface : psci_prepare_next_non_secure_ctx()</a></li>
294<li class="toctree-l4"><a class="reference internal" href="../getting_started/psci-lib-integration-guide.html#interface-psci-register-spd-pm-hook">8.3.3. Interface : psci_register_spd_pm_hook()</a></li>
295<li class="toctree-l4"><a class="reference internal" href="../getting_started/psci-lib-integration-guide.html#interface-psci-smc-handler">8.3.4. Interface : psci_smc_handler()</a></li>
296<li class="toctree-l4"><a class="reference internal" href="../getting_started/psci-lib-integration-guide.html#interface-psci-warmboot-entrypoint">8.3.5. Interface : psci_warmboot_entrypoint()</a></li>
297</ul>
298</li>
299<li class="toctree-l3"><a class="reference internal" href="../getting_started/psci-lib-integration-guide.html#el3-runtime-software-dependencies">8.4. EL3 Runtime Software dependencies</a><ul>
300<li class="toctree-l4"><a class="reference internal" href="../getting_started/psci-lib-integration-guide.html#general-dependencies">8.4.1. General dependencies</a></li>
301<li class="toctree-l4"><a class="reference internal" href="../getting_started/psci-lib-integration-guide.html#cpu-context-management-api">8.4.2. CPU Context management API</a></li>
302<li class="toctree-l4"><a class="reference internal" href="../getting_started/psci-lib-integration-guide.html#platform-api">8.4.3. Platform API</a></li>
303<li class="toctree-l4"><a class="reference internal" href="../getting_started/psci-lib-integration-guide.html#secure-payload-power-management-callback">8.4.4. Secure payload power management callback</a></li>
304<li class="toctree-l4"><a class="reference internal" href="../getting_started/psci-lib-integration-guide.html#cpu-operations">8.4.5. CPU operations</a></li>
305</ul>
306</li>
307</ul>
308</li>
309<li class="toctree-l2"><a class="reference internal" href="../getting_started/rt-svc-writers-guide.html">9. EL3 Runtime Service Writer’s Guide</a><ul>
310<li class="toctree-l3"><a class="reference internal" href="../getting_started/rt-svc-writers-guide.html#introduction">9.1. Introduction</a></li>
311<li class="toctree-l3"><a class="reference internal" href="../getting_started/rt-svc-writers-guide.html#owning-entities-call-types-and-function-ids">9.2. Owning Entities, Call Types and Function IDs</a></li>
312<li class="toctree-l3"><a class="reference internal" href="../getting_started/rt-svc-writers-guide.html#getting-started">9.3. Getting started</a></li>
313<li class="toctree-l3"><a class="reference internal" href="../getting_started/rt-svc-writers-guide.html#registering-a-runtime-service">9.4. Registering a runtime service</a></li>
314<li class="toctree-l3"><a class="reference internal" href="../getting_started/rt-svc-writers-guide.html#initializing-a-runtime-service">9.5. Initializing a runtime service</a></li>
315<li class="toctree-l3"><a class="reference internal" href="../getting_started/rt-svc-writers-guide.html#handling-runtime-service-requests">9.6. Handling runtime service requests</a></li>
316<li class="toctree-l3"><a class="reference internal" href="../getting_started/rt-svc-writers-guide.html#services-that-contain-multiple-sub-services">9.7. Services that contain multiple sub-services</a></li>
317<li class="toctree-l3"><a class="reference internal" href="../getting_started/rt-svc-writers-guide.html#secure-el1-payload-dispatcher-service-spd">9.8. Secure-EL1 Payload Dispatcher service (SPD)</a></li>
318</ul>
319</li>
320</ul>
321</li>
322<li class="toctree-l1"><a class="reference internal" href="../process/index.html">Processes &amp; Policies</a><ul>
323<li class="toctree-l2"><a class="reference internal" href="../process/security.html">1. Security Handling</a><ul>
324<li class="toctree-l3"><a class="reference internal" href="../process/security.html#security-disclosures">1.1. Security Disclosures</a></li>
325<li class="toctree-l3"><a class="reference internal" href="../process/security.html#found-a-security-issue">1.2. Found a Security Issue?</a></li>
326<li class="toctree-l3"><a class="reference internal" href="../process/security.html#attribution">1.3. Attribution</a></li>
327<li class="toctree-l3"><a class="reference internal" href="../process/security.html#security-advisories">1.4. Security Advisories</a></li>
328</ul>
329</li>
330<li class="toctree-l2"><a class="reference internal" href="../process/platform-compatibility-policy.html">2. Platform Compatibility Policy</a><ul>
331<li class="toctree-l3"><a class="reference internal" href="../process/platform-compatibility-policy.html#introduction">2.1. Introduction</a></li>
332<li class="toctree-l3"><a class="reference internal" href="../process/platform-compatibility-policy.html#id1">2.2. Platform compatibility policy</a></li>
333</ul>
334</li>
335<li class="toctree-l2"><a class="reference internal" href="../process/commit-style.html">3. Commit Style</a><ul>
336<li class="toctree-l3"><a class="reference internal" href="../process/commit-style.html#adding-scopes">3.1. Adding Scopes</a></li>
337<li class="toctree-l3"><a class="reference internal" href="../process/commit-style.html#mandated-trailers">3.2. Mandated Trailers</a></li>
338</ul>
339</li>
340<li class="toctree-l2"><a class="reference internal" href="../process/coding-style.html">4. Coding Style</a><ul>
341<li class="toctree-l3"><a class="reference internal" href="../process/coding-style.html#file-encoding">4.1. File Encoding</a></li>
342<li class="toctree-l3"><a class="reference internal" href="../process/coding-style.html#language">4.2. Language</a></li>
343<li class="toctree-l3"><a class="reference internal" href="../process/coding-style.html#c-language-standard">4.3. C Language Standard</a></li>
344<li class="toctree-l3"><a class="reference internal" href="../process/coding-style.html#misra-compliance">4.4. MISRA Compliance</a></li>
345<li class="toctree-l3"><a class="reference internal" href="../process/coding-style.html#indentation">4.5. Indentation</a></li>
346<li class="toctree-l3"><a class="reference internal" href="../process/coding-style.html#spacing">4.6. Spacing</a></li>
347<li class="toctree-l3"><a class="reference internal" href="../process/coding-style.html#line-length">4.7. Line Length</a></li>
348<li class="toctree-l3"><a class="reference internal" href="../process/coding-style.html#blank-lines">4.8. Blank Lines</a></li>
349<li class="toctree-l3"><a class="reference internal" href="../process/coding-style.html#braces">4.9. Braces</a><ul>
350<li class="toctree-l4"><a class="reference internal" href="../process/coding-style.html#opening-brace-placement">4.9.1. Opening Brace Placement</a></li>
351<li class="toctree-l4"><a class="reference internal" href="../process/coding-style.html#conditional-statement-bodies">4.9.2. Conditional Statement Bodies</a></li>
352</ul>
353</li>
354<li class="toctree-l3"><a class="reference internal" href="../process/coding-style.html#naming">4.10. Naming</a><ul>
355<li class="toctree-l4"><a class="reference internal" href="../process/coding-style.html#functions">4.10.1. Functions</a></li>
356<li class="toctree-l4"><a class="reference internal" href="../process/coding-style.html#local-variables-and-parameters">4.10.2. Local Variables and Parameters</a></li>
357<li class="toctree-l4"><a class="reference internal" href="../process/coding-style.html#preprocessor-macros">4.10.3. Preprocessor Macros</a></li>
358</ul>
359</li>
360<li class="toctree-l3"><a class="reference internal" href="../process/coding-style.html#function-attributes">4.11. Function Attributes</a></li>
361<li class="toctree-l3"><a class="reference internal" href="../process/coding-style.html#alignment">4.12. Alignment</a><ul>
362<li class="toctree-l4"><a class="reference internal" href="../process/coding-style.html#switch-statement-alignment">4.12.1. Switch Statement Alignment</a></li>
363<li class="toctree-l4"><a class="reference internal" href="../process/coding-style.html#pointer-alignment">4.12.2. Pointer Alignment</a></li>
364</ul>
365</li>
366<li class="toctree-l3"><a class="reference internal" href="../process/coding-style.html#comments">4.13. Comments</a></li>
367<li class="toctree-l3"><a class="reference internal" href="../process/coding-style.html#headers-and-inclusion">4.14. Headers and inclusion</a><ul>
368<li class="toctree-l4"><a class="reference internal" href="../process/coding-style.html#header-guards">4.14.1. Header guards</a></li>
369<li class="toctree-l4"><a class="reference internal" href="../process/coding-style.html#include-statement-ordering">4.14.2. Include statement ordering</a></li>
370<li class="toctree-l4"><a class="reference internal" href="../process/coding-style.html#include-statement-variants">4.14.3. Include statement variants</a></li>
371</ul>
372</li>
373<li class="toctree-l3"><a class="reference internal" href="../process/coding-style.html#typedefs">4.15. Typedefs</a><ul>
374<li class="toctree-l4"><a class="reference internal" href="../process/coding-style.html#avoid-anonymous-typedefs-of-structs-enums-in-headers">4.15.1. Avoid anonymous typedefs of structs/enums in headers</a></li>
375</ul>
376</li>
377</ul>
378</li>
379<li class="toctree-l2"><a class="reference internal" href="../process/coding-guidelines.html">5. Coding Guidelines</a><ul>
380<li class="toctree-l3"><a class="reference internal" href="../process/coding-guidelines.html#automatic-editor-configuration">5.1. Automatic Editor Configuration</a></li>
381<li class="toctree-l3"><a class="reference internal" href="../process/coding-guidelines.html#automatic-compliance-checking">5.2. Automatic Compliance Checking</a><ul>
382<li class="toctree-l4"><a class="reference internal" href="../process/coding-guidelines.html#ignored-checkpatch-warnings">5.2.1. Ignored Checkpatch Warnings</a></li>
383</ul>
384</li>
385<li class="toctree-l3"><a class="reference internal" href="../process/coding-guidelines.html#performance-considerations">5.3. Performance considerations</a><ul>
386<li class="toctree-l4"><a class="reference internal" href="../process/coding-guidelines.html#avoid-printf-and-use-logging-macros">5.3.1. Avoid printf and use logging macros</a></li>
387<li class="toctree-l4"><a class="reference internal" href="../process/coding-guidelines.html#use-const-data-where-possible">5.3.2. Use const data where possible</a></li>
388</ul>
389</li>
390<li class="toctree-l3"><a class="reference internal" href="../process/coding-guidelines.html#libc-functions-that-are-banned-or-to-be-used-with-caution">5.4. Libc functions that are banned or to be used with caution</a></li>
391<li class="toctree-l3"><a class="reference internal" href="../process/coding-guidelines.html#error-handling-and-robustness">5.5. Error handling and robustness</a><ul>
392<li class="toctree-l4"><a class="reference internal" href="../process/coding-guidelines.html#using-cassert-to-check-for-compile-time-data-errors">5.5.1. Using CASSERT to check for compile time data errors</a></li>
393<li class="toctree-l4"><a class="reference internal" href="../process/coding-guidelines.html#using-assert-to-check-for-programming-errors">5.5.2. Using assert() to check for programming errors</a></li>
394<li class="toctree-l4"><a class="reference internal" href="../process/coding-guidelines.html#handling-integration-errors">5.5.3. Handling integration errors</a></li>
395<li class="toctree-l4"><a class="reference internal" href="../process/coding-guidelines.html#handling-recoverable-errors">5.5.4. Handling recoverable errors</a></li>
396<li class="toctree-l4"><a class="reference internal" href="../process/coding-guidelines.html#handling-unrecoverable-errors">5.5.5. Handling unrecoverable errors</a></li>
397<li class="toctree-l4"><a class="reference internal" href="../process/coding-guidelines.html#handling-critical-unresponsiveness">5.5.6. Handling critical unresponsiveness</a></li>
398</ul>
399</li>
400<li class="toctree-l3"><a class="reference internal" href="../process/coding-guidelines.html#use-of-built-in-c-and-libc-data-types">5.6. Use of built-in <em>C</em> and <em>libc</em> data types</a></li>
401<li class="toctree-l3"><a class="reference internal" href="../process/coding-guidelines.html#favor-c-language-over-assembly-language">5.7. Favor C language over assembly language</a></li>
402</ul>
403</li>
404<li class="toctree-l2"><a class="reference internal" href="../process/contributing.html">6. Contributor’s Guide</a><ul>
405<li class="toctree-l3"><a class="reference internal" href="../process/contributing.html#getting-started">6.1. Getting Started</a></li>
406<li class="toctree-l3"><a class="reference internal" href="../process/contributing.html#making-changes">6.2. Making Changes</a></li>
407<li class="toctree-l3"><a class="reference internal" href="../process/contributing.html#submitting-changes">6.3. Submitting Changes</a></li>
408<li class="toctree-l3"><a class="reference internal" href="../process/contributing.html#add-build-configurations">6.4. Add Build Configurations</a></li>
409<li class="toctree-l3"><a class="reference internal" href="../process/contributing.html#binary-components">6.5. Binary Components</a></li>
410</ul>
411</li>
412<li class="toctree-l2"><a class="reference internal" href="../process/code-review-guidelines.html">7. Code Review Guidelines</a><ul>
413<li class="toctree-l3"><a class="reference internal" href="../process/code-review-guidelines.html#why-do-we-do-code-reviews">7.1. Why do we do code reviews?</a></li>
414<li class="toctree-l3"><a class="reference internal" href="../process/code-review-guidelines.html#good-practices">7.2. Good practices</a></li>
415<li class="toctree-l3"><a class="reference internal" href="../process/code-review-guidelines.html#guidelines-for-patch-contributors">7.3. Guidelines for patch contributors</a></li>
416<li class="toctree-l3"><a class="reference internal" href="../process/code-review-guidelines.html#guidelines-for-all-reviewers">7.4. Guidelines for all reviewers</a></li>
417<li class="toctree-l3"><a class="reference internal" href="../process/code-review-guidelines.html#guidelines-for-code-owners">7.5. Guidelines for code owners</a></li>
418<li class="toctree-l3"><a class="reference internal" href="../process/code-review-guidelines.html#guidelines-for-maintainers">7.6. Guidelines for maintainers</a></li>
419</ul>
420</li>
421<li class="toctree-l2"><a class="reference internal" href="../process/faq.html">8. Frequently-Asked Questions (FAQ)</a><ul>
422<li class="toctree-l3"><a class="reference internal" href="../process/faq.html#how-do-i-update-my-changes">8.1. How do I update my changes?</a></li>
423<li class="toctree-l3"><a class="reference internal" href="../process/faq.html#how-long-will-my-changes-take-to-merge-into-integration">8.2. How long will my changes take to merge into <code class="docutils literal notranslate"><span class="pre">integration</span></code>?</a></li>
424<li class="toctree-l3"><a class="reference internal" href="../process/faq.html#how-long-will-it-take-for-my-changes-to-go-from-integration-to-master">8.3. How long will it take for my changes to go from <code class="docutils literal notranslate"><span class="pre">integration</span></code> to <code class="docutils literal notranslate"><span class="pre">master</span></code>?</a></li>
425<li class="toctree-l3"><a class="reference internal" href="../process/faq.html#what-are-these-strange-comments-in-my-changes">8.4. What are these strange comments in my changes?</a></li>
426</ul>
427</li>
428<li class="toctree-l2"><a class="reference internal" href="../process/security-hardening.html">9. Secure Development Guidelines</a><ul>
429<li class="toctree-l3"><a class="reference internal" href="../process/security-hardening.html#security-considerations">9.1. Security considerations</a><ul>
430<li class="toctree-l4"><a class="reference internal" href="../process/security-hardening.html#do-not-leak-secrets-to-the-normal-world">9.1.1. Do not leak secrets to the normal world</a></li>
431<li class="toctree-l4"><a class="reference internal" href="../process/security-hardening.html#handling-denial-of-service-attacks">9.1.2. Handling Denial of Service attacks</a></li>
432<li class="toctree-l4"><a class="reference internal" href="../process/security-hardening.html#preventing-secure-world-timing-information-leakage-via-pmu-counters">9.1.3. Preventing Secure-world timing information leakage via PMU counters</a></li>
433</ul>
434</li>
435<li class="toctree-l3"><a class="reference internal" href="../process/security-hardening.html#build-options">9.2. Build options</a></li>
436</ul>
437</li>
438</ul>
439</li>
440<li class="toctree-l1"><a class="reference internal" href="../components/index.html">Components</a><ul>
441<li class="toctree-l2"><a class="reference internal" href="../components/spd/index.html">1. Secure Payload Dispatcher (SPD)</a><ul>
442<li class="toctree-l3"><a class="reference internal" href="../components/spd/optee-dispatcher.html">1.1. OP-TEE Dispatcher</a></li>
443<li class="toctree-l3"><a class="reference internal" href="../components/spd/tlk-dispatcher.html">1.2. Trusted Little Kernel (TLK) Dispatcher</a><ul>
444<li class="toctree-l4"><a class="reference internal" href="../components/spd/tlk-dispatcher.html#trusted-little-kernel-tlk">1.2.1. Trusted Little Kernel (TLK)</a></li>
445<li class="toctree-l4"><a class="reference internal" href="../components/spd/tlk-dispatcher.html#build-tlk">1.2.2. Build TLK</a></li>
446<li class="toctree-l4"><a class="reference internal" href="../components/spd/tlk-dispatcher.html#input-parameters-to-tlk">1.2.3. Input parameters to TLK</a></li>
447</ul>
448</li>
449<li class="toctree-l3"><a class="reference internal" href="../components/spd/trusty-dispatcher.html">1.3. Trusty Dispatcher</a><ul>
450<li class="toctree-l4"><a class="reference internal" href="../components/spd/trusty-dispatcher.html#boot-parameters">1.3.1. Boot parameters</a></li>
451<li class="toctree-l4"><a class="reference internal" href="../components/spd/trusty-dispatcher.html#supported-platforms">1.3.2. Supported platforms</a></li>
452</ul>
453</li>
454</ul>
455</li>
456<li class="toctree-l2"><a class="reference internal" href="../components/activity-monitors.html">2. Activity Monitors</a><ul>
457<li class="toctree-l3"><a class="reference internal" href="../components/activity-monitors.html#auxiliary-counters">2.1. Auxiliary counters</a></li>
458</ul>
459</li>
460<li class="toctree-l2"><a class="reference internal" href="../components/arm-sip-service.html">3. Arm SiP Services</a><ul>
461<li class="toctree-l3"><a class="reference internal" href="../components/arm-sip-service.html#performance-measurement-framework-pmf">3.1. Performance Measurement Framework (PMF)</a></li>
462<li class="toctree-l3"><a class="reference internal" href="../components/arm-sip-service.html#execution-state-switching-service">3.2. Execution State Switching service</a><ul>
463<li class="toctree-l4"><a class="reference internal" href="../components/arm-sip-service.html#arm-sip-svc-exe-state-switch">3.2.1. <code class="docutils literal notranslate"><span class="pre">ARM_SIP_SVC_EXE_STATE_SWITCH</span></code></a></li>
464</ul>
465</li>
466<li class="toctree-l3"><a class="reference internal" href="../components/arm-sip-service.html#debugfs-interface">3.3. DebugFS interface</a><ul>
467<li class="toctree-l4"><a class="reference internal" href="../components/arm-sip-service.html#mount">3.3.1. MOUNT</a></li>
468<li class="toctree-l4"><a class="reference internal" href="../components/arm-sip-service.html#open">3.3.2. OPEN</a></li>
469<li class="toctree-l4"><a class="reference internal" href="../components/arm-sip-service.html#close">3.3.3. CLOSE</a></li>
470<li class="toctree-l4"><a class="reference internal" href="../components/arm-sip-service.html#read">3.3.4. READ</a></li>
471<li class="toctree-l4"><a class="reference internal" href="../components/arm-sip-service.html#seek">3.3.5. SEEK</a></li>
472<li class="toctree-l4"><a class="reference internal" href="../components/arm-sip-service.html#bind">3.3.6. BIND</a></li>
473<li class="toctree-l4"><a class="reference internal" href="../components/arm-sip-service.html#stat">3.3.7. STAT</a></li>
474<li class="toctree-l4"><a class="reference internal" href="../components/arm-sip-service.html#init">3.3.8. INIT</a></li>
475<li class="toctree-l4"><a class="reference internal" href="../components/arm-sip-service.html#version">3.3.9. VERSION</a></li>
476</ul>
477</li>
478</ul>
479</li>
480<li class="toctree-l2"><a class="reference internal" href="../components/debugfs-design.html">4. Debug FS</a><ul>
481<li class="toctree-l3"><a class="reference internal" href="../components/debugfs-design.html#overview">4.1. Overview</a></li>
482<li class="toctree-l3"><a class="reference internal" href="../components/debugfs-design.html#virtual-filesystem">4.2. Virtual filesystem</a><ul>
483<li class="toctree-l4"><a class="reference internal" href="../components/debugfs-design.html#namespace">4.2.1. Namespace</a></li>
484<li class="toctree-l4"><a class="reference internal" href="../components/debugfs-design.html#p-interface">4.2.2. 9p interface</a></li>
485</ul>
486</li>
487<li class="toctree-l3"><a class="reference internal" href="../components/debugfs-design.html#smc-interface">4.3. SMC interface</a></li>
488<li class="toctree-l3"><a class="reference internal" href="../components/debugfs-design.html#security-considerations">4.4. Security considerations</a></li>
489<li class="toctree-l3"><a class="reference internal" href="../components/debugfs-design.html#limitations">4.5. Limitations</a></li>
490<li class="toctree-l3"><a class="reference internal" href="../components/debugfs-design.html#applications">4.6. Applications</a></li>
491</ul>
492</li>
493<li class="toctree-l2"><a class="reference internal" href="../components/exception-handling.html">5. Exception Handling Framework</a><ul>
494<li class="toctree-l3"><a class="reference internal" href="../components/exception-handling.html#introduction">5.1. Introduction</a></li>
495<li class="toctree-l3"><a class="reference internal" href="../components/exception-handling.html#the-role-of-exception-handling-framework">5.2. The role of Exception Handling Framework</a></li>
496<li class="toctree-l3"><a class="reference internal" href="../components/exception-handling.html#interrupt-handling">5.3. Interrupt handling</a><ul>
497<li class="toctree-l4"><a class="reference internal" href="../components/exception-handling.html#partitioning-priority-levels">5.3.1. Partitioning priority levels</a></li>
498<li class="toctree-l4"><a class="reference internal" href="../components/exception-handling.html#programming-priority">5.3.2. Programming priority</a></li>
499</ul>
500</li>
501<li class="toctree-l3"><a class="reference internal" href="../components/exception-handling.html#registering-handler">5.4. Registering handler</a></li>
502<li class="toctree-l3"><a class="reference internal" href="../components/exception-handling.html#interrupt-handling-example">5.5. Interrupt handling example</a></li>
503<li class="toctree-l3"><a class="reference internal" href="../components/exception-handling.html#activating-and-deactivating-priorities">5.6. Activating and Deactivating priorities</a></li>
504<li class="toctree-l3"><a class="reference internal" href="../components/exception-handling.html#transition-of-priority-levels">5.7. Transition of priority levels</a></li>
505<li class="toctree-l3"><a class="reference internal" href="../components/exception-handling.html#effect-on-smc-calls">5.8. Effect on SMC calls</a></li>
506<li class="toctree-l3"><a class="reference internal" href="../components/exception-handling.html#build-time-flow">5.9. Build-time flow</a></li>
507<li class="toctree-l3"><a class="reference internal" href="../components/exception-handling.html#run-time-flow">5.10. Run-time flow</a></li>
508<li class="toctree-l3"><a class="reference internal" href="../components/exception-handling.html#interrupt-prioritisation-considerations">5.11. Interrupt Prioritisation Considerations</a></li>
509<li class="toctree-l3"><a class="reference internal" href="../components/exception-handling.html#limitations">5.12. Limitations</a></li>
510</ul>
511</li>
512<li class="toctree-l2"><a class="reference internal" href="../components/fconf/index.html">6. Firmware Configuration Framework</a><ul>
513<li class="toctree-l3"><a class="reference internal" href="../components/fconf/index.html#introduction">6.1. Introduction</a></li>
514<li class="toctree-l3"><a class="reference internal" href="../components/fconf/index.html#accessing-properties">6.2. Accessing properties</a></li>
515<li class="toctree-l3"><a class="reference internal" href="../components/fconf/index.html#defining-properties">6.3. Defining properties</a></li>
516<li class="toctree-l3"><a class="reference internal" href="../components/fconf/index.html#loading-the-property-device-tree">6.4. Loading the property device tree</a></li>
517<li class="toctree-l3"><a class="reference internal" href="../components/fconf/index.html#populating-the-properties">6.5. Populating the properties</a></li>
518<li class="toctree-l3"><a class="reference internal" href="../components/fconf/index.html#namespace-guidance">6.6. Namespace guidance</a></li>
519<li class="toctree-l3"><a class="reference internal" href="../components/fconf/index.html#properties-binding-information">6.7. Properties binding information</a><ul>
520<li class="toctree-l4"><a class="reference internal" href="../components/fconf/fconf_properties.html">6.7.1. DTB binding for FCONF properties</a></li>
521<li class="toctree-l4"><a class="reference internal" href="../components/fconf/amu-bindings.html">6.7.2. Activity Monitor Unit (AMU) Bindings</a></li>
522<li class="toctree-l4"><a class="reference internal" href="../components/fconf/mpmm-bindings.html">6.7.3. Maximum Power Mitigation Mechanism (MPMM) Bindings</a></li>
523</ul>
524</li>
525</ul>
526</li>
527<li class="toctree-l2"><a class="reference internal" href="../components/firmware-update.html">7. Firmware Update (FWU)</a><ul>
528<li class="toctree-l3"><a class="reference internal" href="../components/firmware-update.html#introduction">7.1. Introduction</a><ul>
529<li class="toctree-l4"><a class="reference internal" href="../components/firmware-update.html#scope">7.1.1. Scope</a></li>
530</ul>
531</li>
532<li class="toctree-l3"><a class="reference internal" href="../components/firmware-update.html#fwu-overview">7.2. FWU Overview</a></li>
533<li class="toctree-l3"><a class="reference internal" href="../components/firmware-update.html#image-identification">7.3. Image Identification</a></li>
534<li class="toctree-l3"><a class="reference internal" href="../components/firmware-update.html#fwu-state-machine">7.4. FWU State Machine</a></li>
535<li class="toctree-l3"><a class="reference internal" href="../components/firmware-update.html#bl1-smc-interface">7.5. BL1 SMC Interface</a><ul>
536<li class="toctree-l4"><a class="reference internal" href="../components/firmware-update.html#bl1-smc-call-count">7.5.1. BL1_SMC_CALL_COUNT</a></li>
537<li class="toctree-l4"><a class="reference internal" href="../components/firmware-update.html#bl1-smc-uid">7.5.2. BL1_SMC_UID</a></li>
538<li class="toctree-l4"><a class="reference internal" href="../components/firmware-update.html#bl1-smc-version">7.5.3. BL1_SMC_VERSION</a></li>
539<li class="toctree-l4"><a class="reference internal" href="../components/firmware-update.html#bl1-smc-run-image">7.5.4. BL1_SMC_RUN_IMAGE</a></li>
540<li class="toctree-l4"><a class="reference internal" href="../components/firmware-update.html#fwu-smc-image-copy">7.5.5. FWU_SMC_IMAGE_COPY</a></li>
541<li class="toctree-l4"><a class="reference internal" href="../components/firmware-update.html#fwu-smc-image-auth">7.5.6. FWU_SMC_IMAGE_AUTH</a></li>
542<li class="toctree-l4"><a class="reference internal" href="../components/firmware-update.html#fwu-smc-image-execute">7.5.7. FWU_SMC_IMAGE_EXECUTE</a></li>
543<li class="toctree-l4"><a class="reference internal" href="../components/firmware-update.html#fwu-smc-image-resume">7.5.8. FWU_SMC_IMAGE_RESUME</a></li>
544<li class="toctree-l4"><a class="reference internal" href="../components/firmware-update.html#fwu-smc-sec-image-done">7.5.9. FWU_SMC_SEC_IMAGE_DONE</a></li>
545<li class="toctree-l4"><a class="reference internal" href="../components/firmware-update.html#fwu-smc-update-done">7.5.10. FWU_SMC_UPDATE_DONE</a></li>
546<li class="toctree-l4"><a class="reference internal" href="../components/firmware-update.html#fwu-smc-image-reset">7.5.11. FWU_SMC_IMAGE_RESET</a></li>
547</ul>
548</li>
549</ul>
550</li>
551<li class="toctree-l2"><a class="reference internal" href="../components/measured_boot/index.html">8. Measured Boot Driver (MBD)</a><ul>
552<li class="toctree-l3"><a class="reference internal" href="../components/measured_boot/index.html#properties-binding-information">8.1. Properties binding information</a><ul>
553<li class="toctree-l4"><a class="reference internal" href="../components/measured_boot/event_log.html">8.1.1. DTB binding for Event Log properties</a></li>
554</ul>
555</li>
556</ul>
557</li>
558<li class="toctree-l2"><a class="reference internal" href="../components/mpmm.html">9. Maximum Power Mitigation Mechanism (MPMM)</a></li>
559<li class="toctree-l2"><a class="reference internal" href="../components/platform-interrupt-controller-API.html">10. Platform Interrupt Controller API</a><ul>
560<li class="toctree-l3"><a class="reference internal" href="../components/platform-interrupt-controller-API.html#function-unsigned-int-plat-ic-get-running-priority-void-optional">10.1. Function: unsigned int plat_ic_get_running_priority(void); [optional]</a></li>
561<li class="toctree-l3"><a class="reference internal" href="../components/platform-interrupt-controller-API.html#function-int-plat-ic-is-spi-unsigned-int-id-optional">10.2. Function: int plat_ic_is_spi(unsigned int id); [optional]</a></li>
562<li class="toctree-l3"><a class="reference internal" href="../components/platform-interrupt-controller-API.html#function-int-plat-ic-is-ppi-unsigned-int-id-optional">10.3. Function: int plat_ic_is_ppi(unsigned int id); [optional]</a></li>
563<li class="toctree-l3"><a class="reference internal" href="../components/platform-interrupt-controller-API.html#function-int-plat-ic-is-sgi-unsigned-int-id-optional">10.4. Function: int plat_ic_is_sgi(unsigned int id); [optional]</a></li>
564<li class="toctree-l3"><a class="reference internal" href="../components/platform-interrupt-controller-API.html#function-unsigned-int-plat-ic-get-interrupt-active-unsigned-int-id-optional">10.5. Function: unsigned int plat_ic_get_interrupt_active(unsigned int id); [optional]</a></li>
565<li class="toctree-l3"><a class="reference internal" href="../components/platform-interrupt-controller-API.html#function-void-plat-ic-enable-interrupt-unsigned-int-id-optional">10.6. Function: void plat_ic_enable_interrupt(unsigned int id); [optional]</a></li>
566<li class="toctree-l3"><a class="reference internal" href="../components/platform-interrupt-controller-API.html#function-void-plat-ic-disable-interrupt-unsigned-int-id-optional">10.7. Function: void plat_ic_disable_interrupt(unsigned int id); [optional]</a></li>
567<li class="toctree-l3"><a class="reference internal" href="../components/platform-interrupt-controller-API.html#function-void-plat-ic-set-interrupt-priority-unsigned-int-id-unsigned-int-priority-optional">10.8. Function: void plat_ic_set_interrupt_priority(unsigned int id, unsigned int priority); [optional]</a></li>
568<li class="toctree-l3"><a class="reference internal" href="../components/platform-interrupt-controller-API.html#function-int-plat-ic-has-interrupt-type-unsigned-int-type-optional">10.9. Function: int plat_ic_has_interrupt_type(unsigned int type); [optional]</a></li>
569<li class="toctree-l3"><a class="reference internal" href="../components/platform-interrupt-controller-API.html#function-void-plat-ic-set-interrupt-type-unsigned-int-id-unsigned-int-type-optional">10.10. Function: void plat_ic_set_interrupt_type(unsigned int id, unsigned int type); [optional]</a></li>
570<li class="toctree-l3"><a class="reference internal" href="../components/platform-interrupt-controller-API.html#function-void-plat-ic-raise-el3-sgi-int-sgi-num-u-register-t-target-optional">10.11. Function: void plat_ic_raise_el3_sgi(int sgi_num, u_register_t target); [optional]</a></li>
571<li class="toctree-l3"><a class="reference internal" href="../components/platform-interrupt-controller-API.html#function-void-plat-ic-set-spi-routing-unsigned-int-id-unsigned-int-routing-mode-u-register-t-mpidr-optional">10.12. Function: void plat_ic_set_spi_routing(unsigned int id, unsigned int routing_mode, u_register_t mpidr); [optional]</a></li>
572<li class="toctree-l3"><a class="reference internal" href="../components/platform-interrupt-controller-API.html#function-void-plat-ic-set-interrupt-pending-unsigned-int-id-optional">10.13. Function: void plat_ic_set_interrupt_pending(unsigned int id); [optional]</a></li>
573<li class="toctree-l3"><a class="reference internal" href="../components/platform-interrupt-controller-API.html#function-void-plat-ic-clear-interrupt-pending-unsigned-int-id-optional">10.14. Function: void plat_ic_clear_interrupt_pending(unsigned int id); [optional]</a></li>
574<li class="toctree-l3"><a class="reference internal" href="../components/platform-interrupt-controller-API.html#function-unsigned-int-plat-ic-set-priority-mask-unsigned-int-id-optional">10.15. Function: unsigned int plat_ic_set_priority_mask(unsigned int id); [optional]</a></li>
575<li class="toctree-l3"><a class="reference internal" href="../components/platform-interrupt-controller-API.html#function-unsigned-int-plat-ic-get-interrupt-id-unsigned-int-raw-optional">10.16. Function: unsigned int plat_ic_get_interrupt_id(unsigned int raw); [optional]</a></li>
576</ul>
577</li>
578<li class="toctree-l2"><a class="reference internal" href="../components/ras.html">11. Reliability, Availability, and Serviceability (RAS) Extensions</a><ul>
579<li class="toctree-l3"><a class="reference internal" href="../components/ras.html#overview">11.1. Overview</a></li>
580<li class="toctree-l3"><a class="reference internal" href="../components/ras.html#platform-apis">11.2. Platform APIs</a></li>
581<li class="toctree-l3"><a class="reference internal" href="../components/ras.html#registering-ras-error-records">11.3. Registering RAS error records</a><ul>
582<li class="toctree-l4"><a class="reference internal" href="../components/ras.html#standard-error-record-helpers">11.3.1. Standard Error Record helpers</a></li>
583</ul>
584</li>
585<li class="toctree-l3"><a class="reference internal" href="../components/ras.html#registering-ras-interrupts">11.4. Registering RAS interrupts</a></li>
586<li class="toctree-l3"><a class="reference internal" href="../components/ras.html#double-fault-handling">11.5. Double-fault handling</a></li>
587<li class="toctree-l3"><a class="reference internal" href="../components/ras.html#engaging-the-ras-framework">11.6. Engaging the RAS framework</a></li>
588<li class="toctree-l3"><a class="reference internal" href="../components/ras.html#interaction-with-exception-handling-framework">11.7. Interaction with Exception Handling Framework</a></li>
589</ul>
590</li>
591<li class="toctree-l2"><a class="reference internal" href="../components/romlib-design.html">12. Library at ROM</a><ul>
592<li class="toctree-l3"><a class="reference internal" href="../components/romlib-design.html#introduction">12.1. Introduction</a></li>
593<li class="toctree-l3"><a class="reference internal" href="../components/romlib-design.html#index-file">12.2. Index file</a></li>
594<li class="toctree-l3"><a class="reference internal" href="../components/romlib-design.html#wrapper-functions">12.3. Wrapper functions</a></li>
595<li class="toctree-l3"><a class="reference internal" href="../components/romlib-design.html#script">12.4. Script</a></li>
596<li class="toctree-l3"><a class="reference internal" href="../components/romlib-design.html#patching-of-functions-in-library-at-rom">12.5. Patching of functions in library at ROM</a></li>
597<li class="toctree-l3"><a class="reference internal" href="../components/romlib-design.html#memory-impact">12.6. Memory impact</a></li>
598<li class="toctree-l3"><a class="reference internal" href="../components/romlib-design.html#build-library-at-rom">12.7. Build library at ROM</a></li>
599</ul>
600</li>
601<li class="toctree-l2"><a class="reference internal" href="../components/sdei.html">13. SDEI: Software Delegated Exception Interface</a><ul>
602<li class="toctree-l3"><a class="reference internal" href="../components/sdei.html#introduction">13.1. Introduction</a></li>
603<li class="toctree-l3"><a class="reference internal" href="../components/sdei.html#defining-events">13.2. Defining events</a><ul>
604<li class="toctree-l4"><a class="reference internal" href="../components/sdei.html#event-flags">13.2.1. Event flags</a></li>
605</ul>
606</li>
607<li class="toctree-l3"><a class="reference internal" href="../components/sdei.html#event-definition-example">13.3. Event definition example</a></li>
608<li class="toctree-l3"><a class="reference internal" href="../components/sdei.html#configuration-within-exception-handling-framework">13.4. Configuration within Exception Handling Framework</a></li>
609<li class="toctree-l3"><a class="reference internal" href="../components/sdei.html#determining-client-el">13.5. Determining client EL</a></li>
610<li class="toctree-l3"><a class="reference internal" href="../components/sdei.html#explicit-dispatch-of-events">13.6. Explicit dispatch of events</a><ul>
611<li class="toctree-l4"><a class="reference internal" href="../components/sdei.html#conditions-for-event-dispatch">13.6.1. Conditions for event dispatch</a></li>
612</ul>
613</li>
614<li class="toctree-l3"><a class="reference internal" href="../components/sdei.html#porting-requirements">13.7. Porting requirements</a></li>
615<li class="toctree-l3"><a class="reference internal" href="../components/sdei.html#note-on-writing-sdei-event-handlers">13.8. Note on writing SDEI event handlers</a></li>
616</ul>
617</li>
618<li class="toctree-l2"><a class="reference internal" href="../components/secure-partition-manager.html">14. Secure Partition Manager</a><ul>
619<li class="toctree-l3"><a class="reference internal" href="../components/secure-partition-manager.html#acronyms">14.1. Acronyms</a></li>
620<li class="toctree-l3"><a class="reference internal" href="../components/secure-partition-manager.html#foreword">14.2. Foreword</a><ul>
621<li class="toctree-l4"><a class="reference internal" href="../components/secure-partition-manager.html#terminology">14.2.1. Terminology</a></li>
622<li class="toctree-l4"><a class="reference internal" href="../components/secure-partition-manager.html#support-for-legacy-platforms">14.2.2. Support for legacy platforms</a></li>
623</ul>
624</li>
625<li class="toctree-l3"><a class="reference internal" href="../components/secure-partition-manager.html#sample-reference-stack">14.3. Sample reference stack</a></li>
626<li class="toctree-l3"><a class="reference internal" href="../components/secure-partition-manager.html#tf-a-build-options">14.4. TF-A build options</a></li>
627<li class="toctree-l3"><a class="reference internal" href="../components/secure-partition-manager.html#fvp-model-invocation">14.5. FVP model invocation</a></li>
628<li class="toctree-l3"><a class="reference internal" href="../components/secure-partition-manager.html#boot-process">14.6. Boot process</a><ul>
629<li class="toctree-l4"><a class="reference internal" href="../components/secure-partition-manager.html#loading-hafnium-and-secure-partitions-in-the-secure-world">14.6.1. Loading Hafnium and secure partitions in the secure world</a></li>
630<li class="toctree-l4"><a class="reference internal" href="../components/secure-partition-manager.html#booting-through-tf-a">14.6.2. Booting through TF-A</a></li>
631</ul>
632</li>
633<li class="toctree-l3"><a class="reference internal" href="../components/secure-partition-manager.html#hafnium-in-the-secure-world">14.7. Hafnium in the secure world</a><ul>
634<li class="toctree-l4"><a class="reference internal" href="../components/secure-partition-manager.html#general-considerations">14.7.1. General considerations</a></li>
635<li class="toctree-l4"><a class="reference internal" href="../components/secure-partition-manager.html#parsing-sp-partition-manifests">14.7.2. Parsing SP partition manifests</a></li>
636<li class="toctree-l4"><a class="reference internal" href="../components/secure-partition-manager.html#passing-boot-data-to-the-sp">14.7.3. Passing boot data to the SP</a></li>
637<li class="toctree-l4"><a class="reference internal" href="../components/secure-partition-manager.html#sp-boot-order">14.7.4. SP Boot order</a></li>
638<li class="toctree-l4"><a class="reference internal" href="../components/secure-partition-manager.html#boot-phases">14.7.5. Boot phases</a></li>
639<li class="toctree-l4"><a class="reference internal" href="../components/secure-partition-manager.html#notifications">14.7.6. Notifications</a></li>
640<li class="toctree-l4"><a class="reference internal" href="../components/secure-partition-manager.html#mandatory-interfaces">14.7.7. Mandatory interfaces</a></li>
641<li class="toctree-l4"><a class="reference internal" href="../components/secure-partition-manager.html#spmc-spmd-direct-requests-responses">14.7.8. SPMC-SPMD direct requests/responses</a></li>
642<li class="toctree-l4"><a class="reference internal" href="../components/secure-partition-manager.html#pe-mmu-configuration">14.7.9. PE MMU configuration</a></li>
643<li class="toctree-l4"><a class="reference internal" href="../components/secure-partition-manager.html#interrupt-management">14.7.10. Interrupt management</a></li>
644<li class="toctree-l4"><a class="reference internal" href="../components/secure-partition-manager.html#secure-interrupt-handling">14.7.11. Secure interrupt handling</a></li>
645<li class="toctree-l4"><a class="reference internal" href="../components/secure-partition-manager.html#power-management">14.7.12. Power management</a></li>
646</ul>
647</li>
648<li class="toctree-l3"><a class="reference internal" href="../components/secure-partition-manager.html#smmuv3-support-in-hafnium">14.8. SMMUv3 support in Hafnium</a><ul>
649<li class="toctree-l4"><a class="reference internal" href="../components/secure-partition-manager.html#smmuv3-features">14.8.1. SMMUv3 features</a></li>
650<li class="toctree-l4"><a class="reference internal" href="../components/secure-partition-manager.html#smmuv3-programming-interfaces">14.8.2. SMMUv3 Programming Interfaces</a></li>
651<li class="toctree-l4"><a class="reference internal" href="../components/secure-partition-manager.html#peripheral-device-manifest">14.8.3. Peripheral device manifest</a></li>
652<li class="toctree-l4"><a class="reference internal" href="../components/secure-partition-manager.html#smmuv3-driver-limitations">14.8.4. SMMUv3 driver limitations</a></li>
653</ul>
654</li>
655<li class="toctree-l3"><a class="reference internal" href="../components/secure-partition-manager.html#s-el0-partition-support">14.9. S-EL0 Partition support</a></li>
656<li class="toctree-l3"><a class="reference internal" href="../components/secure-partition-manager.html#references">14.10. References</a></li>
657</ul>
658</li>
659<li class="toctree-l2"><a class="reference internal" href="../components/secure-partition-manager-mm.html">15. Secure Partition Manager (MM)</a><ul>
660<li class="toctree-l3"><a class="reference internal" href="../components/secure-partition-manager-mm.html#foreword">15.1. Foreword</a></li>
661<li class="toctree-l3"><a class="reference internal" href="../components/secure-partition-manager-mm.html#background">15.2. Background</a></li>
662<li class="toctree-l3"><a class="reference internal" href="../components/secure-partition-manager-mm.html#introduction">15.3. Introduction</a></li>
663<li class="toctree-l3"><a class="reference internal" href="../components/secure-partition-manager-mm.html#description">15.4. Description</a><ul>
664<li class="toctree-l4"><a class="reference internal" href="../components/secure-partition-manager-mm.html#building-tf-a-with-secure-partition-support">15.4.1. Building TF-A with Secure Partition support</a></li>
665<li class="toctree-l4"><a class="reference internal" href="../components/secure-partition-manager-mm.html#describing-secure-partition-resources">15.4.2. Describing Secure Partition resources</a></li>
666<li class="toctree-l4"><a class="reference internal" href="../components/secure-partition-manager-mm.html#accessing-secure-partition-services">15.4.3. Accessing Secure Partition services</a></li>
667<li class="toctree-l4"><a class="reference internal" href="../components/secure-partition-manager-mm.html#exchanging-data-with-the-secure-partition">15.4.4. Exchanging data with the Secure Partition</a></li>
668</ul>
669</li>
670<li class="toctree-l3"><a class="reference internal" href="../components/secure-partition-manager-mm.html#runtime-model-of-the-secure-partition">15.5. Runtime model of the Secure Partition</a><ul>
671<li class="toctree-l4"><a class="reference internal" href="../components/secure-partition-manager-mm.html#interface-with-spm">15.5.1. Interface with SPM</a></li>
672<li class="toctree-l4"><a class="reference internal" href="../components/secure-partition-manager-mm.html#miscellaneous-interfaces">15.5.2. Miscellaneous interfaces</a></li>
673<li class="toctree-l4"><a class="reference internal" href="../components/secure-partition-manager-mm.html#secure-partition-initialisation">15.5.3. Secure Partition Initialisation</a></li>
674<li class="toctree-l4"><a class="reference internal" href="../components/secure-partition-manager-mm.html#runtime-event-delegation">15.5.4. Runtime Event Delegation</a></li>
675<li class="toctree-l4"><a class="reference internal" href="../components/secure-partition-manager-mm.html#secure-partition-memory-management">15.5.5. Secure Partition Memory Management</a></li>
676<li class="toctree-l4"><a class="reference internal" href="../components/secure-partition-manager-mm.html#error-codes">15.5.6. Error Codes</a></li>
677</ul>
678</li>
679</ul>
680</li>
681<li class="toctree-l2"><a class="reference internal" href="../components/ffa-manifest-binding.html">16. FF-A manifest binding to device tree</a><ul>
682<li class="toctree-l3"><a class="reference internal" href="../components/ffa-manifest-binding.html#version-1-0">16.1. Version 1.0</a><ul>
683<li class="toctree-l4"><a class="reference internal" href="../components/ffa-manifest-binding.html#partition-properties">16.1.1. Partition Properties</a></li>
684</ul>
685</li>
686<li class="toctree-l3"><a class="reference internal" href="../components/ffa-manifest-binding.html#memory-regions">16.2. Memory Regions</a></li>
687<li class="toctree-l3"><a class="reference internal" href="../components/ffa-manifest-binding.html#device-regions">16.3. Device Regions</a></li>
688</ul>
689</li>
690<li class="toctree-l2"><a class="reference internal" href="../components/xlat-tables-lib-v2-design.html">17. Translation (XLAT) Tables Library</a><ul>
691<li class="toctree-l3"><a class="reference internal" href="../components/xlat-tables-lib-v2-design.html#about-version-1-version-2-and-mpu-libraries">17.1. About version 1, version 2 and MPU libraries</a></li>
692<li class="toctree-l3"><a class="reference internal" href="../components/xlat-tables-lib-v2-design.html#design-concepts-and-interfaces">17.2. Design concepts and interfaces</a><ul>
693<li class="toctree-l4"><a class="reference internal" href="../components/xlat-tables-lib-v2-design.html#mmap-regions">17.2.1. <cite>mmap</cite> regions</a></li>
694<li class="toctree-l4"><a class="reference internal" href="../components/xlat-tables-lib-v2-design.html#translation-context">17.2.2. Translation Context</a></li>
695<li class="toctree-l4"><a class="reference internal" href="../components/xlat-tables-lib-v2-design.html#static-and-dynamic-memory-regions">17.2.3. Static and dynamic memory regions</a></li>
696</ul>
697</li>
698<li class="toctree-l3"><a class="reference internal" href="../components/xlat-tables-lib-v2-design.html#library-apis">17.3. Library APIs</a></li>
699<li class="toctree-l3"><a class="reference internal" href="../components/xlat-tables-lib-v2-design.html#library-limitations">17.4. Library limitations</a></li>
700<li class="toctree-l3"><a class="reference internal" href="../components/xlat-tables-lib-v2-design.html#implementation-details">17.5. Implementation details</a><ul>
701<li class="toctree-l4"><a class="reference internal" href="../components/xlat-tables-lib-v2-design.html#code-structure">17.5.1. Code structure</a></li>
702<li class="toctree-l4"><a class="reference internal" href="../components/xlat-tables-lib-v2-design.html#from-mmap-regions-to-translation-tables">17.5.2. From mmap regions to translation tables</a></li>
703<li class="toctree-l4"><a class="reference internal" href="../components/xlat-tables-lib-v2-design.html#the-memory-mapping-algorithm">17.5.3. The memory mapping algorithm</a></li>
704<li class="toctree-l4"><a class="reference internal" href="../components/xlat-tables-lib-v2-design.html#tlb-maintenance-operations">17.5.4. TLB maintenance operations</a></li>
705</ul>
706</li>
707</ul>
708</li>
709<li class="toctree-l2"><a class="reference internal" href="../components/cot-binding.html">18. Chain of trust bindings</a><ul>
710<li class="toctree-l3"><a class="reference internal" href="../components/cot-binding.html#cot">18.1. cot</a></li>
711<li class="toctree-l3"><a class="reference internal" href="../components/cot-binding.html#manifests-and-certificate-node-bindings-definition">18.2. Manifests and Certificate node bindings definition</a></li>
712<li class="toctree-l3"><a class="reference internal" href="../components/cot-binding.html#images-and-image-node-bindings-definition">18.3. Images and Image node bindings definition</a></li>
713<li class="toctree-l3"><a class="reference internal" href="../components/cot-binding.html#non-volatile-counter-node-binding-definition">18.4. non-volatile counter node binding definition</a></li>
714<li class="toctree-l3"><a class="reference internal" href="../components/cot-binding.html#future-update-to-chain-of-trust-binding">18.5. Future update to chain of trust binding</a></li>
715</ul>
716</li>
717<li class="toctree-l2"><a class="reference internal" href="../components/realm-management-extension.html">19. Realm Management Extension (RME)</a><ul>
718<li class="toctree-l3"><a class="reference internal" href="../components/realm-management-extension.html#rme-support-in-tf-a">19.1. RME support in TF-A</a><ul>
719<li class="toctree-l4"><a class="reference internal" href="../components/realm-management-extension.html#changes-to-translation-tables-library">19.1.1. Changes to translation tables library</a></li>
720<li class="toctree-l4"><a class="reference internal" href="../components/realm-management-extension.html#changes-to-context-management">19.1.2. Changes to context management</a></li>
721<li class="toctree-l4"><a class="reference internal" href="../components/realm-management-extension.html#boot-flow-changes">19.1.3. Boot flow changes</a></li>
722<li class="toctree-l4"><a class="reference internal" href="../components/realm-management-extension.html#granule-protection-tables-gpt-library">19.1.4. Granule Protection Tables (GPT) library</a></li>
723<li class="toctree-l4"><a class="reference internal" href="../components/realm-management-extension.html#rmm-dispatcher-rmmd">19.1.5. RMM Dispatcher (RMMD)</a></li>
724<li class="toctree-l4"><a class="reference internal" href="../components/realm-management-extension.html#test-realm-payload-trp">19.1.6. Test Realm Payload (TRP)</a></li>
725</ul>
726</li>
727<li class="toctree-l3"><a class="reference internal" href="../components/realm-management-extension.html#building-and-running-tf-a-with-rme">19.2. Building and running TF-A with RME</a><ul>
728<li class="toctree-l4"><a class="reference internal" href="../components/realm-management-extension.html#building-tf-a-with-tf-a-tests">19.2.1. Building TF-A with TF-A Tests</a></li>
729<li class="toctree-l4"><a class="reference internal" href="../components/realm-management-extension.html#four-world-execution-with-hafnium-and-tf-a-tests">19.2.2. Four-world execution with Hafnium and TF-A Tests</a></li>
730<li class="toctree-l4"><a class="reference internal" href="../components/realm-management-extension.html#running-the-tests">19.2.3. Running the tests</a></li>
731</ul>
732</li>
733</ul>
734</li>
735<li class="toctree-l2"><a class="reference internal" href="../components/granule-protection-tables-design.html">20. Granule Protection Tables Library</a><ul>
736<li class="toctree-l3"><a class="reference internal" href="../components/granule-protection-tables-design.html#design-concepts-and-interfaces">20.1. Design Concepts and Interfaces</a><ul>
737<li class="toctree-l4"><a class="reference internal" href="../components/granule-protection-tables-design.html#defining-pas-regions">20.1.1. Defining PAS regions</a></li>
738<li class="toctree-l4"><a class="reference internal" href="../components/granule-protection-tables-design.html#level-0-and-level-1-tables">20.1.2. Level 0 and Level 1 Tables</a></li>
739<li class="toctree-l4"><a class="reference internal" href="../components/granule-protection-tables-design.html#granule-transition-service">20.1.3. Granule Transition Service</a></li>
740</ul>
741</li>
742<li class="toctree-l3"><a class="reference internal" href="../components/granule-protection-tables-design.html#library-apis">20.2. Library APIs</a><ul>
743<li class="toctree-l4"><a class="reference internal" href="../components/granule-protection-tables-design.html#api-constraints">20.2.1. API Constraints</a></li>
744<li class="toctree-l4"><a class="reference internal" href="../components/granule-protection-tables-design.html#sample-calculation-for-l0-memory-size-and-alignment">20.2.2. Sample Calculation for L0 memory size and alignment</a></li>
745<li class="toctree-l4"><a class="reference internal" href="../components/granule-protection-tables-design.html#sample-calculation-for-l1-table-size-and-alignment">20.2.3. Sample calculation for L1 table size and alignment</a></li>
746</ul>
747</li>
748</ul>
749</li>
750</ul>
751</li>
752<li class="toctree-l1 current"><a class="reference internal" href="index.html">System Design</a><ul class="current">
753<li class="toctree-l2"><a class="reference internal" href="alt-boot-flows.html">1. Alternative Boot Flows</a><ul>
754<li class="toctree-l3"><a class="reference internal" href="alt-boot-flows.html#el3-payloads-alternative-boot-flow">1.1. EL3 payloads alternative boot flow</a><ul>
755<li class="toctree-l4"><a class="reference internal" href="alt-boot-flows.html#booting-an-el3-payload">1.1.1. Booting an EL3 payload</a></li>
756</ul>
757</li>
758<li class="toctree-l3"><a class="reference internal" href="alt-boot-flows.html#preloaded-bl33-alternative-boot-flow">1.2. Preloaded BL33 alternative boot flow</a></li>
759</ul>
760</li>
761<li class="toctree-l2"><a class="reference internal" href="auth-framework.html">2. Authentication Framework &amp; Chain of Trust</a><ul>
762<li class="toctree-l3"><a class="reference internal" href="auth-framework.html#framework-design">2.1. Framework design</a><ul>
763<li class="toctree-l4"><a class="reference internal" href="auth-framework.html#chain-of-trust">2.1.1. Chain of Trust</a></li>
764<li class="toctree-l4"><a class="reference internal" href="auth-framework.html#image-types">2.1.2. Image types</a></li>
765<li class="toctree-l4"><a class="reference internal" href="auth-framework.html#component-responsibilities">2.1.3. Component responsibilities</a></li>
766<li class="toctree-l4"><a class="reference internal" href="auth-framework.html#authentication-methods">2.1.4. Authentication methods</a></li>
767</ul>
768</li>
769<li class="toctree-l3"><a class="reference internal" href="auth-framework.html#specifying-a-chain-of-trust">2.2. Specifying a Chain of Trust</a><ul>
770<li class="toctree-l4"><a class="reference internal" href="auth-framework.html#describing-the-image-parsing-methods">2.2.1. Describing the image parsing methods</a></li>
771<li class="toctree-l4"><a class="reference internal" href="auth-framework.html#describing-the-authentication-method-s">2.2.2. Describing the authentication method(s)</a></li>
772<li class="toctree-l4"><a class="reference internal" href="auth-framework.html#storing-authentication-parameters">2.2.3. Storing Authentication parameters</a></li>
773<li class="toctree-l4"><a class="reference internal" href="auth-framework.html#describing-an-image-in-a-cot">2.2.4. Describing an image in a CoT</a></li>
774</ul>
775</li>
776<li class="toctree-l3"><a class="reference internal" href="auth-framework.html#implementation-example">2.3. Implementation example</a><ul>
777<li class="toctree-l4"><a class="reference internal" href="auth-framework.html#the-tbbr-cot">2.3.1. The TBBR CoT</a></li>
778<li class="toctree-l4"><a class="reference internal" href="auth-framework.html#the-image-parser-library">2.3.2. The image parser library</a></li>
779<li class="toctree-l4"><a class="reference internal" href="auth-framework.html#the-cryptographic-library">2.3.3. The cryptographic library</a></li>
780</ul>
781</li>
782</ul>
783</li>
784<li class="toctree-l2"><a class="reference internal" href="cpu-specific-build-macros.html">3. Arm CPU Specific Build Macros</a><ul>
785<li class="toctree-l3"><a class="reference internal" href="cpu-specific-build-macros.html#security-vulnerability-workarounds">3.1. Security Vulnerability Workarounds</a></li>
786<li class="toctree-l3"><a class="reference internal" href="cpu-specific-build-macros.html#cpu-errata-workarounds">3.2. CPU Errata Workarounds</a></li>
787<li class="toctree-l3"><a class="reference internal" href="cpu-specific-build-macros.html#dsu-errata-workarounds">3.3. DSU Errata Workarounds</a></li>
788<li class="toctree-l3"><a class="reference internal" href="cpu-specific-build-macros.html#cpu-specific-optimizations">3.4. CPU Specific optimizations</a></li>
789</ul>
790</li>
791<li class="toctree-l2"><a class="reference internal" href="firmware-design.html">4. Firmware Design</a><ul>
792<li class="toctree-l3"><a class="reference internal" href="firmware-design.html#cold-boot">4.1. Cold boot</a><ul>
793<li class="toctree-l4"><a class="reference internal" href="firmware-design.html#dynamic-configuration-during-cold-boot">4.1.1. Dynamic Configuration during cold boot</a></li>
794<li class="toctree-l4"><a class="reference internal" href="firmware-design.html#bl1">4.1.2. BL1</a></li>
795<li class="toctree-l4"><a class="reference internal" href="firmware-design.html#bl2">4.1.3. BL2</a></li>
796<li class="toctree-l4"><a class="reference internal" href="firmware-design.html#running-bl2-at-el3-execution-level">4.1.4. Running BL2 at EL3 execution level</a></li>
797<li class="toctree-l4"><a class="reference internal" href="firmware-design.html#aarch64-bl31">4.1.5. AArch64 BL31</a></li>
798<li class="toctree-l4"><a class="reference internal" href="firmware-design.html#using-alternative-trusted-boot-firmware-in-place-of-bl1-bl2-aarch64-only">4.1.6. Using alternative Trusted Boot Firmware in place of BL1 &amp; BL2 (AArch64 only)</a></li>
799<li class="toctree-l4"><a class="reference internal" href="firmware-design.html#aarch32-el3-runtime-software-entrypoint-interface">4.1.7. AArch32 EL3 Runtime Software entrypoint interface</a></li>
800</ul>
801</li>
802<li class="toctree-l3"><a class="reference internal" href="firmware-design.html#el3-runtime-services-framework">4.2. EL3 runtime services framework</a><ul>
803<li class="toctree-l4"><a class="reference internal" href="firmware-design.html#registration">4.2.1. Registration</a></li>
804<li class="toctree-l4"><a class="reference internal" href="firmware-design.html#initialization">4.2.2. Initialization</a></li>
805<li class="toctree-l4"><a class="reference internal" href="firmware-design.html#handling-an-smc">4.2.3. Handling an SMC</a></li>
806</ul>
807</li>
808<li class="toctree-l3"><a class="reference internal" href="firmware-design.html#exception-handling-framework">4.3. Exception Handling Framework</a></li>
809<li class="toctree-l3"><a class="reference internal" href="firmware-design.html#power-state-coordination-interface">4.4. Power State Coordination Interface</a></li>
810<li class="toctree-l3"><a class="reference internal" href="firmware-design.html#secure-el1-payloads-and-dispatchers">4.5. Secure-EL1 Payloads and Dispatchers</a><ul>
811<li class="toctree-l4"><a class="reference internal" href="firmware-design.html#initializing-a-bl32-image">4.5.1. Initializing a BL32 Image</a></li>
812</ul>
813</li>
814<li class="toctree-l3"><a class="reference internal" href="firmware-design.html#crash-reporting-in-bl31">4.6. Crash Reporting in BL31</a></li>
815<li class="toctree-l3"><a class="reference internal" href="firmware-design.html#guidelines-for-reset-handlers">4.7. Guidelines for Reset Handlers</a></li>
816<li class="toctree-l3"><a class="reference internal" href="firmware-design.html#configuring-secure-interrupts">4.8. Configuring secure interrupts</a></li>
817<li class="toctree-l3"><a class="reference internal" href="firmware-design.html#cpu-specific-operations-framework">4.9. CPU specific operations framework</a><ul>
818<li class="toctree-l4"><a class="reference internal" href="firmware-design.html#cpu-specific-reset-handling">4.9.1. CPU specific Reset Handling</a></li>
819<li class="toctree-l4"><a class="reference internal" href="firmware-design.html#cpu-specific-power-down-sequence">4.9.2. CPU specific power down sequence</a></li>
820<li class="toctree-l4"><a class="reference internal" href="firmware-design.html#cpu-specific-register-reporting-during-crash">4.9.3. CPU specific register reporting during crash</a></li>
821<li class="toctree-l4"><a class="reference internal" href="firmware-design.html#cpu-errata-status-reporting">4.9.4. CPU errata status reporting</a></li>
822</ul>
823</li>
824<li class="toctree-l3"><a class="reference internal" href="firmware-design.html#memory-layout-of-bl-images">4.10. Memory layout of BL images</a><ul>
825<li class="toctree-l4"><a class="reference internal" href="firmware-design.html#linker-scripts-and-symbols">4.10.1. Linker scripts and symbols</a></li>
826<li class="toctree-l4"><a class="reference internal" href="firmware-design.html#how-to-choose-the-right-base-addresses-for-each-bootloader-stage-image">4.10.2. How to choose the right base addresses for each bootloader stage image</a></li>
827</ul>
828</li>
829<li class="toctree-l3"><a class="reference internal" href="firmware-design.html#firmware-image-package-fip">4.11. Firmware Image Package (FIP)</a><ul>
830<li class="toctree-l4"><a class="reference internal" href="firmware-design.html#firmware-image-package-layout">4.11.1. Firmware Image Package layout</a></li>
831<li class="toctree-l4"><a class="reference internal" href="firmware-design.html#firmware-image-package-creation-tool">4.11.2. Firmware Image Package creation tool</a></li>
832<li class="toctree-l4"><a class="reference internal" href="firmware-design.html#loading-from-a-firmware-image-package-fip">4.11.3. Loading from a Firmware Image Package (FIP)</a></li>
833</ul>
834</li>
835<li class="toctree-l3"><a class="reference internal" href="firmware-design.html#use-of-coherent-memory-in-tf-a">4.12. Use of coherent memory in TF-A</a><ul>
836<li class="toctree-l4"><a class="reference internal" href="firmware-design.html#disabling-the-use-of-coherent-memory-in-tf-a">4.12.1. Disabling the use of coherent memory in TF-A</a></li>
837<li class="toctree-l4"><a class="reference internal" href="firmware-design.html#coherent-memory-usage-in-psci-implementation">4.12.2. Coherent memory usage in PSCI implementation</a></li>
838<li class="toctree-l4"><a class="reference internal" href="firmware-design.html#bakery-lock-data">4.12.3. Bakery lock data</a></li>
839<li class="toctree-l4"><a class="reference internal" href="firmware-design.html#non-functional-impact-of-removing-coherent-memory">4.12.4. Non Functional Impact of removing coherent memory</a></li>
840</ul>
841</li>
842<li class="toctree-l3"><a class="reference internal" href="firmware-design.html#isolating-code-and-read-only-data-on-separate-memory-pages">4.13. Isolating code and read-only data on separate memory pages</a></li>
843<li class="toctree-l3"><a class="reference internal" href="firmware-design.html#publish-and-subscribe-framework">4.14. Publish and Subscribe Framework</a><ul>
844<li class="toctree-l4"><a class="reference internal" href="firmware-design.html#publish-and-subscribe-example">4.14.1. Publish and Subscribe Example</a></li>
845<li class="toctree-l4"><a class="reference internal" href="firmware-design.html#reclaiming-the-bl31-initialization-code">4.14.2. Reclaiming the BL31 initialization code</a></li>
846</ul>
847</li>
848<li class="toctree-l3"><a class="reference internal" href="firmware-design.html#performance-measurement-framework">4.15. Performance Measurement Framework</a><ul>
849<li class="toctree-l4"><a class="reference internal" href="firmware-design.html#timestamp-identifier-format">4.15.1. Timestamp identifier format</a></li>
850<li class="toctree-l4"><a class="reference internal" href="firmware-design.html#registering-a-pmf-service">4.15.2. Registering a PMF service</a></li>
851<li class="toctree-l4"><a class="reference internal" href="firmware-design.html#capturing-a-timestamp">4.15.3. Capturing a timestamp</a></li>
852<li class="toctree-l4"><a class="reference internal" href="firmware-design.html#retrieving-a-timestamp">4.15.4. Retrieving a timestamp</a></li>
853<li class="toctree-l4"><a class="reference internal" href="firmware-design.html#pmf-code-structure">4.15.5. PMF code structure</a></li>
854</ul>
855</li>
856<li class="toctree-l3"><a class="reference internal" href="firmware-design.html#armv8-a-architecture-extensions">4.16. Armv8-A Architecture Extensions</a><ul>
857<li class="toctree-l4"><a class="reference internal" href="firmware-design.html#armv8-1-a">4.16.1. Armv8.1-A</a></li>
858<li class="toctree-l4"><a class="reference internal" href="firmware-design.html#armv8-2-a">4.16.2. Armv8.2-A</a></li>
859<li class="toctree-l4"><a class="reference internal" href="firmware-design.html#armv8-3-a">4.16.3. Armv8.3-A</a></li>
860<li class="toctree-l4"><a class="reference internal" href="firmware-design.html#armv8-5-a">4.16.4. Armv8.5-A</a></li>
861<li class="toctree-l4"><a class="reference internal" href="firmware-design.html#armv7-a">4.16.5. Armv7-A</a></li>
862</ul>
863</li>
864<li class="toctree-l3"><a class="reference internal" href="firmware-design.html#code-structure">4.17. Code Structure</a></li>
865</ul>
866</li>
867<li class="toctree-l2 current"><a class="current reference internal" href="#">5. Interrupt Management Framework</a><ul>
868<li class="toctree-l3"><a class="reference internal" href="#concepts">5.1. Concepts</a><ul>
869<li class="toctree-l4"><a class="reference internal" href="#interrupt-types">5.1.1. Interrupt types</a></li>
870<li class="toctree-l4"><a class="reference internal" href="#routing-model">5.1.2. Routing model</a></li>
871<li class="toctree-l4"><a class="reference internal" href="#valid-routing-models">5.1.3. Valid routing models</a></li>
872<li class="toctree-l4"><a class="reference internal" href="#mapping-of-interrupt-type-to-signal">5.1.4. Mapping of interrupt type to signal</a></li>
873</ul>
874</li>
875<li class="toctree-l3"><a class="reference internal" href="#assumptions-in-interrupt-management-framework">5.2. Assumptions in Interrupt Management Framework</a></li>
876<li class="toctree-l3"><a class="reference internal" href="#software-components">5.3. Software components</a></li>
877<li class="toctree-l3"><a class="reference internal" href="#interrupt-registration">5.4. Interrupt registration</a><ul>
878<li class="toctree-l4"><a class="reference internal" href="#el3-runtime-firmware">5.4.1. EL3 runtime firmware</a></li>
879<li class="toctree-l4"><a class="reference internal" href="#secure-payload-dispatcher">5.4.2. Secure payload dispatcher</a></li>
880<li class="toctree-l4"><a class="reference internal" href="#test-secure-payload-dispatcher-behavior">5.4.3. Test secure payload dispatcher behavior</a></li>
881<li class="toctree-l4"><a class="reference internal" href="#secure-payload">5.4.4. Secure payload</a></li>
882<li class="toctree-l4"><a class="reference internal" href="#test-secure-payload-behavior">5.4.5. Test secure payload behavior</a></li>
883</ul>
884</li>
885<li class="toctree-l3"><a class="reference internal" href="#interrupt-handling">5.5. Interrupt handling</a><ul>
886<li class="toctree-l4"><a class="reference internal" href="#id4">5.5.1. EL3 runtime firmware</a></li>
887<li class="toctree-l4"><a class="reference internal" href="#id5">5.5.2. Secure payload dispatcher</a></li>
888<li class="toctree-l4"><a class="reference internal" href="#secure-payload-interrupt-handling">5.5.3. Secure payload interrupt handling</a></li>
889</ul>
890</li>
891<li class="toctree-l3"><a class="reference internal" href="#other-considerations">5.6. Other considerations</a><ul>
892<li class="toctree-l4"><a class="reference internal" href="#implication-of-preempted-smc-on-non-secure-software">5.6.1. Implication of preempted SMC on Non-Secure Software</a></li>
893</ul>
894</li>
895</ul>
896</li>
897<li class="toctree-l2"><a class="reference internal" href="psci-pd-tree.html">6. PSCI Power Domain Tree Structure</a><ul>
898<li class="toctree-l3"><a class="reference internal" href="psci-pd-tree.html#requirements">6.1. Requirements</a></li>
899<li class="toctree-l3"><a class="reference internal" href="psci-pd-tree.html#design">6.2. Design</a><ul>
900<li class="toctree-l4"><a class="reference internal" href="psci-pd-tree.html#describing-a-power-domain-tree">6.2.1. Describing a power domain tree</a></li>
901<li class="toctree-l4"><a class="reference internal" href="psci-pd-tree.html#removing-assumptions-about-mpidrs-used-in-a-platform">6.2.2. Removing assumptions about MPIDRs used in a platform</a></li>
902<li class="toctree-l4"><a class="reference internal" href="psci-pd-tree.html#traversing-through-and-distinguishing-between-core-and-non-core-power-domains">6.2.3. Traversing through and distinguishing between core and non-core power domains</a></li>
903<li class="toctree-l4"><a class="reference internal" href="psci-pd-tree.html#populating-the-power-domain-tree">6.2.4. Populating the power domain tree</a></li>
904</ul>
905</li>
906</ul>
907</li>
908<li class="toctree-l2"><a class="reference internal" href="reset-design.html">7. CPU Reset</a><ul>
909<li class="toctree-l3"><a class="reference internal" href="reset-design.html#general-reset-code-flow">7.1. General reset code flow</a></li>
910<li class="toctree-l3"><a class="reference internal" href="reset-design.html#programmable-cpu-reset-address">7.2. Programmable CPU reset address</a></li>
911<li class="toctree-l3"><a class="reference internal" href="reset-design.html#cold-boot-on-a-single-cpu">7.3. Cold boot on a single CPU</a></li>
912<li class="toctree-l3"><a class="reference internal" href="reset-design.html#programmable-cpu-reset-address-cold-boot-on-a-single-cpu">7.4. Programmable CPU reset address, Cold boot on a single CPU</a></li>
913<li class="toctree-l3"><a class="reference internal" href="reset-design.html#using-bl31-entrypoint-as-the-reset-address">7.5. Using BL31 entrypoint as the reset address</a><ul>
914<li class="toctree-l4"><a class="reference internal" href="reset-design.html#determination-of-boot-path">7.5.1. Determination of boot path</a></li>
915<li class="toctree-l4"><a class="reference internal" href="reset-design.html#platform-initialization">7.5.2. Platform initialization</a></li>
916</ul>
917</li>
918</ul>
919</li>
920<li class="toctree-l2"><a class="reference internal" href="trusted-board-boot.html">8. Trusted Board Boot</a><ul>
921<li class="toctree-l3"><a class="reference internal" href="trusted-board-boot.html#chain-of-trust">8.1. Chain of Trust</a></li>
922<li class="toctree-l3"><a class="reference internal" href="trusted-board-boot.html#trusted-board-boot-sequence">8.2. Trusted Board Boot Sequence</a></li>
923<li class="toctree-l3"><a class="reference internal" href="trusted-board-boot.html#authentication-framework">8.3. Authentication Framework</a></li>
924<li class="toctree-l3"><a class="reference internal" href="trusted-board-boot.html#certificate-generation-tool">8.4. Certificate Generation Tool</a></li>
925<li class="toctree-l3"><a class="reference internal" href="trusted-board-boot.html#authenticated-encryption-framework">8.5. Authenticated Encryption Framework</a></li>
926<li class="toctree-l3"><a class="reference internal" href="trusted-board-boot.html#firmware-encryption-tool">8.6. Firmware Encryption Tool</a></li>
927</ul>
928</li>
929<li class="toctree-l2"><a class="reference internal" href="trusted-board-boot-build.html">9. Building FIP images with support for Trusted Board Boot</a></li>
930</ul>
931</li>
932<li class="toctree-l1"><a class="reference internal" href="../plat/index.html">Platform Ports</a><ul>
933<li class="toctree-l2"><a class="reference internal" href="../plat/allwinner.html">1. Allwinner ARMv8 SoCs</a><ul>
934<li class="toctree-l3"><a class="reference internal" href="../plat/allwinner.html#building-tf-a">1.1. Building TF-A</a></li>
935<li class="toctree-l3"><a class="reference internal" href="../plat/allwinner.html#installation">1.2. Installation</a></li>
936<li class="toctree-l3"><a class="reference internal" href="../plat/allwinner.html#memory-layout">1.3. Memory layout</a><ul>
937<li class="toctree-l4"><a class="reference internal" href="../plat/allwinner.html#a64-h5-and-h6-socs">1.3.1. A64, H5 and H6 SoCs</a></li>
938<li class="toctree-l4"><a class="reference internal" href="../plat/allwinner.html#h616-soc">1.3.2. H616 SoC</a></li>
939</ul>
940</li>
941<li class="toctree-l3"><a class="reference internal" href="../plat/allwinner.html#trusted-os-dispatcher">1.4. Trusted OS dispatcher</a></li>
942</ul>
943</li>
944<li class="toctree-l2"><a class="reference internal" href="../plat/arm/index.html">2. Arm Development Platforms</a><ul>
945<li class="toctree-l3"><a class="reference internal" href="../plat/arm/juno/index.html">2.1. Arm Juno Development Platform</a><ul>
946<li class="toctree-l4"><a class="reference internal" href="../plat/arm/juno/index.html#platform-specific-build-options">2.1.1. Platform-specific build options</a></li>
947<li class="toctree-l4"><a class="reference internal" href="../plat/arm/juno/index.html#running-software-on-juno">2.1.2. Running software on Juno</a></li>
948<li class="toctree-l4"><a class="reference internal" href="../plat/arm/juno/index.html#preparing-tf-a-images">2.1.3. Preparing TF-A images</a></li>
949<li class="toctree-l4"><a class="reference internal" href="../plat/arm/juno/index.html#booting-firmware-update-images">2.1.4. Booting Firmware Update images</a></li>
950<li class="toctree-l4"><a class="reference internal" href="../plat/arm/juno/index.html#booting-an-el3-payload">2.1.5. Booting an EL3 payload</a></li>
951<li class="toctree-l4"><a class="reference internal" href="../plat/arm/juno/index.html#booting-a-preloaded-kernel-image">2.1.6. Booting a preloaded kernel image</a></li>
952<li class="toctree-l4"><a class="reference internal" href="../plat/arm/juno/index.html#testing-system-suspend">2.1.7. Testing System Suspend</a></li>
953<li class="toctree-l4"><a class="reference internal" href="../plat/arm/juno/index.html#additional-resources">2.1.8. Additional Resources</a></li>
954</ul>
955</li>
956<li class="toctree-l3"><a class="reference internal" href="../plat/arm/fvp/index.html">2.2. Arm Fixed Virtual Platforms (FVP)</a><ul>
957<li class="toctree-l4"><a class="reference internal" href="../plat/arm/fvp/index.html#fixed-virtual-platform-fvp-support">2.2.1. Fixed Virtual Platform (FVP) Support</a></li>
958<li class="toctree-l4"><a class="reference internal" href="../plat/arm/fvp/index.html#arm-fvp-platform-specific-build-options">2.2.2. Arm FVP Platform Specific Build Options</a></li>
959<li class="toctree-l4"><a class="reference internal" href="../plat/arm/fvp/index.html#booting-firmware-update-images">2.2.3. Booting Firmware Update images</a></li>
960<li class="toctree-l4"><a class="reference internal" href="../plat/arm/fvp/index.html#booting-an-el3-payload">2.2.4. Booting an EL3 payload</a></li>
961<li class="toctree-l4"><a class="reference internal" href="../plat/arm/fvp/index.html#booting-a-preloaded-kernel-image-base-fvp">2.2.5. Booting a preloaded kernel image (Base FVP)</a></li>
962</ul>
963</li>
964<li class="toctree-l3"><a class="reference internal" href="../plat/arm/fvp_r/index.html">2.3. ARM V8-R64 Fixed Virtual Platform (FVP)</a><ul>
965<li class="toctree-l4"><a class="reference internal" href="../plat/arm/fvp_r/index.html#boot-sequence">2.3.1. Boot Sequence</a></li>
966</ul>
967</li>
968<li class="toctree-l3"><a class="reference internal" href="../plat/arm/fvp-ve/index.html">2.4. Arm Versatile Express</a><ul>
969<li class="toctree-l4"><a class="reference internal" href="../plat/arm/fvp-ve/index.html#boot-sequence">2.4.1. Boot Sequence</a></li>
970<li class="toctree-l4"><a class="reference internal" href="../plat/arm/fvp-ve/index.html#how-to-build">2.4.2. How to build</a></li>
971</ul>
972</li>
973<li class="toctree-l3"><a class="reference internal" href="../plat/arm/tc/index.html">2.5. TC Total Compute Platform</a><ul>
974<li class="toctree-l4"><a class="reference internal" href="../plat/arm/tc/index.html#boot-sequence">2.5.1. Boot Sequence</a></li>
975</ul>
976</li>
977<li class="toctree-l3"><a class="reference internal" href="../plat/arm/arm_fpga/index.html">2.6. Arm FPGA Platform</a><ul>
978<li class="toctree-l4"><a class="reference internal" href="../plat/arm/arm_fpga/index.html#platform-specific-build-options">2.6.1. Platform-specific build options</a></li>
979<li class="toctree-l4"><a class="reference internal" href="../plat/arm/arm_fpga/index.html#building-the-tf-a-image">2.6.2. Building the TF-A image</a></li>
980<li class="toctree-l4"><a class="reference internal" href="../plat/arm/arm_fpga/index.html#running-the-tf-a-image">2.6.3. Running the TF-A image</a></li>
981</ul>
982</li>
983<li class="toctree-l3"><a class="reference internal" href="../plat/arm/arm-build-options.html">2.7. Arm Development Platform Build Options</a><ul>
984<li class="toctree-l4"><a class="reference internal" href="../plat/arm/arm-build-options.html#arm-platform-build-options">2.7.1. Arm Platform Build Options</a></li>
985<li class="toctree-l4"><a class="reference internal" href="../plat/arm/arm-build-options.html#arm-css-platform-specific-build-options">2.7.2. Arm CSS Platform-Specific Build Options</a></li>
986</ul>
987</li>
988<li class="toctree-l3"><a class="reference internal" href="../plat/arm/morello/index.html">2.8. Morello Platform</a><ul>
989<li class="toctree-l4"><a class="reference internal" href="../plat/arm/morello/index.html#boot-sequence">2.8.1. Boot Sequence</a></li>
990</ul>
991</li>
992<li class="toctree-l3"><a class="reference internal" href="../plat/arm/diphda/index.html">2.9. Diphda Platform</a><ul>
993<li class="toctree-l4"><a class="reference internal" href="../plat/arm/diphda/index.html#boot-sequence">2.9.1. Boot Sequence</a></li>
994</ul>
995</li>
996</ul>
997</li>
998<li class="toctree-l2"><a class="reference internal" href="../plat/deprecated.html">3. Deprecated platforms</a><ul>
999<li class="toctree-l3"><a class="reference internal" href="../plat/deprecated.html#process-of-deprecating-a-platform">3.1. Process of deprecating a platform</a></li>
1000<li class="toctree-l3"><a class="reference internal" href="../plat/deprecated.html#list-of-deprecated-platforms">3.2. List of deprecated platforms</a></li>
1001</ul>
1002</li>
1003<li class="toctree-l2"><a class="reference internal" href="../plat/meson-axg.html">4. Amlogic Meson A113D (AXG)</a></li>
1004<li class="toctree-l2"><a class="reference internal" href="../plat/meson-gxbb.html">5. Amlogic Meson S905 (GXBB)</a></li>
1005<li class="toctree-l2"><a class="reference internal" href="../plat/meson-gxl.html">6. Amlogic Meson S905x (GXL)</a></li>
1006<li class="toctree-l2"><a class="reference internal" href="../plat/meson-g12a.html">7. Amlogic Meson S905X2 (G12A)</a></li>
1007<li class="toctree-l2"><a class="reference internal" href="../plat/hikey.html">8. HiKey</a><ul>
1008<li class="toctree-l3"><a class="reference internal" href="../plat/hikey.html#how-to-build">8.1. How to build</a><ul>
1009<li class="toctree-l4"><a class="reference internal" href="../plat/hikey.html#code-locations">8.1.1. Code Locations</a></li>
1010<li class="toctree-l4"><a class="reference internal" href="../plat/hikey.html#build-procedure">8.1.2. Build Procedure</a></li>
1011</ul>
1012</li>
1013<li class="toctree-l3"><a class="reference internal" href="../plat/hikey.html#setup-console">8.2. Setup Console</a></li>
1014<li class="toctree-l3"><a class="reference internal" href="../plat/hikey.html#flash-images-in-recovery-mode">8.3. Flash images in recovery mode</a></li>
1015<li class="toctree-l3"><a class="reference internal" href="../plat/hikey.html#boot-uefi-in-normal-mode">8.4. Boot UEFI in normal mode</a></li>
1016</ul>
1017</li>
1018<li class="toctree-l2"><a class="reference internal" href="../plat/hikey960.html">9. HiKey960</a><ul>
1019<li class="toctree-l3"><a class="reference internal" href="../plat/hikey960.html#how-to-build">9.1. How to build</a><ul>
1020<li class="toctree-l4"><a class="reference internal" href="../plat/hikey960.html#code-locations">9.1.1. Code Locations</a></li>
1021<li class="toctree-l4"><a class="reference internal" href="../plat/hikey960.html#build-procedure">9.1.2. Build Procedure</a></li>
1022</ul>
1023</li>
1024<li class="toctree-l3"><a class="reference internal" href="../plat/hikey960.html#setup-console">9.2. Setup Console</a></li>
1025<li class="toctree-l3"><a class="reference internal" href="../plat/hikey960.html#boot-uefi-in-recovery-mode">9.3. Boot UEFI in recovery mode</a></li>
1026<li class="toctree-l3"><a class="reference internal" href="../plat/hikey960.html#boot-uefi-in-normal-mode">9.4. Boot UEFI in normal mode</a></li>
1027</ul>
1028</li>
1029<li class="toctree-l2"><a class="reference internal" href="../plat/intel-agilex.html">10. Intel Agilex SoCFPGA</a><ul>
1030<li class="toctree-l3"><a class="reference internal" href="../plat/intel-agilex.html#how-to-build">10.1. How to build</a><ul>
1031<li class="toctree-l4"><a class="reference internal" href="../plat/intel-agilex.html#code-locations">10.1.1. Code Locations</a></li>
1032<li class="toctree-l4"><a class="reference internal" href="../plat/intel-agilex.html#build-procedure">10.1.2. Build Procedure</a></li>
1033<li class="toctree-l4"><a class="reference internal" href="../plat/intel-agilex.html#install-procedure">10.1.3. Install Procedure</a></li>
1034</ul>
1035</li>
1036<li class="toctree-l3"><a class="reference internal" href="../plat/intel-agilex.html#boot-trace">10.2. Boot trace</a></li>
1037</ul>
1038</li>
1039<li class="toctree-l2"><a class="reference internal" href="../plat/intel-stratix10.html">11. Intel Stratix 10 SoCFPGA</a><ul>
1040<li class="toctree-l3"><a class="reference internal" href="../plat/intel-stratix10.html#how-to-build">11.1. How to build</a><ul>
1041<li class="toctree-l4"><a class="reference internal" href="../plat/intel-stratix10.html#code-locations">11.1.1. Code Locations</a></li>
1042<li class="toctree-l4"><a class="reference internal" href="../plat/intel-stratix10.html#build-procedure">11.1.2. Build Procedure</a></li>
1043<li class="toctree-l4"><a class="reference internal" href="../plat/intel-stratix10.html#install-procedure">11.1.3. Install Procedure</a></li>
1044</ul>
1045</li>
1046<li class="toctree-l3"><a class="reference internal" href="../plat/intel-stratix10.html#boot-trace">11.2. Boot trace</a></li>
1047</ul>
1048</li>
1049<li class="toctree-l2"><a class="reference internal" href="../plat/marvell/index.html">12. Marvell</a><ul>
1050<li class="toctree-l3"><a class="reference internal" href="../plat/marvell/armada/build.html">12.1. TF-A Build Instructions for Marvell Platforms</a><ul>
1051<li class="toctree-l4"><a class="reference internal" href="../plat/marvell/armada/build.html#build-instructions">12.1.1. Build Instructions</a></li>
1052<li class="toctree-l4"><a class="reference internal" href="../plat/marvell/armada/build.html#special-build-flags">12.1.2. Special Build Flags</a></li>
1053<li class="toctree-l4"><a class="reference internal" href="../plat/marvell/armada/build.html#build-output">12.1.3. Build output</a></li>
1054<li class="toctree-l4"><a class="reference internal" href="../plat/marvell/armada/build.html#tools-and-external-components-installation">12.1.4. Tools and external components installation</a></li>
1055</ul>
1056</li>
1057<li class="toctree-l3"><a class="reference internal" href="../plat/marvell/armada/porting.html">12.2. TF-A Porting Guide for Marvell Platforms</a><ul>
1058<li class="toctree-l4"><a class="reference internal" href="../plat/marvell/armada/porting.html#source-code-structure">12.2.1. Source Code Structure</a></li>
1059<li class="toctree-l4"><a class="reference internal" href="../plat/marvell/armada/porting.html#armada-70x0-armada-80x0-porting">12.2.2. Armada-70x0/Armada-80x0 Porting</a></li>
1060</ul>
1061</li>
1062<li class="toctree-l3"><a class="reference internal" href="../plat/marvell/armada/misc/mvebu-a8k-addr-map.html">12.3. Address decoding flow and address translation units of Marvell Armada 8K SoC family</a></li>
1063<li class="toctree-l3"><a class="reference internal" href="../plat/marvell/armada/misc/mvebu-amb.html">12.4. AMB - AXI MBUS address decoding</a><ul>
1064<li class="toctree-l4"><a class="reference internal" href="../plat/marvell/armada/misc/mvebu-amb.html#mandatory-functions">12.4.1. Mandatory functions</a></li>
1065<li class="toctree-l4"><a class="reference internal" href="../plat/marvell/armada/misc/mvebu-amb.html#mandatory-structures">12.4.2. Mandatory structures</a></li>
1066<li class="toctree-l4"><a class="reference internal" href="../plat/marvell/armada/misc/mvebu-amb.html#examples">12.4.3. Examples</a></li>
1067</ul>
1068</li>
1069<li class="toctree-l3"><a class="reference internal" href="../plat/marvell/armada/misc/mvebu-ccu.html">12.5. Marvell CCU address decoding bindings</a><ul>
1070<li class="toctree-l4"><a class="reference internal" href="../plat/marvell/armada/misc/mvebu-ccu.html#mandatory-functions">12.5.1. Mandatory functions</a></li>
1071<li class="toctree-l4"><a class="reference internal" href="../plat/marvell/armada/misc/mvebu-ccu.html#mandatory-structures">12.5.2. Mandatory structures</a></li>
1072<li class="toctree-l4"><a class="reference internal" href="../plat/marvell/armada/misc/mvebu-ccu.html#example">12.5.3. Example</a></li>
1073</ul>
1074</li>
1075<li class="toctree-l3"><a class="reference internal" href="../plat/marvell/armada/misc/mvebu-io-win.html">12.6. Marvell IO WIN address decoding bindings</a><ul>
1076<li class="toctree-l4"><a class="reference internal" href="../plat/marvell/armada/misc/mvebu-io-win.html#mandatory-functions">12.6.1. Mandatory functions</a></li>
1077<li class="toctree-l4"><a class="reference internal" href="../plat/marvell/armada/misc/mvebu-io-win.html#mandatory-structures">12.6.2. Mandatory structures</a></li>
1078<li class="toctree-l4"><a class="reference internal" href="../plat/marvell/armada/misc/mvebu-io-win.html#example">12.6.3. Example</a></li>
1079</ul>
1080</li>
1081<li class="toctree-l3"><a class="reference internal" href="../plat/marvell/armada/misc/mvebu-iob.html">12.7. Marvell IOB address decoding bindings</a><ul>
1082<li class="toctree-l4"><a class="reference internal" href="../plat/marvell/armada/misc/mvebu-iob.html#mandatory-functions">12.7.1. Mandatory functions</a></li>
1083<li class="toctree-l4"><a class="reference internal" href="../plat/marvell/armada/misc/mvebu-iob.html#mandatory-structures">12.7.2. Mandatory structures</a></li>
1084<li class="toctree-l4"><a class="reference internal" href="../plat/marvell/armada/misc/mvebu-iob.html#target-id-options">12.7.3. Target ID options</a></li>
1085<li class="toctree-l4"><a class="reference internal" href="../plat/marvell/armada/misc/mvebu-iob.html#example">12.7.4. Example</a></li>
1086</ul>
1087</li>
1088</ul>
1089</li>
1090<li class="toctree-l2"><a class="reference internal" href="../plat/mt8183.html">13. MediaTek 8183</a><ul>
1091<li class="toctree-l3"><a class="reference internal" href="../plat/mt8183.html#boot-sequence">13.1. Boot Sequence</a></li>
1092<li class="toctree-l3"><a class="reference internal" href="../plat/mt8183.html#how-to-build">13.2. How to Build</a></li>
1093</ul>
1094</li>
1095<li class="toctree-l2"><a class="reference internal" href="../plat/mt8192.html">14. MediaTek 8192</a><ul>
1096<li class="toctree-l3"><a class="reference internal" href="../plat/mt8192.html#boot-sequence">14.1. Boot Sequence</a></li>
1097<li class="toctree-l3"><a class="reference internal" href="../plat/mt8192.html#how-to-build">14.2. How to Build</a></li>
1098</ul>
1099</li>
1100<li class="toctree-l2"><a class="reference internal" href="../plat/mt8195.html">15. MediaTek 8195</a><ul>
1101<li class="toctree-l3"><a class="reference internal" href="../plat/mt8195.html#boot-sequence">15.1. Boot Sequence</a></li>
1102<li class="toctree-l3"><a class="reference internal" href="../plat/mt8195.html#how-to-build">15.2. How to Build</a></li>
1103</ul>
1104</li>
1105<li class="toctree-l2"><a class="reference internal" href="../plat/nvidia-tegra.html">16. NVIDIA Tegra</a><ul>
1106<li class="toctree-l3"><a class="reference internal" href="../plat/nvidia-tegra.html#directory-structure">16.1. Directory structure</a></li>
1107<li class="toctree-l3"><a class="reference internal" href="../plat/nvidia-tegra.html#trusted-os-dispatcher">16.2. Trusted OS dispatcher</a></li>
1108<li class="toctree-l3"><a class="reference internal" href="../plat/nvidia-tegra.html#scatter-files">16.3. Scatter files</a></li>
1109<li class="toctree-l3"><a class="reference internal" href="../plat/nvidia-tegra.html#preparing-the-bl31-image-to-run-on-tegra-socs">16.4. Preparing the BL31 image to run on Tegra SoCs</a></li>
1110<li class="toctree-l3"><a class="reference internal" href="../plat/nvidia-tegra.html#power-management">16.5. Power Management</a></li>
1111<li class="toctree-l3"><a class="reference internal" href="../plat/nvidia-tegra.html#tegra-configs">16.6. Tegra configs</a></li>
1112</ul>
1113</li>
1114<li class="toctree-l2"><a class="reference internal" href="../plat/warp7.html">17. NXP i.MX7 WaRP7</a><ul>
1115<li class="toctree-l3"><a class="reference internal" href="../plat/warp7.html#boot-flow">17.1. Boot Flow</a></li>
1116<li class="toctree-l3"><a class="reference internal" href="../plat/warp7.html#build-instructions">17.2. Build Instructions</a><ul>
1117<li class="toctree-l4"><a class="reference internal" href="../plat/warp7.html#u-boot">17.2.1. U-Boot</a></li>
1118<li class="toctree-l4"><a class="reference internal" href="../plat/warp7.html#op-tee">17.2.2. OP-TEE</a></li>
1119<li class="toctree-l4"><a class="reference internal" href="../plat/warp7.html#tf-a">17.2.3. TF-A</a></li>
1120<li class="toctree-l4"><a class="reference internal" href="../plat/warp7.html#fip">17.2.4. FIP</a></li>
1121</ul>
1122</li>
1123<li class="toctree-l3"><a class="reference internal" href="../plat/warp7.html#deploy-images">17.3. Deploy Images</a></li>
1124<li class="toctree-l3"><a class="reference internal" href="../plat/warp7.html#signing-bl2">17.4. Signing BL2</a></li>
1125</ul>
1126</li>
1127<li class="toctree-l2"><a class="reference internal" href="../plat/imx8.html">18. NXP i.MX 8 Series</a><ul>
1128<li class="toctree-l3"><a class="reference internal" href="../plat/imx8.html#boot-sequence">18.1. Boot Sequence</a></li>
1129<li class="toctree-l3"><a class="reference internal" href="../plat/imx8.html#how-to-build">18.2. How to build</a><ul>
1130<li class="toctree-l4"><a class="reference internal" href="../plat/imx8.html#build-procedure">18.2.1. Build Procedure</a></li>
1131<li class="toctree-l4"><a class="reference internal" href="../plat/imx8.html#deploy-tf-a-images">18.2.2. Deploy TF-A Images</a></li>
1132</ul>
1133</li>
1134</ul>
1135</li>
1136<li class="toctree-l2"><a class="reference internal" href="../plat/imx8m.html">19. NXP i.MX 8M Series</a><ul>
1137<li class="toctree-l3"><a class="reference internal" href="../plat/imx8m.html#boot-sequence">19.1. Boot Sequence</a></li>
1138<li class="toctree-l3"><a class="reference internal" href="../plat/imx8m.html#how-to-build">19.2. How to build</a><ul>
1139<li class="toctree-l4"><a class="reference internal" href="../plat/imx8m.html#build-procedure">19.2.1. Build Procedure</a></li>
1140<li class="toctree-l4"><a class="reference internal" href="../plat/imx8m.html#deploy-tf-a-images">19.2.2. Deploy TF-A Images</a></li>
1141</ul>
1142</li>
1143<li class="toctree-l3"><a class="reference internal" href="../plat/imx8m.html#tbbr-boot-sequence">19.3. TBBR Boot Sequence</a></li>
1144</ul>
1145</li>
1146<li class="toctree-l2"><a class="reference internal" href="../plat/ls1043a.html">20. NXP QorIQ® LS1043A</a><ul>
1147<li class="toctree-l3"><a class="reference internal" href="../plat/ls1043a.html#ls1043ardb-specification">20.1. LS1043ARDB Specification:</a></li>
1148<li class="toctree-l3"><a class="reference internal" href="../plat/ls1043a.html#boot-sequence">20.2. Boot Sequence</a></li>
1149<li class="toctree-l3"><a class="reference internal" href="../plat/ls1043a.html#how-to-build">20.3. How to build</a><ul>
1150<li class="toctree-l4"><a class="reference internal" href="../plat/ls1043a.html#build-procedure">20.3.1. Build Procedure</a></li>
1151<li class="toctree-l4"><a class="reference internal" href="../plat/ls1043a.html#deploy-tf-a-images">20.3.2. Deploy TF-A Images</a></li>
1152</ul>
1153</li>
1154</ul>
1155</li>
1156<li class="toctree-l2"><a class="reference internal" href="../plat/nxp/index.html">21. NXP Reference Development Platforms</a><ul>
1157<li class="toctree-l3"><a class="reference internal" href="../plat/nxp/nxp-layerscape.html">21.1. <span class="sectnum">1.</span> NXP SoCs - Overview</a><ul>
1158<li class="toctree-l4"><a class="reference internal" href="../plat/nxp/nxp-layerscape.html#table-of-supported-boot-modes-by-each-platform-platform-that-needs-fip-ddr">21.1.1. <span class="sectnum">1.1.</span> Table of supported boot-modes by each platform &amp; platform that needs FIP-DDR:</a></li>
1159<li class="toctree-l4"><a class="reference internal" href="../plat/nxp/nxp-layerscape.html#boot-sequence">21.1.2. <span class="sectnum">1.2.</span> Boot Sequence</a></li>
1160<li class="toctree-l4"><a class="reference internal" href="../plat/nxp/nxp-layerscape.html#boot-sequence-with-fip-ddr">21.1.3. <span class="sectnum">1.3.</span> Boot Sequence with FIP-DDR</a></li>
1161<li class="toctree-l4"><a class="reference internal" href="../plat/nxp/nxp-layerscape.html#ddr-memory-layout">21.1.4. <span class="sectnum">1.4.</span> DDR Memory Layout</a></li>
1162</ul>
1163</li>
1164<li class="toctree-l3"><a class="reference internal" href="../plat/nxp/nxp-layerscape.html#how-to-build">21.2. <span class="sectnum">2.</span> How to build</a><ul>
1165<li class="toctree-l4"><a class="reference internal" href="../plat/nxp/nxp-layerscape.html#code-locations">21.2.1. <span class="sectnum">2.1.</span> Code Locations</a></li>
1166<li class="toctree-l4"><a class="reference internal" href="../plat/nxp/nxp-layerscape.html#build-procedure">21.2.2. <span class="sectnum">2.2.</span> Build Procedure</a></li>
1167</ul>
1168</li>
1169<li class="toctree-l3"><a class="reference internal" href="../plat/nxp/nxp-layerscape.html#deploy-atf-images">21.3. <span class="sectnum">3.</span> Deploy ATF Images</a></li>
1170<li class="toctree-l3"><a class="reference internal" href="../plat/nxp/nxp-layerscape.html#trusted-board-boot">21.4. <span class="sectnum">4.</span> Trusted Board Boot:</a></li>
1171<li class="toctree-l3"><a class="reference internal" href="../plat/nxp/nxp-ls-fuse-prov.html">21.5. Steps to blow fuses on NXP LS SoC:</a></li>
1172<li class="toctree-l3"><a class="reference internal" href="../plat/nxp/nxp-ls-fuse-prov.html#second-method-to-do-the-fuse-provsioning">21.6. Second method to do the fuse provsioning:</a></li>
1173<li class="toctree-l3"><a class="reference internal" href="../plat/nxp/nxp-ls-tbbr.html">21.7. NXP Platforms:</a><ul>
1174<li class="toctree-l4"><a class="reference internal" href="../plat/nxp/nxp-ls-tbbr.html#bare-minimum-preparation-to-run-tbbr-on-nxp-platforms">21.7.1. Bare-Minimum Preparation to run  TBBR on NXP Platforms:</a></li>
1175<li class="toctree-l4"><a class="reference internal" href="../plat/nxp/nxp-ls-tbbr.html#two-options-are-provided-for-trusted-board-boot">21.7.2. Two options are provided for TRUSTED_BOARD_BOOT:</a></li>
1176</ul>
1177</li>
1178<li class="toctree-l3"><a class="reference internal" href="../plat/nxp/nxp-ls-tbbr.html#option-1-cot-using-x-509-certificates">21.8. Option 1: CoT using X 509 certificates</a></li>
1179<li class="toctree-l3"><a class="reference internal" href="../plat/nxp/nxp-ls-tbbr.html#option-2-cot-using-nxp-csf-headers">21.9. Option 2: CoT using NXP CSF headers.</a><ul>
1180<li class="toctree-l4"><a class="reference internal" href="../plat/nxp/nxp-ls-tbbr.html#deploy-atf-images">21.9.1. Deploy ATF Images</a></li>
1181<li class="toctree-l4"><a class="reference internal" href="../plat/nxp/nxp-ls-tbbr.html#verification-to-check-if-secure-state-is-achieved">21.9.2. Verification to check if Secure state is achieved:</a></li>
1182</ul>
1183</li>
1184</ul>
1185</li>
1186<li class="toctree-l2"><a class="reference internal" href="../plat/poplar.html">22. Poplar</a><ul>
1187<li class="toctree-l3"><a class="reference internal" href="../plat/poplar.html#how-to-build">22.1. How to build</a><ul>
1188<li class="toctree-l4"><a class="reference internal" href="../plat/poplar.html#code-locations">22.1.1. Code Locations</a></li>
1189<li class="toctree-l4"><a class="reference internal" href="../plat/poplar.html#build-procedure">22.1.2. Build Procedure</a></li>
1190</ul>
1191</li>
1192<li class="toctree-l3"><a class="reference internal" href="../plat/poplar.html#install-procedure">22.2. Install Procedure</a></li>
1193<li class="toctree-l3"><a class="reference internal" href="../plat/poplar.html#boot-trace">22.3. Boot trace</a></li>
1194</ul>
1195</li>
1196<li class="toctree-l2"><a class="reference internal" href="../plat/qemu.html">23. QEMU virt Armv8-A</a><ul>
1197<li class="toctree-l3"><a class="reference internal" href="../plat/qemu.html#getting-non-tf-images">23.1. Getting non-TF images</a></li>
1198<li class="toctree-l3"><a class="reference internal" href="../plat/qemu.html#booting-via-semi-hosting-option">23.2. Booting via semi-hosting option</a></li>
1199<li class="toctree-l3"><a class="reference internal" href="../plat/qemu.html#booting-via-flash-based-firmwares">23.3. Booting via flash based firmwares</a></li>
1200</ul>
1201</li>
1202<li class="toctree-l2"><a class="reference internal" href="../plat/qemu-sbsa.html">24. QEMU SBSA Target</a></li>
1203<li class="toctree-l2"><a class="reference internal" href="../plat/qti.html">25. Qualcomm Technologies, Inc.</a><ul>
1204<li class="toctree-l3"><a class="reference internal" href="../plat/qti.html#boot-trace">25.1. Boot Trace</a></li>
1205<li class="toctree-l3"><a class="reference internal" href="../plat/qti.html#how-to-build">25.2. How to build</a><ul>
1206<li class="toctree-l4"><a class="reference internal" href="../plat/qti.html#code-locations">25.2.1. Code Locations</a></li>
1207<li class="toctree-l4"><a class="reference internal" href="../plat/qti.html#build-procedure">25.2.2. Build Procedure</a></li>
1208</ul>
1209</li>
1210</ul>
1211</li>
1212<li class="toctree-l2"><a class="reference internal" href="../plat/rpi3.html">26. Raspberry Pi 3</a><ul>
1213<li class="toctree-l3"><a class="reference internal" href="../plat/rpi3.html#design">26.1. Design</a><ul>
1214<li class="toctree-l4"><a class="reference internal" href="../plat/rpi3.html#placement-of-images">26.1.1. Placement of images</a></li>
1215<li class="toctree-l4"><a class="reference internal" href="../plat/rpi3.html#boot-sequence">26.1.2. Boot sequence</a></li>
1216<li class="toctree-l4"><a class="reference internal" href="../plat/rpi3.html#secondary-cores">26.1.3. Secondary cores</a></li>
1217</ul>
1218</li>
1219<li class="toctree-l3"><a class="reference internal" href="../plat/rpi3.html#build-instructions">26.2. Build Instructions</a><ul>
1220<li class="toctree-l4"><a class="reference internal" href="../plat/rpi3.html#building-the-firmware-for-kernels-that-don-t-support-psci">26.2.1. Building the firmware for kernels that don’t support PSCI</a></li>
1221<li class="toctree-l4"><a class="reference internal" href="../plat/rpi3.html#building-the-firmware-for-kernels-that-support-psci">26.2.2. Building the firmware for kernels that support PSCI</a></li>
1222</ul>
1223</li>
1224<li class="toctree-l3"><a class="reference internal" href="../plat/rpi3.html#aarch64-kernel-build-instructions">26.3. AArch64 kernel build instructions</a></li>
1225<li class="toctree-l3"><a class="reference internal" href="../plat/rpi3.html#setup-sd-card">26.4. Setup SD card</a></li>
1226</ul>
1227</li>
1228<li class="toctree-l2"><a class="reference internal" href="../plat/rpi4.html">27. Raspberry Pi 4</a><ul>
1229<li class="toctree-l3"><a class="reference internal" href="../plat/rpi4.html#build-instructions">27.1. Build Instructions</a></li>
1230<li class="toctree-l3"><a class="reference internal" href="../plat/rpi4.html#tf-a-port-design">27.2. TF-A port design</a></li>
1231</ul>
1232</li>
1233<li class="toctree-l2"><a class="reference internal" href="../plat/rcar-gen3.html">28. Renesas R-Car</a><ul>
1234<li class="toctree-l3"><a class="reference internal" href="../plat/rcar-gen3.html#renesas-r-car-gen3-evaluation-boards">28.1. Renesas R-Car Gen3 evaluation boards:</a></li>
1235<li class="toctree-l3"><a class="reference internal" href="../plat/rcar-gen3.html#overview">28.2. Overview</a></li>
1236<li class="toctree-l3"><a class="reference internal" href="../plat/rcar-gen3.html#how-to-build">28.3. How to build</a><ul>
1237<li class="toctree-l4"><a class="reference internal" href="../plat/rcar-gen3.html#build-tested">28.3.1. Build Tested:</a></li>
1238<li class="toctree-l4"><a class="reference internal" href="../plat/rcar-gen3.html#system-tested">28.3.2. System Tested:</a></li>
1239<li class="toctree-l4"><a class="reference internal" href="../plat/rcar-gen3.html#tf-a-build-procedure">28.3.3. TF-A Build Procedure</a></li>
1240<li class="toctree-l4"><a class="reference internal" href="../plat/rcar-gen3.html#install-procedure">28.3.4. Install Procedure</a></li>
1241</ul>
1242</li>
1243<li class="toctree-l3"><a class="reference internal" href="../plat/rcar-gen3.html#boot-trace">28.4. Boot trace</a></li>
1244</ul>
1245</li>
1246<li class="toctree-l2"><a class="reference internal" href="../plat/rz-g2.html">29. Renesas RZ/G</a><ul>
1247<li class="toctree-l3"><a class="reference internal" href="../plat/rz-g2.html#renesas-rz-g2-reference-platforms">29.1. Renesas RZ/G2 reference platforms:</a></li>
1248<li class="toctree-l3"><a class="reference internal" href="../plat/rz-g2.html#overview">29.2. Overview</a></li>
1249<li class="toctree-l3"><a class="reference internal" href="../plat/rz-g2.html#how-to-build">29.3. How to build</a><ul>
1250<li class="toctree-l4"><a class="reference internal" href="../plat/rz-g2.html#build-tested">29.3.1. Build Tested:</a></li>
1251<li class="toctree-l4"><a class="reference internal" href="../plat/rz-g2.html#system-tested">29.3.2. System Tested:</a></li>
1252<li class="toctree-l4"><a class="reference internal" href="../plat/rz-g2.html#tf-a-build-procedure">29.3.3. TF-A Build Procedure</a></li>
1253<li class="toctree-l4"><a class="reference internal" href="../plat/rz-g2.html#install-procedure">29.3.4. Install Procedure</a></li>
1254</ul>
1255</li>
1256<li class="toctree-l3"><a class="reference internal" href="../plat/rz-g2.html#boot-trace">29.4. Boot trace</a></li>
1257</ul>
1258</li>
1259<li class="toctree-l2"><a class="reference internal" href="../plat/rockchip.html">30. Rockchip SoCs</a><ul>
1260<li class="toctree-l3"><a class="reference internal" href="../plat/rockchip.html#boot-sequence">30.1. Boot Sequence</a></li>
1261<li class="toctree-l3"><a class="reference internal" href="../plat/rockchip.html#how-to-build">30.2. How to build</a></li>
1262<li class="toctree-l3"><a class="reference internal" href="../plat/rockchip.html#how-to-deploy">30.3. How to deploy</a></li>
1263</ul>
1264</li>
1265<li class="toctree-l2"><a class="reference internal" href="../plat/socionext-uniphier.html">31. Socionext UniPhier</a><ul>
1266<li class="toctree-l3"><a class="reference internal" href="../plat/socionext-uniphier.html#boot-flow">31.1. Boot Flow</a></li>
1267<li class="toctree-l3"><a class="reference internal" href="../plat/socionext-uniphier.html#basic-build">31.2. Basic Build</a></li>
1268<li class="toctree-l3"><a class="reference internal" href="../plat/socionext-uniphier.html#optional-features">31.3. Optional features</a></li>
1269</ul>
1270</li>
1271<li class="toctree-l2"><a class="reference internal" href="../plat/synquacer.html">32. Socionext Synquacer</a><ul>
1272<li class="toctree-l3"><a class="reference internal" href="../plat/synquacer.html#how-to-build">32.1. How to build</a><ul>
1273<li class="toctree-l4"><a class="reference internal" href="../plat/synquacer.html#code-locations">32.1.1. Code Locations</a></li>
1274<li class="toctree-l4"><a class="reference internal" href="../plat/synquacer.html#boot-flow">32.1.2. Boot Flow</a></li>
1275<li class="toctree-l4"><a class="reference internal" href="../plat/synquacer.html#build-procedure">32.1.3. Build Procedure</a></li>
1276<li class="toctree-l4"><a class="reference internal" href="../plat/synquacer.html#install-the-system-firmware">32.1.4. Install the System Firmware</a></li>
1277</ul>
1278</li>
1279</ul>
1280</li>
1281<li class="toctree-l2"><a class="reference internal" href="../plat/stm32mp1.html">33. STMicroelectronics STM32MP1</a><ul>
1282<li class="toctree-l3"><a class="reference internal" href="../plat/stm32mp1.html#stm32mp1-versions">33.1. STM32MP1 Versions</a></li>
1283<li class="toctree-l3"><a class="reference internal" href="../plat/stm32mp1.html#design">33.2. Design</a><ul>
1284<li class="toctree-l4"><a class="reference internal" href="../plat/stm32mp1.html#boot-with-fip">33.2.1. Boot with FIP</a></li>
1285<li class="toctree-l4"><a class="reference internal" href="../plat/stm32mp1.html#stm32image-bootchain">33.2.2. STM32IMAGE bootchain</a></li>
1286<li class="toctree-l4"><a class="reference internal" href="../plat/stm32mp1.html#memory-mapping">33.2.3. Memory mapping</a></li>
1287<li class="toctree-l4"><a class="reference internal" href="../plat/stm32mp1.html#boot-sequence">33.2.4. Boot sequence</a></li>
1288</ul>
1289</li>
1290<li class="toctree-l3"><a class="reference internal" href="../plat/stm32mp1.html#build-instructions">33.3. Build Instructions</a><ul>
1291<li class="toctree-l4"><a class="reference internal" href="../plat/stm32mp1.html#id1">33.3.1. Boot with FIP</a></li>
1292<li class="toctree-l4"><a class="reference internal" href="../plat/stm32mp1.html#id2">33.3.2. STM32IMAGE bootchain</a></li>
1293</ul>
1294</li>
1295<li class="toctree-l3"><a class="reference internal" href="../plat/stm32mp1.html#populate-sd-card">33.4. Populate SD-card</a><ul>
1296<li class="toctree-l4"><a class="reference internal" href="../plat/stm32mp1.html#id3">33.4.1. Boot with FIP</a></li>
1297<li class="toctree-l4"><a class="reference internal" href="../plat/stm32mp1.html#id4">33.4.2. STM32IMAGE bootchain</a></li>
1298</ul>
1299</li>
1300</ul>
1301</li>
1302<li class="toctree-l2"><a class="reference internal" href="../plat/ti-k3.html">34. Texas Instruments K3</a><ul>
1303<li class="toctree-l3"><a class="reference internal" href="../plat/ti-k3.html#boot-flow">34.1. Boot Flow</a></li>
1304<li class="toctree-l3"><a class="reference internal" href="../plat/ti-k3.html#build-instructions">34.2. Build Instructions</a></li>
1305<li class="toctree-l3"><a class="reference internal" href="../plat/ti-k3.html#deploy-images">34.3. Deploy Images</a></li>
1306</ul>
1307</li>
1308<li class="toctree-l2"><a class="reference internal" href="../plat/xilinx-versal.html">35. Xilinx Versal</a><ul>
1309<li class="toctree-l3"><a class="reference internal" href="../plat/xilinx-versal.html#xilinx-versal-platform-specific-build-options">35.1. Xilinx Versal platform specific build options</a></li>
1310<li class="toctree-l3"><a class="reference internal" href="../plat/xilinx-versal.html#plm-tf-a-parameter-passing">35.2. # PLM-&gt;TF-A Parameter Passing</a></li>
1311</ul>
1312</li>
1313<li class="toctree-l2"><a class="reference internal" href="../plat/xilinx-zynqmp.html">36. Xilinx Zynq UltraScale+ MPSoC</a><ul>
1314<li class="toctree-l3"><a class="reference internal" href="../plat/xilinx-zynqmp.html#zynqmp-platform-specific-build-options">36.1. ZynqMP platform specific build options</a></li>
1315<li class="toctree-l3"><a class="reference internal" href="../plat/xilinx-zynqmp.html#fsbl-tf-a-parameter-passing">36.2. FSBL-&gt;TF-A Parameter Passing</a></li>
1316<li class="toctree-l3"><a class="reference internal" href="../plat/xilinx-zynqmp.html#power-domain-tree">36.3. Power Domain Tree</a></li>
1317</ul>
1318</li>
1319<li class="toctree-l2"><a class="reference internal" href="../plat/brcm-stingray.html">37. Broadcom Stingray</a><ul>
1320<li class="toctree-l3"><a class="reference internal" href="../plat/brcm-stingray.html#description">37.1. Description</a></li>
1321<li class="toctree-l3"><a class="reference internal" href="../plat/brcm-stingray.html#boot-sequence">37.2. Boot Sequence</a><ul>
1322<li class="toctree-l4"><a class="reference internal" href="../plat/brcm-stingray.html#code-locations">37.2.1. Code Locations</a></li>
1323</ul>
1324</li>
1325<li class="toctree-l3"><a class="reference internal" href="../plat/brcm-stingray.html#how-to-build">37.3. How to build</a><ul>
1326<li class="toctree-l4"><a class="reference internal" href="../plat/brcm-stingray.html#build-procedure">37.3.1. Build Procedure</a></li>
1327<li class="toctree-l4"><a class="reference internal" href="../plat/brcm-stingray.html#deploy-tf-a-images">37.3.2. Deploy TF-A Images</a></li>
1328</ul>
1329</li>
1330</ul>
1331</li>
1332</ul>
1333</li>
1334<li class="toctree-l1"><a class="reference internal" href="../perf/index.html">Performance &amp; Testing</a><ul>
1335<li class="toctree-l2"><a class="reference internal" href="../perf/psci-performance-juno.html">1. PSCI Performance Measurements on Arm Juno Development Platform</a><ul>
1336<li class="toctree-l3"><a class="reference internal" href="../perf/psci-performance-juno.html#method">1.1. Method</a></li>
1337<li class="toctree-l3"><a class="reference internal" href="../perf/psci-performance-juno.html#results-and-commentary">1.2. Results and Commentary</a><ul>
1338<li class="toctree-l4"><a class="reference internal" href="../perf/psci-performance-juno.html#cpu-suspend-to-deepest-power-level-on-all-cpus-in-parallel">1.2.1. <code class="docutils literal notranslate"><span class="pre">CPU_SUSPEND</span></code> to deepest power level on all CPUs in parallel</a></li>
1339<li class="toctree-l4"><a class="reference internal" href="../perf/psci-performance-juno.html#cpu-suspend-to-power-level-0-on-all-cpus-in-parallel">1.2.2. <code class="docutils literal notranslate"><span class="pre">CPU_SUSPEND</span></code> to power level 0 on all CPUs in parallel</a></li>
1340<li class="toctree-l4"><a class="reference internal" href="../perf/psci-performance-juno.html#cpu-suspend-to-deepest-power-level-on-all-cpus-in-sequence">1.2.3. <code class="docutils literal notranslate"><span class="pre">CPU_SUSPEND</span></code> to deepest power level on all CPUs in sequence</a></li>
1341<li class="toctree-l4"><a class="reference internal" href="../perf/psci-performance-juno.html#cpu-suspend-to-power-level-0-on-all-cpus-in-sequence">1.2.4. <code class="docutils literal notranslate"><span class="pre">CPU_SUSPEND</span></code> to power level 0 on all CPUs in sequence</a></li>
1342<li class="toctree-l4"><a class="reference internal" href="../perf/psci-performance-juno.html#cpu-off-on-all-non-lead-cpus-in-sequence-then-cpu-suspend-on-lead-cpu-to-deepest-power-level">1.2.5. <code class="docutils literal notranslate"><span class="pre">CPU_OFF</span></code> on all non-lead CPUs in sequence then <code class="docutils literal notranslate"><span class="pre">CPU_SUSPEND</span></code> on lead CPU to deepest power level</a></li>
1343<li class="toctree-l4"><a class="reference internal" href="../perf/psci-performance-juno.html#psci-version-on-all-cpus-in-parallel">1.2.6. <code class="docutils literal notranslate"><span class="pre">PSCI_VERSION</span></code> on all CPUs in parallel</a></li>
1344</ul>
1345</li>
1346</ul>
1347</li>
1348<li class="toctree-l2"><a class="reference internal" href="../perf/tsp.html">2. Test Secure Payload (TSP) and Dispatcher (TSPD)</a><ul>
1349<li class="toctree-l3"><a class="reference internal" href="../perf/tsp.html#building-the-test-secure-payload">2.1. Building the Test Secure Payload</a></li>
1350</ul>
1351</li>
1352<li class="toctree-l2"><a class="reference internal" href="../perf/performance-monitoring-unit.html">3. Performance Monitoring Unit</a><ul>
1353<li class="toctree-l3"><a class="reference internal" href="../perf/performance-monitoring-unit.html#pmu-counters">3.1. PMU Counters</a><ul>
1354<li class="toctree-l4"><a class="reference internal" href="../perf/performance-monitoring-unit.html#architectural-mappings">3.1.1. Architectural mappings</a></li>
1355</ul>
1356</li>
1357<li class="toctree-l3"><a class="reference internal" href="../perf/performance-monitoring-unit.html#configuring-the-pmu-for-counting-events">3.2. Configuring the PMU for counting events</a><ul>
1358<li class="toctree-l4"><a class="reference internal" href="../perf/performance-monitoring-unit.html#id1">3.2.1. Architectural mappings</a></li>
1359<li class="toctree-l4"><a class="reference internal" href="../perf/performance-monitoring-unit.html#relevant-register-fields">3.2.2. Relevant register fields</a></li>
1360</ul>
1361</li>
1362</ul>
1363</li>
1364</ul>
1365</li>
1366<li class="toctree-l1"><a class="reference internal" href="../security_advisories/index.html">Security Advisories</a><ul>
1367<li class="toctree-l2"><a class="reference internal" href="../security_advisories/security-advisory-tfv-1.html">1. Advisory TFV-1 (CVE-2016-10319)</a></li>
1368<li class="toctree-l2"><a class="reference internal" href="../security_advisories/security-advisory-tfv-2.html">2. Advisory TFV-2 (CVE-2017-7564)</a></li>
1369<li class="toctree-l2"><a class="reference internal" href="../security_advisories/security-advisory-tfv-3.html">3. Advisory TFV-3 (CVE-2017-7563)</a></li>
1370<li class="toctree-l2"><a class="reference internal" href="../security_advisories/security-advisory-tfv-4.html">4. Advisory TFV-4 (CVE-2017-9607)</a></li>
1371<li class="toctree-l2"><a class="reference internal" href="../security_advisories/security-advisory-tfv-5.html">5. Advisory TFV-5 (CVE-2017-15031)</a></li>
1372<li class="toctree-l2"><a class="reference internal" href="../security_advisories/security-advisory-tfv-6.html">6. Advisory TFV-6 (CVE-2017-5753, CVE-2017-5715, CVE-2017-5754)</a><ul>
1373<li class="toctree-l3"><a class="reference internal" href="../security_advisories/security-advisory-tfv-6.html#variant-1-cve-2017-5753">6.1. Variant 1 (CVE-2017-5753)</a></li>
1374<li class="toctree-l3"><a class="reference internal" href="../security_advisories/security-advisory-tfv-6.html#variant-2-cve-2017-5715">6.2. Variant 2 (CVE-2017-5715)</a></li>
1375<li class="toctree-l3"><a class="reference internal" href="../security_advisories/security-advisory-tfv-6.html#variant-3-cve-2017-5754">6.3. Variant 3 (CVE-2017-5754)</a></li>
1376</ul>
1377</li>
1378<li class="toctree-l2"><a class="reference internal" href="../security_advisories/security-advisory-tfv-7.html">7. Advisory TFV-7 (CVE-2018-3639)</a><ul>
1379<li class="toctree-l3"><a class="reference internal" href="../security_advisories/security-advisory-tfv-7.html#static-mitigation">7.1. Static mitigation</a></li>
1380<li class="toctree-l3"><a class="reference internal" href="../security_advisories/security-advisory-tfv-7.html#dynamic-mitigation">7.2. Dynamic mitigation</a></li>
1381</ul>
1382</li>
1383<li class="toctree-l2"><a class="reference internal" href="../security_advisories/security-advisory-tfv-8.html">8. Advisory TFV-8 (CVE-2018-19440)</a></li>
1384</ul>
1385</li>
1386<li class="toctree-l1"><a class="reference internal" href="../design_documents/index.html">Design Documents</a><ul>
1387<li class="toctree-l2"><a class="reference internal" href="../design_documents/cmake_framework.html">1. TF-A CMake buildsystem</a><ul>
1388<li class="toctree-l3"><a class="reference internal" href="../design_documents/cmake_framework.html#abstract">1.1. Abstract</a></li>
1389<li class="toctree-l3"><a class="reference internal" href="../design_documents/cmake_framework.html#introduction">1.2. Introduction</a></li>
1390<li class="toctree-l3"><a class="reference internal" href="../design_documents/cmake_framework.html#main-features">1.3. Main features</a><ul>
1391<li class="toctree-l4"><a class="reference internal" href="../design_documents/cmake_framework.html#structured-configuration-description">1.3.1. Structured configuration description</a></li>
1392<li class="toctree-l4"><a class="reference internal" href="../design_documents/cmake_framework.html#target-description">1.3.2. Target description</a></li>
1393<li class="toctree-l4"><a class="reference internal" href="../design_documents/cmake_framework.html#compiler-abstraction">1.3.3. Compiler abstraction</a></li>
1394<li class="toctree-l4"><a class="reference internal" href="../design_documents/cmake_framework.html#external-tools">1.3.4. External tools</a></li>
1395</ul>
1396</li>
1397<li class="toctree-l3"><a class="reference internal" href="../design_documents/cmake_framework.html#workflow">1.4. Workflow</a></li>
1398<li class="toctree-l3"><a class="reference internal" href="../design_documents/cmake_framework.html#example">1.5. Example</a></li>
1399</ul>
1400</li>
1401<li class="toctree-l2"><a class="reference internal" href="../design_documents/measured_boot_poc.html">2. Interaction between Measured Boot and an fTPM (PoC)</a><ul>
1402<li class="toctree-l3"><a class="reference internal" href="../design_documents/measured_boot_poc.html#components">2.1. Components</a></li>
1403<li class="toctree-l3"><a class="reference internal" href="../design_documents/measured_boot_poc.html#building-the-poc-for-the-arm-fvp-platform">2.2. Building the PoC for the Arm FVP platform</a></li>
1404<li class="toctree-l3"><a class="reference internal" href="../design_documents/measured_boot_poc.html#running-and-using-the-poc-on-the-armv8-a-foundation-aem-fvp">2.3. Running and using the PoC on the Armv8-A Foundation AEM FVP</a></li>
1405<li class="toctree-l3"><a class="reference internal" href="../design_documents/measured_boot_poc.html#fine-tuning-the-ftpm-ta">2.4. Fine-tuning the fTPM TA</a></li>
1406</ul>
1407</li>
1408</ul>
1409</li>
1410<li class="toctree-l1"><a class="reference internal" href="../threat_model/index.html">Threat Model</a><ul>
1411<li class="toctree-l2"><a class="reference internal" href="../threat_model/threat_model.html">1. Generic threat model</a><ul>
1412<li class="toctree-l3"><a class="reference internal" href="../threat_model/threat_model.html#introduction">1.1. Introduction</a></li>
1413<li class="toctree-l3"><a class="reference internal" href="../threat_model/threat_model.html#target-of-evaluation">1.2. Target of Evaluation</a><ul>
1414<li class="toctree-l4"><a class="reference internal" href="../threat_model/threat_model.html#data-flow-diagram">1.2.1. Data Flow Diagram</a></li>
1415</ul>
1416</li>
1417<li class="toctree-l3"><a class="reference internal" href="../threat_model/threat_model.html#threat-analysis">1.3. Threat Analysis</a><ul>
1418<li class="toctree-l4"><a class="reference internal" href="../threat_model/threat_model.html#assets">1.3.1. Assets</a></li>
1419<li class="toctree-l4"><a class="reference internal" href="../threat_model/threat_model.html#threat-agents">1.3.2. Threat Agents</a></li>
1420<li class="toctree-l4"><a class="reference internal" href="../threat_model/threat_model.html#threat-types">1.3.3. Threat Types</a></li>
1421<li class="toctree-l4"><a class="reference internal" href="../threat_model/threat_model.html#threat-risk-ratings">1.3.4. Threat Risk Ratings</a></li>
1422<li class="toctree-l4"><a class="reference internal" href="../threat_model/threat_model.html#threat-assessment">1.3.5. Threat Assessment</a></li>
1423</ul>
1424</li>
1425</ul>
1426</li>
1427<li class="toctree-l2"><a class="reference internal" href="../threat_model/threat_model_spm.html">2. SPMC threat model</a><ul>
1428<li class="toctree-l3"><a class="reference internal" href="../threat_model/threat_model_spm.html#introduction">2.1. Introduction</a></li>
1429<li class="toctree-l3"><a class="reference internal" href="../threat_model/threat_model_spm.html#target-of-evaluation">2.2. Target of Evaluation</a><ul>
1430<li class="toctree-l4"><a class="reference internal" href="../threat_model/threat_model_spm.html#data-flow-diagram">2.2.1. Data Flow Diagram</a></li>
1431</ul>
1432</li>
1433<li class="toctree-l3"><a class="reference internal" href="../threat_model/threat_model_spm.html#threat-analysis">2.3. Threat Analysis</a><ul>
1434<li class="toctree-l4"><a class="reference internal" href="../threat_model/threat_model_spm.html#trust-boundaries">2.3.1. Trust boundaries</a></li>
1435<li class="toctree-l4"><a class="reference internal" href="../threat_model/threat_model_spm.html#assets">2.3.2. Assets</a></li>
1436<li class="toctree-l4"><a class="reference internal" href="../threat_model/threat_model_spm.html#threat-agents">2.3.3. Threat Agents</a></li>
1437<li class="toctree-l4"><a class="reference internal" href="../threat_model/threat_model_spm.html#threat-types">2.3.4. Threat types</a></li>
1438<li class="toctree-l4"><a class="reference internal" href="../threat_model/threat_model_spm.html#threat-assessment">2.3.5. Threat Assessment</a></li>
1439</ul>
1440</li>
1441</ul>
1442</li>
1443</ul>
1444</li>
1445<li class="toctree-l1"><a class="reference internal" href="../change-log.html">Change Log &amp; Release Notes</a><ul>
1446<li class="toctree-l2"><a class="reference internal" href="../change-log.html#id1">2.6 (2021-11-22)</a><ul>
1447<li class="toctree-l3"><a class="reference internal" href="../change-log.html#breaking-changes">⚠ BREAKING CHANGES</a></li>
1448<li class="toctree-l3"><a class="reference internal" href="../change-log.html#new-features">New Features</a></li>
1449<li class="toctree-l3"><a class="reference internal" href="../change-log.html#resolved-issues">Resolved Issues</a></li>
1450</ul>
1451</li>
1452<li class="toctree-l2"><a class="reference internal" href="../change-log.html#id2">2.5.0 (2021-05-17)</a><ul>
1453<li class="toctree-l3"><a class="reference internal" href="../change-log.html#id3">New Features</a></li>
1454<li class="toctree-l3"><a class="reference internal" href="../change-log.html#changed">Changed</a></li>
1455<li class="toctree-l3"><a class="reference internal" href="../change-log.html#id4">Resolved Issues</a></li>
1456</ul>
1457</li>
1458<li class="toctree-l2"><a class="reference internal" href="../change-log.html#id5">2.4.0 (2020-11-17)</a><ul>
1459<li class="toctree-l3"><a class="reference internal" href="../change-log.html#id6">New Features</a></li>
1460<li class="toctree-l3"><a class="reference internal" href="../change-log.html#id7">Changed</a></li>
1461<li class="toctree-l3"><a class="reference internal" href="../change-log.html#id8">Resolved Issues</a></li>
1462<li class="toctree-l3"><a class="reference internal" href="../change-log.html#known-issues">Known Issues</a></li>
1463</ul>
1464</li>
1465<li class="toctree-l2"><a class="reference internal" href="../change-log.html#id9">2.3 (2020-04-20)</a><ul>
1466<li class="toctree-l3"><a class="reference internal" href="../change-log.html#id10">New Features</a></li>
1467<li class="toctree-l3"><a class="reference internal" href="../change-log.html#id11">Changed</a></li>
1468<li class="toctree-l3"><a class="reference internal" href="../change-log.html#id12">Resolved Issues</a></li>
1469<li class="toctree-l3"><a class="reference internal" href="../change-log.html#id13">Known Issues</a></li>
1470</ul>
1471</li>
1472<li class="toctree-l2"><a class="reference internal" href="../change-log.html#id14">2.2 (2019-10-22)</a><ul>
1473<li class="toctree-l3"><a class="reference internal" href="../change-log.html#id15">New Features</a></li>
1474<li class="toctree-l3"><a class="reference internal" href="../change-log.html#id16">Changed</a></li>
1475<li class="toctree-l3"><a class="reference internal" href="../change-log.html#id17">Resolved Issues</a></li>
1476<li class="toctree-l3"><a class="reference internal" href="../change-log.html#deprecations">Deprecations</a></li>
1477<li class="toctree-l3"><a class="reference internal" href="../change-log.html#id18">Known Issues</a></li>
1478</ul>
1479</li>
1480<li class="toctree-l2"><a class="reference internal" href="../change-log.html#id19">2.1 (2019-03-29)</a><ul>
1481<li class="toctree-l3"><a class="reference internal" href="../change-log.html#id20">New Features</a></li>
1482<li class="toctree-l3"><a class="reference internal" href="../change-log.html#id21">Changed</a></li>
1483<li class="toctree-l3"><a class="reference internal" href="../change-log.html#id22">Resolved Issues</a></li>
1484<li class="toctree-l3"><a class="reference internal" href="../change-log.html#id23">Deprecations</a></li>
1485<li class="toctree-l3"><a class="reference internal" href="../change-log.html#id24">Known Issues</a></li>
1486</ul>
1487</li>
1488<li class="toctree-l2"><a class="reference internal" href="../change-log.html#id25">2.0 (2018-10-02)</a><ul>
1489<li class="toctree-l3"><a class="reference internal" href="../change-log.html#id26">New Features</a></li>
1490<li class="toctree-l3"><a class="reference internal" href="../change-log.html#issues-resolved-since-last-release">Issues resolved since last release</a></li>
1491<li class="toctree-l3"><a class="reference internal" href="../change-log.html#id27">Known Issues</a></li>
1492</ul>
1493</li>
1494<li class="toctree-l2"><a class="reference internal" href="../change-log.html#id28">1.6 (2018-09-21)</a><ul>
1495<li class="toctree-l3"><a class="reference internal" href="../change-log.html#id29">New Features</a></li>
1496<li class="toctree-l3"><a class="reference internal" href="../change-log.html#id30">Issues resolved since last release</a></li>
1497<li class="toctree-l3"><a class="reference internal" href="../change-log.html#id31">Known Issues</a></li>
1498</ul>
1499</li>
1500<li class="toctree-l2"><a class="reference internal" href="../change-log.html#id32">1.5 (2018-03-20)</a><ul>
1501<li class="toctree-l3"><a class="reference internal" href="../change-log.html#id33">New features</a></li>
1502<li class="toctree-l3"><a class="reference internal" href="../change-log.html#id34">Issues resolved since last release</a></li>
1503<li class="toctree-l3"><a class="reference internal" href="../change-log.html#id35">Known Issues</a></li>
1504</ul>
1505</li>
1506<li class="toctree-l2"><a class="reference internal" href="../change-log.html#id36">1.4 (2017-07-07)</a><ul>
1507<li class="toctree-l3"><a class="reference internal" href="../change-log.html#id37">New features</a></li>
1508<li class="toctree-l3"><a class="reference internal" href="../change-log.html#id38">Issues resolved since last release</a></li>
1509<li class="toctree-l3"><a class="reference internal" href="../change-log.html#id39">Known Issues</a></li>
1510</ul>
1511</li>
1512<li class="toctree-l2"><a class="reference internal" href="../change-log.html#id40">1.3 (2016-10-13)</a><ul>
1513<li class="toctree-l3"><a class="reference internal" href="../change-log.html#id41">New features</a></li>
1514<li class="toctree-l3"><a class="reference internal" href="../change-log.html#id42">Issues resolved since last release</a></li>
1515<li class="toctree-l3"><a class="reference internal" href="../change-log.html#id43">Known issues</a></li>
1516</ul>
1517</li>
1518<li class="toctree-l2"><a class="reference internal" href="../change-log.html#id44">1.2 (2015-12-22)</a><ul>
1519<li class="toctree-l3"><a class="reference internal" href="../change-log.html#id45">New features</a></li>
1520<li class="toctree-l3"><a class="reference internal" href="../change-log.html#id46">Issues resolved since last release</a></li>
1521<li class="toctree-l3"><a class="reference internal" href="../change-log.html#id47">Known issues</a></li>
1522</ul>
1523</li>
1524<li class="toctree-l2"><a class="reference internal" href="../change-log.html#id48">1.1 (2015-02-04)</a><ul>
1525<li class="toctree-l3"><a class="reference internal" href="../change-log.html#id49">New features</a></li>
1526<li class="toctree-l3"><a class="reference internal" href="../change-log.html#id50">Issues resolved since last release</a></li>
1527<li class="toctree-l3"><a class="reference internal" href="../change-log.html#id51">Known issues</a></li>
1528</ul>
1529</li>
1530<li class="toctree-l2"><a class="reference internal" href="../change-log.html#id52">1.0 (2014-08-28)</a><ul>
1531<li class="toctree-l3"><a class="reference internal" href="../change-log.html#id53">New features</a></li>
1532<li class="toctree-l3"><a class="reference internal" href="../change-log.html#id54">Issues resolved since last release</a></li>
1533<li class="toctree-l3"><a class="reference internal" href="../change-log.html#id55">Known issues</a></li>
1534</ul>
1535</li>
1536<li class="toctree-l2"><a class="reference internal" href="../change-log.html#id56">0.4 (2014-06-03)</a><ul>
1537<li class="toctree-l3"><a class="reference internal" href="../change-log.html#id57">New features</a></li>
1538<li class="toctree-l3"><a class="reference internal" href="../change-log.html#id58">Issues resolved since last release</a></li>
1539<li class="toctree-l3"><a class="reference internal" href="../change-log.html#id59">Known issues</a></li>
1540</ul>
1541</li>
1542<li class="toctree-l2"><a class="reference internal" href="../change-log.html#id60">0.3 (2014-02-28)</a><ul>
1543<li class="toctree-l3"><a class="reference internal" href="../change-log.html#id61">New features</a></li>
1544<li class="toctree-l3"><a class="reference internal" href="../change-log.html#id62">Issues resolved since last release</a></li>
1545<li class="toctree-l3"><a class="reference internal" href="../change-log.html#id63">Known issues</a></li>
1546</ul>
1547</li>
1548<li class="toctree-l2"><a class="reference internal" href="../change-log.html#id64">0.2 (2013-10-25)</a><ul>
1549<li class="toctree-l3"><a class="reference internal" href="../change-log.html#id65">New features</a></li>
1550<li class="toctree-l3"><a class="reference internal" href="../change-log.html#id66">Issues resolved since last release</a></li>
1551<li class="toctree-l3"><a class="reference internal" href="../change-log.html#id67">Known issues</a></li>
1552</ul>
1553</li>
1554</ul>
1555</li>
1556<li class="toctree-l1"><a class="reference internal" href="../glossary.html">Glossary</a></li>
1557<li class="toctree-l1"><a class="reference internal" href="../license.html">License</a><ul>
1558<li class="toctree-l2"><a class="reference internal" href="../license.html#spdx-identifiers">SPDX Identifiers</a></li>
1559<li class="toctree-l2"><a class="reference internal" href="../license.html#other-projects">Other Projects</a></li>
1560</ul>
1561</li>
1562</ul>
1563
1564        </div>
1565      </div>
1566    </nav>
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1568    <section data-toggle="wy-nav-shift" class="wy-nav-content-wrap"><nav class="wy-nav-top" aria-label="Mobile navigation menu" >
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1579      <li><span class="section-number">5. </span>Interrupt Management Framework</li>
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1591
1592  <div class="section" id="interrupt-management-framework">
1593<h1><span class="section-number">5. </span>Interrupt Management Framework<a class="headerlink" href="#interrupt-management-framework" title="Permalink to this headline"></a></h1>
1594<p>This framework is responsible for managing interrupts routed to EL3. It also
1595allows EL3 software to configure the interrupt routing behavior. Its main
1596objective is to implement the following two requirements.</p>
1597<ol class="arabic simple">
1598<li><p>It should be possible to route interrupts meant to be handled by secure
1599software (Secure interrupts) to EL3, when execution is in non-secure state
1600(normal world). The framework should then take care of handing control of
1601the interrupt to either software in EL3 or Secure-EL1 depending upon the
1602software configuration and the GIC implementation. This requirement ensures
1603that secure interrupts are under the control of the secure software with
1604respect to their delivery and handling without the possibility of
1605intervention from non-secure software.</p></li>
1606<li><p>It should be possible to route interrupts meant to be handled by
1607non-secure software (Non-secure interrupts) to the last executed exception
1608level in the normal world when the execution is in secure world at
1609exception levels lower than EL3. This could be done with or without the
1610knowledge of software executing in Secure-EL1/Secure-EL0. The choice of
1611approach should be governed by the secure software. This requirement
1612ensures that non-secure software is able to execute in tandem with the
1613secure software without overriding it.</p></li>
1614</ol>
1615<div class="section" id="concepts">
1616<h2><span class="section-number">5.1. </span>Concepts<a class="headerlink" href="#concepts" title="Permalink to this headline"></a></h2>
1617<div class="section" id="interrupt-types">
1618<h3><span class="section-number">5.1.1. </span>Interrupt types<a class="headerlink" href="#interrupt-types" title="Permalink to this headline"></a></h3>
1619<p>The framework categorises an interrupt to be one of the following depending upon
1620the exception level(s) it is handled in.</p>
1621<ol class="arabic simple">
1622<li><p>Secure EL1 interrupt. This type of interrupt can be routed to EL3 or
1623Secure-EL1 depending upon the security state of the current execution
1624context. It is always handled in Secure-EL1.</p></li>
1625<li><p>Non-secure interrupt. This type of interrupt can be routed to EL3,
1626Secure-EL1, Non-secure EL1 or EL2 depending upon the security state of the
1627current execution context. It is always handled in either Non-secure EL1
1628or EL2.</p></li>
1629<li><p>EL3 interrupt. This type of interrupt can be routed to EL3 or Secure-EL1
1630depending upon the security state of the current execution context. It is
1631always handled in EL3.</p></li>
1632</ol>
1633<p>The following constants define the various interrupt types in the framework
1634implementation.</p>
1635<div class="highlight-c notranslate"><div class="highlight"><pre><span></span><span class="cp">#define INTR_TYPE_S_EL1      0</span>
1636<span class="cp">#define INTR_TYPE_EL3        1</span>
1637<span class="cp">#define INTR_TYPE_NS         2</span>
1638</pre></div>
1639</div>
1640</div>
1641<div class="section" id="routing-model">
1642<h3><span class="section-number">5.1.2. </span>Routing model<a class="headerlink" href="#routing-model" title="Permalink to this headline"></a></h3>
1643<p>A type of interrupt can be either generated as an FIQ or an IRQ. The target
1644exception level of an interrupt type is configured through the FIQ and IRQ bits
1645in the Secure Configuration Register at EL3 (<code class="docutils literal notranslate"><span class="pre">SCR_EL3.FIQ</span></code> and <code class="docutils literal notranslate"><span class="pre">SCR_EL3.IRQ</span></code>
1646bits). When <code class="docutils literal notranslate"><span class="pre">SCR_EL3.FIQ</span></code>=1, FIQs are routed to EL3. Otherwise they are routed
1647to the First Exception Level (FEL) capable of handling interrupts. When
1648<code class="docutils literal notranslate"><span class="pre">SCR_EL3.IRQ</span></code>=1, IRQs are routed to EL3. Otherwise they are routed to the
1649FEL. This register is configured independently by EL3 software for each security
1650state prior to entry into a lower exception level in that security state.</p>
1651<p>A routing model for a type of interrupt (generated as FIQ or IRQ) is defined as
1652its target exception level for each security state. It is represented by a
1653single bit for each security state. A value of <code class="docutils literal notranslate"><span class="pre">0</span></code> means that the interrupt
1654should be routed to the FEL. A value of <code class="docutils literal notranslate"><span class="pre">1</span></code> means that the interrupt should be
1655routed to EL3. A routing model is applicable only when execution is not in EL3.</p>
1656<p>The default routing model for an interrupt type is to route it to the FEL in
1657either security state.</p>
1658</div>
1659<div class="section" id="valid-routing-models">
1660<h3><span class="section-number">5.1.3. </span>Valid routing models<a class="headerlink" href="#valid-routing-models" title="Permalink to this headline"></a></h3>
1661<p>The framework considers certain routing models for each type of interrupt to be
1662incorrect as they conflict with the requirements mentioned in Section 1. The
1663following sub-sections describe all the possible routing models and specify
1664which ones are valid or invalid. EL3 interrupts are currently supported only
1665for GIC version 3.0 (Arm GICv3) and only the Secure-EL1 and Non-secure interrupt
1666types are supported for GIC version 2.0 (Arm GICv2) (see <a class="reference internal" href="#assumptions-in-interrupt-management-framework">Assumptions in
1667Interrupt Management Framework</a>). The terminology used in the following
1668sub-sections is explained below.</p>
1669<ol class="arabic simple">
1670<li><p><strong>CSS</strong>. Current Security State. <code class="docutils literal notranslate"><span class="pre">0</span></code> when secure and <code class="docutils literal notranslate"><span class="pre">1</span></code> when non-secure</p></li>
1671<li><p><strong>TEL3</strong>. Target Exception Level 3. <code class="docutils literal notranslate"><span class="pre">0</span></code> when targeted to the FEL. <code class="docutils literal notranslate"><span class="pre">1</span></code> when
1672targeted to EL3.</p></li>
1673</ol>
1674<div class="section" id="secure-el1-interrupts">
1675<h4><span class="section-number">5.1.3.1. </span>Secure-EL1 interrupts<a class="headerlink" href="#secure-el1-interrupts" title="Permalink to this headline"></a></h4>
1676<ol class="arabic simple">
1677<li><p><strong>CSS=0, TEL3=0</strong>. Interrupt is routed to the FEL when execution is in
1678secure state. This is a valid routing model as secure software is in
1679control of handling secure interrupts.</p></li>
1680<li><p><strong>CSS=0, TEL3=1</strong>. Interrupt is routed to EL3 when execution is in secure
1681state. This is a valid routing model as secure software in EL3 can
1682handover the interrupt to Secure-EL1 for handling.</p></li>
1683<li><p><strong>CSS=1, TEL3=0</strong>. Interrupt is routed to the FEL when execution is in
1684non-secure state. This is an invalid routing model as a secure interrupt
1685is not visible to the secure software which violates the motivation behind
1686the Arm Security Extensions.</p></li>
1687<li><p><strong>CSS=1, TEL3=1</strong>. Interrupt is routed to EL3 when execution is in
1688non-secure state. This is a valid routing model as secure software in EL3
1689can handover the interrupt to Secure-EL1 for handling.</p></li>
1690</ol>
1691</div>
1692<div class="section" id="non-secure-interrupts">
1693<h4><span class="section-number">5.1.3.2. </span>Non-secure interrupts<a class="headerlink" href="#non-secure-interrupts" title="Permalink to this headline"></a></h4>
1694<ol class="arabic simple">
1695<li><p><strong>CSS=0, TEL3=0</strong>. Interrupt is routed to the FEL when execution is in
1696secure state. This allows the secure software to trap non-secure
1697interrupts, perform its book-keeping and hand the interrupt to the
1698non-secure software through EL3. This is a valid routing model as secure
1699software is in control of how its execution is preempted by non-secure
1700interrupts.</p></li>
1701<li><p><strong>CSS=0, TEL3=1</strong>. Interrupt is routed to EL3 when execution is in secure
1702state. This is a valid routing model as secure software in EL3 can save
1703the state of software in Secure-EL1/Secure-EL0 before handing the
1704interrupt to non-secure software. This model requires additional
1705coordination between Secure-EL1 and EL3 software to ensure that the
1706former’s state is correctly saved by the latter.</p></li>
1707<li><p><strong>CSS=1, TEL3=0</strong>. Interrupt is routed to FEL when execution is in
1708non-secure state. This is a valid routing model as a non-secure interrupt
1709is handled by non-secure software.</p></li>
1710<li><p><strong>CSS=1, TEL3=1</strong>. Interrupt is routed to EL3 when execution is in
1711non-secure state. This is an invalid routing model as there is no valid
1712reason to route the interrupt to EL3 software and then hand it back to
1713non-secure software for handling.</p></li>
1714</ol>
1715</div>
1716<div class="section" id="el3-interrupts">
1717<span id="id1"></span><h4><span class="section-number">5.1.3.3. </span>EL3 interrupts<a class="headerlink" href="#el3-interrupts" title="Permalink to this headline"></a></h4>
1718<ol class="arabic">
1719<li><p><strong>CSS=0, TEL3=0</strong>. Interrupt is routed to the FEL when execution is in
1720Secure-EL1/Secure-EL0. This is a valid routing model as secure software
1721in Secure-EL1/Secure-EL0 is in control of how its execution is preempted
1722by EL3 interrupt and can handover the interrupt to EL3 for handling.</p>
1723<p>However, when <code class="docutils literal notranslate"><span class="pre">EL3_EXCEPTION_HANDLING</span></code> is <code class="docutils literal notranslate"><span class="pre">1</span></code>, this routing model is
1724invalid as EL3 interrupts are unconditionally routed to EL3, and EL3
1725interrupts will always preempt Secure EL1/EL0 execution. See <a class="reference internal" href="../components/exception-handling.html#interrupt-handling"><span class="std std-ref">exception
1726handling</span></a> documentation.</p>
1727</li>
1728<li><p><strong>CSS=0, TEL3=1</strong>. Interrupt is routed to EL3 when execution is in
1729Secure-EL1/Secure-EL0. This is a valid routing model as secure software
1730in EL3 can handle the interrupt.</p></li>
1731<li><p><strong>CSS=1, TEL3=0</strong>. Interrupt is routed to the FEL when execution is in
1732non-secure state. This is an invalid routing model as a secure interrupt
1733is not visible to the secure software which violates the motivation behind
1734the Arm Security Extensions.</p></li>
1735<li><p><strong>CSS=1, TEL3=1</strong>. Interrupt is routed to EL3 when execution is in
1736non-secure state. This is a valid routing model as secure software in EL3
1737can handle the interrupt.</p></li>
1738</ol>
1739</div>
1740</div>
1741<div class="section" id="mapping-of-interrupt-type-to-signal">
1742<h3><span class="section-number">5.1.4. </span>Mapping of interrupt type to signal<a class="headerlink" href="#mapping-of-interrupt-type-to-signal" title="Permalink to this headline"></a></h3>
1743<p>The framework is meant to work with any interrupt controller implemented by a
1744platform. A interrupt controller could generate a type of interrupt as either an
1745FIQ or IRQ signal to the CPU depending upon the current security state. The
1746mapping between the type and signal is known only to the platform. The framework
1747uses this information to determine whether the IRQ or the FIQ bit should be
1748programmed in <code class="docutils literal notranslate"><span class="pre">SCR_EL3</span></code> while applying the routing model for a type of
1749interrupt. The platform provides this information through the
1750<code class="docutils literal notranslate"><span class="pre">plat_interrupt_type_to_line()</span></code> API (described in the
1751<a class="reference internal" href="../getting_started/porting-guide.html#porting-guide"><span class="std std-ref">Porting Guide</span></a>). For example, on the FVP port when the platform uses an
1752Arm GICv2 interrupt controller, Secure-EL1 interrupts are signaled through the
1753FIQ signal while Non-secure interrupts are signaled through the IRQ signal.
1754This applies when execution is in either security state.</p>
1755<div class="section" id="effect-of-mapping-of-several-interrupt-types-to-one-signal">
1756<h4><span class="section-number">5.1.4.1. </span>Effect of mapping of several interrupt types to one signal<a class="headerlink" href="#effect-of-mapping-of-several-interrupt-types-to-one-signal" title="Permalink to this headline"></a></h4>
1757<p>It should be noted that if more than one interrupt type maps to a single
1758interrupt signal, and if any one of the interrupt type sets <strong>TEL3=1</strong> for a
1759particular security state, then interrupt signal will be routed to EL3 when in
1760that security state. This means that all the other interrupt types using the
1761same interrupt signal will be forced to the same routing model. This should be
1762borne in mind when choosing the routing model for an interrupt type.</p>
1763<p>For example, in Arm GICv3, when the execution context is Secure-EL1/
1764Secure-EL0, both the EL3 and the non secure interrupt types map to the FIQ
1765signal. So if either one of the interrupt type sets the routing model so
1766that <strong>TEL3=1</strong> when <strong>CSS=0</strong>, the FIQ bit in <code class="docutils literal notranslate"><span class="pre">SCR_EL3</span></code> will be programmed to
1767route the FIQ signal to EL3 when executing in Secure-EL1/Secure-EL0, thereby
1768effectively routing the other interrupt type also to EL3.</p>
1769</div>
1770</div>
1771</div>
1772<div class="section" id="assumptions-in-interrupt-management-framework">
1773<h2><span class="section-number">5.2. </span>Assumptions in Interrupt Management Framework<a class="headerlink" href="#assumptions-in-interrupt-management-framework" title="Permalink to this headline"></a></h2>
1774<p>The framework makes the following assumptions to simplify its implementation.</p>
1775<ol class="arabic simple">
1776<li><p>Although the framework has support for 2 types of secure interrupts (EL3
1777and Secure-EL1 interrupt), only interrupt controller architectures
1778like Arm GICv3 has architectural support for EL3 interrupts in the form of
1779Group 0 interrupts. In Arm GICv2, all secure interrupts are assumed to be
1780handled in Secure-EL1. They can be delivered to Secure-EL1 via EL3 but they
1781cannot be handled in EL3.</p></li>
1782<li><p>Interrupt exceptions (<code class="docutils literal notranslate"><span class="pre">PSTATE.I</span></code> and <code class="docutils literal notranslate"><span class="pre">F</span></code> bits) are masked during execution
1783in EL3.</p></li>
1784<li><p>Interrupt management: the following sections describe how interrupts are
1785managed by the interrupt handling framework. This entails:</p>
1786<ol class="arabic simple">
1787<li><p>Providing an interface to allow registration of a handler and
1788specification of the routing model for a type of interrupt.</p></li>
1789<li><p>Implementing support to hand control of an interrupt type to its
1790registered handler when the interrupt is generated.</p></li>
1791</ol>
1792</li>
1793</ol>
1794<p>Both aspects of interrupt management involve various components in the secure
1795software stack spanning from EL3 to Secure-EL1. These components are described
1796in the section <a class="reference internal" href="#software-components">Software components</a>. The framework stores information
1797associated with each type of interrupt in the following data structure.</p>
1798<div class="highlight-c notranslate"><div class="highlight"><pre><span></span><span class="k">typedef</span><span class="w"> </span><span class="k">struct</span> <span class="nc">intr_type_desc</span><span class="w"> </span><span class="p">{</span><span class="w"></span>
1799<span class="w">        </span><span class="n">interrupt_type_handler_t</span><span class="w"> </span><span class="n">handler</span><span class="p">;</span><span class="w"></span>
1800<span class="w">        </span><span class="kt">uint32_t</span><span class="w"> </span><span class="n">flags</span><span class="p">;</span><span class="w"></span>
1801<span class="w">        </span><span class="kt">uint32_t</span><span class="w"> </span><span class="n">scr_el3</span><span class="p">[</span><span class="mi">2</span><span class="p">];</span><span class="w"></span>
1802<span class="p">}</span><span class="w"> </span><span class="n">intr_type_desc_t</span><span class="p">;</span><span class="w"></span>
1803</pre></div>
1804</div>
1805<p>The <code class="docutils literal notranslate"><span class="pre">flags</span></code> field stores the routing model for the interrupt type in
1806bits[1:0]. Bit[0] stores the routing model when execution is in the secure
1807state. Bit[1] stores the routing model when execution is in the non-secure
1808state. As mentioned in Section <a class="reference internal" href="#routing-model">Routing model</a>, a value of <code class="docutils literal notranslate"><span class="pre">0</span></code> implies that
1809the interrupt should be targeted to the FEL. A value of <code class="docutils literal notranslate"><span class="pre">1</span></code> implies that it
1810should be targeted to EL3. The remaining bits are reserved and SBZ. The helper
1811macro <code class="docutils literal notranslate"><span class="pre">set_interrupt_rm_flag()</span></code> should be used to set the bits in the
1812<code class="docutils literal notranslate"><span class="pre">flags</span></code> parameter.</p>
1813<p>The <code class="docutils literal notranslate"><span class="pre">scr_el3[2]</span></code> field also stores the routing model but as a mapping of the
1814model in the <code class="docutils literal notranslate"><span class="pre">flags</span></code> field to the corresponding bit in the <code class="docutils literal notranslate"><span class="pre">SCR_EL3</span></code> for each
1815security state.</p>
1816<p>The framework also depends upon the platform port to configure the interrupt
1817controller to distinguish between secure and non-secure interrupts. The platform
1818is expected to be aware of the secure devices present in the system and their
1819associated interrupt numbers. It should configure the interrupt controller to
1820enable the secure interrupts, ensure that their priority is always higher than
1821the non-secure interrupts and target them to the primary CPU. It should also
1822export the interface described in the <a class="reference internal" href="../getting_started/porting-guide.html#porting-guide"><span class="std std-ref">Porting Guide</span></a> to enable
1823handling of interrupts.</p>
1824<p>In the remainder of this document, for the sake of simplicity a Arm GICv2 system
1825is considered and it is assumed that the FIQ signal is used to generate Secure-EL1
1826interrupts and the IRQ signal is used to generate non-secure interrupts in either
1827security state. EL3 interrupts are not considered.</p>
1828</div>
1829<div class="section" id="software-components">
1830<h2><span class="section-number">5.3. </span>Software components<a class="headerlink" href="#software-components" title="Permalink to this headline"></a></h2>
1831<p>Roles and responsibilities for interrupt management are sub-divided between the
1832following components of software running in EL3 and Secure-EL1. Each component is
1833briefly described below.</p>
1834<ol class="arabic">
1835<li><p>EL3 Runtime Firmware. This component is common to all ports of TF-A.</p></li>
1836<li><p>Secure Payload Dispatcher (SPD) service. This service interfaces with the
1837Secure Payload (SP) software which runs in Secure-EL1/Secure-EL0 and is
1838responsible for switching execution between secure and non-secure states.
1839A switch is triggered by a Secure Monitor Call and it uses the APIs
1840exported by the Context management library to implement this functionality.
1841Switching execution between the two security states is a requirement for
1842interrupt management as well. This results in a significant dependency on
1843the SPD service. TF-A implements an example Test Secure Payload Dispatcher
1844(TSPD) service.</p>
1845<p>An SPD service plugs into the EL3 runtime firmware and could be common to
1846some ports of TF-A.</p>
1847</li>
1848<li><p>Secure Payload (SP). On a production system, the Secure Payload corresponds
1849to a Secure OS which runs in Secure-EL1/Secure-EL0. It interfaces with the
1850SPD service to manage communication with non-secure software. TF-A
1851implements an example secure payload called Test Secure Payload (TSP)
1852which runs only in Secure-EL1.</p>
1853<p>A Secure payload implementation could be common to some ports of TF-A,
1854just like the SPD service.</p>
1855</li>
1856</ol>
1857</div>
1858<div class="section" id="interrupt-registration">
1859<h2><span class="section-number">5.4. </span>Interrupt registration<a class="headerlink" href="#interrupt-registration" title="Permalink to this headline"></a></h2>
1860<p>This section describes in detail the role of each software component (see
1861<a class="reference internal" href="#software-components">Software components</a>) during the registration of a handler for an interrupt
1862type.</p>
1863<div class="section" id="el3-runtime-firmware">
1864<span id="id2"></span><h3><span class="section-number">5.4.1. </span>EL3 runtime firmware<a class="headerlink" href="#el3-runtime-firmware" title="Permalink to this headline"></a></h3>
1865<p>This component declares the following prototype for a handler of an interrupt type.</p>
1866<div class="highlight-c notranslate"><div class="highlight"><pre><span></span><span class="k">typedef</span><span class="w"> </span><span class="kt">uint64_t</span><span class="w"> </span><span class="p">(</span><span class="o">*</span><span class="n">interrupt_type_handler_t</span><span class="p">)(</span><span class="kt">uint32_t</span><span class="w"> </span><span class="n">id</span><span class="p">,</span><span class="w"></span>
1867<span class="w">                                             </span><span class="kt">uint32_t</span><span class="w"> </span><span class="n">flags</span><span class="p">,</span><span class="w"></span>
1868<span class="w">                                             </span><span class="kt">void</span><span class="w"> </span><span class="o">*</span><span class="n">handle</span><span class="p">,</span><span class="w"></span>
1869<span class="w">                                             </span><span class="kt">void</span><span class="w"> </span><span class="o">*</span><span class="n">cookie</span><span class="p">);</span><span class="w"></span>
1870</pre></div>
1871</div>
1872<p>The <code class="docutils literal notranslate"><span class="pre">id</span></code> is parameter is reserved and could be used in the future for passing
1873the interrupt id of the highest pending interrupt only if there is a foolproof
1874way of determining the id. Currently it contains <code class="docutils literal notranslate"><span class="pre">INTR_ID_UNAVAILABLE</span></code>.</p>
1875<p>The <code class="docutils literal notranslate"><span class="pre">flags</span></code> parameter contains miscellaneous information as follows.</p>
1876<ol class="arabic simple">
1877<li><p>Security state, bit[0]. This bit indicates the security state of the lower
1878exception level when the interrupt was generated. A value of <code class="docutils literal notranslate"><span class="pre">1</span></code> means
1879that it was in the non-secure state. A value of <code class="docutils literal notranslate"><span class="pre">0</span></code> indicates that it was
1880in the secure state. This bit can be used by the handler to ensure that
1881interrupt was generated and routed as per the routing model specified
1882during registration.</p></li>
1883<li><p>Reserved, bits[31:1]. The remaining bits are reserved for future use.</p></li>
1884</ol>
1885<p>The <code class="docutils literal notranslate"><span class="pre">handle</span></code> parameter points to the <code class="docutils literal notranslate"><span class="pre">cpu_context</span></code> structure of the current CPU
1886for the security state specified in the <code class="docutils literal notranslate"><span class="pre">flags</span></code> parameter.</p>
1887<p>Once the handler routine completes, execution will return to either the secure
1888or non-secure state. The handler routine must return a pointer to
1889<code class="docutils literal notranslate"><span class="pre">cpu_context</span></code> structure of the current CPU for the target security state. On
1890AArch64, this return value is currently ignored by the caller as the
1891appropriate <code class="docutils literal notranslate"><span class="pre">cpu_context</span></code> to be used is expected to be set by the handler
1892via the context management library APIs.
1893A portable interrupt handler implementation must set the target context both in
1894the structure pointed to by the returned pointer and via the context management
1895library APIs. The handler should treat all error conditions as critical errors
1896and take appropriate action within its implementation e.g. use assertion
1897failures.</p>
1898<p>The runtime firmware provides the following API for registering a handler for a
1899particular type of interrupt. A Secure Payload Dispatcher service should use
1900this API to register a handler for Secure-EL1 and optionally for non-secure
1901interrupts. This API also requires the caller to specify the routing model for
1902the type of interrupt.</p>
1903<div class="highlight-c notranslate"><div class="highlight"><pre><span></span><span class="kt">int32_t</span><span class="w"> </span><span class="nf">register_interrupt_type_handler</span><span class="p">(</span><span class="kt">uint32_t</span><span class="w"> </span><span class="n">type</span><span class="p">,</span><span class="w"></span>
1904<span class="w">                                        </span><span class="n">interrupt_type_handler</span><span class="w"> </span><span class="n">handler</span><span class="p">,</span><span class="w"></span>
1905<span class="w">                                        </span><span class="kt">uint64_t</span><span class="w"> </span><span class="n">flags</span><span class="p">);</span><span class="w"></span>
1906</pre></div>
1907</div>
1908<p>The <code class="docutils literal notranslate"><span class="pre">type</span></code> parameter can be one of the three interrupt types listed above i.e.
1909<code class="docutils literal notranslate"><span class="pre">INTR_TYPE_S_EL1</span></code>, <code class="docutils literal notranslate"><span class="pre">INTR_TYPE_NS</span></code> &amp; <code class="docutils literal notranslate"><span class="pre">INTR_TYPE_EL3</span></code>. The <code class="docutils literal notranslate"><span class="pre">flags</span></code> parameter
1910is as described in Section 2.</p>
1911<p>The function will return <code class="docutils literal notranslate"><span class="pre">0</span></code> upon a successful registration. It will return
1912<code class="docutils literal notranslate"><span class="pre">-EALREADY</span></code> in case a handler for the interrupt type has already been
1913registered. If the <code class="docutils literal notranslate"><span class="pre">type</span></code> is unrecognised or the <code class="docutils literal notranslate"><span class="pre">flags</span></code> or the <code class="docutils literal notranslate"><span class="pre">handler</span></code> are
1914invalid it will return <code class="docutils literal notranslate"><span class="pre">-EINVAL</span></code>.</p>
1915<p>Interrupt routing is governed by the configuration of the <code class="docutils literal notranslate"><span class="pre">SCR_EL3.FIQ/IRQ</span></code> bits
1916prior to entry into a lower exception level in either security state. The
1917context management library maintains a copy of the <code class="docutils literal notranslate"><span class="pre">SCR_EL3</span></code> system register for
1918each security state in the <code class="docutils literal notranslate"><span class="pre">cpu_context</span></code> structure of each CPU. It exports the
1919following APIs to let EL3 Runtime Firmware program and retrieve the routing
1920model for each security state for the current CPU. The value of <code class="docutils literal notranslate"><span class="pre">SCR_EL3</span></code> stored
1921in the <code class="docutils literal notranslate"><span class="pre">cpu_context</span></code> is used by the <code class="docutils literal notranslate"><span class="pre">el3_exit()</span></code> function to program the
1922<code class="docutils literal notranslate"><span class="pre">SCR_EL3</span></code> register prior to returning from the EL3 exception level.</p>
1923<div class="highlight-c notranslate"><div class="highlight"><pre><span></span><span class="kt">uint32_t</span><span class="w"> </span><span class="nf">cm_get_scr_el3</span><span class="p">(</span><span class="kt">uint32_t</span><span class="w"> </span><span class="n">security_state</span><span class="p">);</span><span class="w"></span>
1924<span class="kt">void</span><span class="w"> </span><span class="nf">cm_write_scr_el3_bit</span><span class="p">(</span><span class="kt">uint32_t</span><span class="w"> </span><span class="n">security_state</span><span class="p">,</span><span class="w"></span>
1925<span class="w">                          </span><span class="kt">uint32_t</span><span class="w"> </span><span class="n">bit_pos</span><span class="p">,</span><span class="w"></span>
1926<span class="w">                          </span><span class="kt">uint32_t</span><span class="w"> </span><span class="n">value</span><span class="p">);</span><span class="w"></span>
1927</pre></div>
1928</div>
1929<p><code class="docutils literal notranslate"><span class="pre">cm_get_scr_el3()</span></code> returns the value of the <code class="docutils literal notranslate"><span class="pre">SCR_EL3</span></code> register for the specified
1930security state of the current CPU. <code class="docutils literal notranslate"><span class="pre">cm_write_scr_el3_bit()</span></code> writes a <code class="docutils literal notranslate"><span class="pre">0</span></code> or <code class="docutils literal notranslate"><span class="pre">1</span></code>
1931to the bit specified by <code class="docutils literal notranslate"><span class="pre">bit_pos</span></code>. <code class="docutils literal notranslate"><span class="pre">register_interrupt_type_handler()</span></code> invokes
1932<code class="docutils literal notranslate"><span class="pre">set_routing_model()</span></code> API which programs the <code class="docutils literal notranslate"><span class="pre">SCR_EL3</span></code> according to the routing
1933model using the <code class="docutils literal notranslate"><span class="pre">cm_get_scr_el3()</span></code> and <code class="docutils literal notranslate"><span class="pre">cm_write_scr_el3_bit()</span></code> APIs.</p>
1934<p>It is worth noting that in the current implementation of the framework, the EL3
1935runtime firmware is responsible for programming the routing model. The SPD is
1936responsible for ensuring that the routing model has been adhered to upon
1937receiving an interrupt.</p>
1938</div>
1939<div class="section" id="secure-payload-dispatcher">
1940<span id="spd-int-registration"></span><h3><span class="section-number">5.4.2. </span>Secure payload dispatcher<a class="headerlink" href="#secure-payload-dispatcher" title="Permalink to this headline"></a></h3>
1941<p>A SPD service is responsible for determining and maintaining the interrupt
1942routing model supported by itself and the Secure Payload. It is also responsible
1943for ferrying interrupts between secure and non-secure software depending upon
1944the routing model. It could determine the routing model at build time or at
1945runtime. It must use this information to register a handler for each interrupt
1946type using the <code class="docutils literal notranslate"><span class="pre">register_interrupt_type_handler()</span></code> API in EL3 runtime firmware.</p>
1947<p>If the routing model is not known to the SPD service at build time, then it must
1948be provided by the SP as the result of its initialisation. The SPD should
1949program the routing model only after SP initialisation has completed e.g. in the
1950SPD initialisation function pointed to by the <code class="docutils literal notranslate"><span class="pre">bl32_init</span></code> variable.</p>
1951<p>The SPD should determine the mechanism to pass control to the Secure Payload
1952after receiving an interrupt from the EL3 runtime firmware. This information
1953could either be provided to the SPD service at build time or by the SP at
1954runtime.</p>
1955</div>
1956<div class="section" id="test-secure-payload-dispatcher-behavior">
1957<h3><span class="section-number">5.4.3. </span>Test secure payload dispatcher behavior<a class="headerlink" href="#test-secure-payload-dispatcher-behavior" title="Permalink to this headline"></a></h3>
1958<div class="admonition note">
1959<p class="admonition-title">Note</p>
1960<p>Where this document discusses <code class="docutils literal notranslate"><span class="pre">TSP_NS_INTR_ASYNC_PREEMPT</span></code> as being
1961<code class="docutils literal notranslate"><span class="pre">1</span></code>, the same results also apply when <code class="docutils literal notranslate"><span class="pre">EL3_EXCEPTION_HANDLING</span></code> is <code class="docutils literal notranslate"><span class="pre">1</span></code>.</p>
1962</div>
1963<p>The TSPD only handles Secure-EL1 interrupts and is provided with the following
1964routing model at build time.</p>
1965<ul class="simple">
1966<li><p>Secure-EL1 interrupts are routed to EL3 when execution is in non-secure
1967state and are routed to the FEL when execution is in the secure state
1968i.e <strong>CSS=0, TEL3=0</strong> &amp; <strong>CSS=1, TEL3=1</strong> for Secure-EL1 interrupts</p></li>
1969<li><p>When the build flag <code class="docutils literal notranslate"><span class="pre">TSP_NS_INTR_ASYNC_PREEMPT</span></code> is zero, the default routing
1970model is used for non-secure interrupts. They are routed to the FEL in
1971either security state i.e <strong>CSS=0, TEL3=0</strong> &amp; <strong>CSS=1, TEL3=0</strong> for
1972Non-secure interrupts.</p></li>
1973<li><p>When the build flag <code class="docutils literal notranslate"><span class="pre">TSP_NS_INTR_ASYNC_PREEMPT</span></code> is defined to 1, then the
1974non secure interrupts are routed to EL3 when execution is in secure state
1975i.e <strong>CSS=0, TEL3=1</strong> for non-secure interrupts. This effectively preempts
1976Secure-EL1. The default routing model is used for non secure interrupts in
1977non-secure state. i.e <strong>CSS=1, TEL3=0</strong>.</p></li>
1978</ul>
1979<p>It performs the following actions in the <code class="docutils literal notranslate"><span class="pre">tspd_init()</span></code> function to fulfill the
1980requirements mentioned earlier.</p>
1981<ol class="arabic">
1982<li><p>It passes control to the Test Secure Payload to perform its
1983initialisation. The TSP provides the address of the vector table
1984<code class="docutils literal notranslate"><span class="pre">tsp_vectors</span></code> in the SP which also includes the handler for Secure-EL1
1985interrupts in the <code class="docutils literal notranslate"><span class="pre">sel1_intr_entry</span></code> field. The TSPD passes control to the TSP at
1986this address when it receives a Secure-EL1 interrupt.</p>
1987<p>The handover agreement between the TSP and the TSPD requires that the TSPD
1988masks all interrupts (<code class="docutils literal notranslate"><span class="pre">PSTATE.DAIF</span></code> bits) when it calls
1989<code class="docutils literal notranslate"><span class="pre">tsp_sel1_intr_entry()</span></code>. The TSP has to preserve the callee saved general
1990purpose, SP_EL1/Secure-EL0, LR, VFP and system registers. It can use
1991<code class="docutils literal notranslate"><span class="pre">x0-x18</span></code> to enable its C runtime.</p>
1992</li>
1993<li><p>The TSPD implements a handler function for Secure-EL1 interrupts. This
1994function is registered with the EL3 runtime firmware using the
1995<code class="docutils literal notranslate"><span class="pre">register_interrupt_type_handler()</span></code> API as follows</p>
1996<div class="highlight-c notranslate"><div class="highlight"><pre><span></span><span class="cm">/* Forward declaration */</span><span class="w"></span>
1997<span class="n">interrupt_type_handler</span><span class="w"> </span><span class="n">tspd_secure_el1_interrupt_handler</span><span class="p">;</span><span class="w"></span>
1998<span class="kt">int32_t</span><span class="w"> </span><span class="n">rc</span><span class="p">,</span><span class="w"> </span><span class="n">flags</span><span class="w"> </span><span class="o">=</span><span class="w"> </span><span class="mi">0</span><span class="p">;</span><span class="w"></span>
1999<span class="n">set_interrupt_rm_flag</span><span class="p">(</span><span class="n">flags</span><span class="p">,</span><span class="w"> </span><span class="n">NON_SECURE</span><span class="p">);</span><span class="w"></span>
2000<span class="n">rc</span><span class="w"> </span><span class="o">=</span><span class="w"> </span><span class="n">register_interrupt_type_handler</span><span class="p">(</span><span class="n">INTR_TYPE_S_EL1</span><span class="p">,</span><span class="w"></span>
2001<span class="w">                                 </span><span class="n">tspd_secure_el1_interrupt_handler</span><span class="p">,</span><span class="w"></span>
2002<span class="w">                                 </span><span class="n">flags</span><span class="p">);</span><span class="w"></span>
2003<span class="k">if</span><span class="w"> </span><span class="p">(</span><span class="n">rc</span><span class="p">)</span><span class="w"></span>
2004<span class="w">    </span><span class="n">panic</span><span class="p">();</span><span class="w"></span>
2005</pre></div>
2006</div>
2007</li>
2008<li><p>When the build flag <code class="docutils literal notranslate"><span class="pre">TSP_NS_INTR_ASYNC_PREEMPT</span></code> is defined to 1, the TSPD
2009implements a handler function for non-secure interrupts. This function is
2010registered with the EL3 runtime firmware using the
2011<code class="docutils literal notranslate"><span class="pre">register_interrupt_type_handler()</span></code> API as follows</p>
2012<div class="highlight-c notranslate"><div class="highlight"><pre><span></span><span class="cm">/* Forward declaration */</span><span class="w"></span>
2013<span class="n">interrupt_type_handler</span><span class="w"> </span><span class="n">tspd_ns_interrupt_handler</span><span class="p">;</span><span class="w"></span>
2014<span class="kt">int32_t</span><span class="w"> </span><span class="n">rc</span><span class="p">,</span><span class="w"> </span><span class="n">flags</span><span class="w"> </span><span class="o">=</span><span class="w"> </span><span class="mi">0</span><span class="p">;</span><span class="w"></span>
2015<span class="n">set_interrupt_rm_flag</span><span class="p">(</span><span class="n">flags</span><span class="p">,</span><span class="w"> </span><span class="n">SECURE</span><span class="p">);</span><span class="w"></span>
2016<span class="n">rc</span><span class="w"> </span><span class="o">=</span><span class="w"> </span><span class="n">register_interrupt_type_handler</span><span class="p">(</span><span class="n">INTR_TYPE_NS</span><span class="p">,</span><span class="w"></span>
2017<span class="w">                                </span><span class="n">tspd_ns_interrupt_handler</span><span class="p">,</span><span class="w"></span>
2018<span class="w">                                </span><span class="n">flags</span><span class="p">);</span><span class="w"></span>
2019<span class="k">if</span><span class="w"> </span><span class="p">(</span><span class="n">rc</span><span class="p">)</span><span class="w"></span>
2020<span class="w">    </span><span class="n">panic</span><span class="p">();</span><span class="w"></span>
2021</pre></div>
2022</div>
2023</li>
2024</ol>
2025</div>
2026<div class="section" id="secure-payload">
2027<span id="sp-int-registration"></span><h3><span class="section-number">5.4.4. </span>Secure payload<a class="headerlink" href="#secure-payload" title="Permalink to this headline"></a></h3>
2028<p>A Secure Payload must implement an interrupt handling framework at Secure-EL1
2029(Secure-EL1 IHF) to support its chosen interrupt routing model. Secure payload
2030execution will alternate between the below cases.</p>
2031<ol class="arabic simple">
2032<li><p>In the code where IRQ, FIQ or both interrupts are enabled, if an interrupt
2033type is targeted to the FEL, then it will be routed to the Secure-EL1
2034exception vector table. This is defined as the <strong>asynchronous mode</strong> of
2035handling interrupts. This mode applies to both Secure-EL1 and non-secure
2036interrupts.</p></li>
2037<li><p>In the code where both interrupts are disabled, if an interrupt type is
2038targeted to the FEL, then execution will eventually migrate to the
2039non-secure state. Any non-secure interrupts will be handled as described
2040in the routing model where <strong>CSS=1 and TEL3=0</strong>. Secure-EL1 interrupts
2041will be routed to EL3 (as per the routing model where <strong>CSS=1 and
2042TEL3=1</strong>) where the SPD service will hand them to the SP. This is defined
2043as the <strong>synchronous mode</strong> of handling interrupts.</p></li>
2044</ol>
2045<p>The interrupt handling framework implemented by the SP should support one or
2046both these interrupt handling models depending upon the chosen routing model.</p>
2047<p>The following list briefly describes how the choice of a valid routing model
2048(see <a class="reference internal" href="#valid-routing-models">Valid routing models</a>) effects the implementation of the Secure-EL1
2049IHF. If the choice of the interrupt routing model is not known to the SPD
2050service at compile time, then the SP should pass this information to the SPD
2051service at runtime during its initialisation phase.</p>
2052<p>As mentioned earlier, an Arm GICv2 system is considered and it is assumed that
2053the FIQ signal is used to generate Secure-EL1 interrupts and the IRQ signal
2054is used to generate non-secure interrupts in either security state.</p>
2055<div class="section" id="secure-payload-ihf-design-w-r-t-secure-el1-interrupts">
2056<h4><span class="section-number">5.4.4.1. </span>Secure payload IHF design w.r.t secure-EL1 interrupts<a class="headerlink" href="#secure-payload-ihf-design-w-r-t-secure-el1-interrupts" title="Permalink to this headline"></a></h4>
2057<ol class="arabic">
2058<li><p><strong>CSS=0, TEL3=0</strong>. If <code class="docutils literal notranslate"><span class="pre">PSTATE.F=0</span></code>, Secure-EL1 interrupts will be
2059triggered at one of the Secure-EL1 FIQ exception vectors. The Secure-EL1
2060IHF should implement support for handling FIQ interrupts asynchronously.</p>
2061<p>If <code class="docutils literal notranslate"><span class="pre">PSTATE.F=1</span></code> then Secure-EL1 interrupts will be handled as per the
2062synchronous interrupt handling model. The SP could implement this scenario
2063by exporting a separate entrypoint for Secure-EL1 interrupts to the SPD
2064service during the registration phase. The SPD service would also need to
2065know the state of the system, general purpose and the <code class="docutils literal notranslate"><span class="pre">PSTATE</span></code> registers
2066in which it should arrange to return execution to the SP. The SP should
2067provide this information in an implementation defined way during the
2068registration phase if it is not known to the SPD service at build time.</p>
2069</li>
2070<li><p><strong>CSS=1, TEL3=1</strong>. Interrupts are routed to EL3 when execution is in
2071non-secure state. They should be handled through the synchronous interrupt
2072handling model as described in 1. above.</p></li>
2073<li><p><strong>CSS=0, TEL3=1</strong>. Secure-EL1 interrupts are routed to EL3 when execution
2074is in secure state. They will not be visible to the SP. The <code class="docutils literal notranslate"><span class="pre">PSTATE.F</span></code> bit
2075in Secure-EL1/Secure-EL0 will not mask FIQs. The EL3 runtime firmware will
2076call the handler registered by the SPD service for Secure-EL1 interrupts.
2077Secure-EL1 IHF should then handle all Secure-EL1 interrupt through the
2078synchronous interrupt handling model described in 1. above.</p></li>
2079</ol>
2080</div>
2081<div class="section" id="secure-payload-ihf-design-w-r-t-non-secure-interrupts">
2082<h4><span class="section-number">5.4.4.2. </span>Secure payload IHF design w.r.t non-secure interrupts<a class="headerlink" href="#secure-payload-ihf-design-w-r-t-non-secure-interrupts" title="Permalink to this headline"></a></h4>
2083<ol class="arabic">
2084<li><p><strong>CSS=0, TEL3=0</strong>. If <code class="docutils literal notranslate"><span class="pre">PSTATE.I=0</span></code>, non-secure interrupts will be
2085triggered at one of the Secure-EL1 IRQ exception vectors . The Secure-EL1
2086IHF should co-ordinate with the SPD service to transfer execution to the
2087non-secure state where the interrupt should be handled e.g the SP could
2088allocate a function identifier to issue a SMC64 or SMC32 to the SPD
2089service which indicates that the SP execution has been preempted by a
2090non-secure interrupt. If this function identifier is not known to the SPD
2091service at compile time then the SP could provide it during the
2092registration phase.</p>
2093<p>If <code class="docutils literal notranslate"><span class="pre">PSTATE.I=1</span></code> then the non-secure interrupt will pend until execution
2094resumes in the non-secure state.</p>
2095</li>
2096<li><p><strong>CSS=0, TEL3=1</strong>. Non-secure interrupts are routed to EL3. They will not
2097be visible to the SP. The <code class="docutils literal notranslate"><span class="pre">PSTATE.I</span></code> bit in Secure-EL1/Secure-EL0 will
2098have not effect. The SPD service should register a non-secure interrupt
2099handler which should save the SP state correctly and resume execution in
2100the non-secure state where the interrupt will be handled. The Secure-EL1
2101IHF does not need to take any action.</p></li>
2102<li><p><strong>CSS=1, TEL3=0</strong>. Non-secure interrupts are handled in the FEL in
2103non-secure state (EL1/EL2) and are not visible to the SP. This routing
2104model does not affect the SP behavior.</p></li>
2105</ol>
2106<p>A Secure Payload must also ensure that all Secure-EL1 interrupts are correctly
2107configured at the interrupt controller by the platform port of the EL3 runtime
2108firmware. It should configure any additional Secure-EL1 interrupts which the EL3
2109runtime firmware is not aware of through its platform port.</p>
2110</div>
2111</div>
2112<div class="section" id="test-secure-payload-behavior">
2113<h3><span class="section-number">5.4.5. </span>Test secure payload behavior<a class="headerlink" href="#test-secure-payload-behavior" title="Permalink to this headline"></a></h3>
2114<p>The routing model for Secure-EL1 and non-secure interrupts chosen by the TSP is
2115described in Section <a class="reference external" href="#spd-int-registration">Secure Payload Dispatcher</a>. It is known to the TSPD
2116service at build time.</p>
2117<p>The TSP implements an entrypoint (<code class="docutils literal notranslate"><span class="pre">tsp_sel1_intr_entry()</span></code>) for handling Secure-EL1
2118interrupts taken in non-secure state and routed through the TSPD service
2119(synchronous handling model). It passes the reference to this entrypoint via
2120<code class="docutils literal notranslate"><span class="pre">tsp_vectors</span></code> to the TSPD service.</p>
2121<p>The TSP also replaces the default exception vector table referenced through the
2122<code class="docutils literal notranslate"><span class="pre">early_exceptions</span></code> variable, with a vector table capable of handling FIQ and IRQ
2123exceptions taken at the same (Secure-EL1) exception level. This table is
2124referenced through the <code class="docutils literal notranslate"><span class="pre">tsp_exceptions</span></code> variable and programmed into the
2125VBAR_EL1. It caters for the asynchronous handling model.</p>
2126<p>The TSP also programs the Secure Physical Timer in the Arm Generic Timer block
2127to raise a periodic interrupt (every half a second) for the purpose of testing
2128interrupt management across all the software components listed in <a class="reference internal" href="#software-components">Software
2129components</a>.</p>
2130</div>
2131</div>
2132<div class="section" id="interrupt-handling">
2133<h2><span class="section-number">5.5. </span>Interrupt handling<a class="headerlink" href="#interrupt-handling" title="Permalink to this headline"></a></h2>
2134<p>This section describes in detail the role of each software component (see
2135Section <a class="reference internal" href="#software-components">Software components</a>) in handling an interrupt of a particular type.</p>
2136<div class="section" id="id4">
2137<h3><span class="section-number">5.5.1. </span>EL3 runtime firmware<a class="headerlink" href="#id4" title="Permalink to this headline"></a></h3>
2138<p>The EL3 runtime firmware populates the IRQ and FIQ exception vectors referenced
2139by the <code class="docutils literal notranslate"><span class="pre">runtime_exceptions</span></code> variable as follows.</p>
2140<ol class="arabic simple">
2141<li><p>IRQ and FIQ exceptions taken from the current exception level with
2142<code class="docutils literal notranslate"><span class="pre">SP_EL0</span></code> or <code class="docutils literal notranslate"><span class="pre">SP_EL3</span></code> are reported as irrecoverable error conditions. As
2143mentioned earlier, EL3 runtime firmware always executes with the
2144<code class="docutils literal notranslate"><span class="pre">PSTATE.I</span></code> and <code class="docutils literal notranslate"><span class="pre">PSTATE.F</span></code> bits set.</p></li>
2145<li><p>The following text describes how the IRQ and FIQ exceptions taken from a
2146lower exception level using AArch64 or AArch32 are handled.</p></li>
2147</ol>
2148<p>When an interrupt is generated, the vector for each interrupt type is
2149responsible for:</p>
2150<ol class="arabic">
2151<li><p>Saving the entire general purpose register context (x0-x30) immediately
2152upon exception entry. The registers are saved in the per-cpu <code class="docutils literal notranslate"><span class="pre">cpu_context</span></code>
2153data structure referenced by the <code class="docutils literal notranslate"><span class="pre">SP_EL3</span></code>register.</p></li>
2154<li><p>Saving the <code class="docutils literal notranslate"><span class="pre">ELR_EL3</span></code>, <code class="docutils literal notranslate"><span class="pre">SP_EL0</span></code> and <code class="docutils literal notranslate"><span class="pre">SPSR_EL3</span></code> system registers in the
2155per-cpu <code class="docutils literal notranslate"><span class="pre">cpu_context</span></code> data structure referenced by the <code class="docutils literal notranslate"><span class="pre">SP_EL3</span></code> register.</p></li>
2156<li><p>Switching to the C runtime stack by restoring the <code class="docutils literal notranslate"><span class="pre">CTX_RUNTIME_SP</span></code> value
2157from the per-cpu <code class="docutils literal notranslate"><span class="pre">cpu_context</span></code> data structure in <code class="docutils literal notranslate"><span class="pre">SP_EL0</span></code> and
2158executing the <code class="docutils literal notranslate"><span class="pre">msr</span> <span class="pre">spsel,</span> <span class="pre">#0</span></code> instruction.</p></li>
2159<li><p>Determining the type of interrupt. Secure-EL1 interrupts will be signaled
2160at the FIQ vector. Non-secure interrupts will be signaled at the IRQ
2161vector. The platform should implement the following API to determine the
2162type of the pending interrupt.</p>
2163<div class="highlight-c notranslate"><div class="highlight"><pre><span></span><span class="kt">uint32_t</span><span class="w"> </span><span class="nf">plat_ic_get_interrupt_type</span><span class="p">(</span><span class="kt">void</span><span class="p">);</span><span class="w"></span>
2164</pre></div>
2165</div>
2166<p>It should return either <code class="docutils literal notranslate"><span class="pre">INTR_TYPE_S_EL1</span></code> or <code class="docutils literal notranslate"><span class="pre">INTR_TYPE_NS</span></code>.</p>
2167</li>
2168<li><p>Determining the handler for the type of interrupt that has been generated.
2169The following API has been added for this purpose.</p>
2170<div class="highlight-c notranslate"><div class="highlight"><pre><span></span><span class="n">interrupt_type_handler</span><span class="w"> </span><span class="nf">get_interrupt_type_handler</span><span class="p">(</span><span class="kt">uint32_t</span><span class="w"> </span><span class="n">interrupt_type</span><span class="p">);</span><span class="w"></span>
2171</pre></div>
2172</div>
2173<p>It returns the reference to the registered handler for this interrupt
2174type. The <code class="docutils literal notranslate"><span class="pre">handler</span></code> is retrieved from the <code class="docutils literal notranslate"><span class="pre">intr_type_desc_t</span></code> structure as
2175described in Section 2. <code class="docutils literal notranslate"><span class="pre">NULL</span></code> is returned if no handler has been
2176registered for this type of interrupt. This scenario is reported as an
2177irrecoverable error condition.</p>
2178</li>
2179<li><p>Calling the registered handler function for the interrupt type generated.
2180The <code class="docutils literal notranslate"><span class="pre">id</span></code> parameter is set to <code class="docutils literal notranslate"><span class="pre">INTR_ID_UNAVAILABLE</span></code> currently. The id along
2181with the current security state and a reference to the <code class="docutils literal notranslate"><span class="pre">cpu_context_t</span></code>
2182structure for the current security state are passed to the handler function
2183as its arguments.</p>
2184<p>The handler function returns a reference to the per-cpu <code class="docutils literal notranslate"><span class="pre">cpu_context_t</span></code>
2185structure for the target security state.</p>
2186</li>
2187<li><p>Calling <code class="docutils literal notranslate"><span class="pre">el3_exit()</span></code> to return from EL3 into a lower exception level in
2188the security state determined by the handler routine. The <code class="docutils literal notranslate"><span class="pre">el3_exit()</span></code>
2189function is responsible for restoring the register context from the
2190<code class="docutils literal notranslate"><span class="pre">cpu_context_t</span></code> data structure for the target security state.</p></li>
2191</ol>
2192</div>
2193<div class="section" id="id5">
2194<h3><span class="section-number">5.5.2. </span>Secure payload dispatcher<a class="headerlink" href="#id5" title="Permalink to this headline"></a></h3>
2195<div class="section" id="interrupt-entry">
2196<h4><span class="section-number">5.5.2.1. </span>Interrupt entry<a class="headerlink" href="#interrupt-entry" title="Permalink to this headline"></a></h4>
2197<p>The SPD service begins handling an interrupt when the EL3 runtime firmware calls
2198the handler function for that type of interrupt. The SPD service is responsible
2199for the following:</p>
2200<ol class="arabic">
2201<li><p>Validating the interrupt. This involves ensuring that the interrupt was
2202generated according to the interrupt routing model specified by the SPD
2203service during registration. It should use the security state of the
2204exception level (passed in the <code class="docutils literal notranslate"><span class="pre">flags</span></code> parameter of the handler) where
2205the interrupt was taken from to determine this. If the interrupt is not
2206recognised then the handler should treat it as an irrecoverable error
2207condition.</p>
2208<p>An SPD service can register a handler for Secure-EL1 and/or Non-secure
2209interrupts. A non-secure interrupt should never be routed to EL3 from
2210from non-secure state. Also if a routing model is chosen where Secure-EL1
2211interrupts are routed to S-EL1 when execution is in Secure state, then a
2212S-EL1 interrupt should never be routed to EL3 from secure state. The handler
2213could use the security state flag to check this.</p>
2214</li>
2215<li><p>Determining whether a context switch is required. This depends upon the
2216routing model and interrupt type. For non secure and S-EL1 interrupt,
2217if the security state of the execution context where the interrupt was
2218generated is not the same as the security state required for handling
2219the interrupt, a context switch is required. The following 2 cases
2220require a context switch from secure to non-secure or vice-versa:</p>
2221<ol class="arabic simple">
2222<li><p>A Secure-EL1 interrupt taken from the non-secure state should be
2223routed to the Secure Payload.</p></li>
2224<li><p>A non-secure interrupt taken from the secure state should be routed
2225to the last known non-secure exception level.</p></li>
2226</ol>
2227<p>The SPD service must save the system register context of the current
2228security state. It must then restore the system register context of the
2229target security state. It should use the <code class="docutils literal notranslate"><span class="pre">cm_set_next_eret_context()</span></code> API
2230to ensure that the next <code class="docutils literal notranslate"><span class="pre">cpu_context</span></code> to be restored is of the target
2231security state.</p>
2232<p>If the target state is secure then execution should be handed to the SP as
2233per the synchronous interrupt handling model it implements. A Secure-EL1
2234interrupt can be routed to EL3 while execution is in the SP. This implies
2235that SP execution can be preempted while handling an interrupt by a
2236another higher priority Secure-EL1 interrupt or a EL3 interrupt. The SPD
2237service should be able to handle this preemption or manage secure interrupt
2238priorities before handing control to the SP.</p>
2239</li>
2240<li><p>Setting the return value of the handler to the per-cpu <code class="docutils literal notranslate"><span class="pre">cpu_context</span></code> if
2241the interrupt has been successfully validated and ready to be handled at a
2242lower exception level.</p></li>
2243</ol>
2244<p>The routing model allows non-secure interrupts to interrupt Secure-EL1 when in
2245secure state if it has been configured to do so. The SPD service and the SP
2246should implement a mechanism for routing these interrupts to the last known
2247exception level in the non-secure state. The former should save the SP context,
2248restore the non-secure context and arrange for entry into the non-secure state
2249so that the interrupt can be handled.</p>
2250</div>
2251<div class="section" id="interrupt-exit">
2252<h4><span class="section-number">5.5.2.2. </span>Interrupt exit<a class="headerlink" href="#interrupt-exit" title="Permalink to this headline"></a></h4>
2253<p>When the Secure Payload has finished handling a Secure-EL1 interrupt, it could
2254return control back to the SPD service through a SMC32 or SMC64. The SPD service
2255should handle this secure monitor call so that execution resumes in the
2256exception level and the security state from where the Secure-EL1 interrupt was
2257originally taken.</p>
2258</div>
2259<div class="section" id="test-secure-payload-dispatcher-secure-el1-interrupt-handling">
2260<h4><span class="section-number">5.5.2.3. </span>Test secure payload dispatcher Secure-EL1 interrupt handling<a class="headerlink" href="#test-secure-payload-dispatcher-secure-el1-interrupt-handling" title="Permalink to this headline"></a></h4>
2261<p>The example TSPD service registers a handler for Secure-EL1 interrupts taken
2262from the non-secure state. During execution in S-EL1, the TSPD expects that the
2263Secure-EL1 interrupts are handled in S-EL1 by TSP. Its handler
2264<code class="docutils literal notranslate"><span class="pre">tspd_secure_el1_interrupt_handler()</span></code> expects only to be invoked for Secure-EL1
2265originating from the non-secure state. It takes the following actions upon being
2266invoked.</p>
2267<ol class="arabic simple">
2268<li><p>It uses the security state provided in the <code class="docutils literal notranslate"><span class="pre">flags</span></code> parameter to ensure
2269that the secure interrupt originated from the non-secure state. It asserts
2270if this is not the case.</p></li>
2271<li><p>It saves the system register context for the non-secure state by calling
2272<code class="docutils literal notranslate"><span class="pre">cm_el1_sysregs_context_save(NON_SECURE);</span></code>.</p></li>
2273<li><p>It sets the <code class="docutils literal notranslate"><span class="pre">ELR_EL3</span></code> system register to <code class="docutils literal notranslate"><span class="pre">tsp_sel1_intr_entry</span></code> and sets the
2274<code class="docutils literal notranslate"><span class="pre">SPSR_EL3.DAIF</span></code> bits in the secure CPU context. It sets <code class="docutils literal notranslate"><span class="pre">x0</span></code> to
2275<code class="docutils literal notranslate"><span class="pre">TSP_HANDLE_SEL1_INTR_AND_RETURN</span></code>. If the TSP was preempted earlier by a non
2276secure interrupt during <code class="docutils literal notranslate"><span class="pre">yielding</span></code> SMC processing, save the registers that
2277will be trashed, which is the <code class="docutils literal notranslate"><span class="pre">ELR_EL3</span></code> and <code class="docutils literal notranslate"><span class="pre">SPSR_EL3</span></code>, in order to be able
2278to re-enter TSP for Secure-EL1 interrupt processing. It does not need to
2279save any other secure context since the TSP is expected to preserve it
2280(see section <a class="reference internal" href="#test-secure-payload-dispatcher-behavior">Test secure payload dispatcher behavior</a>).</p></li>
2281<li><p>It restores the system register context for the secure state by calling
2282<code class="docutils literal notranslate"><span class="pre">cm_el1_sysregs_context_restore(SECURE);</span></code>.</p></li>
2283<li><p>It ensures that the secure CPU context is used to program the next
2284exception return from EL3 by calling <code class="docutils literal notranslate"><span class="pre">cm_set_next_eret_context(SECURE);</span></code>.</p></li>
2285<li><p>It returns the per-cpu <code class="docutils literal notranslate"><span class="pre">cpu_context</span></code> to indicate that the interrupt can
2286now be handled by the SP. <code class="docutils literal notranslate"><span class="pre">x1</span></code> is written with the value of <code class="docutils literal notranslate"><span class="pre">elr_el3</span></code>
2287register for the non-secure state. This information is used by the SP for
2288debugging purposes.</p></li>
2289</ol>
2290<p>The figure below describes how the interrupt handling is implemented by the TSPD
2291when a Secure-EL1 interrupt is generated when execution is in the non-secure
2292state.</p>
2293<p><img alt="Image 1" src="../_images/sec-int-handling.png" /></p>
2294<p>The TSP issues an SMC with <code class="docutils literal notranslate"><span class="pre">TSP_HANDLED_S_EL1_INTR</span></code> as the function identifier to
2295signal completion of interrupt handling.</p>
2296<p>The TSPD service takes the following actions in <code class="docutils literal notranslate"><span class="pre">tspd_smc_handler()</span></code> function
2297upon receiving an SMC with <code class="docutils literal notranslate"><span class="pre">TSP_HANDLED_S_EL1_INTR</span></code> as the function identifier:</p>
2298<ol class="arabic simple">
2299<li><p>It ensures that the call originated from the secure state otherwise
2300execution returns to the non-secure state with <code class="docutils literal notranslate"><span class="pre">SMC_UNK</span></code> in <code class="docutils literal notranslate"><span class="pre">x0</span></code>.</p></li>
2301<li><p>It restores the saved <code class="docutils literal notranslate"><span class="pre">ELR_EL3</span></code> and <code class="docutils literal notranslate"><span class="pre">SPSR_EL3</span></code> system registers back to
2302the secure CPU context (see step 3 above) in case the TSP had been preempted
2303by a non secure interrupt earlier.</p></li>
2304<li><p>It restores the system register context for the non-secure state by
2305calling <code class="docutils literal notranslate"><span class="pre">cm_el1_sysregs_context_restore(NON_SECURE)</span></code>.</p></li>
2306<li><p>It ensures that the non-secure CPU context is used to program the next
2307exception return from EL3 by calling <code class="docutils literal notranslate"><span class="pre">cm_set_next_eret_context(NON_SECURE)</span></code>.</p></li>
2308<li><p><code class="docutils literal notranslate"><span class="pre">tspd_smc_handler()</span></code> returns a reference to the non-secure <code class="docutils literal notranslate"><span class="pre">cpu_context</span></code>
2309as the return value.</p></li>
2310</ol>
2311</div>
2312<div class="section" id="test-secure-payload-dispatcher-non-secure-interrupt-handling">
2313<h4><span class="section-number">5.5.2.4. </span>Test secure payload dispatcher non-secure interrupt handling<a class="headerlink" href="#test-secure-payload-dispatcher-non-secure-interrupt-handling" title="Permalink to this headline"></a></h4>
2314<p>The TSP in Secure-EL1 can be preempted by a non-secure interrupt during
2315<code class="docutils literal notranslate"><span class="pre">yielding</span></code> SMC processing or by a higher priority EL3 interrupt during
2316Secure-EL1 interrupt processing. When <code class="docutils literal notranslate"><span class="pre">EL3_EXCEPTION_HANDLING</span></code> is <code class="docutils literal notranslate"><span class="pre">0</span></code>, only
2317non-secure interrupts can cause preemption of TSP since there are no EL3
2318interrupts in the system. With <code class="docutils literal notranslate"><span class="pre">EL3_EXCEPTION_HANDLING=1</span></code> however, any EL3
2319interrupt may preempt Secure execution.</p>
2320<p>It should be noted that while TSP is preempted, the TSPD only allows entry into
2321the TSP either for Secure-EL1 interrupt handling or for resuming the preempted
2322<code class="docutils literal notranslate"><span class="pre">yielding</span></code> SMC in response to the <code class="docutils literal notranslate"><span class="pre">TSP_FID_RESUME</span></code> SMC from the normal world.
2323(See Section <a class="reference internal" href="#implication-of-preempted-smc-on-non-secure-software">Implication of preempted SMC on Non-Secure Software</a>).</p>
2324<p>The non-secure interrupt triggered in Secure-EL1 during <code class="docutils literal notranslate"><span class="pre">yielding</span></code> SMC
2325processing can be routed to either EL3 or Secure-EL1 and is controlled by build
2326option <code class="docutils literal notranslate"><span class="pre">TSP_NS_INTR_ASYNC_PREEMPT</span></code> (see Section <a class="reference internal" href="#test-secure-payload-dispatcher-behavior">Test secure payload
2327dispatcher behavior</a>). If the build option is set, the TSPD will set the
2328routing model for the non-secure interrupt to be routed to EL3 from secure state
2329i.e. <strong>TEL3=1, CSS=0</strong> and registers <code class="docutils literal notranslate"><span class="pre">tspd_ns_interrupt_handler()</span></code> as the
2330non-secure interrupt handler. The <code class="docutils literal notranslate"><span class="pre">tspd_ns_interrupt_handler()</span></code> on being
2331invoked ensures that the interrupt originated from the secure state and disables
2332routing of non-secure interrupts from secure state to EL3. This is to prevent
2333further preemption (by a non-secure interrupt) when TSP is reentered for
2334handling Secure-EL1 interrupts that triggered while execution was in the normal
2335world. The <code class="docutils literal notranslate"><span class="pre">tspd_ns_interrupt_handler()</span></code> then invokes
2336<code class="docutils literal notranslate"><span class="pre">tspd_handle_sp_preemption()</span></code> for further handling.</p>
2337<p>If the <code class="docutils literal notranslate"><span class="pre">TSP_NS_INTR_ASYNC_PREEMPT</span></code> build option is zero (default), the default
2338routing model for non-secure interrupt in secure state is in effect
2339i.e. <strong>TEL3=0, CSS=0</strong>. During <code class="docutils literal notranslate"><span class="pre">yielding</span></code> SMC processing, the IRQ
2340exceptions are unmasked i.e. <code class="docutils literal notranslate"><span class="pre">PSTATE.I=0</span></code>, and a non-secure interrupt will
2341trigger at Secure-EL1 IRQ exception vector. The TSP saves the general purpose
2342register context and issues an SMC with <code class="docutils literal notranslate"><span class="pre">TSP_PREEMPTED</span></code> as the function
2343identifier to signal preemption of TSP. The TSPD SMC handler,
2344<code class="docutils literal notranslate"><span class="pre">tspd_smc_handler()</span></code>, ensures that the SMC call originated from the
2345secure state otherwise execution returns to the non-secure state with
2346<code class="docutils literal notranslate"><span class="pre">SMC_UNK</span></code> in <code class="docutils literal notranslate"><span class="pre">x0</span></code>. It then invokes <code class="docutils literal notranslate"><span class="pre">tspd_handle_sp_preemption()</span></code> for
2347further handling.</p>
2348<p>The <code class="docutils literal notranslate"><span class="pre">tspd_handle_sp_preemption()</span></code> takes the following actions upon being
2349invoked:</p>
2350<ol class="arabic simple">
2351<li><p>It saves the system register context for the secure state by calling
2352<code class="docutils literal notranslate"><span class="pre">cm_el1_sysregs_context_save(SECURE)</span></code>.</p></li>
2353<li><p>It restores the system register context for the non-secure state by
2354calling <code class="docutils literal notranslate"><span class="pre">cm_el1_sysregs_context_restore(NON_SECURE)</span></code>.</p></li>
2355<li><p>It ensures that the non-secure CPU context is used to program the next
2356exception return from EL3 by calling <code class="docutils literal notranslate"><span class="pre">cm_set_next_eret_context(NON_SECURE)</span></code>.</p></li>
2357<li><p><code class="docutils literal notranslate"><span class="pre">SMC_PREEMPTED</span></code> is set in x0 and return to non secure state after
2358restoring non secure context.</p></li>
2359</ol>
2360<p>The Normal World is expected to resume the TSP after the <code class="docutils literal notranslate"><span class="pre">yielding</span></code> SMC
2361preemption by issuing an SMC with <code class="docutils literal notranslate"><span class="pre">TSP_FID_RESUME</span></code> as the function identifier
2362(see section <a class="reference internal" href="#implication-of-preempted-smc-on-non-secure-software">Implication of preempted SMC on Non-Secure Software</a>).  The TSPD
2363service takes the following actions in <code class="docutils literal notranslate"><span class="pre">tspd_smc_handler()</span></code> function upon
2364receiving this SMC:</p>
2365<ol class="arabic simple">
2366<li><p>It ensures that the call originated from the non secure state. An
2367assertion is raised otherwise.</p></li>
2368<li><p>Checks whether the TSP needs a resume i.e check if it was preempted. It
2369then saves the system register context for the non-secure state by calling
2370<code class="docutils literal notranslate"><span class="pre">cm_el1_sysregs_context_save(NON_SECURE)</span></code>.</p></li>
2371<li><p>Restores the secure context by calling
2372<code class="docutils literal notranslate"><span class="pre">cm_el1_sysregs_context_restore(SECURE)</span></code></p></li>
2373<li><p>It ensures that the secure CPU context is used to program the next
2374exception return from EL3 by calling <code class="docutils literal notranslate"><span class="pre">cm_set_next_eret_context(SECURE)</span></code>.</p></li>
2375<li><p><code class="docutils literal notranslate"><span class="pre">tspd_smc_handler()</span></code> returns a reference to the secure <code class="docutils literal notranslate"><span class="pre">cpu_context</span></code> as the
2376return value.</p></li>
2377</ol>
2378<p>The figure below describes how the TSP/TSPD handle a non-secure interrupt when
2379it is generated during execution in the TSP with <code class="docutils literal notranslate"><span class="pre">PSTATE.I</span></code> = 0 when the
2380<code class="docutils literal notranslate"><span class="pre">TSP_NS_INTR_ASYNC_PREEMPT</span></code> build flag is 0.</p>
2381<p><img alt="Image 2" src="../_images/non-sec-int-handling.png" /></p>
2382</div>
2383</div>
2384<div class="section" id="secure-payload-interrupt-handling">
2385<span id="sp-synchronous-int"></span><h3><span class="section-number">5.5.3. </span>Secure payload interrupt handling<a class="headerlink" href="#secure-payload-interrupt-handling" title="Permalink to this headline"></a></h3>
2386<p>The SP should implement one or both of the synchronous and asynchronous
2387interrupt handling models depending upon the interrupt routing model it has
2388chosen (as described in section <a class="reference internal" href="#sp-int-registration"><span class="std std-ref">Secure Payload</span></a>).</p>
2389<p>In the synchronous model, it should begin handling a Secure-EL1 interrupt after
2390receiving control from the SPD service at an entrypoint agreed upon during build
2391time or during the registration phase. Before handling the interrupt, the SP
2392should save any Secure-EL1 system register context which is needed for resuming
2393normal execution in the SP later e.g. <code class="docutils literal notranslate"><span class="pre">SPSR_EL1</span></code>, <code class="docutils literal notranslate"><span class="pre">ELR_EL1</span></code>. After handling
2394the interrupt, the SP could return control back to the exception level and
2395security state where the interrupt was originally taken from. The SP should use
2396an SMC32 or SMC64 to ask the SPD service to do this.</p>
2397<p>In the asynchronous model, the Secure Payload is responsible for handling
2398non-secure and Secure-EL1 interrupts at the IRQ and FIQ vectors in its exception
2399vector table when <code class="docutils literal notranslate"><span class="pre">PSTATE.I</span></code> and <code class="docutils literal notranslate"><span class="pre">PSTATE.F</span></code> bits are 0. As described earlier,
2400when a non-secure interrupt is generated, the SP should coordinate with the SPD
2401service to pass control back to the non-secure state in the last known exception
2402level. This will allow the non-secure interrupt to be handled in the non-secure
2403state.</p>
2404<div class="section" id="id6">
2405<h4><span class="section-number">5.5.3.1. </span>Test secure payload behavior<a class="headerlink" href="#id6" title="Permalink to this headline"></a></h4>
2406<p>The TSPD hands control of a Secure-EL1 interrupt to the TSP at the
2407<code class="docutils literal notranslate"><span class="pre">tsp_sel1_intr_entry()</span></code>. The TSP handles the interrupt while ensuring that the
2408handover agreement described in Section <a class="reference internal" href="#test-secure-payload-dispatcher-behavior">Test secure payload dispatcher
2409behavior</a> is maintained. It updates some statistics by calling
2410<code class="docutils literal notranslate"><span class="pre">tsp_update_sync_sel1_intr_stats()</span></code>. It then calls
2411<code class="docutils literal notranslate"><span class="pre">tsp_common_int_handler()</span></code> which.</p>
2412<ol class="arabic simple">
2413<li><p>Checks whether the interrupt is the secure physical timer interrupt. It
2414uses the platform API <code class="docutils literal notranslate"><span class="pre">plat_ic_get_pending_interrupt_id()</span></code> to get the
2415interrupt number. If it is not the secure physical timer interrupt, then
2416that means that a higher priority interrupt has preempted it. Invoke
2417<code class="docutils literal notranslate"><span class="pre">tsp_handle_preemption()</span></code> to handover control back to EL3 by issuing
2418an SMC with <code class="docutils literal notranslate"><span class="pre">TSP_PREEMPTED</span></code> as the function identifier.</p></li>
2419<li><p>Handles the secure timer interrupt interrupt by acknowledging it using the
2420<code class="docutils literal notranslate"><span class="pre">plat_ic_acknowledge_interrupt()</span></code> platform API, calling
2421<code class="docutils literal notranslate"><span class="pre">tsp_generic_timer_handler()</span></code> to reprogram the secure physical generic
2422timer and calling the <code class="docutils literal notranslate"><span class="pre">plat_ic_end_of_interrupt()</span></code> platform API to signal
2423end of interrupt processing.</p></li>
2424</ol>
2425<p>The TSP passes control back to the TSPD by issuing an SMC64 with
2426<code class="docutils literal notranslate"><span class="pre">TSP_HANDLED_S_EL1_INTR</span></code> as the function identifier.</p>
2427<p>The TSP handles interrupts under the asynchronous model as follows.</p>
2428<ol class="arabic simple">
2429<li><p>Secure-EL1 interrupts are handled by calling the <code class="docutils literal notranslate"><span class="pre">tsp_common_int_handler()</span></code>
2430function. The function has been described above.</p></li>
2431<li><p>Non-secure interrupts are handled by calling the <code class="docutils literal notranslate"><span class="pre">tsp_common_int_handler()</span></code>
2432function which ends up invoking <code class="docutils literal notranslate"><span class="pre">tsp_handle_preemption()</span></code> and issuing an
2433SMC64 with <code class="docutils literal notranslate"><span class="pre">TSP_PREEMPTED</span></code> as the function identifier. Execution resumes at
2434the instruction that follows this SMC instruction when the TSPD hands control
2435to the TSP in response to an SMC with <code class="docutils literal notranslate"><span class="pre">TSP_FID_RESUME</span></code> as the function
2436identifier from the non-secure state (see section <a class="reference internal" href="#test-secure-payload-dispatcher-non-secure-interrupt-handling">Test secure payload
2437dispatcher non-secure interrupt handling</a>).</p></li>
2438</ol>
2439</div>
2440</div>
2441</div>
2442<div class="section" id="other-considerations">
2443<h2><span class="section-number">5.6. </span>Other considerations<a class="headerlink" href="#other-considerations" title="Permalink to this headline"></a></h2>
2444<div class="section" id="implication-of-preempted-smc-on-non-secure-software">
2445<h3><span class="section-number">5.6.1. </span>Implication of preempted SMC on Non-Secure Software<a class="headerlink" href="#implication-of-preempted-smc-on-non-secure-software" title="Permalink to this headline"></a></h3>
2446<p>A <code class="docutils literal notranslate"><span class="pre">yielding</span></code> SMC call to Secure payload can be preempted by a non-secure
2447interrupt and the execution can return to the non-secure world for handling
2448the interrupt (For details on <code class="docutils literal notranslate"><span class="pre">yielding</span></code> SMC refer <a class="reference external" href="https://developer.arm.com/docs/den0028/latest">SMC calling convention</a>).
2449In this case, the SMC call has not completed its execution and the execution
2450must return back to the secure payload to resume the preempted SMC call.
2451This can be achieved by issuing an SMC call which instructs to resume the
2452preempted SMC.</p>
2453<p>A <code class="docutils literal notranslate"><span class="pre">fast</span></code> SMC cannot be preempted and hence this case will not happen for
2454a fast SMC call.</p>
2455<p>In the Test Secure Payload implementation, <code class="docutils literal notranslate"><span class="pre">TSP_FID_RESUME</span></code> is designated
2456as the resume SMC FID. It is important to note that <code class="docutils literal notranslate"><span class="pre">TSP_FID_RESUME</span></code> is a
2457<code class="docutils literal notranslate"><span class="pre">yielding</span></code> SMC which means it too can be be preempted. The typical non
2458secure software sequence for issuing a <code class="docutils literal notranslate"><span class="pre">yielding</span></code> SMC would look like this,
2459assuming <code class="docutils literal notranslate"><span class="pre">P.STATE.I=0</span></code> in the non secure state :</p>
2460<div class="highlight-c notranslate"><div class="highlight"><pre><span></span><span class="kt">int</span><span class="w"> </span><span class="n">rc</span><span class="p">;</span><span class="w"></span>
2461<span class="n">rc</span><span class="w"> </span><span class="o">=</span><span class="w"> </span><span class="n">smc</span><span class="p">(</span><span class="n">TSP_YIELD_SMC_FID</span><span class="p">,</span><span class="w"> </span><span class="p">...);</span><span class="w">     </span><span class="cm">/* Issue a Yielding SMC call */</span><span class="w"></span>
2462<span class="cm">/* The pending non-secure interrupt is handled by the interrupt handler</span>
2463<span class="cm">   and returns back here. */</span><span class="w"></span>
2464<span class="k">while</span><span class="w"> </span><span class="p">(</span><span class="n">rc</span><span class="w"> </span><span class="o">==</span><span class="w"> </span><span class="n">SMC_PREEMPTED</span><span class="p">)</span><span class="w"> </span><span class="p">{</span><span class="w">       </span><span class="cm">/* Check if the SMC call is preempted */</span><span class="w"></span>
2465<span class="w">    </span><span class="n">rc</span><span class="w"> </span><span class="o">=</span><span class="w"> </span><span class="n">smc</span><span class="p">(</span><span class="n">TSP_FID_RESUME</span><span class="p">);</span><span class="w">       </span><span class="cm">/* Issue resume SMC call */</span><span class="w"></span>
2466<span class="p">}</span><span class="w"></span>
2467</pre></div>
2468</div>
2469<p>The <code class="docutils literal notranslate"><span class="pre">TSP_YIELD_SMC_FID</span></code> is any <code class="docutils literal notranslate"><span class="pre">yielding</span></code> SMC function identifier and the smc()
2470function invokes a SMC call with the required arguments. The pending non-secure
2471interrupt causes an IRQ exception and the IRQ handler registered at the
2472exception vector handles the non-secure interrupt and returns. The return value
2473from the SMC call is tested for <code class="docutils literal notranslate"><span class="pre">SMC_PREEMPTED</span></code> to check whether it is
2474preempted. If it is, then the resume SMC call <code class="docutils literal notranslate"><span class="pre">TSP_FID_RESUME</span></code> is issued. The
2475return value of the SMC call is tested again to check if it is preempted.
2476This is done in a loop till the SMC call succeeds or fails. If a <code class="docutils literal notranslate"><span class="pre">yielding</span></code>
2477SMC is preempted, until it is resumed using <code class="docutils literal notranslate"><span class="pre">TSP_FID_RESUME</span></code> SMC and
2478completed, the current TSPD prevents any other SMC call from re-entering
2479TSP by returning <code class="docutils literal notranslate"><span class="pre">SMC_UNK</span></code> error.</p>
2480<hr class="docutils" />
2481<p><em>Copyright (c) 2014-2020, Arm Limited and Contributors. All rights reserved.</em></p>
2482</div>
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