1  /* SPDX-License-Identifier: GPL-2.0 */
2  /* Copyright (c) 2017, 2019 The Linux Foundation. All rights reserved. */
3  
4  #ifndef __A6XX_GPU_H__
5  #define __A6XX_GPU_H__
6  
7  
8  #include "adreno_gpu.h"
9  #include "a6xx.xml.h"
10  
11  #include "a6xx_gmu.h"
12  
13  extern bool hang_debug;
14  
15  struct a6xx_gpu {
16  	struct adreno_gpu base;
17  
18  	struct drm_gem_object *sqe_bo;
19  	uint64_t sqe_iova;
20  
21  	struct msm_ringbuffer *cur_ring;
22  
23  	/**
24  	 * cur_ctx_seqno:
25  	 *
26  	 * The ctx->seqno value of the context with current pgtables
27  	 * installed.  Tracked by seqno rather than pointer value to
28  	 * avoid dangling pointers, and cases where a ctx can be freed
29  	 * and a new one created with the same address.
30  	 */
31  	int cur_ctx_seqno;
32  
33  	struct a6xx_gmu gmu;
34  
35  	struct drm_gem_object *shadow_bo;
36  	uint64_t shadow_iova;
37  	uint32_t *shadow;
38  
39  	bool has_whereami;
40  
41  	void __iomem *llc_mmio;
42  	void *llc_slice;
43  	void *htw_llc_slice;
44  	bool have_mmu500;
45  };
46  
47  #define to_a6xx_gpu(x) container_of(x, struct a6xx_gpu, base)
48  
49  /*
50   * Given a register and a count, return a value to program into
51   * REG_CP_PROTECT_REG(n) - this will block both reads and writes for _len
52   * registers starting at _reg.
53   */
54  #define A6XX_PROTECT_NORDWR(_reg, _len) \
55  	((1 << 31) | \
56  	(((_len) & 0x3FFF) << 18) | ((_reg) & 0x3FFFF))
57  
58  /*
59   * Same as above, but allow reads over the range. For areas of mixed use (such
60   * as performance counters) this allows us to protect a much larger range with a
61   * single register
62   */
63  #define A6XX_PROTECT_RDONLY(_reg, _len) \
64  	((((_len) & 0x3FFF) << 18) | ((_reg) & 0x3FFFF))
65  
a6xx_has_gbif(struct adreno_gpu * gpu)66  static inline bool a6xx_has_gbif(struct adreno_gpu *gpu)
67  {
68  	if(adreno_is_a630(gpu))
69  		return false;
70  
71  	return true;
72  }
73  
74  #define shadowptr(_a6xx_gpu, _ring) ((_a6xx_gpu)->shadow_iova + \
75  		((_ring)->id * sizeof(uint32_t)))
76  
77  int a6xx_gmu_resume(struct a6xx_gpu *gpu);
78  int a6xx_gmu_stop(struct a6xx_gpu *gpu);
79  
80  int a6xx_gmu_wait_for_idle(struct a6xx_gmu *gmu);
81  
82  bool a6xx_gmu_isidle(struct a6xx_gmu *gmu);
83  
84  int a6xx_gmu_set_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state);
85  void a6xx_gmu_clear_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state);
86  
87  int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node);
88  void a6xx_gmu_remove(struct a6xx_gpu *a6xx_gpu);
89  
90  void a6xx_gmu_set_freq(struct msm_gpu *gpu, struct dev_pm_opp *opp);
91  unsigned long a6xx_gmu_get_freq(struct msm_gpu *gpu);
92  
93  void a6xx_show(struct msm_gpu *gpu, struct msm_gpu_state *state,
94  		struct drm_printer *p);
95  
96  struct msm_gpu_state *a6xx_gpu_state_get(struct msm_gpu *gpu);
97  int a6xx_gpu_state_put(struct msm_gpu_state *state);
98  
99  #endif /* __A6XX_GPU_H__ */
100