1/* 2 * Device Tree Source for AM4372 SoC 3 * 4 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ 5 * 6 * This file is licensed under the terms of the GNU General Public License 7 * version 2. This program is licensed "as is" without any warranty of any 8 * kind, whether express or implied. 9 */ 10 11#include <dt-bindings/bus/ti-sysc.h> 12#include <dt-bindings/gpio/gpio.h> 13#include <dt-bindings/interrupt-controller/arm-gic.h> 14#include <dt-bindings/clock/am4.h> 15 16/ { 17 compatible = "ti,am4372", "ti,am43"; 18 interrupt-parent = <&wakeupgen>; 19 #address-cells = <1>; 20 #size-cells = <1>; 21 chosen { }; 22 23 memory@0 { 24 device_type = "memory"; 25 reg = <0 0>; 26 }; 27 28 aliases { 29 i2c0 = &i2c0; 30 i2c1 = &i2c1; 31 i2c2 = &i2c2; 32 serial0 = &uart0; 33 serial1 = &uart1; 34 serial2 = &uart2; 35 serial3 = &uart3; 36 serial4 = &uart4; 37 serial5 = &uart5; 38 ethernet0 = &cpsw_port1; 39 ethernet1 = &cpsw_port2; 40 spi0 = &qspi; 41 }; 42 43 cpus { 44 #address-cells = <1>; 45 #size-cells = <0>; 46 cpu: cpu@0 { 47 compatible = "arm,cortex-a9"; 48 enable-method = "ti,am4372"; 49 device_type = "cpu"; 50 reg = <0>; 51 52 clocks = <&dpll_mpu_ck>; 53 clock-names = "cpu"; 54 55 operating-points-v2 = <&cpu0_opp_table>; 56 57 clock-latency = <300000>; /* From omap-cpufreq driver */ 58 cpu-idle-states = <&mpu_gate>; 59 }; 60 61 idle-states { 62 mpu_gate: mpu_gate { 63 compatible = "arm,idle-state"; 64 entry-latency-us = <40>; 65 exit-latency-us = <100>; 66 min-residency-us = <300>; 67 local-timer-stop; 68 }; 69 }; 70 }; 71 72 cpu0_opp_table: opp-table { 73 compatible = "operating-points-v2-ti-cpu"; 74 syscon = <&scm_conf>; 75 76 opp50-300000000 { 77 opp-hz = /bits/ 64 <300000000>; 78 opp-microvolt = <950000 931000 969000>; 79 opp-supported-hw = <0xFF 0x01>; 80 opp-suspend; 81 }; 82 83 opp100-600000000 { 84 opp-hz = /bits/ 64 <600000000>; 85 opp-microvolt = <1100000 1078000 1122000>; 86 opp-supported-hw = <0xFF 0x04>; 87 }; 88 89 opp120-720000000 { 90 opp-hz = /bits/ 64 <720000000>; 91 opp-microvolt = <1200000 1176000 1224000>; 92 opp-supported-hw = <0xFF 0x08>; 93 }; 94 95 oppturbo-800000000 { 96 opp-hz = /bits/ 64 <800000000>; 97 opp-microvolt = <1260000 1234800 1285200>; 98 opp-supported-hw = <0xFF 0x10>; 99 }; 100 101 oppnitro-1000000000 { 102 opp-hz = /bits/ 64 <1000000000>; 103 opp-microvolt = <1325000 1298500 1351500>; 104 opp-supported-hw = <0xFF 0x20>; 105 }; 106 }; 107 108 soc { 109 compatible = "ti,omap-infra"; 110 }; 111 112 gic: interrupt-controller@48241000 { 113 compatible = "arm,cortex-a9-gic"; 114 interrupt-controller; 115 #interrupt-cells = <3>; 116 reg = <0x48241000 0x1000>, 117 <0x48240100 0x0100>; 118 interrupt-parent = <&gic>; 119 }; 120 121 wakeupgen: interrupt-controller@48281000 { 122 compatible = "ti,omap4-wugen-mpu"; 123 interrupt-controller; 124 #interrupt-cells = <3>; 125 reg = <0x48281000 0x1000>; 126 interrupt-parent = <&gic>; 127 }; 128 129 scu: scu@48240000 { 130 compatible = "arm,cortex-a9-scu"; 131 reg = <0x48240000 0x100>; 132 }; 133 134 global_timer: timer@48240200 { 135 compatible = "arm,cortex-a9-global-timer"; 136 reg = <0x48240200 0x100>; 137 interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>; 138 interrupt-parent = <&gic>; 139 clocks = <&mpu_periphclk>; 140 }; 141 142 local_timer: timer@48240600 { 143 compatible = "arm,cortex-a9-twd-timer"; 144 reg = <0x48240600 0x100>; 145 interrupts = <GIC_PPI 13 IRQ_TYPE_EDGE_RISING>; 146 interrupt-parent = <&gic>; 147 clocks = <&mpu_periphclk>; 148 }; 149 150 cache-controller@48242000 { 151 compatible = "arm,pl310-cache"; 152 reg = <0x48242000 0x1000>; 153 cache-unified; 154 cache-level = <2>; 155 }; 156 157 ocp@44000000 { 158 compatible = "simple-pm-bus"; 159 power-domains = <&prm_per>; 160 clocks = <&l3_clkctrl AM4_L3_L3_MAIN_CLKCTRL 0>; 161 clock-names = "fck"; 162 #address-cells = <1>; 163 #size-cells = <1>; 164 ranges; 165 ti,no-idle; 166 167 l3-noc@44000000 { 168 compatible = "ti,am4372-l3-noc"; 169 reg = <0x44000000 0x400000>, 170 <0x44800000 0x400000>; 171 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 172 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 173 }; 174 175 l4_wkup: interconnect@44c00000 { 176 }; 177 l4_per: interconnect@48000000 { 178 }; 179 l4_fast: interconnect@4a000000 { 180 }; 181 182 target-module@4c000000 { 183 compatible = "ti,sysc-omap4-simple", "ti,sysc"; 184 reg = <0x4c000000 0x4>; 185 reg-names = "rev"; 186 clocks = <&emif_clkctrl AM4_EMIF_EMIF_CLKCTRL 0>; 187 clock-names = "fck"; 188 ti,no-idle; 189 #address-cells = <1>; 190 #size-cells = <1>; 191 ranges = <0x0 0x4c000000 0x1000000>; 192 193 emif: emif@0 { 194 compatible = "ti,emif-am4372"; 195 reg = <0 0x1000000>; 196 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 197 sram = <&pm_sram_code 198 &pm_sram_data>; 199 }; 200 }; 201 202 target-module@49000000 { 203 compatible = "ti,sysc-omap4", "ti,sysc"; 204 reg = <0x49000000 0x4>; 205 reg-names = "rev"; 206 clocks = <&l3_clkctrl AM4_L3_TPCC_CLKCTRL 0>; 207 clock-names = "fck"; 208 #address-cells = <1>; 209 #size-cells = <1>; 210 ranges = <0x0 0x49000000 0x10000>; 211 212 edma: dma@0 { 213 compatible = "ti,edma3-tpcc"; 214 reg = <0 0x10000>; 215 reg-names = "edma3_cc"; 216 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 217 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 218 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 219 interrupt-names = "edma3_ccint", "edma3_mperr", 220 "edma3_ccerrint"; 221 dma-requests = <64>; 222 #dma-cells = <2>; 223 224 ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>, 225 <&edma_tptc2 0>; 226 227 ti,edma-memcpy-channels = <58 59>; 228 }; 229 }; 230 231 target-module@49800000 { 232 compatible = "ti,sysc-omap4", "ti,sysc"; 233 reg = <0x49800000 0x4>, 234 <0x49800010 0x4>; 235 reg-names = "rev", "sysc"; 236 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 237 ti,sysc-midle = <SYSC_IDLE_FORCE>; 238 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 239 <SYSC_IDLE_SMART>; 240 clocks = <&l3_clkctrl AM4_L3_TPTC0_CLKCTRL 0>; 241 clock-names = "fck"; 242 #address-cells = <1>; 243 #size-cells = <1>; 244 ranges = <0x0 0x49800000 0x100000>; 245 246 edma_tptc0: dma@0 { 247 compatible = "ti,edma3-tptc"; 248 reg = <0 0x100000>; 249 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 250 interrupt-names = "edma3_tcerrint"; 251 }; 252 }; 253 254 target-module@49900000 { 255 compatible = "ti,sysc-omap4", "ti,sysc"; 256 reg = <0x49900000 0x4>, 257 <0x49900010 0x4>; 258 reg-names = "rev", "sysc"; 259 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 260 ti,sysc-midle = <SYSC_IDLE_FORCE>; 261 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 262 <SYSC_IDLE_SMART>; 263 clocks = <&l3_clkctrl AM4_L3_TPTC1_CLKCTRL 0>; 264 clock-names = "fck"; 265 #address-cells = <1>; 266 #size-cells = <1>; 267 ranges = <0x0 0x49900000 0x100000>; 268 269 edma_tptc1: dma@0 { 270 compatible = "ti,edma3-tptc"; 271 reg = <0 0x100000>; 272 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 273 interrupt-names = "edma3_tcerrint"; 274 }; 275 }; 276 277 target-module@49a00000 { 278 compatible = "ti,sysc-omap4", "ti,sysc"; 279 reg = <0x49a00000 0x4>, 280 <0x49a00010 0x4>; 281 reg-names = "rev", "sysc"; 282 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 283 ti,sysc-midle = <SYSC_IDLE_FORCE>; 284 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 285 <SYSC_IDLE_SMART>; 286 clocks = <&l3_clkctrl AM4_L3_TPTC2_CLKCTRL 0>; 287 clock-names = "fck"; 288 #address-cells = <1>; 289 #size-cells = <1>; 290 ranges = <0x0 0x49a00000 0x100000>; 291 292 edma_tptc2: dma@0 { 293 compatible = "ti,edma3-tptc"; 294 reg = <0 0x100000>; 295 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 296 interrupt-names = "edma3_tcerrint"; 297 }; 298 }; 299 300 target-module@47810000 { 301 compatible = "ti,sysc-omap2", "ti,sysc"; 302 reg = <0x478102fc 0x4>, 303 <0x47810110 0x4>, 304 <0x47810114 0x4>; 305 reg-names = "rev", "sysc", "syss"; 306 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 307 SYSC_OMAP2_ENAWAKEUP | 308 SYSC_OMAP2_SOFTRESET | 309 SYSC_OMAP2_AUTOIDLE)>; 310 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 311 <SYSC_IDLE_NO>, 312 <SYSC_IDLE_SMART>; 313 ti,syss-mask = <1>; 314 clocks = <&l3s_clkctrl AM4_L3S_MMC3_CLKCTRL 0>; 315 clock-names = "fck"; 316 #address-cells = <1>; 317 #size-cells = <1>; 318 ranges = <0x0 0x47810000 0x1000>; 319 320 mmc3: mmc@0 { 321 compatible = "ti,am437-sdhci"; 322 ti,needs-special-reset; 323 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 324 reg = <0x0 0x1000>; 325 status = "disabled"; 326 }; 327 }; 328 329 sham_target: target-module@53100000 { 330 compatible = "ti,sysc-omap3-sham", "ti,sysc"; 331 reg = <0x53100100 0x4>, 332 <0x53100110 0x4>, 333 <0x53100114 0x4>; 334 reg-names = "rev", "sysc", "syss"; 335 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | 336 SYSC_OMAP2_AUTOIDLE)>; 337 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 338 <SYSC_IDLE_NO>, 339 <SYSC_IDLE_SMART>; 340 ti,syss-mask = <1>; 341 /* Domains (P, C): per_pwrdm, l3_clkdm */ 342 clocks = <&l3_clkctrl AM4_L3_SHAM_CLKCTRL 0>; 343 clock-names = "fck"; 344 #address-cells = <1>; 345 #size-cells = <1>; 346 ranges = <0x0 0x53100000 0x1000>; 347 348 sham: sham@0 { 349 compatible = "ti,omap5-sham"; 350 reg = <0 0x300>; 351 dmas = <&edma 36 0>; 352 dma-names = "rx"; 353 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 354 }; 355 }; 356 357 aes_target: target-module@53501000 { 358 compatible = "ti,sysc-omap2", "ti,sysc"; 359 reg = <0x53501080 0x4>, 360 <0x53501084 0x4>, 361 <0x53501088 0x4>; 362 reg-names = "rev", "sysc", "syss"; 363 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | 364 SYSC_OMAP2_AUTOIDLE)>; 365 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 366 <SYSC_IDLE_NO>, 367 <SYSC_IDLE_SMART>, 368 <SYSC_IDLE_SMART_WKUP>; 369 ti,syss-mask = <1>; 370 /* Domains (P, C): per_pwrdm, l3_clkdm */ 371 clocks = <&l3_clkctrl AM4_L3_AES_CLKCTRL 0>; 372 clock-names = "fck"; 373 #address-cells = <1>; 374 #size-cells = <1>; 375 ranges = <0x0 0x53501000 0x1000>; 376 377 aes: aes@0 { 378 compatible = "ti,omap4-aes"; 379 reg = <0 0xa0>; 380 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 381 dmas = <&edma 6 0>, 382 <&edma 5 0>; 383 dma-names = "tx", "rx"; 384 }; 385 }; 386 387 des_target: target-module@53701000 { 388 compatible = "ti,sysc-omap2", "ti,sysc"; 389 reg = <0x53701030 0x4>, 390 <0x53701034 0x4>, 391 <0x53701038 0x4>; 392 reg-names = "rev", "sysc", "syss"; 393 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | 394 SYSC_OMAP2_AUTOIDLE)>; 395 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 396 <SYSC_IDLE_NO>, 397 <SYSC_IDLE_SMART>, 398 <SYSC_IDLE_SMART_WKUP>; 399 ti,syss-mask = <1>; 400 /* Domains (P, C): per_pwrdm, l3_clkdm */ 401 clocks = <&l3_clkctrl AM4_L3_DES_CLKCTRL 0>; 402 clock-names = "fck"; 403 #address-cells = <1>; 404 #size-cells = <1>; 405 ranges = <0 0x53701000 0x1000>; 406 407 des: des@0 { 408 compatible = "ti,omap4-des"; 409 reg = <0 0xa0>; 410 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; 411 dmas = <&edma 34 0>, 412 <&edma 33 0>; 413 dma-names = "tx", "rx"; 414 }; 415 }; 416 417 pruss_tm: target-module@54400000 { 418 compatible = "ti,sysc-pruss", "ti,sysc"; 419 reg = <0x54426000 0x4>, 420 <0x54426004 0x4>; 421 reg-names = "rev", "sysc"; 422 ti,sysc-mask = <(SYSC_PRUSS_STANDBY_INIT | 423 SYSC_PRUSS_SUB_MWAIT)>; 424 ti,sysc-midle = <SYSC_IDLE_FORCE>, 425 <SYSC_IDLE_NO>, 426 <SYSC_IDLE_SMART>; 427 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 428 <SYSC_IDLE_NO>, 429 <SYSC_IDLE_SMART>; 430 clocks = <&pruss_ocp_clkctrl AM4_PRUSS_OCP_PRUSS_CLKCTRL 0>; 431 clock-names = "fck"; 432 resets = <&prm_per 1>; 433 reset-names = "rstctrl"; 434 #address-cells = <1>; 435 #size-cells = <1>; 436 ranges = <0x0 0x54400000 0x80000>; 437 438 pruss1: pruss@0 { 439 compatible = "ti,am4376-pruss1"; 440 reg = <0x0 0x40000>; 441 #address-cells = <1>; 442 #size-cells = <1>; 443 ranges; 444 445 pruss1_mem: memories@0 { 446 reg = <0x0 0x2000>, 447 <0x2000 0x2000>, 448 <0x10000 0x8000>; 449 reg-names = "dram0", "dram1", 450 "shrdram2"; 451 }; 452 453 pruss1_cfg: cfg@26000 { 454 compatible = "ti,pruss-cfg", "syscon"; 455 reg = <0x26000 0x2000>; 456 #address-cells = <1>; 457 #size-cells = <1>; 458 ranges = <0x0 0x26000 0x2000>; 459 460 clocks { 461 #address-cells = <1>; 462 #size-cells = <0>; 463 464 pruss1_iepclk_mux: iepclk-mux@30 { 465 reg = <0x30>; 466 #clock-cells = <0>; 467 clocks = <&sysclk_div>, /* icss_iep_gclk */ 468 <&pruss_ocp_gclk>; /* icss_ocp_gclk */ 469 }; 470 }; 471 }; 472 473 pruss1_mii_rt: mii-rt@32000 { 474 compatible = "ti,pruss-mii", "syscon"; 475 reg = <0x32000 0x58>; 476 }; 477 478 pruss1_intc: interrupt-controller@20000 { 479 compatible = "ti,pruss-intc"; 480 reg = <0x20000 0x2000>; 481 interrupt-controller; 482 #interrupt-cells = <3>; 483 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 484 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 485 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 486 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 487 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 488 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 489 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 490 interrupt-names = "host_intr0", "host_intr1", 491 "host_intr2", "host_intr3", 492 "host_intr4", 493 "host_intr6", "host_intr7"; 494 ti,irqs-reserved = /bits/ 8 <0x20>; /* BIT(5) */ 495 }; 496 497 pru1_0: pru@34000 { 498 compatible = "ti,am4376-pru"; 499 reg = <0x34000 0x3000>, 500 <0x22000 0x400>, 501 <0x22400 0x100>; 502 reg-names = "iram", "control", "debug"; 503 firmware-name = "am437x-pru1_0-fw"; 504 }; 505 506 pru1_1: pru@38000 { 507 compatible = "ti,am4376-pru"; 508 reg = <0x38000 0x3000>, 509 <0x24000 0x400>, 510 <0x24400 0x100>; 511 reg-names = "iram", "control", "debug"; 512 firmware-name = "am437x-pru1_1-fw"; 513 }; 514 515 pruss1_mdio: mdio@32400 { 516 compatible = "ti,davinci_mdio"; 517 reg = <0x32400 0x90>; 518 clocks = <&dpll_core_m4_ck>; 519 clock-names = "fck"; 520 bus_freq = <1000000>; 521 #address-cells = <1>; 522 #size-cells = <0>; 523 }; 524 }; 525 526 pruss0: pruss@40000 { 527 compatible = "ti,am4376-pruss0"; 528 reg = <0x40000 0x40000>; 529 #address-cells = <1>; 530 #size-cells = <1>; 531 ranges; 532 533 pruss0_mem: memories@40000 { 534 reg = <0x40000 0x1000>, 535 <0x42000 0x1000>; 536 reg-names = "dram0", "dram1"; 537 }; 538 539 pruss0_cfg: cfg@66000 { 540 compatible = "ti,pruss-cfg", "syscon"; 541 reg = <0x66000 0x2000>; 542 #address-cells = <1>; 543 #size-cells = <1>; 544 ranges = <0x0 0x66000 0x2000>; 545 546 clocks { 547 #address-cells = <1>; 548 #size-cells = <0>; 549 550 pruss0_iepclk_mux: iepclk-mux@30 { 551 reg = <0x30>; 552 #clock-cells = <0>; 553 clocks = <&sysclk_div>, /* icss_iep_gclk */ 554 <&pruss_ocp_gclk>; /* icss_ocp_gclk */ 555 }; 556 }; 557 }; 558 559 pruss0_mii_rt: mii-rt@72000 { 560 compatible = "ti,pruss-mii", "syscon"; 561 reg = <0x72000 0x58>; 562 status = "disabled"; 563 }; 564 565 pruss0_intc: interrupt-controller@60000 { 566 compatible = "ti,pruss-intc"; 567 reg = <0x60000 0x2000>; 568 interrupt-controller; 569 #interrupt-cells = <3>; 570 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 571 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 572 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 573 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, 574 <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 575 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, 576 <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; 577 interrupt-names = "host_intr0", "host_intr1", 578 "host_intr2", "host_intr3", 579 "host_intr4", 580 "host_intr6", "host_intr7"; 581 ti,irqs-reserved = /bits/ 8 <0x20>; /* BIT(5) */ 582 }; 583 584 pru0_0: pru@74000 { 585 compatible = "ti,am4376-pru"; 586 reg = <0x74000 0x1000>, 587 <0x62000 0x400>, 588 <0x62400 0x100>; 589 reg-names = "iram", "control", "debug"; 590 firmware-name = "am437x-pru0_0-fw"; 591 }; 592 593 pru0_1: pru@78000 { 594 compatible = "ti,am4376-pru"; 595 reg = <0x78000 0x1000>, 596 <0x64000 0x400>, 597 <0x64400 0x100>; 598 reg-names = "iram", "control", "debug"; 599 firmware-name = "am437x-pru0_1-fw"; 600 }; 601 }; 602 }; 603 604 target-module@50000000 { 605 compatible = "ti,sysc-omap2", "ti,sysc"; 606 reg = <0x50000000 4>, 607 <0x50000010 4>, 608 <0x50000014 4>; 609 reg-names = "rev", "sysc", "syss"; 610 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 611 <SYSC_IDLE_NO>, 612 <SYSC_IDLE_SMART>; 613 ti,syss-mask = <1>; 614 clocks = <&l3s_clkctrl AM4_L3S_GPMC_CLKCTRL 0>; 615 clock-names = "fck"; 616 #address-cells = <1>; 617 #size-cells = <1>; 618 ranges = <0x50000000 0x50000000 0x00001000>, /* regs */ 619 <0x00000000 0x00000000 0x40000000>; /* data */ 620 621 gpmc: gpmc@50000000 { 622 compatible = "ti,am3352-gpmc"; 623 dmas = <&edma 52 0>; 624 dma-names = "rxtx"; 625 clocks = <&l3s_gclk>; 626 clock-names = "fck"; 627 reg = <0x50000000 0x2000>; 628 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 629 gpmc,num-cs = <7>; 630 gpmc,num-waitpins = <2>; 631 #address-cells = <2>; 632 #size-cells = <1>; 633 interrupt-controller; 634 #interrupt-cells = <2>; 635 gpio-controller; 636 #gpio-cells = <2>; 637 status = "disabled"; 638 }; 639 }; 640 641 target-module@47900000 { 642 compatible = "ti,sysc-omap4", "ti,sysc"; 643 reg = <0x47900000 0x4>, 644 <0x47900010 0x4>; 645 reg-names = "rev", "sysc"; 646 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 647 <SYSC_IDLE_NO>, 648 <SYSC_IDLE_SMART>, 649 <SYSC_IDLE_SMART_WKUP>; 650 clocks = <&l3s_clkctrl AM4_L3S_QSPI_CLKCTRL 0>; 651 clock-names = "fck"; 652 #address-cells = <1>; 653 #size-cells = <1>; 654 ranges = <0x0 0x47900000 0x1000>, 655 <0x30000000 0x30000000 0x4000000>; 656 657 qspi: spi@0 { 658 compatible = "ti,am4372-qspi"; 659 reg = <0 0x100>, 660 <0x30000000 0x4000000>; 661 reg-names = "qspi_base", "qspi_mmap"; 662 clocks = <&dpll_per_m2_div4_ck>; 663 clock-names = "fck"; 664 #address-cells = <1>; 665 #size-cells = <0>; 666 interrupts = <0 138 0x4>; 667 num-cs = <4>; 668 }; 669 }; 670 671 target-module@40300000 { 672 compatible = "ti,sysc-omap4-simple", "ti,sysc"; 673 clocks = <&l3_clkctrl AM4_L3_OCMCRAM_CLKCTRL 0>; 674 clock-names = "fck"; 675 ti,no-idle; 676 #address-cells = <1>; 677 #size-cells = <1>; 678 ranges = <0 0x40300000 0x40000>; 679 680 ocmcram: sram@0 { 681 compatible = "mmio-sram"; 682 reg = <0 0x40000>; /* 256k */ 683 ranges = <0 0 0x40000>; 684 #address-cells = <1>; 685 #size-cells = <1>; 686 687 pm_sram_code: pm-code-sram@0 { 688 compatible = "ti,sram"; 689 reg = <0x0 0x1000>; 690 protect-exec; 691 }; 692 693 pm_sram_data: pm-data-sram@1000 { 694 compatible = "ti,sram"; 695 reg = <0x1000 0x1000>; 696 pool; 697 }; 698 }; 699 }; 700 701 target-module@56000000 { 702 compatible = "ti,sysc-omap4", "ti,sysc"; 703 reg = <0x5600fe00 0x4>, 704 <0x5600fe10 0x4>; 705 reg-names = "rev", "sysc"; 706 ti,sysc-midle = <SYSC_IDLE_FORCE>, 707 <SYSC_IDLE_NO>, 708 <SYSC_IDLE_SMART>; 709 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 710 <SYSC_IDLE_NO>, 711 <SYSC_IDLE_SMART>; 712 clocks = <&gfx_l3_clkctrl AM4_GFX_L3_GFX_CLKCTRL 0>; 713 clock-names = "fck"; 714 power-domains = <&prm_gfx>; 715 resets = <&prm_gfx 0>; 716 reset-names = "rstctrl"; 717 #address-cells = <1>; 718 #size-cells = <1>; 719 ranges = <0 0x56000000 0x1000000>; 720 }; 721 }; 722}; 723 724#include "am437x-l4.dtsi" 725#include "am43xx-clocks.dtsi" 726 727&prcm { 728 prm_mpu: prm@300 { 729 compatible = "ti,am4-prm-inst", "ti,omap-prm-inst"; 730 reg = <0x300 0x100>; 731 #power-domain-cells = <0>; 732 }; 733 734 prm_gfx: prm@400 { 735 compatible = "ti,am4-prm-inst", "ti,omap-prm-inst"; 736 reg = <0x400 0x100>; 737 #power-domain-cells = <0>; 738 #reset-cells = <1>; 739 }; 740 741 prm_rtc: prm@500 { 742 compatible = "ti,am4-prm-inst", "ti,omap-prm-inst"; 743 reg = <0x500 0x100>; 744 #power-domain-cells = <0>; 745 }; 746 747 prm_tamper: prm@600 { 748 compatible = "ti,am4-prm-inst", "ti,omap-prm-inst"; 749 reg = <0x600 0x100>; 750 #power-domain-cells = <0>; 751 }; 752 753 prm_cefuse: prm@700 { 754 compatible = "ti,am4-prm-inst", "ti,omap-prm-inst"; 755 reg = <0x700 0x100>; 756 #power-domain-cells = <0>; 757 }; 758 759 prm_per: prm@800 { 760 compatible = "ti,am4-prm-inst", "ti,omap-prm-inst"; 761 reg = <0x800 0x100>; 762 #reset-cells = <1>; 763 #power-domain-cells = <0>; 764 }; 765 766 prm_wkup: prm@2000 { 767 compatible = "ti,am4-prm-inst", "ti,omap-prm-inst"; 768 reg = <0x2000 0x100>; 769 #reset-cells = <1>; 770 #power-domain-cells = <0>; 771 }; 772 773 prm_device: prm@4000 { 774 compatible = "ti,am4-prm-inst", "ti,omap-prm-inst"; 775 reg = <0x4000 0x100>; 776 #reset-cells = <1>; 777 }; 778}; 779 780/* Preferred always-on timer for clocksource */ 781&timer1_target { 782 ti,no-reset-on-init; 783 ti,no-idle; 784 clocks = <&l4_wkup_clkctrl AM4_L4_WKUP_TIMER1_CLKCTRL 0>, 785 <&l4_wkup_clkctrl AM4_L4_WKUP_L4_WKUP_CLKCTRL 0>; 786 clock-names = "fck", "ick"; 787 timer@0 { 788 assigned-clocks = <&timer1_fck>; 789 assigned-clock-parents = <&sys_clkin_ck>; 790 }; 791}; 792 793/* Preferred timer for clockevent */ 794&timer2_target { 795 ti,no-reset-on-init; 796 ti,no-idle; 797 clocks = <&l4ls_clkctrl AM4_L4LS_TIMER2_CLKCTRL 0>, 798 <&l4ls_clkctrl AM4_L4LS_L4_LS_CLKCTRL 0>; 799 clock-names = "fck", "ick"; 800 timer@0 { 801 assigned-clocks = <&timer2_fck>; 802 assigned-clock-parents = <&sys_clkin_ck>; 803 }; 804}; 805