1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Synopsys DesignWare PCIe host controller driver
4 *
5 * Copyright (C) 2013 Samsung Electronics Co., Ltd.
6 * https://www.samsung.com
7 *
8 * Author: Jingoo Han <jg1.han@samsung.com>
9 */
10
11 #include <linux/irqchip/chained_irq.h>
12 #include <linux/irqdomain.h>
13 #include <linux/msi.h>
14 #include <linux/of_address.h>
15 #include <linux/of_pci.h>
16 #include <linux/pci_regs.h>
17 #include <linux/platform_device.h>
18
19 #include "../../pci.h"
20 #include "pcie-designware.h"
21
22 static struct pci_ops dw_pcie_ops;
23 static struct pci_ops dw_child_pcie_ops;
24
dw_msi_ack_irq(struct irq_data * d)25 static void dw_msi_ack_irq(struct irq_data *d)
26 {
27 irq_chip_ack_parent(d);
28 }
29
dw_msi_mask_irq(struct irq_data * d)30 static void dw_msi_mask_irq(struct irq_data *d)
31 {
32 pci_msi_mask_irq(d);
33 irq_chip_mask_parent(d);
34 }
35
dw_msi_unmask_irq(struct irq_data * d)36 static void dw_msi_unmask_irq(struct irq_data *d)
37 {
38 pci_msi_unmask_irq(d);
39 irq_chip_unmask_parent(d);
40 }
41
42 static struct irq_chip dw_pcie_msi_irq_chip = {
43 .name = "PCI-MSI",
44 .irq_ack = dw_msi_ack_irq,
45 .irq_mask = dw_msi_mask_irq,
46 .irq_unmask = dw_msi_unmask_irq,
47 };
48
49 static struct msi_domain_info dw_pcie_msi_domain_info = {
50 .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
51 MSI_FLAG_PCI_MSIX | MSI_FLAG_MULTI_PCI_MSI),
52 .chip = &dw_pcie_msi_irq_chip,
53 };
54
55 /* MSI int handler */
dw_handle_msi_irq(struct pcie_port * pp)56 irqreturn_t dw_handle_msi_irq(struct pcie_port *pp)
57 {
58 int i, pos;
59 unsigned long val;
60 u32 status, num_ctrls;
61 irqreturn_t ret = IRQ_NONE;
62 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
63
64 num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL;
65
66 for (i = 0; i < num_ctrls; i++) {
67 status = dw_pcie_readl_dbi(pci, PCIE_MSI_INTR0_STATUS +
68 (i * MSI_REG_CTRL_BLOCK_SIZE));
69 if (!status)
70 continue;
71
72 ret = IRQ_HANDLED;
73 val = status;
74 pos = 0;
75 while ((pos = find_next_bit(&val, MAX_MSI_IRQS_PER_CTRL,
76 pos)) != MAX_MSI_IRQS_PER_CTRL) {
77 generic_handle_domain_irq(pp->irq_domain,
78 (i * MAX_MSI_IRQS_PER_CTRL) +
79 pos);
80 pos++;
81 }
82 }
83
84 return ret;
85 }
86
87 /* Chained MSI interrupt service routine */
dw_chained_msi_isr(struct irq_desc * desc)88 static void dw_chained_msi_isr(struct irq_desc *desc)
89 {
90 struct irq_chip *chip = irq_desc_get_chip(desc);
91 struct pcie_port *pp;
92
93 chained_irq_enter(chip, desc);
94
95 pp = irq_desc_get_handler_data(desc);
96 dw_handle_msi_irq(pp);
97
98 chained_irq_exit(chip, desc);
99 }
100
dw_pci_setup_msi_msg(struct irq_data * d,struct msi_msg * msg)101 static void dw_pci_setup_msi_msg(struct irq_data *d, struct msi_msg *msg)
102 {
103 struct pcie_port *pp = irq_data_get_irq_chip_data(d);
104 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
105 u64 msi_target;
106
107 msi_target = (u64)pp->msi_data;
108
109 msg->address_lo = lower_32_bits(msi_target);
110 msg->address_hi = upper_32_bits(msi_target);
111
112 msg->data = d->hwirq;
113
114 dev_dbg(pci->dev, "msi#%d address_hi %#x address_lo %#x\n",
115 (int)d->hwirq, msg->address_hi, msg->address_lo);
116 }
117
dw_pci_msi_set_affinity(struct irq_data * d,const struct cpumask * mask,bool force)118 static int dw_pci_msi_set_affinity(struct irq_data *d,
119 const struct cpumask *mask, bool force)
120 {
121 return -EINVAL;
122 }
123
dw_pci_bottom_mask(struct irq_data * d)124 static void dw_pci_bottom_mask(struct irq_data *d)
125 {
126 struct pcie_port *pp = irq_data_get_irq_chip_data(d);
127 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
128 unsigned int res, bit, ctrl;
129 unsigned long flags;
130
131 raw_spin_lock_irqsave(&pp->lock, flags);
132
133 ctrl = d->hwirq / MAX_MSI_IRQS_PER_CTRL;
134 res = ctrl * MSI_REG_CTRL_BLOCK_SIZE;
135 bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL;
136
137 pp->irq_mask[ctrl] |= BIT(bit);
138 dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_MASK + res, pp->irq_mask[ctrl]);
139
140 raw_spin_unlock_irqrestore(&pp->lock, flags);
141 }
142
dw_pci_bottom_unmask(struct irq_data * d)143 static void dw_pci_bottom_unmask(struct irq_data *d)
144 {
145 struct pcie_port *pp = irq_data_get_irq_chip_data(d);
146 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
147 unsigned int res, bit, ctrl;
148 unsigned long flags;
149
150 raw_spin_lock_irqsave(&pp->lock, flags);
151
152 ctrl = d->hwirq / MAX_MSI_IRQS_PER_CTRL;
153 res = ctrl * MSI_REG_CTRL_BLOCK_SIZE;
154 bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL;
155
156 pp->irq_mask[ctrl] &= ~BIT(bit);
157 dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_MASK + res, pp->irq_mask[ctrl]);
158
159 raw_spin_unlock_irqrestore(&pp->lock, flags);
160 }
161
dw_pci_bottom_ack(struct irq_data * d)162 static void dw_pci_bottom_ack(struct irq_data *d)
163 {
164 struct pcie_port *pp = irq_data_get_irq_chip_data(d);
165 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
166 unsigned int res, bit, ctrl;
167
168 ctrl = d->hwirq / MAX_MSI_IRQS_PER_CTRL;
169 res = ctrl * MSI_REG_CTRL_BLOCK_SIZE;
170 bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL;
171
172 dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_STATUS + res, BIT(bit));
173 }
174
175 static struct irq_chip dw_pci_msi_bottom_irq_chip = {
176 .name = "DWPCI-MSI",
177 .irq_ack = dw_pci_bottom_ack,
178 .irq_compose_msi_msg = dw_pci_setup_msi_msg,
179 .irq_set_affinity = dw_pci_msi_set_affinity,
180 .irq_mask = dw_pci_bottom_mask,
181 .irq_unmask = dw_pci_bottom_unmask,
182 };
183
dw_pcie_irq_domain_alloc(struct irq_domain * domain,unsigned int virq,unsigned int nr_irqs,void * args)184 static int dw_pcie_irq_domain_alloc(struct irq_domain *domain,
185 unsigned int virq, unsigned int nr_irqs,
186 void *args)
187 {
188 struct pcie_port *pp = domain->host_data;
189 unsigned long flags;
190 u32 i;
191 int bit;
192
193 raw_spin_lock_irqsave(&pp->lock, flags);
194
195 bit = bitmap_find_free_region(pp->msi_irq_in_use, pp->num_vectors,
196 order_base_2(nr_irqs));
197
198 raw_spin_unlock_irqrestore(&pp->lock, flags);
199
200 if (bit < 0)
201 return -ENOSPC;
202
203 for (i = 0; i < nr_irqs; i++)
204 irq_domain_set_info(domain, virq + i, bit + i,
205 pp->msi_irq_chip,
206 pp, handle_edge_irq,
207 NULL, NULL);
208
209 return 0;
210 }
211
dw_pcie_irq_domain_free(struct irq_domain * domain,unsigned int virq,unsigned int nr_irqs)212 static void dw_pcie_irq_domain_free(struct irq_domain *domain,
213 unsigned int virq, unsigned int nr_irqs)
214 {
215 struct irq_data *d = irq_domain_get_irq_data(domain, virq);
216 struct pcie_port *pp = domain->host_data;
217 unsigned long flags;
218
219 raw_spin_lock_irqsave(&pp->lock, flags);
220
221 bitmap_release_region(pp->msi_irq_in_use, d->hwirq,
222 order_base_2(nr_irqs));
223
224 raw_spin_unlock_irqrestore(&pp->lock, flags);
225 }
226
227 static const struct irq_domain_ops dw_pcie_msi_domain_ops = {
228 .alloc = dw_pcie_irq_domain_alloc,
229 .free = dw_pcie_irq_domain_free,
230 };
231
dw_pcie_allocate_domains(struct pcie_port * pp)232 int dw_pcie_allocate_domains(struct pcie_port *pp)
233 {
234 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
235 struct fwnode_handle *fwnode = of_node_to_fwnode(pci->dev->of_node);
236
237 pp->irq_domain = irq_domain_create_linear(fwnode, pp->num_vectors,
238 &dw_pcie_msi_domain_ops, pp);
239 if (!pp->irq_domain) {
240 dev_err(pci->dev, "Failed to create IRQ domain\n");
241 return -ENOMEM;
242 }
243
244 irq_domain_update_bus_token(pp->irq_domain, DOMAIN_BUS_NEXUS);
245
246 pp->msi_domain = pci_msi_create_irq_domain(fwnode,
247 &dw_pcie_msi_domain_info,
248 pp->irq_domain);
249 if (!pp->msi_domain) {
250 dev_err(pci->dev, "Failed to create MSI domain\n");
251 irq_domain_remove(pp->irq_domain);
252 return -ENOMEM;
253 }
254
255 return 0;
256 }
257
dw_pcie_free_msi(struct pcie_port * pp)258 static void dw_pcie_free_msi(struct pcie_port *pp)
259 {
260 if (pp->msi_irq)
261 irq_set_chained_handler_and_data(pp->msi_irq, NULL, NULL);
262
263 irq_domain_remove(pp->msi_domain);
264 irq_domain_remove(pp->irq_domain);
265
266 if (pp->msi_data) {
267 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
268 struct device *dev = pci->dev;
269
270 dma_unmap_single_attrs(dev, pp->msi_data, sizeof(pp->msi_msg),
271 DMA_FROM_DEVICE, DMA_ATTR_SKIP_CPU_SYNC);
272 }
273 }
274
dw_pcie_msi_init(struct pcie_port * pp)275 static void dw_pcie_msi_init(struct pcie_port *pp)
276 {
277 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
278 u64 msi_target = (u64)pp->msi_data;
279
280 if (!pci_msi_enabled() || !pp->has_msi_ctrl)
281 return;
282
283 /* Program the msi_data */
284 dw_pcie_writel_dbi(pci, PCIE_MSI_ADDR_LO, lower_32_bits(msi_target));
285 dw_pcie_writel_dbi(pci, PCIE_MSI_ADDR_HI, upper_32_bits(msi_target));
286 }
287
dw_pcie_host_init(struct pcie_port * pp)288 int dw_pcie_host_init(struct pcie_port *pp)
289 {
290 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
291 struct device *dev = pci->dev;
292 struct device_node *np = dev->of_node;
293 struct platform_device *pdev = to_platform_device(dev);
294 struct resource_entry *win;
295 struct pci_host_bridge *bridge;
296 struct resource *cfg_res;
297 int ret;
298
299 raw_spin_lock_init(&pci->pp.lock);
300
301 cfg_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config");
302 if (cfg_res) {
303 pp->cfg0_size = resource_size(cfg_res);
304 pp->cfg0_base = cfg_res->start;
305
306 pp->va_cfg0_base = devm_pci_remap_cfg_resource(dev, cfg_res);
307 if (IS_ERR(pp->va_cfg0_base))
308 return PTR_ERR(pp->va_cfg0_base);
309 } else {
310 dev_err(dev, "Missing *config* reg space\n");
311 return -ENODEV;
312 }
313
314 if (!pci->dbi_base) {
315 struct resource *dbi_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
316 pci->dbi_base = devm_pci_remap_cfg_resource(dev, dbi_res);
317 if (IS_ERR(pci->dbi_base))
318 return PTR_ERR(pci->dbi_base);
319 }
320
321 bridge = devm_pci_alloc_host_bridge(dev, 0);
322 if (!bridge)
323 return -ENOMEM;
324
325 pp->bridge = bridge;
326
327 /* Get the I/O range from DT */
328 win = resource_list_first_type(&bridge->windows, IORESOURCE_IO);
329 if (win) {
330 pp->io_size = resource_size(win->res);
331 pp->io_bus_addr = win->res->start - win->offset;
332 pp->io_base = pci_pio_to_address(win->res->start);
333 }
334
335 if (pci->link_gen < 1)
336 pci->link_gen = of_pci_get_max_link_speed(np);
337
338 /* Set default bus ops */
339 bridge->ops = &dw_pcie_ops;
340 bridge->child_ops = &dw_child_pcie_ops;
341
342 if (pp->ops->host_init) {
343 ret = pp->ops->host_init(pp);
344 if (ret)
345 return ret;
346 }
347
348 if (pci_msi_enabled()) {
349 pp->has_msi_ctrl = !(pp->ops->msi_host_init ||
350 of_property_read_bool(np, "msi-parent") ||
351 of_property_read_bool(np, "msi-map"));
352
353 if (!pp->num_vectors) {
354 pp->num_vectors = MSI_DEF_NUM_VECTORS;
355 } else if (pp->num_vectors > MAX_MSI_IRQS) {
356 dev_err(dev, "Invalid number of vectors\n");
357 return -EINVAL;
358 }
359
360 if (pp->ops->msi_host_init) {
361 ret = pp->ops->msi_host_init(pp);
362 if (ret < 0)
363 return ret;
364 } else if (pp->has_msi_ctrl) {
365 if (!pp->msi_irq) {
366 pp->msi_irq = platform_get_irq_byname_optional(pdev, "msi");
367 if (pp->msi_irq < 0) {
368 pp->msi_irq = platform_get_irq(pdev, 0);
369 if (pp->msi_irq < 0)
370 return pp->msi_irq;
371 }
372 }
373
374 pp->msi_irq_chip = &dw_pci_msi_bottom_irq_chip;
375
376 ret = dw_pcie_allocate_domains(pp);
377 if (ret)
378 return ret;
379
380 if (pp->msi_irq > 0)
381 irq_set_chained_handler_and_data(pp->msi_irq,
382 dw_chained_msi_isr,
383 pp);
384
385 ret = dma_set_mask(pci->dev, DMA_BIT_MASK(32));
386 if (ret)
387 dev_warn(pci->dev, "Failed to set DMA mask to 32-bit. Devices with only 32-bit MSI support may not work properly\n");
388
389 pp->msi_data = dma_map_single_attrs(pci->dev, &pp->msi_msg,
390 sizeof(pp->msi_msg),
391 DMA_FROM_DEVICE,
392 DMA_ATTR_SKIP_CPU_SYNC);
393 if (dma_mapping_error(pci->dev, pp->msi_data)) {
394 dev_err(pci->dev, "Failed to map MSI data\n");
395 pp->msi_data = 0;
396 goto err_free_msi;
397 }
398 }
399 }
400
401 dw_pcie_iatu_detect(pci);
402
403 dw_pcie_setup_rc(pp);
404
405 if (!dw_pcie_link_up(pci) && pci->ops && pci->ops->start_link) {
406 ret = pci->ops->start_link(pci);
407 if (ret)
408 goto err_free_msi;
409 }
410
411 /* Ignore errors, the link may come up later */
412 dw_pcie_wait_for_link(pci);
413
414 bridge->sysdata = pp;
415
416 ret = pci_host_probe(bridge);
417 if (!ret)
418 return 0;
419
420 err_free_msi:
421 if (pp->has_msi_ctrl)
422 dw_pcie_free_msi(pp);
423 return ret;
424 }
425 EXPORT_SYMBOL_GPL(dw_pcie_host_init);
426
dw_pcie_host_deinit(struct pcie_port * pp)427 void dw_pcie_host_deinit(struct pcie_port *pp)
428 {
429 pci_stop_root_bus(pp->bridge->bus);
430 pci_remove_root_bus(pp->bridge->bus);
431 if (pp->has_msi_ctrl)
432 dw_pcie_free_msi(pp);
433 }
434 EXPORT_SYMBOL_GPL(dw_pcie_host_deinit);
435
dw_pcie_other_conf_map_bus(struct pci_bus * bus,unsigned int devfn,int where)436 static void __iomem *dw_pcie_other_conf_map_bus(struct pci_bus *bus,
437 unsigned int devfn, int where)
438 {
439 int type;
440 u32 busdev;
441 struct pcie_port *pp = bus->sysdata;
442 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
443
444 /*
445 * Checking whether the link is up here is a last line of defense
446 * against platforms that forward errors on the system bus as
447 * SError upon PCI configuration transactions issued when the link
448 * is down. This check is racy by definition and does not stop
449 * the system from triggering an SError if the link goes down
450 * after this check is performed.
451 */
452 if (!dw_pcie_link_up(pci))
453 return NULL;
454
455 busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) |
456 PCIE_ATU_FUNC(PCI_FUNC(devfn));
457
458 if (pci_is_root_bus(bus->parent))
459 type = PCIE_ATU_TYPE_CFG0;
460 else
461 type = PCIE_ATU_TYPE_CFG1;
462
463
464 dw_pcie_prog_outbound_atu(pci, 0, type, pp->cfg0_base, busdev, pp->cfg0_size);
465
466 return pp->va_cfg0_base + where;
467 }
468
dw_pcie_rd_other_conf(struct pci_bus * bus,unsigned int devfn,int where,int size,u32 * val)469 static int dw_pcie_rd_other_conf(struct pci_bus *bus, unsigned int devfn,
470 int where, int size, u32 *val)
471 {
472 int ret;
473 struct pcie_port *pp = bus->sysdata;
474 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
475
476 ret = pci_generic_config_read(bus, devfn, where, size, val);
477
478 if (!ret && pci->io_cfg_atu_shared)
479 dw_pcie_prog_outbound_atu(pci, 0, PCIE_ATU_TYPE_IO, pp->io_base,
480 pp->io_bus_addr, pp->io_size);
481
482 return ret;
483 }
484
dw_pcie_wr_other_conf(struct pci_bus * bus,unsigned int devfn,int where,int size,u32 val)485 static int dw_pcie_wr_other_conf(struct pci_bus *bus, unsigned int devfn,
486 int where, int size, u32 val)
487 {
488 int ret;
489 struct pcie_port *pp = bus->sysdata;
490 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
491
492 ret = pci_generic_config_write(bus, devfn, where, size, val);
493
494 if (!ret && pci->io_cfg_atu_shared)
495 dw_pcie_prog_outbound_atu(pci, 0, PCIE_ATU_TYPE_IO, pp->io_base,
496 pp->io_bus_addr, pp->io_size);
497
498 return ret;
499 }
500
501 static struct pci_ops dw_child_pcie_ops = {
502 .map_bus = dw_pcie_other_conf_map_bus,
503 .read = dw_pcie_rd_other_conf,
504 .write = dw_pcie_wr_other_conf,
505 };
506
dw_pcie_own_conf_map_bus(struct pci_bus * bus,unsigned int devfn,int where)507 void __iomem *dw_pcie_own_conf_map_bus(struct pci_bus *bus, unsigned int devfn, int where)
508 {
509 struct pcie_port *pp = bus->sysdata;
510 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
511
512 if (PCI_SLOT(devfn) > 0)
513 return NULL;
514
515 return pci->dbi_base + where;
516 }
517 EXPORT_SYMBOL_GPL(dw_pcie_own_conf_map_bus);
518
519 static struct pci_ops dw_pcie_ops = {
520 .map_bus = dw_pcie_own_conf_map_bus,
521 .read = pci_generic_config_read,
522 .write = pci_generic_config_write,
523 };
524
dw_pcie_setup_rc(struct pcie_port * pp)525 void dw_pcie_setup_rc(struct pcie_port *pp)
526 {
527 int i;
528 u32 val, ctrl, num_ctrls;
529 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
530
531 /*
532 * Enable DBI read-only registers for writing/updating configuration.
533 * Write permission gets disabled towards the end of this function.
534 */
535 dw_pcie_dbi_ro_wr_en(pci);
536
537 dw_pcie_setup(pci);
538
539 if (pp->has_msi_ctrl) {
540 num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL;
541
542 /* Initialize IRQ Status array */
543 for (ctrl = 0; ctrl < num_ctrls; ctrl++) {
544 pp->irq_mask[ctrl] = ~0;
545 dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_MASK +
546 (ctrl * MSI_REG_CTRL_BLOCK_SIZE),
547 pp->irq_mask[ctrl]);
548 dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_ENABLE +
549 (ctrl * MSI_REG_CTRL_BLOCK_SIZE),
550 ~0);
551 }
552 }
553
554 dw_pcie_msi_init(pp);
555
556 /* Setup RC BARs */
557 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0x00000004);
558 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_1, 0x00000000);
559
560 /* Setup interrupt pins */
561 val = dw_pcie_readl_dbi(pci, PCI_INTERRUPT_LINE);
562 val &= 0xffff00ff;
563 val |= 0x00000100;
564 dw_pcie_writel_dbi(pci, PCI_INTERRUPT_LINE, val);
565
566 /* Setup bus numbers */
567 val = dw_pcie_readl_dbi(pci, PCI_PRIMARY_BUS);
568 val &= 0xff000000;
569 val |= 0x00ff0100;
570 dw_pcie_writel_dbi(pci, PCI_PRIMARY_BUS, val);
571
572 /* Setup command register */
573 val = dw_pcie_readl_dbi(pci, PCI_COMMAND);
574 val &= 0xffff0000;
575 val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
576 PCI_COMMAND_MASTER | PCI_COMMAND_SERR;
577 dw_pcie_writel_dbi(pci, PCI_COMMAND, val);
578
579 /* Ensure all outbound windows are disabled so there are multiple matches */
580 for (i = 0; i < pci->num_ob_windows; i++)
581 dw_pcie_disable_atu(pci, i, DW_PCIE_REGION_OUTBOUND);
582
583 /*
584 * If the platform provides its own child bus config accesses, it means
585 * the platform uses its own address translation component rather than
586 * ATU, so we should not program the ATU here.
587 */
588 if (pp->bridge->child_ops == &dw_child_pcie_ops) {
589 int atu_idx = 0;
590 struct resource_entry *entry;
591
592 /* Get last memory resource entry */
593 resource_list_for_each_entry(entry, &pp->bridge->windows) {
594 if (resource_type(entry->res) != IORESOURCE_MEM)
595 continue;
596
597 if (pci->num_ob_windows <= ++atu_idx)
598 break;
599
600 dw_pcie_prog_outbound_atu(pci, atu_idx,
601 PCIE_ATU_TYPE_MEM, entry->res->start,
602 entry->res->start - entry->offset,
603 resource_size(entry->res));
604 }
605
606 if (pp->io_size) {
607 if (pci->num_ob_windows > ++atu_idx)
608 dw_pcie_prog_outbound_atu(pci, atu_idx,
609 PCIE_ATU_TYPE_IO, pp->io_base,
610 pp->io_bus_addr, pp->io_size);
611 else
612 pci->io_cfg_atu_shared = true;
613 }
614
615 if (pci->num_ob_windows <= atu_idx)
616 dev_warn(pci->dev, "Resources exceed number of ATU entries (%d)",
617 pci->num_ob_windows);
618 }
619
620 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0);
621
622 /* Program correct class for RC */
623 dw_pcie_writew_dbi(pci, PCI_CLASS_DEVICE, PCI_CLASS_BRIDGE_PCI);
624
625 val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
626 val |= PORT_LOGIC_SPEED_CHANGE;
627 dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val);
628
629 dw_pcie_dbi_ro_wr_dis(pci);
630 }
631 EXPORT_SYMBOL_GPL(dw_pcie_setup_rc);
632