1/*
2 * Gazerbeam Device Tree Source
3 *
4 * (C) Copyright 2015
5 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
6 *
7 * This program is free software; you can redistribute  it and/or modify it
8 * under  the terms of  the GNU General  Public License as published by the
9 * Free Software Foundation;  either version 2 of the  License, or (at your
10 * option) any later version.
11 */
12
13/ {
14	model = "gdsys,gazerbeam";
15	compatible = "fsl,mpc8308rdb";
16
17	aliases {
18		ethernet0 = &enet0;
19		ethernet1 = &enet1;
20	};
21
22	memory {
23		device_type = "memory";
24	};
25};
26
27&enet1 {
28	status = "okay";
29};
30
31&IIC {
32	fsl,preserve-clocking;
33
34	at97sc3205t@29 {
35		compatible = "atmel,at97sc3204t";
36		reg = <0x29>;
37	};
38
39	lm77@48 {
40		compatible = "national,lm77";
41		reg = <0x48>;
42	};
43
44	ads1015@49 {
45		compatible = "ti,ads1015";
46		reg = <0x49>;
47	};
48
49	lm77@4a {
50		compatible = "national,lm77";
51		reg = <0x4a>;
52	};
53
54	emc2305@2e {
55		compatible = "smsc,emc2305";
56		#address-cells = <1>;
57		#size-cells = <0>;
58		reg = <0x2e>;
59		fan@0 {
60			reg = <0>;
61		};
62		fan@1 {
63			reg = <1>;
64		};
65		fan@2 {
66			reg = <2>;
67		};
68		fan@3 {
69			reg = <3>;
70		};
71		fan@4 {
72			reg = <4>;
73		};
74	};
75
76	emc2305@4c {
77		compatible = "smsc,emc2305";
78		#address-cells = <1>;
79		#size-cells = <0>;
80		reg = <0x4c>;
81		fan@0 {
82			reg = <0>;
83		};
84		fan@1 {
85			reg = <1>;
86		};
87		fan@2 {
88			reg = <2>;
89		};
90		fan@3 {
91			reg = <3>;
92		};
93		fan@4 {
94			reg = <4>;
95		};
96	};
97
98	at24c512@54 {
99		compatible = "atmel,24c512";
100		reg = <0x54>;
101	};
102
103	/* PPC-Board */
104	pca9698@22 {
105		compatible = "nxp,pca9698";
106		reg = <0x22>;
107		#gpio-cells = <2>;
108		gpio-controller;
109	};
110
111	/* IO-Board */
112	pca9698@20 {
113		compatible = "nxp,pca9698";
114		reg = <0x20>;
115		#gpio-cells = <2>;
116		gpio-controller;
117	};
118};
119
120&IIC2 {
121	fsl,preserve-clocking;
122
123	status = "okay";
124
125	/* MC2/SC-Board */
126	GPIO_VB0: pca9698@20 {
127		compatible = "nxp,pca9698";
128		reg = <0x20>;
129		#gpio-cells = <2>;
130		gpio-controller;
131	};
132
133	/* MC4-Board */
134	GPIO_VB1: pca9698@22 {
135		compatible = "nxp,pca9698";
136		reg = <0x22>;
137		#gpio-cells = <2>;
138		gpio-controller;
139	};
140};
141
142&SPI {
143	gpios = < /*SPI-CSS-FPGA-U-FLASH#*/ &gpio0 8 0
144		  /*SPI-CSS-FPGA-O-FLASH#*/ &gpio0 6 0
145		  /*SPI-CSS-STDP1_U-FLASH#*/ &gpio0 12 0
146		  /*SPI-CSS-STDP2_U-FLASH#*/ &gpio0 11 0
147		  /*SPI-CSS-STDP1_O-FLASH#*/ &gpio0 15 0
148		  /*SPI-CSS-STDP2_O-FLASH#*/ &gpio0 3 0>;
149
150	m25p16@0 {
151		compatible = "st,n25q128a11";
152		reg = <0x0>;
153		spi-max-frequency = <20000000>;
154	};
155
156	m25p16@1 {
157		compatible = "st,n25q128a11";
158		reg = <0x1>;
159		spi-max-frequency = <20000000>;
160	};
161
162	m25p16@2 {
163		compatible = "st,m25p40";
164		reg = <0x2>;
165		spi-max-frequency = <20000000>;
166	};
167
168	m25p16@3 {
169		compatible = "st,m25p40";
170		reg = <0x3>;
171		spi-max-frequency = <20000000>;
172	};
173
174	m25p16@4 {
175		compatible = "st,m25p40";
176		reg = <0x4>;
177		spi-max-frequency = <20000000>;
178	};
179
180	m25p16@5 {
181		compatible = "st,m25p40";
182		reg = <0x5>;
183		spi-max-frequency = <20000000>;
184	};
185};
186