1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2015 Freescale Semiconductor 4 * Copyright 2019-2020 NXP 5 */ 6 7 #ifndef __LS1043A_COMMON_H 8 #define __LS1043A_COMMON_H 9 10 /* SPL build */ 11 #ifdef CONFIG_SPL_BUILD 12 #define SPL_NO_FMAN 13 #define SPL_NO_DSPI 14 #define SPL_NO_PCIE 15 #define SPL_NO_ENV 16 #define SPL_NO_MISC 17 #define SPL_NO_USB 18 #define SPL_NO_SATA 19 #define SPL_NO_QE 20 #define SPL_NO_EEPROM 21 #endif 22 #if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_NAND_BOOT)) 23 #define SPL_NO_MMC 24 #endif 25 #if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SD_BOOT_QSPI)) 26 #define SPL_NO_IFC 27 #endif 28 29 #define CONFIG_REMAKE_ELF 30 #define CONFIG_GICV2 31 32 #include <asm/arch/stream_id_lsch2.h> 33 #include <asm/arch/config.h> 34 35 /* Link Definitions */ 36 #ifdef CONFIG_TFABOOT 37 #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE 38 #else 39 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) 40 #endif 41 42 #define CONFIG_SKIP_LOWLEVEL_INIT 43 44 #define CONFIG_VERY_BIG_RAM 45 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 46 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 47 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 48 #define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL 49 50 #define CPU_RELEASE_ADDR secondary_boot_addr 51 52 /* Generic Timer Definitions */ 53 #define COUNTER_FREQUENCY 25000000 /* 25MHz */ 54 55 /* Size of malloc() pool */ 56 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024) 57 58 /* Serial Port */ 59 #define CONFIG_SYS_NS16550_SERIAL 60 #define CONFIG_SYS_NS16550_REG_SIZE 1 61 #define CONFIG_SYS_NS16550_CLK (get_serial_clock()) 62 63 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 64 65 /* SD boot SPL */ 66 #ifdef CONFIG_SD_BOOT 67 68 #define CONFIG_SPL_MAX_SIZE 0x17000 69 #define CONFIG_SPL_STACK 0x1001e000 70 #define CONFIG_SPL_PAD_TO 0x1d000 71 72 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ 73 CONFIG_SPL_BSS_MAX_SIZE) 74 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 75 #define CONFIG_SPL_BSS_START_ADDR 0x8f000000 76 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 77 78 #ifdef CONFIG_NXP_ESBC 79 #define CONFIG_U_BOOT_HDR_SIZE (16 << 10) 80 /* 81 * HDR would be appended at end of image and copied to DDR along 82 * with U-Boot image. Here u-boot max. size is 512K. So if binary 83 * size increases then increase this size in case of secure boot as 84 * it uses raw u-boot image instead of fit image. 85 */ 86 #define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE) 87 #else 88 #define CONFIG_SYS_MONITOR_LEN 0x100000 89 #endif /* ifdef CONFIG_NXP_ESBC */ 90 #endif 91 92 /* NAND SPL */ 93 #ifdef CONFIG_NAND_BOOT 94 #define CONFIG_SPL_PBL_PAD 95 #define CONFIG_SPL_MAX_SIZE 0x1a000 96 #define CONFIG_SPL_STACK 0x1001d000 97 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE 98 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 99 #define CONFIG_SYS_SPL_MALLOC_START 0x80200000 100 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 101 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 102 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 103 104 #ifdef CONFIG_NXP_ESBC 105 #define CONFIG_U_BOOT_HDR_SIZE (16 << 10) 106 #endif /* ifdef CONFIG_NXP_ESBC */ 107 108 #ifdef CONFIG_U_BOOT_HDR_SIZE 109 /* 110 * HDR would be appended at end of image and copied to DDR along 111 * with U-Boot image. Here u-boot max. size is 512K. So if binary 112 * size increases then increase this size in case of secure boot as 113 * it uses raw u-boot image instead of fit image. 114 */ 115 #define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE) 116 #else 117 #define CONFIG_SYS_MONITOR_LEN 0x100000 118 #endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */ 119 120 #endif 121 122 /* GPIO */ 123 #ifdef CONFIG_DM_GPIO 124 #ifndef CONFIG_MPC8XXX_GPIO 125 #define CONFIG_MPC8XXX_GPIO 126 #endif 127 #endif 128 129 /* IFC */ 130 #ifndef SPL_NO_IFC 131 #if defined(CONFIG_TFABOOT) || \ 132 (!defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)) 133 #define CONFIG_FSL_IFC 134 /* 135 * CONFIG_SYS_FLASH_BASE has the final address (core view) 136 * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view) 137 * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address 138 * CONFIG_SYS_TEXT_BASE is linked to 0x60000000 for booting 139 */ 140 #define CONFIG_SYS_FLASH_BASE 0x60000000 141 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 142 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000 143 144 #ifdef CONFIG_MTD_NOR_FLASH 145 #define CONFIG_SYS_FLASH_QUIET_TEST 146 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 147 #endif 148 #endif 149 #endif 150 151 /* I2C */ 152 #if !CONFIG_IS_ENABLED(DM_I2C) 153 #define CONFIG_SYS_I2C 154 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ 155 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ 156 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ 157 #define CONFIG_SYS_I2C_MXC_I2C4 /* enable I2C bus 4 */ 158 #else 159 #define CONFIG_I2C_SET_DEFAULT_BUS_NUM 160 #define CONFIG_I2C_DEFAULT_BUS_NUMBER 0 161 #endif 162 163 /* PCIe */ 164 #ifndef SPL_NO_PCIE 165 #define CONFIG_PCIE1 /* PCIE controller 1 */ 166 #define CONFIG_PCIE2 /* PCIE controller 2 */ 167 #define CONFIG_PCIE3 /* PCIE controller 3 */ 168 169 #ifdef CONFIG_PCI 170 #define CONFIG_PCI_SCAN_SHOW 171 #endif 172 #endif 173 174 /* MMC */ 175 #ifndef SPL_NO_MMC 176 #ifdef CONFIG_MMC 177 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 178 #endif 179 #endif 180 181 /* DSPI */ 182 #ifndef SPL_NO_DSPI 183 #ifdef CONFIG_FSL_DSPI 184 #define CONFIG_SPI_FLASH_STMICRO /* cs0 */ 185 #define CONFIG_SPI_FLASH_SST /* cs1 */ 186 #define CONFIG_SPI_FLASH_EON /* cs2 */ 187 #endif 188 #endif 189 190 /* FMan ucode */ 191 #ifndef SPL_NO_FMAN 192 #define CONFIG_SYS_DPAA_FMAN 193 #ifdef CONFIG_SYS_DPAA_FMAN 194 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 195 196 #ifdef CONFIG_TFABOOT 197 #define CONFIG_SYS_FMAN_FW_ADDR 0x900000 198 #define CONFIG_SYS_QE_FW_ADDR 0x940000 199 200 201 #else 202 #ifdef CONFIG_NAND_BOOT 203 /* Store Fman ucode at offeset 0x900000(72 blocks). */ 204 #define CONFIG_SYS_FMAN_FW_ADDR (72 * CONFIG_SYS_NAND_BLOCK_SIZE) 205 #elif defined(CONFIG_SD_BOOT) 206 /* 207 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 208 * about 1MB (2040 blocks), Env is stored after the image, and the env size is 209 * 0x2000 (16 blocks), 8 + 2040 + 16 = 2064, enlarge it to 18432(0x4800). 210 */ 211 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x4800) 212 #define CONFIG_SYS_QE_FW_ADDR (512 * 0x4A00) 213 #elif defined(CONFIG_QSPI_BOOT) 214 #define CONFIG_SYS_FMAN_FW_ADDR 0x40900000 215 #else 216 /* FMan fireware Pre-load address */ 217 #define CONFIG_SYS_FMAN_FW_ADDR 0x60900000 218 #define CONFIG_SYS_QE_FW_ADDR 0x60940000 219 #endif 220 #endif 221 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 222 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 223 #endif 224 #endif 225 226 /* Miscellaneous configurable options */ 227 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000) 228 229 #define CONFIG_HWCONFIG 230 #define HWCONFIG_BUFFER_SIZE 128 231 232 #ifndef SPL_NO_MISC 233 #ifndef CONFIG_SPL_BUILD 234 #define BOOT_TARGET_DEVICES(func) \ 235 func(MMC, mmc, 0) \ 236 func(USB, usb, 0) \ 237 func(DHCP, dhcp, na) 238 #include <config_distro_bootcmd.h> 239 #endif 240 241 /* Initial environment variables */ 242 #define CONFIG_EXTRA_ENV_SETTINGS \ 243 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 244 "fdt_high=0xffffffffffffffff\0" \ 245 "initrd_high=0xffffffffffffffff\0" \ 246 "fdt_addr=0x64f00000\0" \ 247 "kernel_addr=0x61000000\0" \ 248 "scriptaddr=0x80000000\0" \ 249 "scripthdraddr=0x80080000\0" \ 250 "fdtheader_addr_r=0x80100000\0" \ 251 "kernelheader_addr_r=0x80200000\0" \ 252 "kernel_addr_r=0x81000000\0" \ 253 "kernel_start=0x1000000\0" \ 254 "kernelheader_start=0x800000\0" \ 255 "fdt_addr_r=0x90000000\0" \ 256 "load_addr=0xa0000000\0" \ 257 "kernelheader_addr=0x60600000\0" \ 258 "kernel_size=0x2800000\0" \ 259 "kernelheader_size=0x40000\0" \ 260 "kernel_addr_sd=0x8000\0" \ 261 "kernel_size_sd=0x14000\0" \ 262 "kernelhdr_addr_sd=0x3000\0" \ 263 "kernelhdr_size_sd=0x10\0" \ 264 "console=ttyS0,115200\0" \ 265 "boot_os=y\0" \ 266 "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ 267 BOOTENV \ 268 "boot_scripts=ls1043ardb_boot.scr\0" \ 269 "boot_script_hdr=hdr_ls1043ardb_bs.out\0" \ 270 "scan_dev_for_boot_part=" \ 271 "part list ${devtype} ${devnum} devplist; " \ 272 "env exists devplist || setenv devplist 1; " \ 273 "for distro_bootpart in ${devplist}; do " \ 274 "if fstype ${devtype} " \ 275 "${devnum}:${distro_bootpart} " \ 276 "bootfstype; then " \ 277 "run scan_dev_for_boot; " \ 278 "fi; " \ 279 "done\0" \ 280 "boot_a_script=" \ 281 "load ${devtype} ${devnum}:${distro_bootpart} " \ 282 "${scriptaddr} ${prefix}${script}; " \ 283 "env exists secureboot && load ${devtype} " \ 284 "${devnum}:${distro_bootpart} " \ 285 "${scripthdraddr} ${prefix}${boot_script_hdr}; " \ 286 "env exists secureboot " \ 287 "&& esbc_validate ${scripthdraddr};" \ 288 "source ${scriptaddr}\0" \ 289 "qspi_bootcmd=echo Trying load from qspi..;" \ 290 "sf probe && sf read $load_addr " \ 291 "$kernel_start $kernel_size; env exists secureboot " \ 292 "&& sf read $kernelheader_addr_r $kernelheader_start " \ 293 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \ 294 "bootm $load_addr#$board\0" \ 295 "nor_bootcmd=echo Trying load from nor..;" \ 296 "cp.b $kernel_addr $load_addr " \ 297 "$kernel_size; env exists secureboot " \ 298 "&& cp.b $kernelheader_addr $kernelheader_addr_r " \ 299 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \ 300 "bootm $load_addr#$board\0" \ 301 "nand_bootcmd=echo Trying load from NAND..;" \ 302 "nand info; nand read $load_addr " \ 303 "$kernel_start $kernel_size; env exists secureboot " \ 304 "&& nand read $kernelheader_addr_r $kernelheader_start " \ 305 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \ 306 "bootm $load_addr#$board\0" \ 307 "sd_bootcmd=echo Trying load from SD ..;" \ 308 "mmcinfo; mmc read $load_addr " \ 309 "$kernel_addr_sd $kernel_size_sd && " \ 310 "env exists secureboot && mmc read $kernelheader_addr_r " \ 311 "$kernelhdr_addr_sd $kernelhdr_size_sd " \ 312 " && esbc_validate ${kernelheader_addr_r};" \ 313 "bootm $load_addr#$board\0" 314 315 316 #undef CONFIG_BOOTCOMMAND 317 #ifdef CONFIG_TFABOOT 318 #define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \ 319 "env exists secureboot && esbc_halt;" 320 #define SD_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; " \ 321 "env exists secureboot && esbc_halt;" 322 #define IFC_NOR_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; " \ 323 "env exists secureboot && esbc_halt;" 324 #define IFC_NAND_BOOTCOMMAND "run distro_bootcmd; run nand_bootcmd; " \ 325 "env exists secureboot && esbc_halt;" 326 #else 327 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 328 #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \ 329 "env exists secureboot && esbc_halt;" 330 #elif defined(CONFIG_SD_BOOT) 331 #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; " \ 332 "env exists secureboot && esbc_halt;" 333 #else 334 #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; " \ 335 "env exists secureboot && esbc_halt;" 336 #endif 337 #endif 338 #endif 339 340 /* Monitor Command Prompt */ 341 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 342 343 #define CONFIG_SYS_MAXARGS 64 /* max command args */ 344 345 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 346 347 #include <asm/arch/soc.h> 348 349 #endif /* __LS1043A_COMMON_H */ 350