1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2009-2012 Freescale Semiconductor, Inc.
4 * Copyright 2020 NXP
5 * Dave Liu <daveliu@freescale.com>
6 */
7 #include <common.h>
8 #include <log.h>
9 #include <part.h>
10 #include <asm/io.h>
11 #ifdef CONFIG_DM_ETH
12 #include <dm.h>
13 #include <dm/ofnode.h>
14 #include <linux/compat.h>
15 #include <phy_interface.h>
16 #endif
17 #include <malloc.h>
18 #include <net.h>
19 #include <hwconfig.h>
20 #include <fm_eth.h>
21 #include <fsl_mdio.h>
22 #include <miiphy.h>
23 #include <phy.h>
24 #include <fsl_dtsec.h>
25 #include <fsl_tgec.h>
26 #include <fsl_memac.h>
27 #include <linux/delay.h>
28
29 #include "fm.h"
30
31 #ifndef CONFIG_DM_ETH
32 static struct eth_device *devlist[NUM_FM_PORTS];
33 static int num_controllers;
34 #endif
35
36 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) && !defined(BITBANGMII)
37
38 #define TBIANA_SETTINGS (TBIANA_ASYMMETRIC_PAUSE | TBIANA_SYMMETRIC_PAUSE | \
39 TBIANA_FULL_DUPLEX)
40
41 #define TBIANA_SGMII_ACK 0x4001
42
43 #define TBICR_SETTINGS (TBICR_ANEG_ENABLE | TBICR_RESTART_ANEG | \
44 TBICR_FULL_DUPLEX | TBICR_SPEED1_SET)
45
46 /* Configure the TBI for SGMII operation */
dtsec_configure_serdes(struct fm_eth * priv)47 static void dtsec_configure_serdes(struct fm_eth *priv)
48 {
49 #ifdef CONFIG_SYS_FMAN_V3
50 u32 value;
51 struct mii_dev bus;
52 bool sgmii_2500 = (priv->enet_if ==
53 PHY_INTERFACE_MODE_SGMII_2500) ? true : false;
54 int i = 0, j;
55
56 #ifndef CONFIG_DM_ETH
57 bus.priv = priv->mac->phyregs;
58 #else
59 bus.priv = priv->pcs_mdio;
60 bus.read = memac_mdio_read;
61 bus.write = memac_mdio_write;
62 bus.reset = memac_mdio_reset;
63 #endif
64
65 qsgmii_loop:
66 /* SGMII IF mode + AN enable only for 1G SGMII, not for 2.5G */
67 if (sgmii_2500)
68 value = PHY_SGMII_CR_PHY_RESET |
69 PHY_SGMII_IF_SPEED_GIGABIT |
70 PHY_SGMII_IF_MODE_SGMII;
71 else
72 value = PHY_SGMII_IF_MODE_SGMII | PHY_SGMII_IF_MODE_AN;
73
74 for (j = 0; j <= 3; j++)
75 debug("dump PCS reg %#x: %#x\n", j,
76 memac_mdio_read(&bus, i, MDIO_DEVAD_NONE, j));
77
78 memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x14, value);
79
80 /* Dev ability according to SGMII specification */
81 value = PHY_SGMII_DEV_ABILITY_SGMII;
82 memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x4, value);
83
84 if (sgmii_2500) {
85 /* Adjust link timer for 2.5G SGMII,
86 * 1.6 ms in units of 3.2 ns:
87 * 1.6ms / 3.2ns = 5 * 10^5 = 0x7a120.
88 */
89 memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x13, 0x0007);
90 memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x12, 0xa120);
91 } else {
92 /* Adjust link timer for SGMII,
93 * 1.6 ms in units of 8 ns:
94 * 1.6ms / 8ns = 2 * 10^5 = 0x30d40.
95 */
96 memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x13, 0x0003);
97 memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x12, 0x0d40);
98 }
99
100 /* Restart AN */
101 value = PHY_SGMII_CR_DEF_VAL | PHY_SGMII_CR_RESET_AN;
102 memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0, value);
103
104 if ((priv->enet_if == PHY_INTERFACE_MODE_QSGMII) && (i < 3)) {
105 i++;
106 goto qsgmii_loop;
107 }
108 #else
109 struct dtsec *regs = priv->mac->base;
110 struct tsec_mii_mng *phyregs = priv->mac->phyregs;
111
112 /*
113 * Access TBI PHY registers at given TSEC register offset as
114 * opposed to the register offset used for external PHY accesses
115 */
116 tsec_local_mdio_write(phyregs, in_be32(®s->tbipa), 0, TBI_TBICON,
117 TBICON_CLK_SELECT);
118 tsec_local_mdio_write(phyregs, in_be32(®s->tbipa), 0, TBI_ANA,
119 TBIANA_SGMII_ACK);
120 tsec_local_mdio_write(phyregs, in_be32(®s->tbipa), 0,
121 TBI_CR, TBICR_SETTINGS);
122 #endif
123 }
124
dtsec_init_phy(struct fm_eth * fm_eth)125 static void dtsec_init_phy(struct fm_eth *fm_eth)
126 {
127 #ifndef CONFIG_SYS_FMAN_V3
128 struct dtsec *regs = (struct dtsec *)CONFIG_SYS_FSL_FM1_DTSEC1_ADDR;
129
130 /* Assign a Physical address to the TBI */
131 out_be32(®s->tbipa, CONFIG_SYS_TBIPA_VALUE);
132 #endif
133
134 if (fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII ||
135 fm_eth->enet_if == PHY_INTERFACE_MODE_QSGMII ||
136 fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII_2500)
137 dtsec_configure_serdes(fm_eth);
138 }
139
140 #ifndef CONFIG_DM_ETH
141 #ifdef CONFIG_PHYLIB
tgec_is_fibre(struct fm_eth * fm)142 static int tgec_is_fibre(struct fm_eth *fm)
143 {
144 char phyopt[20];
145
146 sprintf(phyopt, "fsl_fm%d_xaui_phy", fm->fm_index + 1);
147
148 return hwconfig_arg_cmp(phyopt, "xfi");
149 }
150 #endif
151 #endif /* CONFIG_DM_ETH */
152 #endif
153
muram_readw(u16 * addr)154 static u16 muram_readw(u16 *addr)
155 {
156 ulong base = (ulong)addr & ~0x3UL;
157 u32 val32 = in_be32((void *)base);
158 int byte_pos;
159 u16 ret;
160
161 byte_pos = (ulong)addr & 0x3UL;
162 if (byte_pos)
163 ret = (u16)(val32 & 0x0000ffff);
164 else
165 ret = (u16)((val32 & 0xffff0000) >> 16);
166
167 return ret;
168 }
169
muram_writew(u16 * addr,u16 val)170 static void muram_writew(u16 *addr, u16 val)
171 {
172 ulong base = (ulong)addr & ~0x3UL;
173 u32 org32 = in_be32((void *)base);
174 u32 val32;
175 int byte_pos;
176
177 byte_pos = (ulong)addr & 0x3UL;
178 if (byte_pos)
179 val32 = (org32 & 0xffff0000) | val;
180 else
181 val32 = (org32 & 0x0000ffff) | ((u32)val << 16);
182
183 out_be32((void *)base, val32);
184 }
185
bmi_rx_port_disable(struct fm_bmi_rx_port * rx_port)186 static void bmi_rx_port_disable(struct fm_bmi_rx_port *rx_port)
187 {
188 int timeout = 1000000;
189
190 clrbits_be32(&rx_port->fmbm_rcfg, FMBM_RCFG_EN);
191
192 /* wait until the rx port is not busy */
193 while ((in_be32(&rx_port->fmbm_rst) & FMBM_RST_BSY) && timeout--)
194 ;
195 if (!timeout)
196 printf("%s - timeout\n", __func__);
197 }
198
bmi_rx_port_init(struct fm_bmi_rx_port * rx_port)199 static void bmi_rx_port_init(struct fm_bmi_rx_port *rx_port)
200 {
201 /* set BMI to independent mode, Rx port disable */
202 out_be32(&rx_port->fmbm_rcfg, FMBM_RCFG_IM);
203 /* clear FOF in IM case */
204 out_be32(&rx_port->fmbm_rim, 0);
205 /* Rx frame next engine -RISC */
206 out_be32(&rx_port->fmbm_rfne, NIA_ENG_RISC | NIA_RISC_AC_IM_RX);
207 /* Rx command attribute - no order, MR[3] = 1 */
208 clrbits_be32(&rx_port->fmbm_rfca, FMBM_RFCA_ORDER | FMBM_RFCA_MR_MASK);
209 setbits_be32(&rx_port->fmbm_rfca, FMBM_RFCA_MR(4));
210 /* enable Rx statistic counters */
211 out_be32(&rx_port->fmbm_rstc, FMBM_RSTC_EN);
212 /* disable Rx performance counters */
213 out_be32(&rx_port->fmbm_rpc, 0);
214 }
215
bmi_tx_port_disable(struct fm_bmi_tx_port * tx_port)216 static void bmi_tx_port_disable(struct fm_bmi_tx_port *tx_port)
217 {
218 int timeout = 1000000;
219
220 clrbits_be32(&tx_port->fmbm_tcfg, FMBM_TCFG_EN);
221
222 /* wait until the tx port is not busy */
223 while ((in_be32(&tx_port->fmbm_tst) & FMBM_TST_BSY) && timeout--)
224 ;
225 if (!timeout)
226 printf("%s - timeout\n", __func__);
227 }
228
bmi_tx_port_init(struct fm_bmi_tx_port * tx_port)229 static void bmi_tx_port_init(struct fm_bmi_tx_port *tx_port)
230 {
231 /* set BMI to independent mode, Tx port disable */
232 out_be32(&tx_port->fmbm_tcfg, FMBM_TCFG_IM);
233 /* Tx frame next engine -RISC */
234 out_be32(&tx_port->fmbm_tfne, NIA_ENG_RISC | NIA_RISC_AC_IM_TX);
235 out_be32(&tx_port->fmbm_tfene, NIA_ENG_RISC | NIA_RISC_AC_IM_TX);
236 /* Tx command attribute - no order, MR[3] = 1 */
237 clrbits_be32(&tx_port->fmbm_tfca, FMBM_TFCA_ORDER | FMBM_TFCA_MR_MASK);
238 setbits_be32(&tx_port->fmbm_tfca, FMBM_TFCA_MR(4));
239 /* enable Tx statistic counters */
240 out_be32(&tx_port->fmbm_tstc, FMBM_TSTC_EN);
241 /* disable Tx performance counters */
242 out_be32(&tx_port->fmbm_tpc, 0);
243 }
244
fm_eth_rx_port_parameter_init(struct fm_eth * fm_eth)245 static int fm_eth_rx_port_parameter_init(struct fm_eth *fm_eth)
246 {
247 struct fm_port_global_pram *pram;
248 u32 pram_page_offset;
249 void *rx_bd_ring_base;
250 void *rx_buf_pool;
251 u32 bd_ring_base_lo, bd_ring_base_hi;
252 u32 buf_lo, buf_hi;
253 struct fm_port_bd *rxbd;
254 struct fm_port_qd *rxqd;
255 struct fm_bmi_rx_port *bmi_rx_port = fm_eth->rx_port;
256 int i;
257
258 /* alloc global parameter ram at MURAM */
259 pram = (struct fm_port_global_pram *)fm_muram_alloc(fm_eth->fm_index,
260 FM_PRAM_SIZE, FM_PRAM_ALIGN);
261 if (!pram) {
262 printf("%s: No muram for Rx global parameter\n", __func__);
263 return -ENOMEM;
264 }
265
266 fm_eth->rx_pram = pram;
267
268 /* parameter page offset to MURAM */
269 pram_page_offset = (void *)pram - fm_muram_base(fm_eth->fm_index);
270
271 /* enable global mode- snooping data buffers and BDs */
272 out_be32(&pram->mode, PRAM_MODE_GLOBAL);
273
274 /* init the Rx queue descriptor pionter */
275 out_be32(&pram->rxqd_ptr, pram_page_offset + 0x20);
276
277 /* set the max receive buffer length, power of 2 */
278 muram_writew(&pram->mrblr, MAX_RXBUF_LOG2);
279
280 /* alloc Rx buffer descriptors from main memory */
281 rx_bd_ring_base = malloc(sizeof(struct fm_port_bd)
282 * RX_BD_RING_SIZE);
283 if (!rx_bd_ring_base)
284 return -ENOMEM;
285
286 memset(rx_bd_ring_base, 0, sizeof(struct fm_port_bd)
287 * RX_BD_RING_SIZE);
288
289 /* alloc Rx buffer from main memory */
290 rx_buf_pool = malloc(MAX_RXBUF_LEN * RX_BD_RING_SIZE);
291 if (!rx_buf_pool)
292 return -ENOMEM;
293
294 memset(rx_buf_pool, 0, MAX_RXBUF_LEN * RX_BD_RING_SIZE);
295 debug("%s: rx_buf_pool = %p\n", __func__, rx_buf_pool);
296
297 /* save them to fm_eth */
298 fm_eth->rx_bd_ring = rx_bd_ring_base;
299 fm_eth->cur_rxbd = rx_bd_ring_base;
300 fm_eth->rx_buf = rx_buf_pool;
301
302 /* init Rx BDs ring */
303 rxbd = (struct fm_port_bd *)rx_bd_ring_base;
304 for (i = 0; i < RX_BD_RING_SIZE; i++) {
305 muram_writew(&rxbd->status, RxBD_EMPTY);
306 muram_writew(&rxbd->len, 0);
307 buf_hi = upper_32_bits(virt_to_phys(rx_buf_pool +
308 i * MAX_RXBUF_LEN));
309 buf_lo = lower_32_bits(virt_to_phys(rx_buf_pool +
310 i * MAX_RXBUF_LEN));
311 muram_writew(&rxbd->buf_ptr_hi, (u16)buf_hi);
312 out_be32(&rxbd->buf_ptr_lo, buf_lo);
313 rxbd++;
314 }
315
316 /* set the Rx queue descriptor */
317 rxqd = &pram->rxqd;
318 muram_writew(&rxqd->gen, 0);
319 bd_ring_base_hi = upper_32_bits(virt_to_phys(rx_bd_ring_base));
320 bd_ring_base_lo = lower_32_bits(virt_to_phys(rx_bd_ring_base));
321 muram_writew(&rxqd->bd_ring_base_hi, (u16)bd_ring_base_hi);
322 out_be32(&rxqd->bd_ring_base_lo, bd_ring_base_lo);
323 muram_writew(&rxqd->bd_ring_size, sizeof(struct fm_port_bd)
324 * RX_BD_RING_SIZE);
325 muram_writew(&rxqd->offset_in, 0);
326 muram_writew(&rxqd->offset_out, 0);
327
328 /* set IM parameter ram pointer to Rx Frame Queue ID */
329 out_be32(&bmi_rx_port->fmbm_rfqid, pram_page_offset);
330
331 return 0;
332 }
333
fm_eth_tx_port_parameter_init(struct fm_eth * fm_eth)334 static int fm_eth_tx_port_parameter_init(struct fm_eth *fm_eth)
335 {
336 struct fm_port_global_pram *pram;
337 u32 pram_page_offset;
338 void *tx_bd_ring_base;
339 u32 bd_ring_base_lo, bd_ring_base_hi;
340 struct fm_port_bd *txbd;
341 struct fm_port_qd *txqd;
342 struct fm_bmi_tx_port *bmi_tx_port = fm_eth->tx_port;
343 int i;
344
345 /* alloc global parameter ram at MURAM */
346 pram = (struct fm_port_global_pram *)fm_muram_alloc(fm_eth->fm_index,
347 FM_PRAM_SIZE, FM_PRAM_ALIGN);
348 if (!pram) {
349 printf("%s: No muram for Tx global parameter\n", __func__);
350 return -ENOMEM;
351 }
352 fm_eth->tx_pram = pram;
353
354 /* parameter page offset to MURAM */
355 pram_page_offset = (void *)pram - fm_muram_base(fm_eth->fm_index);
356
357 /* enable global mode- snooping data buffers and BDs */
358 out_be32(&pram->mode, PRAM_MODE_GLOBAL);
359
360 /* init the Tx queue descriptor pionter */
361 out_be32(&pram->txqd_ptr, pram_page_offset + 0x40);
362
363 /* alloc Tx buffer descriptors from main memory */
364 tx_bd_ring_base = malloc(sizeof(struct fm_port_bd)
365 * TX_BD_RING_SIZE);
366 if (!tx_bd_ring_base)
367 return -ENOMEM;
368
369 memset(tx_bd_ring_base, 0, sizeof(struct fm_port_bd)
370 * TX_BD_RING_SIZE);
371 /* save it to fm_eth */
372 fm_eth->tx_bd_ring = tx_bd_ring_base;
373 fm_eth->cur_txbd = tx_bd_ring_base;
374
375 /* init Tx BDs ring */
376 txbd = (struct fm_port_bd *)tx_bd_ring_base;
377 for (i = 0; i < TX_BD_RING_SIZE; i++) {
378 muram_writew(&txbd->status, TxBD_LAST);
379 muram_writew(&txbd->len, 0);
380 muram_writew(&txbd->buf_ptr_hi, 0);
381 out_be32(&txbd->buf_ptr_lo, 0);
382 txbd++;
383 }
384
385 /* set the Tx queue decriptor */
386 txqd = &pram->txqd;
387 bd_ring_base_hi = upper_32_bits(virt_to_phys(tx_bd_ring_base));
388 bd_ring_base_lo = lower_32_bits(virt_to_phys(tx_bd_ring_base));
389 muram_writew(&txqd->bd_ring_base_hi, (u16)bd_ring_base_hi);
390 out_be32(&txqd->bd_ring_base_lo, bd_ring_base_lo);
391 muram_writew(&txqd->bd_ring_size, sizeof(struct fm_port_bd)
392 * TX_BD_RING_SIZE);
393 muram_writew(&txqd->offset_in, 0);
394 muram_writew(&txqd->offset_out, 0);
395
396 /* set IM parameter ram pointer to Tx Confirmation Frame Queue ID */
397 out_be32(&bmi_tx_port->fmbm_tcfqid, pram_page_offset);
398
399 return 0;
400 }
401
fm_eth_init(struct fm_eth * fm_eth)402 static int fm_eth_init(struct fm_eth *fm_eth)
403 {
404 int ret;
405
406 ret = fm_eth_rx_port_parameter_init(fm_eth);
407 if (ret)
408 return ret;
409
410 ret = fm_eth_tx_port_parameter_init(fm_eth);
411 if (ret)
412 return ret;
413
414 return 0;
415 }
416
fm_eth_startup(struct fm_eth * fm_eth)417 static int fm_eth_startup(struct fm_eth *fm_eth)
418 {
419 struct fsl_enet_mac *mac;
420 int ret;
421
422 mac = fm_eth->mac;
423
424 /* Rx/TxBDs, Rx/TxQDs, Rx buff and parameter ram init */
425 ret = fm_eth_init(fm_eth);
426 if (ret)
427 return ret;
428 /* setup the MAC controller */
429 mac->init_mac(mac);
430
431 /* For some reason we need to set SPEED_100 */
432 if (((fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII) ||
433 (fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII_2500) ||
434 (fm_eth->enet_if == PHY_INTERFACE_MODE_QSGMII)) &&
435 mac->set_if_mode)
436 mac->set_if_mode(mac, fm_eth->enet_if, SPEED_100);
437
438 /* init bmi rx port, IM mode and disable */
439 bmi_rx_port_init(fm_eth->rx_port);
440 /* init bmi tx port, IM mode and disable */
441 bmi_tx_port_init(fm_eth->tx_port);
442
443 return 0;
444 }
445
fmc_tx_port_graceful_stop_enable(struct fm_eth * fm_eth)446 static void fmc_tx_port_graceful_stop_enable(struct fm_eth *fm_eth)
447 {
448 struct fm_port_global_pram *pram;
449
450 pram = fm_eth->tx_pram;
451 /* graceful stop transmission of frames */
452 setbits_be32(&pram->mode, PRAM_MODE_GRACEFUL_STOP);
453 sync();
454 }
455
fmc_tx_port_graceful_stop_disable(struct fm_eth * fm_eth)456 static void fmc_tx_port_graceful_stop_disable(struct fm_eth *fm_eth)
457 {
458 struct fm_port_global_pram *pram;
459
460 pram = fm_eth->tx_pram;
461 /* re-enable transmission of frames */
462 clrbits_be32(&pram->mode, PRAM_MODE_GRACEFUL_STOP);
463 sync();
464 }
465
466 #ifndef CONFIG_DM_ETH
fm_eth_open(struct eth_device * dev,struct bd_info * bd)467 static int fm_eth_open(struct eth_device *dev, struct bd_info *bd)
468 #else
469 static int fm_eth_open(struct udevice *dev)
470 #endif
471 {
472 #ifndef CONFIG_DM_ETH
473 struct fm_eth *fm_eth = dev->priv;
474 #else
475 struct eth_pdata *pdata = dev_get_plat(dev);
476 struct fm_eth *fm_eth = dev_get_priv(dev);
477 #endif
478 unsigned char *enetaddr;
479 struct fsl_enet_mac *mac;
480 #ifdef CONFIG_PHYLIB
481 int ret;
482 #endif
483
484 mac = fm_eth->mac;
485
486 #ifndef CONFIG_DM_ETH
487 enetaddr = &dev->enetaddr[0];
488 #else
489 enetaddr = pdata->enetaddr;
490 #endif
491
492 /* setup the MAC address */
493 if (enetaddr[0] & 0x01) {
494 printf("%s: MacAddress is multicast address\n", __func__);
495 enetaddr[0] = 0;
496 enetaddr[5] = fm_eth->num;
497 }
498 mac->set_mac_addr(mac, enetaddr);
499
500 /* enable bmi Rx port */
501 setbits_be32(&fm_eth->rx_port->fmbm_rcfg, FMBM_RCFG_EN);
502 /* enable MAC rx/tx port */
503 mac->enable_mac(mac);
504 /* enable bmi Tx port */
505 setbits_be32(&fm_eth->tx_port->fmbm_tcfg, FMBM_TCFG_EN);
506 /* re-enable transmission of frame */
507 fmc_tx_port_graceful_stop_disable(fm_eth);
508
509 #ifdef CONFIG_PHYLIB
510 if (fm_eth->phydev) {
511 ret = phy_startup(fm_eth->phydev);
512 if (ret) {
513 #ifndef CONFIG_DM_ETH
514 printf("%s: Could not initialize\n",
515 fm_eth->phydev->dev->name);
516 #else
517 printf("%s: Could not initialize\n", dev->name);
518 #endif
519 return ret;
520 }
521 } else {
522 return 0;
523 }
524 #else
525 fm_eth->phydev->speed = SPEED_1000;
526 fm_eth->phydev->link = 1;
527 fm_eth->phydev->duplex = DUPLEX_FULL;
528 #endif
529
530 /* set the MAC-PHY mode */
531 mac->set_if_mode(mac, fm_eth->enet_if, fm_eth->phydev->speed);
532 debug("MAC IF mode %d, speed %d, link %d\n", fm_eth->enet_if,
533 fm_eth->phydev->speed, fm_eth->phydev->link);
534
535 if (!fm_eth->phydev->link)
536 printf("%s: No link.\n", fm_eth->phydev->dev->name);
537
538 return fm_eth->phydev->link ? 0 : -1;
539 }
540
541 #ifndef CONFIG_DM_ETH
fm_eth_halt(struct eth_device * dev)542 static void fm_eth_halt(struct eth_device *dev)
543 #else
544 static void fm_eth_halt(struct udevice *dev)
545 #endif
546 {
547 struct fm_eth *fm_eth;
548 struct fsl_enet_mac *mac;
549
550 #ifndef CONFIG_DM_ETH
551 fm_eth = (struct fm_eth *)dev->priv;
552 #else
553 fm_eth = dev_get_priv(dev);
554 #endif
555 mac = fm_eth->mac;
556
557 /* graceful stop the transmission of frames */
558 fmc_tx_port_graceful_stop_enable(fm_eth);
559 /* disable bmi Tx port */
560 bmi_tx_port_disable(fm_eth->tx_port);
561 /* disable MAC rx/tx port */
562 mac->disable_mac(mac);
563 /* disable bmi Rx port */
564 bmi_rx_port_disable(fm_eth->rx_port);
565
566 #ifdef CONFIG_PHYLIB
567 if (fm_eth->phydev)
568 phy_shutdown(fm_eth->phydev);
569 #endif
570 }
571
572 #ifndef CONFIG_DM_ETH
fm_eth_send(struct eth_device * dev,void * buf,int len)573 static int fm_eth_send(struct eth_device *dev, void *buf, int len)
574 #else
575 static int fm_eth_send(struct udevice *dev, void *buf, int len)
576 #endif
577 {
578 struct fm_eth *fm_eth;
579 struct fm_port_global_pram *pram;
580 struct fm_port_bd *txbd, *txbd_base;
581 u16 offset_in;
582 int i;
583
584 #ifndef CONFIG_DM_ETH
585 fm_eth = (struct fm_eth *)dev->priv;
586 #else
587 fm_eth = dev_get_priv(dev);
588 #endif
589 pram = fm_eth->tx_pram;
590 txbd = fm_eth->cur_txbd;
591
592 /* find one empty TxBD */
593 for (i = 0; muram_readw(&txbd->status) & TxBD_READY; i++) {
594 udelay(100);
595 if (i > 0x1000) {
596 printf("%s: Tx buffer not ready, txbd->status = 0x%x\n",
597 dev->name, muram_readw(&txbd->status));
598 return 0;
599 }
600 }
601 /* setup TxBD */
602 muram_writew(&txbd->buf_ptr_hi, (u16)upper_32_bits(virt_to_phys(buf)));
603 out_be32(&txbd->buf_ptr_lo, lower_32_bits(virt_to_phys(buf)));
604 muram_writew(&txbd->len, len);
605 sync();
606 muram_writew(&txbd->status, TxBD_READY | TxBD_LAST);
607 sync();
608
609 /* update TxQD, let RISC to send the packet */
610 offset_in = muram_readw(&pram->txqd.offset_in);
611 offset_in += sizeof(struct fm_port_bd);
612 if (offset_in >= muram_readw(&pram->txqd.bd_ring_size))
613 offset_in = 0;
614 muram_writew(&pram->txqd.offset_in, offset_in);
615 sync();
616
617 /* wait for buffer to be transmitted */
618 for (i = 0; muram_readw(&txbd->status) & TxBD_READY; i++) {
619 udelay(100);
620 if (i > 0x10000) {
621 printf("%s: Tx error, txbd->status = 0x%x\n",
622 dev->name, muram_readw(&txbd->status));
623 return 0;
624 }
625 }
626
627 /* advance the TxBD */
628 txbd++;
629 txbd_base = (struct fm_port_bd *)fm_eth->tx_bd_ring;
630 if (txbd >= (txbd_base + TX_BD_RING_SIZE))
631 txbd = txbd_base;
632 /* update current txbd */
633 fm_eth->cur_txbd = (void *)txbd;
634
635 return 1;
636 }
637
fm_eth_free_one(struct fm_eth * fm_eth,struct fm_port_bd * rxbd)638 static struct fm_port_bd *fm_eth_free_one(struct fm_eth *fm_eth,
639 struct fm_port_bd *rxbd)
640 {
641 struct fm_port_global_pram *pram;
642 struct fm_port_bd *rxbd_base;
643 u16 offset_out;
644
645 pram = fm_eth->rx_pram;
646
647 /* clear the RxBDs */
648 muram_writew(&rxbd->status, RxBD_EMPTY);
649 muram_writew(&rxbd->len, 0);
650 sync();
651
652 /* advance RxBD */
653 rxbd++;
654 rxbd_base = (struct fm_port_bd *)fm_eth->rx_bd_ring;
655 if (rxbd >= (rxbd_base + RX_BD_RING_SIZE))
656 rxbd = rxbd_base;
657
658 /* update RxQD */
659 offset_out = muram_readw(&pram->rxqd.offset_out);
660 offset_out += sizeof(struct fm_port_bd);
661 if (offset_out >= muram_readw(&pram->rxqd.bd_ring_size))
662 offset_out = 0;
663 muram_writew(&pram->rxqd.offset_out, offset_out);
664 sync();
665
666 return rxbd;
667 }
668
669 #ifndef CONFIG_DM_ETH
fm_eth_recv(struct eth_device * dev)670 static int fm_eth_recv(struct eth_device *dev)
671 #else
672 static int fm_eth_recv(struct udevice *dev, int flags, uchar **packetp)
673 #endif
674 {
675 struct fm_eth *fm_eth;
676 struct fm_port_bd *rxbd;
677 u32 buf_lo, buf_hi;
678 u16 status, len;
679 int ret = -1;
680 u8 *data;
681
682 #ifndef CONFIG_DM_ETH
683 fm_eth = (struct fm_eth *)dev->priv;
684 #else
685 fm_eth = dev_get_priv(dev);
686 #endif
687 rxbd = fm_eth->cur_rxbd;
688 status = muram_readw(&rxbd->status);
689
690 while (!(status & RxBD_EMPTY)) {
691 if (!(status & RxBD_ERROR)) {
692 buf_hi = muram_readw(&rxbd->buf_ptr_hi);
693 buf_lo = in_be32(&rxbd->buf_ptr_lo);
694 data = (u8 *)((ulong)(buf_hi << 16) << 16 | buf_lo);
695 len = muram_readw(&rxbd->len);
696 #ifndef CONFIG_DM_ETH
697 net_process_received_packet(data, len);
698 #else
699 *packetp = data;
700 return len;
701 #endif
702 } else {
703 printf("%s: Rx error\n", dev->name);
704 ret = 0;
705 }
706
707 /* free current bd, advance to next one */
708 rxbd = fm_eth_free_one(fm_eth, rxbd);
709
710 /* read next status */
711 status = muram_readw(&rxbd->status);
712 }
713 fm_eth->cur_rxbd = (void *)rxbd;
714
715 return ret;
716 }
717
718 #ifdef CONFIG_DM_ETH
fm_eth_free_pkt(struct udevice * dev,uchar * packet,int length)719 static int fm_eth_free_pkt(struct udevice *dev, uchar *packet, int length)
720 {
721 struct fm_eth *fm_eth = (struct fm_eth *)dev_get_priv(dev);
722
723 fm_eth->cur_rxbd = fm_eth_free_one(fm_eth, fm_eth->cur_rxbd);
724
725 return 0;
726 }
727 #endif /* CONFIG_DM_ETH */
728
729 #ifndef CONFIG_DM_ETH
fm_eth_init_mac(struct fm_eth * fm_eth,struct ccsr_fman * reg)730 static int fm_eth_init_mac(struct fm_eth *fm_eth, struct ccsr_fman *reg)
731 {
732 struct fsl_enet_mac *mac;
733 int num;
734 void *base, *phyregs = NULL;
735
736 num = fm_eth->num;
737
738 #ifdef CONFIG_SYS_FMAN_V3
739 #ifndef CONFIG_FSL_FM_10GEC_REGULAR_NOTATION
740 if (fm_eth->type == FM_ETH_10G_E) {
741 /* 10GEC1/10GEC2 use mEMAC9/mEMAC10 on T2080/T4240.
742 * 10GEC3/10GEC4 use mEMAC1/mEMAC2 on T2080.
743 * 10GEC1 uses mEMAC1 on T1024.
744 * so it needs to change the num.
745 */
746 if (fm_eth->num >= 2)
747 num -= 2;
748 else
749 num += 8;
750 }
751 #endif
752 base = ®->memac[num].fm_memac;
753 phyregs = ®->memac[num].fm_memac_mdio;
754 #else
755 /* Get the mac registers base address */
756 if (fm_eth->type == FM_ETH_1G_E) {
757 base = ®->mac_1g[num].fm_dtesc;
758 phyregs = ®->mac_1g[num].fm_mdio.miimcfg;
759 } else {
760 base = ®->mac_10g[num].fm_10gec;
761 phyregs = ®->mac_10g[num].fm_10gec_mdio;
762 }
763 #endif
764
765 /* alloc mac controller */
766 mac = malloc(sizeof(struct fsl_enet_mac));
767 if (!mac)
768 return -ENOMEM;
769 memset(mac, 0, sizeof(struct fsl_enet_mac));
770
771 /* save the mac to fm_eth struct */
772 fm_eth->mac = mac;
773
774 #ifdef CONFIG_SYS_FMAN_V3
775 init_memac(mac, base, phyregs, MAX_RXBUF_LEN);
776 #else
777 if (fm_eth->type == FM_ETH_1G_E)
778 init_dtsec(mac, base, phyregs, MAX_RXBUF_LEN);
779 else
780 init_tgec(mac, base, phyregs, MAX_RXBUF_LEN);
781 #endif
782
783 return 0;
784 }
785 #else /* CONFIG_DM_ETH */
fm_eth_init_mac(struct fm_eth * fm_eth,void * reg)786 static int fm_eth_init_mac(struct fm_eth *fm_eth, void *reg)
787 {
788 #ifndef CONFIG_SYS_FMAN_V3
789 void *mdio;
790 #endif
791
792 fm_eth->mac = kzalloc(sizeof(*fm_eth->mac), GFP_KERNEL);
793 if (!fm_eth->mac)
794 return -ENOMEM;
795
796 #ifndef CONFIG_SYS_FMAN_V3
797 mdio = fman_mdio(fm_eth->dev->parent, fm_eth->mac_type, fm_eth->num);
798 debug("MDIO %d @ %p\n", fm_eth->num, mdio);
799 #endif
800
801 switch (fm_eth->mac_type) {
802 #ifdef CONFIG_SYS_FMAN_V3
803 case FM_MEMAC:
804 init_memac(fm_eth->mac, reg, NULL, MAX_RXBUF_LEN);
805 break;
806 #else
807 case FM_DTSEC:
808 init_dtsec(fm_eth->mac, reg, mdio, MAX_RXBUF_LEN);
809 break;
810 case FM_TGEC:
811 init_tgec(fm_eth->mac, reg, mdio, MAX_RXBUF_LEN);
812 break;
813 #endif
814 }
815
816 return 0;
817 }
818 #endif /* CONFIG_DM_ETH */
819
init_phy(struct fm_eth * fm_eth)820 static int init_phy(struct fm_eth *fm_eth)
821 {
822 #ifdef CONFIG_PHYLIB
823 u32 supported = PHY_GBIT_FEATURES;
824 #ifndef CONFIG_DM_ETH
825 struct phy_device *phydev = NULL;
826 #endif
827
828 if (fm_eth->type == FM_ETH_10G_E)
829 supported = PHY_10G_FEATURES;
830 if (fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII_2500)
831 supported |= SUPPORTED_2500baseX_Full;
832 #endif
833
834 if (fm_eth->type == FM_ETH_1G_E)
835 dtsec_init_phy(fm_eth);
836
837 #ifdef CONFIG_DM_ETH
838 #ifdef CONFIG_PHYLIB
839 #ifdef CONFIG_DM_MDIO
840 fm_eth->phydev = dm_eth_phy_connect(fm_eth->dev);
841 if (!fm_eth->phydev)
842 return -ENODEV;
843 #endif
844 fm_eth->phydev->advertising &= supported;
845 fm_eth->phydev->supported &= supported;
846
847 phy_config(fm_eth->phydev);
848 #endif
849 #else /* CONFIG_DM_ETH */
850 #ifdef CONFIG_PHYLIB
851 if (fm_eth->bus) {
852 phydev = phy_connect(fm_eth->bus, fm_eth->phyaddr, fm_eth->dev,
853 fm_eth->enet_if);
854 if (!phydev) {
855 printf("Failed to connect\n");
856 return -1;
857 }
858 } else {
859 return 0;
860 }
861
862 if (fm_eth->type == FM_ETH_1G_E) {
863 supported = (SUPPORTED_10baseT_Half |
864 SUPPORTED_10baseT_Full |
865 SUPPORTED_100baseT_Half |
866 SUPPORTED_100baseT_Full |
867 SUPPORTED_1000baseT_Full);
868 } else {
869 supported = SUPPORTED_10000baseT_Full;
870
871 if (tgec_is_fibre(fm_eth))
872 phydev->port = PORT_FIBRE;
873 }
874
875 phydev->supported &= supported;
876 phydev->advertising = phydev->supported;
877
878 fm_eth->phydev = phydev;
879
880 phy_config(phydev);
881 #endif
882 #endif /* CONFIG_DM_ETH */
883 return 0;
884 }
885
886 #ifndef CONFIG_DM_ETH
fm_eth_initialize(struct ccsr_fman * reg,struct fm_eth_info * info)887 int fm_eth_initialize(struct ccsr_fman *reg, struct fm_eth_info *info)
888 {
889 struct eth_device *dev;
890 struct fm_eth *fm_eth;
891 int i, num = info->num;
892 int ret;
893
894 /* alloc eth device */
895 dev = (struct eth_device *)malloc(sizeof(struct eth_device));
896 if (!dev)
897 return -ENOMEM;
898 memset(dev, 0, sizeof(struct eth_device));
899
900 /* alloc the FMan ethernet private struct */
901 fm_eth = (struct fm_eth *)malloc(sizeof(struct fm_eth));
902 if (!fm_eth)
903 return -ENOMEM;
904 memset(fm_eth, 0, sizeof(struct fm_eth));
905
906 /* save off some things we need from the info struct */
907 fm_eth->fm_index = info->index - 1; /* keep as 0 based for muram */
908 fm_eth->num = num;
909 fm_eth->type = info->type;
910
911 fm_eth->rx_port = (void *)®->port[info->rx_port_id - 1].fm_bmi;
912 fm_eth->tx_port = (void *)®->port[info->tx_port_id - 1].fm_bmi;
913
914 /* set the ethernet max receive length */
915 fm_eth->max_rx_len = MAX_RXBUF_LEN;
916
917 /* init global mac structure */
918 ret = fm_eth_init_mac(fm_eth, reg);
919 if (ret)
920 return ret;
921
922 /* keep same as the manual, we call FMAN1, FMAN2, DTSEC1, DTSEC2, etc */
923 if (fm_eth->type == FM_ETH_1G_E)
924 sprintf(dev->name, "FM%d@DTSEC%d", info->index, num + 1);
925 else
926 sprintf(dev->name, "FM%d@TGEC%d", info->index, num + 1);
927
928 devlist[num_controllers++] = dev;
929 dev->iobase = 0;
930 dev->priv = (void *)fm_eth;
931 dev->init = fm_eth_open;
932 dev->halt = fm_eth_halt;
933 dev->send = fm_eth_send;
934 dev->recv = fm_eth_recv;
935 fm_eth->dev = dev;
936 fm_eth->bus = info->bus;
937 fm_eth->phyaddr = info->phy_addr;
938 fm_eth->enet_if = info->enet_if;
939
940 /* startup the FM im */
941 ret = fm_eth_startup(fm_eth);
942 if (ret)
943 return ret;
944
945 init_phy(fm_eth);
946
947 /* clear the ethernet address */
948 for (i = 0; i < 6; i++)
949 dev->enetaddr[i] = 0;
950 eth_register(dev);
951
952 return 0;
953 }
954 #else /* CONFIG_DM_ETH */
955 #ifdef CONFIG_PHYLIB
fman_read_sys_if(struct udevice * dev)956 phy_interface_t fman_read_sys_if(struct udevice *dev)
957 {
958 const char *if_str;
959
960 if_str = ofnode_read_string(dev_ofnode(dev), "phy-connection-type");
961 debug("MAC system interface mode %s\n", if_str);
962
963 return phy_get_interface_by_name(if_str);
964 }
965 #endif
966
fm_eth_bind(struct udevice * dev)967 static int fm_eth_bind(struct udevice *dev)
968 {
969 char mac_name[11];
970 u32 fm, num;
971
972 if (ofnode_read_u32(ofnode_get_parent(dev_ofnode(dev)), "cell-index", &fm)) {
973 printf("FMan node property cell-index missing\n");
974 return -EINVAL;
975 }
976
977 if (dev && dev_read_u32(dev, "cell-index", &num)) {
978 printf("FMan MAC node property cell-index missing\n");
979 return -EINVAL;
980 }
981
982 sprintf(mac_name, "fm%d-mac%d", fm + 1, num + 1);
983 device_set_name(dev, mac_name);
984
985 debug("%s - binding %s\n", __func__, mac_name);
986
987 return 0;
988 }
989
fm_get_internal_mdio(struct udevice * dev)990 static struct udevice *fm_get_internal_mdio(struct udevice *dev)
991 {
992 struct ofnode_phandle_args phandle = {.node = ofnode_null()};
993 struct udevice *mdiodev;
994
995 if (dev_read_phandle_with_args(dev, "pcsphy-handle", NULL,
996 0, 0, &phandle) ||
997 !ofnode_valid(phandle.node)) {
998 if (dev_read_phandle_with_args(dev, "tbi-handle", NULL,
999 0, 0, &phandle) ||
1000 !ofnode_valid(phandle.node)) {
1001 printf("Issue reading pcsphy-handle/tbi-handle for MAC %s\n",
1002 dev->name);
1003 return NULL;
1004 }
1005 }
1006
1007 if (uclass_get_device_by_ofnode(UCLASS_MDIO,
1008 ofnode_get_parent(phandle.node),
1009 &mdiodev)) {
1010 printf("can't find MDIO bus for node %s\n",
1011 ofnode_get_name(ofnode_get_parent(phandle.node)));
1012 return NULL;
1013 }
1014 debug("Found internal MDIO bus %p\n", mdiodev);
1015
1016 return mdiodev;
1017 }
1018
fm_eth_probe(struct udevice * dev)1019 static int fm_eth_probe(struct udevice *dev)
1020 {
1021 struct fm_eth *fm_eth = (struct fm_eth *)dev_get_priv(dev);
1022 struct ofnode_phandle_args args;
1023 void *reg;
1024 int ret, index;
1025
1026 debug("%s enter for dev %p fm_eth %p - %s\n", __func__, dev, fm_eth,
1027 (dev) ? dev->name : "-");
1028
1029 if (fm_eth->dev) {
1030 printf("%s already probed, exit\n", (dev) ? dev->name : "-");
1031 return 0;
1032 }
1033
1034 fm_eth->dev = dev;
1035 fm_eth->fm_index = fman_id(dev->parent);
1036 reg = (void *)(uintptr_t)dev_read_addr(dev);
1037 fm_eth->mac_type = dev_get_driver_data(dev);
1038 #ifdef CONFIG_PHYLIB
1039 fm_eth->enet_if = fman_read_sys_if(dev);
1040 #else
1041 fm_eth->enet_if = PHY_INTERFACE_MODE_SGMII;
1042 printf("%s: warning - unable to determine interface type\n", __func__);
1043 #endif
1044 switch (fm_eth->mac_type) {
1045 #ifndef CONFIG_SYS_FMAN_V3
1046 case FM_TGEC:
1047 fm_eth->type = FM_ETH_10G_E;
1048 break;
1049 case FM_DTSEC:
1050 #else
1051 case FM_MEMAC:
1052 /* default to 1G, 10G is indicated by port property in dts */
1053 #endif
1054 fm_eth->type = FM_ETH_1G_E;
1055 break;
1056 }
1057
1058 if (dev_read_u32(dev, "cell-index", &fm_eth->num)) {
1059 printf("FMan MAC node property cell-index missing\n");
1060 return -EINVAL;
1061 }
1062
1063 if (dev_read_phandle_with_args(dev, "fsl,fman-ports", NULL,
1064 0, 0, &args))
1065 goto ports_ref_failure;
1066 index = ofnode_read_u32_default(args.node, "cell-index", 0);
1067 if (index <= 0)
1068 goto ports_ref_failure;
1069 fm_eth->rx_port = fman_port(dev->parent, index);
1070
1071 if (ofnode_read_bool(args.node, "fsl,fman-10g-port"))
1072 fm_eth->type = FM_ETH_10G_E;
1073
1074 if (dev_read_phandle_with_args(dev, "fsl,fman-ports", NULL,
1075 0, 1, &args))
1076 goto ports_ref_failure;
1077 index = ofnode_read_u32_default(args.node, "cell-index", 0);
1078 if (index <= 0)
1079 goto ports_ref_failure;
1080 fm_eth->tx_port = fman_port(dev->parent, index);
1081
1082 /* set the ethernet max receive length */
1083 fm_eth->max_rx_len = MAX_RXBUF_LEN;
1084
1085 switch (fm_eth->enet_if) {
1086 case PHY_INTERFACE_MODE_QSGMII:
1087 /* all PCS blocks are accessed on one controller */
1088 if (fm_eth->num != 0)
1089 break;
1090 case PHY_INTERFACE_MODE_SGMII:
1091 case PHY_INTERFACE_MODE_SGMII_2500:
1092 fm_eth->pcs_mdio = fm_get_internal_mdio(dev);
1093 break;
1094 default:
1095 break;
1096 }
1097
1098 /* init global mac structure */
1099 ret = fm_eth_init_mac(fm_eth, reg);
1100 if (ret)
1101 return ret;
1102
1103 /* startup the FM im */
1104 ret = fm_eth_startup(fm_eth);
1105
1106 if (!ret)
1107 ret = init_phy(fm_eth);
1108
1109 return ret;
1110
1111 ports_ref_failure:
1112 printf("Issue reading fsl,fman-ports for MAC %s\n", dev->name);
1113 return -ENOENT;
1114 }
1115
fm_eth_remove(struct udevice * dev)1116 static int fm_eth_remove(struct udevice *dev)
1117 {
1118 return 0;
1119 }
1120
1121 static const struct eth_ops fm_eth_ops = {
1122 .start = fm_eth_open,
1123 .send = fm_eth_send,
1124 .recv = fm_eth_recv,
1125 .free_pkt = fm_eth_free_pkt,
1126 .stop = fm_eth_halt,
1127 };
1128
1129 static const struct udevice_id fm_eth_ids[] = {
1130 #ifdef CONFIG_SYS_FMAN_V3
1131 { .compatible = "fsl,fman-memac", .data = FM_MEMAC },
1132 #else
1133 { .compatible = "fsl,fman-dtsec", .data = FM_DTSEC },
1134 { .compatible = "fsl,fman-xgec", .data = FM_TGEC },
1135 #endif
1136 {}
1137 };
1138
1139 U_BOOT_DRIVER(eth_fman) = {
1140 .name = "eth_fman",
1141 .id = UCLASS_ETH,
1142 .of_match = fm_eth_ids,
1143 .bind = fm_eth_bind,
1144 .probe = fm_eth_probe,
1145 .remove = fm_eth_remove,
1146 .ops = &fm_eth_ops,
1147 .priv_auto = sizeof(struct fm_eth),
1148 .plat_auto = sizeof(struct eth_pdata),
1149 .flags = DM_FLAG_ALLOC_PRIV_DMA,
1150 };
1151 #endif /* CONFIG_DM_ETH */
1152