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Searched refs:AMDGPU_IRQ_STATE_ENABLE (Results 1 – 25 of 35) sorted by relevance

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/linux/drivers/gpu/drm/amd/display/amdgpu_dm/
A Damdgpu_dm_irq.c693 bool st = (state == AMDGPU_IRQ_STATE_ENABLE); in amdgpu_dm_set_hpd_irq_state()
724 st = (state == AMDGPU_IRQ_STATE_ENABLE); in dm_irq_state()
778 bool st = (state == AMDGPU_IRQ_STATE_ENABLE); in amdgpu_dm_set_dmub_outbox_irq_state()
804 bool st = (state == AMDGPU_IRQ_STATE_ENABLE); in amdgpu_dm_set_dmub_trace_irq_state()
/linux/drivers/gpu/drm/amd/amdgpu/
A Dmxgpu_ai.c239 (state == AMDGPU_IRQ_STATE_ENABLE) ? 1 : 0); in xgpu_ai_set_mailbox_ack_irq()
290 (state == AMDGPU_IRQ_STATE_ENABLE) ? 1 : 0); in xgpu_ai_set_mailbox_rcv_irq()
A Dmxgpu_nv.c264 if (state == AMDGPU_IRQ_STATE_ENABLE) in xgpu_nv_set_mailbox_ack_irq()
321 if (state == AMDGPU_IRQ_STATE_ENABLE) in xgpu_nv_set_mailbox_rcv_irq()
A Damdgpu_irq.h43 AMDGPU_IRQ_STATE_ENABLE, enumerator
A Dmxgpu_vi.c505 (state == AMDGPU_IRQ_STATE_ENABLE) ? 1 : 0); in xgpu_vi_set_mailbox_ack_irq()
535 (state == AMDGPU_IRQ_STATE_ENABLE) ? 1 : 0); in xgpu_vi_set_mailbox_rcv_irq()
A Dnbio_v7_4.c471 if (state == AMDGPU_IRQ_STATE_ENABLE) { in nbio_v7_4_set_ras_controller_irq_state()
516 if (state == AMDGPU_IRQ_STATE_ENABLE) { in nbio_v7_4_set_ras_err_event_athub_irq_state()
A Dsi_dma.c606 case AMDGPU_IRQ_STATE_ENABLE: in si_dma_set_trap_irq_state()
622 case AMDGPU_IRQ_STATE_ENABLE: in si_dma_set_trap_irq_state()
A Dsdma_v2_4.c1024 case AMDGPU_IRQ_STATE_ENABLE: in sdma_v2_4_set_trap_irq_state()
1040 case AMDGPU_IRQ_STATE_ENABLE: in sdma_v2_4_set_trap_irq_state()
A Dvce_v2_0.c554 if (state == AMDGPU_IRQ_STATE_ENABLE) in vce_v2_0_set_interrupt_state()
A Dcik_sdma.c1129 case AMDGPU_IRQ_STATE_ENABLE: in cik_sdma_set_trap_irq_state()
1145 case AMDGPU_IRQ_STATE_ENABLE: in cik_sdma_set_trap_irq_state()
A Damdgpu_irq.c573 state = AMDGPU_IRQ_STATE_ENABLE; in amdgpu_irq_update()
A Dgmc_v9_0.c438 case AMDGPU_IRQ_STATE_ENABLE: in gmc_v9_0_ecc_interrupt_state()
487 case AMDGPU_IRQ_STATE_ENABLE: in gmc_v9_0_vm_fault_interrupt_state()
A Dsdma_v3_0.c1358 case AMDGPU_IRQ_STATE_ENABLE: in sdma_v3_0_set_trap_irq_state()
1374 case AMDGPU_IRQ_STATE_ENABLE: in sdma_v3_0_set_trap_irq_state()
A Dgfx_v9_0.c5752 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v9_0_set_gfx_eop_interrupt_state()
5755 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in gfx_v9_0_set_gfx_eop_interrupt_state()
5804 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v9_0_set_compute_eop_interrupt_state()
5822 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v9_0_set_priv_reg_fault_state()
5825 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in gfx_v9_0_set_priv_reg_fault_state()
5841 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v9_0_set_priv_inst_fault_state()
5844 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in gfx_v9_0_set_priv_inst_fault_state()
5876 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v9_0_set_cp_ecc_error_state()
A Dgmc_v6_0.c1055 case AMDGPU_IRQ_STATE_ENABLE: in gmc_v6_0_vm_fault_interrupt_state()
A Dgfx_v6_0.c3248 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v6_0_set_gfx_eop_interrupt_state()
3277 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v6_0_set_compute_eop_interrupt_state()
3311 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v6_0_set_priv_reg_fault_state()
3336 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v6_0_set_priv_inst_fault_state()
A Dvce_v3_0.c736 if (state == AMDGPU_IRQ_STATE_ENABLE) in vce_v3_0_set_interrupt_state()
A Dgmc_v10_0.c78 case AMDGPU_IRQ_STATE_ENABLE: in gmc_v10_0_vm_fault_interrupt_state()
A Ddce_v8_0.c2911 case AMDGPU_IRQ_STATE_ENABLE: in dce_v8_0_set_crtc_vblank_interrupt_state()
2962 case AMDGPU_IRQ_STATE_ENABLE: in dce_v8_0_set_crtc_vline_interrupt_state()
2990 case AMDGPU_IRQ_STATE_ENABLE: in dce_v8_0_set_hpd_interrupt_state()
A Dgfx_v7_0.c4742 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v7_0_set_gfx_eop_interrupt_state()
4793 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v7_0_set_compute_eop_interrupt_state()
4816 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v7_0_set_priv_reg_fault_state()
4841 case AMDGPU_IRQ_STATE_ENABLE: in gfx_v7_0_set_priv_inst_fault_state()
A Ddce_v10_0.c2996 case AMDGPU_IRQ_STATE_ENABLE: in dce_v10_0_set_crtc_vblank_interrupt_state()
3025 case AMDGPU_IRQ_STATE_ENABLE: in dce_v10_0_set_crtc_vline_interrupt_state()
3054 case AMDGPU_IRQ_STATE_ENABLE: in dce_v10_0_set_hpd_irq_state()
A Dsdma_v4_0.c2120 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in sdma_v4_0_set_trap_irq_state()
2205 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); in sdma_v4_0_set_ecc_irq_state()
A Dvce_v4_0.c1050 if (state == AMDGPU_IRQ_STATE_ENABLE) in vce_v4_0_set_interrupt_state()
A Ddce_v11_0.c3119 case AMDGPU_IRQ_STATE_ENABLE: in dce_v11_0_set_crtc_vblank_interrupt_state()
3148 case AMDGPU_IRQ_STATE_ENABLE: in dce_v11_0_set_crtc_vline_interrupt_state()
3177 case AMDGPU_IRQ_STATE_ENABLE: in dce_v11_0_set_hpd_irq_state()
A Dgmc_v7_0.c1254 case AMDGPU_IRQ_STATE_ENABLE: in gmc_v7_0_vm_fault_interrupt_state()

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