Home
last modified time | relevance | path

Searched refs:BIT_1 (Results 1 – 25 of 37) sorted by relevance

12

/linux/drivers/scsi/
A Dqla1280.h18 #define BIT_1 0x2 macro
121 #define ISP_CFG0_1020A BIT_1 /* ISP1020A */
135 #define ISP_EN_INT BIT_1 /* ISP enable interrupts. */
142 #define PCI_INT BIT_1 /* PCI interrupt */
147 #define NV_SELECT BIT_1
159 #define CDMA_CONF_BENAB BIT_1 /* Bus burst enable */
176 #define DDMA_CONF_BENAB BIT_1 /* Bus burst enable */
568 #define RF_FULL BIT_1 /* Full */
966 #define OF_ENABLE_TAG BIT_1 /* Tagged queue action enable */
A Dqla1280.c1121 mr = BIT_3 | BIT_2 | BIT_1 | BIT_0; in qla1280_set_target_parameters()
1705 #define CMD_ARGS (BIT_4 | BIT_3 | BIT_2 | BIT_1 | BIT_0)
1829 err = qla1280_mailbox_command(ha, BIT_1 | BIT_0, mb); in qla1280_start_firmware()
1906 BIT_3 | BIT_2 | BIT_1 | BIT_0, in qla1280_init_rings()
1920 BIT_3 | BIT_2 | BIT_1 | BIT_0, in qla1280_init_rings()
2213 BIT_7 | BIT_3 | BIT_2 | BIT_1 | BIT_0); in qla1280_nvram_config()
2248 BIT_1 | BIT_0, &mb[0]); in qla1280_nvram_config()
2276 mb[1] = BIT_1; /* Data DMA Channel Burst Enable */ in qla1280_nvram_config()
2277 mb[2] = BIT_1; /* Command DMA Channel Burst Enable */ in qla1280_nvram_config()
3703 else if (pkt->entry_status & BIT_1) in qla1280_error_entry()
[all …]
/linux/drivers/scsi/qla2xxx/
A Dqla_fw.h30 #define PDO_FORCE_ADISC BIT_1
45 #define PDF_HARD_ADDR BIT_1
457 #define BD_READ_DATA BIT_1
498 #define CF_READ_DATA BIT_1
540 #define TMF_READ_DATA BIT_1
974 #define TCF_TARGET_RESET BIT_1
1265 #define GPDX_DATA_INOUT (BIT_1|BIT_0)
1273 #define GPEX_ENABLE (BIT_1|BIT_0)
1396 #define MDBS_ID_ACQUIRED BIT_1
1747 #define FSTATE_NSL_LINK_DOWN BIT_1
[all …]
A Dqla_edif.h20 #define EDIF_SA_CTL_FLG_DEL BIT_1
79 #define SA_FLAG_TX BIT_1 // 1=tx, 0=rx
A Dqla_def.h104 #define BIT_1 0x2 macro
783 #define NVR_SELECT BIT_1
1040 #define MBX_DMA_OUT BIT_1
1053 #define MBX_DMA_OUT BIT_1
1189 #define FO2_REV_LOOPBACK BIT_1
1192 #define FO3_AE_RND_ERROR BIT_1
1357 #define MBX_1 BIT_1
1950 #define CF_HEAD_TAG BIT_1
3219 SF_QUEUED = BIT_1,
3224 FS_FC4TYPE_NVME = BIT_1,
[all …]
A Dqla_target.h225 #define ATIO_EXEC_READ BIT_1
422 #define EF_NEW_SA BIT_1
483 #define CTIO7_FLAGS_DATA_IN BIT_1 /* data to initiator */
844 TRC_DO_WORK = BIT_1,
972 #define QLA24XX_MGMT_ABORT_IO_ATTR_VALID BIT_1
A Dqla_nvme.h60 #define CF_READ_DATA BIT_1
A Dqla_tmpl.h61 #define CAPTURE_FLAG_PHYS_VIRT BIT_1
A Dqla_init.c4133 (BIT_3 | BIT_2 | BIT_1 | BIT_0); in qla2x00_update_fw_options()
4144 (tx_sens & (BIT_1 | BIT_0)); in qla2x00_update_fw_options()
4151 (BIT_3 | BIT_2 | BIT_1 | BIT_0); in qla2x00_update_fw_options()
4162 (tx_sens & (BIT_1 | BIT_0)); in qla2x00_update_fw_options()
5112 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0); in qla2x00_nvram_config()
5969 0xfc, mb, BIT_1|BIT_0); in qla2x00_configure_fabric()
6472 if (mb[1] & BIT_1) { in qla2x00_fabric_login()
6479 if (mb[10] & BIT_1) in qla2x00_fabric_login()
7777 (BIT_3 | BIT_2 | BIT_1 | BIT_0); in qla24xx_nvram_config()
8619 BIT_1); in qla24xx_configure_vhba()
[all …]
A Dqla_mbx.c788 (BIT_0 | BIT_1 | BIT_2); in qla2x00_execute_fw()
1883 mcp->mb[1] |= BIT_1; in qla2x00_init_firmware()
2383 mcp->mb[1] = BIT_1; in qla2x00_lip_reset()
2516 if (opt & BIT_1) in qla24xx_login_fabric()
2576 mb[1] |= BIT_1; in qla24xx_login_fabric()
2585 mb[10] |= BIT_1; /* Class 3. */ in qla24xx_login_fabric()
4320 rval = BIT_1; in qla2x00_send_change_request()
4323 rval = BIT_1; in qla2x00_send_change_request()
5733 mcp->mb[2] = BIT_1; in qla24xx_set_fcp_prio()
6773 addr, offset, SFP_BLOCK_SIZE, BIT_1); in qla2x00_read_sfp_dev()
[all …]
A Dqla_mid.c890 options |= BIT_1; in qla25xx_create_rsp_que()
A Dqla_gbl.h1005 #define QLA2XX_SHT_LNK_DWN BIT_1
A Dqla_attr.c1395 options |= BIT_3|BIT_2|BIT_1; in qla2x00_beacon_config_store()
1417 options |= BIT_1; in qla2x00_beacon_config_store()
/linux/drivers/net/ethernet/qlogic/qlcnic/
A Dqlcnic_hw.h140 #define QLCNIC_GET_OWNER(val) ((val) & (BIT_0 | BIT_1))
A Dqlcnic_hdr.h196 #define BIT_1 0x2 macro
493 #define TA_CTL_ENABLE BIT_1
A Dqlcnic_ctx.c1346 arg2 |= (BIT_0 | BIT_1); in qlcnic_config_switch_port()
1358 arg2 &= ~(BIT_1 | BIT_2 | BIT_3); in qlcnic_config_switch_port()
1359 if (!(esw_cfg->offload_flags & BIT_1)) in qlcnic_config_switch_port()
A Dqlcnic_83xx_hw.h531 #define QLC_REGISTER_DCB_AEN BIT_1
A Dqlcnic.h913 #define QLCNIC_FW_CAPABILITY_TSO BIT_1
929 #define QLCNIC_83XX_FW_CAPAB_ENCAP_TX_OFFLOAD BIT_1
1315 #define QLCNIC_SWITCH_ENABLE BIT_1
A Dqlcnic_hw.c815 #define QLCNIC_ENABLE_IPV6_LRO (BIT_1 | BIT_9)
1033 if (!(offload_flags & BIT_1)) in qlcnic_process_flags()
A Dqlcnic_minidump.c24 #define QLCNIC_DUMP_RWCRB BIT_1
753 if (dma_sts & BIT_1) in qlcnic_start_pex_dma()
A Dqlcnic_sriov_pf.c390 cmd.req.arg[1] = ((func & 0xf) << 2) | BIT_6 | BIT_1; in qlcnic_sriov_pf_cfg_eswitch()
703 cmd.req.arg[2] |= BIT_1 | BIT_3 | BIT_8; in qlcnic_sriov_set_vf_acl()
A Dqlcnic_83xx_hw.c2023 lro_bit_mask = (mode ? (BIT_0 | BIT_1 | BIT_2 | BIT_3) : 0); in qlcnic_83xx_config_hw_lro()
3539 cmd.req.arg[1] = BIT_1 | (adapter->tx_ring->ctx_id << 16); in qlcnic_83xx_get_stats()
3570 #define QLCNIC_83XX_ADD_PORT1 BIT_1
/linux/drivers/scsi/qla4xxx/
A Dql4_def.h82 #define BIT_1 0x2 macro
A Dql4_os.c3537 sess->erl |= BIT_1; in qla4xxx_copy_from_fwddb_param()
3550 conn->tcp_timer_scale |= BIT_1; in qla4xxx_copy_from_fwddb_param()
3668 SET_BITVAL(sess->erl & BIT_1, options, BIT_1); in qla4xxx_copy_to_fwddb_param()
3677 SET_BITVAL(conn->tcp_timer_scale & BIT_1, options, BIT_2); in qla4xxx_copy_to_fwddb_param()
3678 SET_BITVAL(conn->tcp_timer_scale & BIT_0, options, BIT_1); in qla4xxx_copy_to_fwddb_param()
3774 sess->erl |= BIT_1; in qla4xxx_copy_to_sess_conn_params()
3787 conn->tcp_timer_scale |= BIT_1; in qla4xxx_copy_to_sess_conn_params()
8895 if (PCI_FUNC(ha->pdev->devfn) & BIT_1) in qla4xxx_prevent_other_port_reinit()
A Dql4_fw.h61 #define HSRX_RISC_IOCB_INT BIT_1 /* RISC to Host IOCB interrupt */

Completed in 177 milliseconds

12