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Searched refs:BIT_ULL (Results 1 – 25 of 360) sorted by relevance

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/linux/drivers/gpu/drm/panfrost/
A Dpanfrost_features.h48 BIT_ULL(HW_FEATURE_V4))
55 BIT_ULL(HW_FEATURE_V4))
66 BIT_ULL(HW_FEATURE_V4))
79 BIT_ULL(HW_FEATURE_MRT) | \
98 BIT_ULL(HW_FEATURE_MRT) | \
121 BIT_ULL(HW_FEATURE_MRT) | \
141 BIT_ULL(HW_FEATURE_MRT) | \
161 BIT_ULL(HW_FEATURE_MRT) | \
185 BIT_ULL(HW_FEATURE_MRT) | \
210 BIT_ULL(HW_FEATURE_MRT) | \
[all …]
A Dpanfrost_issues.h132 BIT_ULL(HW_ISSUE_9435))
135 BIT_ULL(HW_ISSUE_6367) | \
136 BIT_ULL(HW_ISSUE_6787) | \
137 BIT_ULL(HW_ISSUE_8408) | \
138 BIT_ULL(HW_ISSUE_9510) | \
148 BIT_ULL(HW_ISSUE_8186) | \
149 BIT_ULL(HW_ISSUE_8245) | \
150 BIT_ULL(HW_ISSUE_8316) | \
157 BIT_ULL(GPUCORE_1619))
172 BIT_ULL(HW_ISSUE_11035))
[all …]
/linux/drivers/mmc/host/
A Dcavium.h134 #define MIO_EMM_CMD_VAL BIT_ULL(59)
135 #define MIO_EMM_CMD_DBUF BIT_ULL(55)
144 #define MIO_EMM_DMA_VAL BIT_ULL(59)
145 #define MIO_EMM_DMA_SECTOR BIT_ULL(58)
148 #define MIO_EMM_DMA_REL_WR BIT_ULL(50)
149 #define MIO_EMM_DMA_RW BIT_ULL(49)
150 #define MIO_EMM_DMA_MULTI BIT_ULL(48)
154 #define MIO_EMM_DMA_CFG_EN BIT_ULL(63)
155 #define MIO_EMM_DMA_CFG_RW BIT_ULL(62)
166 #define MIO_EMM_INT_DMA_ERR BIT_ULL(4)
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/linux/arch/mips/include/asm/
A Dcpu.h366 #define MIPS_CPU_TLB BIT_ULL( 0) /* CPU has TLB */
367 #define MIPS_CPU_4KEX BIT_ULL( 1) /* "R4K" exception model */
368 #define MIPS_CPU_3K_CACHE BIT_ULL( 2) /* R3000-style caches */
369 #define MIPS_CPU_4K_CACHE BIT_ULL( 3) /* R4000-style caches */
371 #define MIPS_CPU_FPU BIT_ULL( 5) /* CPU has FPU */
380 #define MIPS_CPU_EJTAG BIT_ULL(14) /* EJTAG exception */
381 #define MIPS_CPU_NOFPUEX BIT_ULL(15) /* no FPU exception */
387 #define MIPS_CPU_ULRI BIT_ULL(21) /* CPU has ULRI feature */
408 #define MIPS_CPU_EBASE_WG BIT_ULL(43) /* CPU has EBase.WG */
420 BIT_ULL(54) /* CPU shares FTLB RAM with another */
[all …]
/linux/drivers/net/ethernet/cavium/thunder/
A Dthunder_bgx.h36 #define CMR_PKT_TX_EN BIT_ULL(13)
37 #define CMR_PKT_RX_EN BIT_ULL(14)
38 #define CMR_EN BIT_ULL(15)
57 #define RX_DMACX_CAM_EN BIT_ULL(48)
89 #define SPU_CTL_RESET BIT_ULL(15)
141 #define SMU_CTL_RX_IDLE BIT_ULL(0)
142 #define SMU_CTL_TX_IDLE BIT_ULL(1)
144 #define RX_EN BIT_ULL(0)
145 #define TX_EN BIT_ULL(1)
146 #define BCK_EN BIT_ULL(2)
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/linux/drivers/infiniband/hw/irdma/
A Ddefs.h464 #define IRDMA_CQ_EXTCQE BIT_ULL(50)
465 #define IRDMA_OOO_CMPL BIT_ULL(54)
466 #define IRDMA_CQ_ERROR BIT_ULL(55)
467 #define IRDMA_CQ_SQ BIT_ULL(62)
469 #define IRDMA_CQ_VALID BIT_ULL(63)
487 #define IRDMACQ_STAG BIT_ULL(53)
488 #define IRDMACQ_IPV4 BIT_ULL(53)
703 #define IRDMAQPC_IPV4 BIT_ULL(3)
706 #define IRDMAQPC_ISQP1 BIT_ULL(6)
723 #define IRDMAQPC_PMENA BIT_ULL(47)
[all …]
A Duda_d.h17 #define IRDMA_UDA_QPSQ_PUSHWQE BIT_ULL(56)
22 #define IRDMA_UDA_QPSQ_NOCHECKSUM BIT_ULL(45)
23 #define IRDMA_UDA_QPSQ_AHIDXVALID BIT_ULL(46)
24 #define IRDMA_UDA_QPSQ_LOCAL_FENCE BIT_ULL(61)
28 #define IRDMA_UDA_QPSQ_MULTICAST BIT_ULL(63)
44 #define IRDMA_UDAQPC_IPV4_M BIT_ULL(3)
46 #define IRDMA_UDAQPC_ISQP1 BIT_ULL(6)
48 #define IRDMA_UDAQPC_ECNENABLE BIT_ULL(14)
58 #define IRDMA_UDAQPC_INSERTTAG2 BIT_ULL(11)
59 #define IRDMA_UDAQPC_INSERTTAG3 BIT_ULL(14)
[all …]
/linux/drivers/iommu/intel/
A Dcap_audit.h13 #define CAP_FL5LP_MASK BIT_ULL(60)
14 #define CAP_PI_MASK BIT_ULL(59)
15 #define CAP_FL1GP_MASK BIT_ULL(56)
16 #define CAP_RD_MASK BIT_ULL(55)
17 #define CAP_WD_MASK BIT_ULL(54)
20 #define CAP_PSI_MASK BIT_ULL(39)
23 #define CAP_ZLR_MASK BIT_ULL(22)
26 #define CAP_CM_MASK BIT_ULL(7)
27 #define CAP_PHMR_MASK BIT_ULL(6)
28 #define CAP_PLMR_MASK BIT_ULL(5)
[all …]
/linux/drivers/gpu/drm/arm/display/komeda/
A Dkomeda_dev.h16 #define KOMEDA_EVENT_VSYNC BIT_ULL(0)
17 #define KOMEDA_EVENT_FLIP BIT_ULL(1)
18 #define KOMEDA_EVENT_URUN BIT_ULL(2)
19 #define KOMEDA_EVENT_IBSY BIT_ULL(3)
20 #define KOMEDA_EVENT_OVR BIT_ULL(4)
21 #define KOMEDA_EVENT_EOW BIT_ULL(5)
22 #define KOMEDA_EVENT_MODE BIT_ULL(6)
23 #define KOMEDA_EVENT_FULL BIT_ULL(7)
26 #define KOMEDA_ERR_TETO BIT_ULL(14)
27 #define KOMEDA_ERR_TEMR BIT_ULL(15)
[all …]
/linux/drivers/gpu/drm/i915/display/
A Dintel_display_power.c2500 BIT_ULL(POWER_DOMAIN_INIT))
2520 BIT_ULL(POWER_DOMAIN_INIT))
2528 BIT_ULL(POWER_DOMAIN_INIT))
2533 BIT_ULL(POWER_DOMAIN_INIT))
2538 BIT_ULL(POWER_DOMAIN_INIT))
2543 BIT_ULL(POWER_DOMAIN_INIT))
2548 BIT_ULL(POWER_DOMAIN_INIT))
2572 BIT_ULL(POWER_DOMAIN_INIT))
2579 BIT_ULL(POWER_DOMAIN_INIT))
2584 BIT_ULL(POWER_DOMAIN_INIT))
[all …]
/linux/arch/x86/include/asm/
A Dmce.h15 #define MCG_CMCI_P BIT_ULL(10) /* CMCI supported */
33 #define MCI_STATUS_VAL BIT_ULL(63) /* valid error */
91 #define MCI_CTL2_CMCI_EN BIT_ULL(30)
133 #define MCE_HANDLED_CEC BIT_ULL(0)
134 #define MCE_HANDLED_UC BIT_ULL(1)
135 #define MCE_HANDLED_EXTLOG BIT_ULL(2)
136 #define MCE_HANDLED_NFIT BIT_ULL(3)
137 #define MCE_HANDLED_EDAC BIT_ULL(4)
138 #define MCE_HANDLED_MCELOG BIT_ULL(5)
146 #define MCE_IN_KERNEL_RECOV BIT_ULL(6)
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/linux/drivers/net/ethernet/intel/ice/
A Dice_flow.h12 (BIT_ULL(ICE_FLOW_FIELD_IDX_ETH_DA) | \
13 BIT_ULL(ICE_FLOW_FIELD_IDX_ETH_SA))
15 (BIT_ULL(ICE_FLOW_FIELD_IDX_IPV4_SA) | \
16 BIT_ULL(ICE_FLOW_FIELD_IDX_IPV4_DA))
18 (BIT_ULL(ICE_FLOW_FIELD_IDX_IPV6_SA) | \
19 BIT_ULL(ICE_FLOW_FIELD_IDX_IPV6_DA))
22 BIT_ULL(ICE_FLOW_FIELD_IDX_TCP_DST_PORT))
25 BIT_ULL(ICE_FLOW_FIELD_IDX_UDP_DST_PORT))
37 (BIT_ULL(ICE_FLOW_FIELD_IDX_GTPC_TEID))
90 (BIT_ULL(ICE_FLOW_FIELD_IDX_ESP_SPI))
[all …]
A Dice_adminq_cmd.h961 #define ICE_PHY_TYPE_LOW_100BASE_TX BIT_ULL(0)
962 #define ICE_PHY_TYPE_LOW_100M_SGMII BIT_ULL(1)
963 #define ICE_PHY_TYPE_LOW_1000BASE_T BIT_ULL(2)
967 #define ICE_PHY_TYPE_LOW_1G_SGMII BIT_ULL(6)
968 #define ICE_PHY_TYPE_LOW_2500BASE_T BIT_ULL(7)
969 #define ICE_PHY_TYPE_LOW_2500BASE_X BIT_ULL(8)
971 #define ICE_PHY_TYPE_LOW_5GBASE_T BIT_ULL(10)
972 #define ICE_PHY_TYPE_LOW_5GBASE_KR BIT_ULL(11)
973 #define ICE_PHY_TYPE_LOW_10GBASE_T BIT_ULL(12)
1004 #define ICE_PHY_TYPE_LOW_50G_AUI2 BIT_ULL(43)
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/linux/drivers/firmware/efi/
A Dcper-x86.c11 #define VALID_LAPIC_ID BIT_ULL(0)
12 #define VALID_CPUID_INFO BIT_ULL(1)
30 #define INFO_VALID_TARGET_ID BIT_ULL(1)
33 #define INFO_VALID_IP BIT_ULL(4)
37 #define CHECK_VALID_LEVEL BIT_ULL(2)
38 #define CHECK_VALID_PCC BIT_ULL(3)
52 #define CHECK_PCC BIT_ULL(25)
53 #define CHECK_UNCORRECTED BIT_ULL(26)
54 #define CHECK_PRECISE_IP BIT_ULL(27)
56 #define CHECK_OVERFLOW BIT_ULL(29)
[all …]
/linux/include/media/
A Drc-map.h16 #define RC_PROTO_BIT_OTHER BIT_ULL(RC_PROTO_OTHER)
17 #define RC_PROTO_BIT_RC5 BIT_ULL(RC_PROTO_RC5)
19 #define RC_PROTO_BIT_RC5_SZ BIT_ULL(RC_PROTO_RC5_SZ)
20 #define RC_PROTO_BIT_JVC BIT_ULL(RC_PROTO_JVC)
24 #define RC_PROTO_BIT_NEC BIT_ULL(RC_PROTO_NEC)
25 #define RC_PROTO_BIT_NECX BIT_ULL(RC_PROTO_NECX)
26 #define RC_PROTO_BIT_NEC32 BIT_ULL(RC_PROTO_NEC32)
27 #define RC_PROTO_BIT_SANYO BIT_ULL(RC_PROTO_SANYO)
36 #define RC_PROTO_BIT_XMP BIT_ULL(RC_PROTO_XMP)
37 #define RC_PROTO_BIT_CEC BIT_ULL(RC_PROTO_CEC)
[all …]
/linux/drivers/net/ethernet/cavium/liquidio/
A Dcn66xx_regs.h367 #define CN6XXX_INTR_DMA0_FORCE BIT_ULL(32)
368 #define CN6XXX_INTR_DMA1_FORCE BIT_ULL(33)
369 #define CN6XXX_INTR_DMA0_COUNT BIT_ULL(34)
370 #define CN6XXX_INTR_DMA1_COUNT BIT_ULL(35)
371 #define CN6XXX_INTR_DMA0_TIME BIT_ULL(36)
372 #define CN6XXX_INTR_DMA1_TIME BIT_ULL(37)
486 #define CN6XXX_DPI_DMA_COMMIT_MODE BIT_ULL(58)
487 #define CN6XXX_DPI_DMA_PKT_HP BIT_ULL(57)
488 #define CN6XXX_DPI_DMA_PKT_EN BIT_ULL(56)
489 #define CN6XXX_DPI_DMA_O_ES BIT_ULL(15)
[all …]
A Dcn23xx_pf_regs.h389 #define CN23XX_MSIX_ENTRY_VECTOR_CTL BIT_ULL(32)
425 #define CN23XX_INTR_PO_INT BIT_ULL(63)
426 #define CN23XX_INTR_PI_INT BIT_ULL(62)
427 #define CN23XX_INTR_MBOX_INT BIT_ULL(61)
428 #define CN23XX_INTR_RESEND BIT_ULL(60)
430 #define CN23XX_INTR_CINT_ENB BIT_ULL(48)
451 #define CN23XX_INTR_DMA0_FORCE BIT_ULL(32)
452 #define CN23XX_INTR_DMA1_FORCE BIT_ULL(33)
454 #define CN23XX_INTR_DMA0_COUNT BIT_ULL(34)
574 #define CN23XX_DPI_DMA_COMMIT_MODE BIT_ULL(58)
[all …]
/linux/drivers/extcon/
A Dextcon-fsa9480.c128 [DEV_DEDICATED_CHG] = BIT_ULL(EXTCON_USB) | BIT_ULL(EXTCON_CHG_USB_DCP),
129 [DEV_USB_CHG] = BIT_ULL(EXTCON_USB) | BIT_ULL(EXTCON_CHG_USB_SDP),
130 [DEV_CAR_KIT] = BIT_ULL(EXTCON_USB) | BIT_ULL(EXTCON_CHG_USB_SDP)
132 [DEV_UART] = BIT_ULL(EXTCON_JIG),
133 [DEV_USB] = BIT_ULL(EXTCON_USB) | BIT_ULL(EXTCON_CHG_USB_SDP),
138 [DEV_TTY] = BIT_ULL(EXTCON_JIG),
139 [DEV_PPD] = BIT_ULL(EXTCON_JACK_LINE_OUT) | BIT_ULL(EXTCON_CHG_USB_ACA),
142 [DEV_JIG_USB_OFF] = BIT_ULL(EXTCON_USB) | BIT_ULL(EXTCON_JIG),
143 [DEV_JIG_USB_ON] = BIT_ULL(EXTCON_USB) | BIT_ULL(EXTCON_JIG),
213 cables &= ~BIT_ULL(cable); in fsa9480_handle_change()
[all …]
/linux/drivers/net/ethernet/marvell/octeontx2/af/
A Dcgx.h33 #define CMR_EN BIT_ULL(55)
34 #define DATA_PKT_TX_EN BIT_ULL(53)
35 #define DATA_PKT_RX_EN BIT_ULL(54)
39 #define FW_CGX_INT BIT_ULL(1)
45 #define CGX_DMAC_CTL0_CAM_ENABLE BIT_ULL(3)
46 #define CGX_DMAC_CAM_ACCEPT BIT_ULL(3)
47 #define CGX_DMAC_MCAST_MODE_CAM BIT_ULL(2)
48 #define CGX_DMAC_MCAST_MODE BIT_ULL(1)
49 #define CGX_DMAC_BCAST_MODE BIT_ULL(0)
51 #define CGX_DMAC_CAM_ADDR_ENABLE BIT_ULL(48)
[all …]
/linux/drivers/usb/typec/tipd/
A Dtps6598x.h87 #define TPS_REG_INT_USER_VID_ALT_MODE_EXIT BIT_ULL(25+32)
89 #define TPS_REG_INT_EXIT_MODES_COMPLETE BIT_ULL(20+32)
90 #define TPS_REG_INT_DISCOVER_MODES_COMPLETE BIT_ULL(19+32)
91 #define TPS_REG_INT_VDM_MSG_SENT BIT_ULL(18+32)
92 #define TPS_REG_INT_VDM_ENTERED_MODE BIT_ULL(17+32)
93 #define TPS_REG_INT_ERROR_UNABLE_TO_SOURCE BIT_ULL(14+32)
94 #define TPS_REG_INT_SRC_TRANSITION BIT_ULL(10+32)
95 #define TPS_REG_INT_ERROR_DISCHARGE_FAILED BIT_ULL(9+32)
96 #define TPS_REG_INT_ERROR_MESSAGE_DATA BIT_ULL(7+32)
97 #define TPS_REG_INT_ERROR_PROTOCOL_ERROR BIT_ULL(6+32)
[all …]
/linux/drivers/gpu/drm/i915/
A Di915_gem_gtt.h36 #define PIN_NOEVICT BIT_ULL(0)
37 #define PIN_NOSEARCH BIT_ULL(1)
38 #define PIN_NONBLOCK BIT_ULL(2)
39 #define PIN_MAPPABLE BIT_ULL(3)
40 #define PIN_ZONE_4G BIT_ULL(4)
41 #define PIN_HIGH BIT_ULL(5)
42 #define PIN_OFFSET_BIAS BIT_ULL(6)
43 #define PIN_OFFSET_FIXED BIT_ULL(7)
45 #define PIN_GLOBAL BIT_ULL(10) /* I915_VMA_GLOBAL_BIND */
46 #define PIN_USER BIT_ULL(11) /* I915_VMA_LOCAL_BIND */
/linux/drivers/net/ethernet/intel/i40e/
A Di40e_type.h199 #define I40E_CAP_PHY_TYPE_XFI BIT_ULL(I40E_PHY_TYPE_XFI)
200 #define I40E_CAP_PHY_TYPE_SFI BIT_ULL(I40E_PHY_TYPE_SFI)
220 BIT_ULL(I40E_PHY_TYPE_1000BASE_T_OPTICAL)
588 #define I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE BIT_ULL(0)
589 #define I40E_HW_FLAG_802_1AD_CAPABLE BIT_ULL(1)
590 #define I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE BIT_ULL(2)
591 #define I40E_HW_FLAG_NVM_READ_REQUIRES_LOCK BIT_ULL(3)
592 #define I40E_HW_FLAG_FW_LLDP_STOPPABLE BIT_ULL(4)
593 #define I40E_HW_FLAG_FW_LLDP_PERSISTENT BIT_ULL(5)
594 #define I40E_HW_FLAG_AQ_PHY_ACCESS_EXTENDED BIT_ULL(6)
[all …]
/linux/drivers/net/ethernet/intel/iavf/
A Diavf_adv_rss.h56 BIT_ULL(IAVF_ADV_RSS_FLOW_FIELD_IDX_IPV4_SA)
58 BIT_ULL(IAVF_ADV_RSS_FLOW_FIELD_IDX_IPV6_SA)
60 BIT_ULL(IAVF_ADV_RSS_FLOW_FIELD_IDX_IPV4_DA)
62 BIT_ULL(IAVF_ADV_RSS_FLOW_FIELD_IDX_IPV6_DA)
64 BIT_ULL(IAVF_ADV_RSS_FLOW_FIELD_IDX_TCP_SRC_PORT)
66 BIT_ULL(IAVF_ADV_RSS_FLOW_FIELD_IDX_TCP_DST_PORT)
68 BIT_ULL(IAVF_ADV_RSS_FLOW_FIELD_IDX_UDP_SRC_PORT)
70 BIT_ULL(IAVF_ADV_RSS_FLOW_FIELD_IDX_UDP_DST_PORT)
72 BIT_ULL(IAVF_ADV_RSS_FLOW_FIELD_IDX_SCTP_SRC_PORT)
74 BIT_ULL(IAVF_ADV_RSS_FLOW_FIELD_IDX_SCTP_DST_PORT)
/linux/drivers/i2c/busses/
A Di2c-octeon-core.h12 #define SW_TWSI_V BIT_ULL(63) /* Valid bit */
77 #define TWSI_INT_ST_INT BIT_ULL(0)
78 #define TWSI_INT_TS_INT BIT_ULL(1)
79 #define TWSI_INT_CORE_INT BIT_ULL(2)
80 #define TWSI_INT_ST_EN BIT_ULL(4)
81 #define TWSI_INT_TS_EN BIT_ULL(5)
82 #define TWSI_INT_CORE_EN BIT_ULL(6)
83 #define TWSI_INT_SDA_OVR BIT_ULL(8)
84 #define TWSI_INT_SCL_OVR BIT_ULL(9)
85 #define TWSI_INT_SDA BIT_ULL(10)
[all …]
/linux/drivers/net/ethernet/freescale/dpaa2/
A Ddpmac.h88 #define DPMAC_LINK_OPT_AUTONEG BIT_ULL(0)
89 #define DPMAC_LINK_OPT_HALF_DUPLEX BIT_ULL(1)
90 #define DPMAC_LINK_OPT_PAUSE BIT_ULL(2)
91 #define DPMAC_LINK_OPT_ASYM_PAUSE BIT_ULL(3)
94 #define DPMAC_ADVERTISED_10BASET_FULL BIT_ULL(0)
95 #define DPMAC_ADVERTISED_100BASET_FULL BIT_ULL(1)
96 #define DPMAC_ADVERTISED_1000BASET_FULL BIT_ULL(2)
97 #define DPMAC_ADVERTISED_10000BASET_FULL BIT_ULL(4)
98 #define DPMAC_ADVERTISED_2500BASEX_FULL BIT_ULL(5)
101 #define DPMAC_ADVERTISED_AUTONEG BIT_ULL(3)

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