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Searched refs:CLKID_VCLK2_DIV1 (Results 1 – 8 of 8) sorted by relevance

/linux/include/dt-bindings/clock/
A Daxg-clkc.h92 #define CLKID_VCLK2_DIV1 127 macro
A Dg12a-clkc.h118 #define CLKID_VCLK2_DIV1 153 macro
A Dgxbb-clkc.h139 #define CLKID_VCLK2_DIV1 190 macro
/linux/drivers/clk/meson/
A Dmeson8b.h136 #define CLKID_VCLK2_DIV1 151 macro
A Dmeson8b.c2926 [CLKID_VCLK2_DIV1] = &meson8b_vclk2_div1_gate.hw,
3134 [CLKID_VCLK2_DIV1] = &meson8b_vclk2_div1_gate.hw,
3353 [CLKID_VCLK2_DIV1] = &meson8b_vclk2_div1_gate.hw,
A Dgxbb.c2880 [CLKID_VCLK2_DIV1] = &gxbb_vclk2_div1.hw,
3091 [CLKID_VCLK2_DIV1] = &gxbb_vclk2_div1.hw,
A Dg12a.c4394 [CLKID_VCLK2_DIV1] = &g12a_vclk2_div1.hw,
4623 [CLKID_VCLK2_DIV1] = &g12a_vclk2_div1.hw,
4887 [CLKID_VCLK2_DIV1] = &g12a_vclk2_div1.hw,
A Daxg.c2021 [CLKID_VCLK2_DIV1] = &axg_vclk2_div1.hw,

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