Searched refs:CLK_SCLK_UART0 (Results 1 – 25 of 26) sorted by relevance
12
| /linux/include/dt-bindings/clock/ |
| A D | exynos5410.h | 22 #define CLK_SCLK_UART0 128 macro
|
| A D | exynos5250.h | 42 #define CLK_SCLK_UART0 146 macro
|
| A D | exynos7-clk.h | 37 #define CLK_SCLK_UART0 3 macro
|
| A D | exynos4.h | 64 #define CLK_SCLK_UART0 151 macro
|
| A D | exynos5420.h | 29 #define CLK_SCLK_UART0 128 macro
|
| A D | exynos3250.h | 255 #define CLK_SCLK_UART0 247 macro
|
| A D | exynos5433.h | 437 #define CLK_SCLK_UART0 36 macro
|
| /linux/Documentation/devicetree/bindings/clock/ |
| A D | exynos5410-clock.txt | 48 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
|
| A D | exynos5433-clock.txt | 503 <&cmu_peric CLK_SCLK_UART0>;
|
| /linux/drivers/clk/samsung/ |
| A D | clk-exynos5410.c | 212 GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0",
|
| A D | clk-exynos5250.c | 491 GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0",
|
| A D | clk-exynos3250.c | 567 GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0",
|
| A D | clk-exynos7.c | 365 GATE(CLK_SCLK_UART0, "sclk_uart0", "dout_sclk_uart0",
|
| A D | clk-exynos4.c | 777 GATE(CLK_SCLK_UART0, "uclk0", "div_uart0", SRC_MASK_PERIL0, 0,
|
| A D | clk-exynos5420.c | 979 GATE(CLK_SCLK_UART0, "sclk_uart0", "dout_uart0",
|
| /linux/arch/arm/boot/dts/ |
| A D | exynos3250-artik5.dtsi | 404 assigned-clocks = <&cmu CLK_SCLK_UART0>;
|
| A D | exynos5410.dtsi | 344 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
|
| A D | exynos3250-monk.dts | 457 assigned-clocks = <&cmu CLK_SCLK_UART0>;
|
| A D | exynos3250-rinato.dts | 667 assigned-clocks = <&cmu CLK_SCLK_UART0>;
|
| A D | exynos3250.dtsi | 514 clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>;
|
| A D | exynos4.dtsi | 453 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
|
| A D | exynos5250.dtsi | 1204 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
|
| A D | exynos5420.dtsi | 1326 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
|
| /linux/arch/arm64/boot/dts/exynos/ |
| A D | exynos7.dtsi | 212 <&clock_top0 CLK_SCLK_UART0>;
|
| A D | exynos5433.dtsi | 1422 <&cmu_peric CLK_SCLK_UART0>;
|
Completed in 65 milliseconds
12