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Searched refs:CLK_TOP_AUD_1 (Results 1 – 4 of 4) sorted by relevance

/linux/include/dt-bindings/clock/
A Dmt6765-clk.h98 #define CLK_TOP_AUD_1 63 macro
A Dmt6779-clk.h30 #define CLK_TOP_AUD_1 20 macro
/linux/drivers/clk/mediatek/
A Dclk-mt6779.c757 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_1, "aud_1_sel", aud_1_parents,
A Dclk-mt6765.c145 FACTOR(CLK_TOP_AUD_1, "aud_1_ck", "aud_1_sel", 1, 1),

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