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Searched refs:CLK_TOP_SPISLV_SEL (Results 1 – 4 of 4) sorted by relevance

/linux/Documentation/devicetree/bindings/spi/
A Dspi-slave-mt27xx.txt14 - assigned-clocks: it's mux clock, should be <&topckgen CLK_TOP_SPISLV_SEL>.
31 assigned-clocks = <&topckgen CLK_TOP_SPISLV_SEL>;
/linux/include/dt-bindings/clock/
A Dmt2712-clk.h188 #define CLK_TOP_SPISLV_SEL 157 macro
/linux/drivers/clk/mediatek/
A Dclk-mt2712.c868 MUX_GATE(CLK_TOP_SPISLV_SEL, "spislv_sel",
/linux/arch/arm64/boot/dts/mediatek/
A Dmt2712e.dtsi321 assigned-clocks = <&topckgen CLK_TOP_SPISLV_SEL>;

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