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/linux/Documentation/driver-api/media/drivers/
A Dpxa_camera.rst46 | | DMA: stop | | DMA: stop | |
56 | | DMA: stop | / | DMA: run | | |
66 | DMA: run | | DMA: run | |
75 | DMA: run | | DMA: stop |
84 - "DMA: stop" means all 3 DMA channels are stopped
85 - "DMA: run" means at least 1 DMA channel is still running
87 DMA usage
90 a) DMA flow
94 starts the DMA chain.
148 As DMA chaining is done while DMA _is_ running, the linking may be done
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/linux/Documentation/translations/zh_CN/PCI/
A Dpci.rst55 - 设置DMA掩码大小（对于流式和一致的DMA）
183 - 设置DMA掩码大小（对于流式和一致的DMA）
250 设置DMA掩码大小
254 驱动程序需要说明设备的DMA功能，并不是DMA接口的权威来源。
274 用设备的动态DMA映射，了解DMA API的完整描述。本节只是提醒大家，需要在设备上启
275 用DMA之前完成。
318 2) MSI避免了DMA/IRQ竞争条件。到主机内存的DMA被保证在MSI交付时对主机CPU是可
364 在试图取消分配DMA控制数据之前，停止所有的DMA操作是非常重要的。如果不这样做，
367 在停止IRQ后停止DMA可以避免IRQ处理程序可能重新启动DMA引擎的竞争。
373 释放DMA缓冲区
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/linux/drivers/dma/
A DKconfig3 # DMA engine configuration
7 bool "DMA Engine support"
18 bool "DMA Engine debugging"
35 comment "DMA Devices"
471 Support the MXS DMA engine. This engine including APBH-DMA
567 It supports 16 independent DMA channels, accepts up to 32 DMA requests
619 DMA controller is having multiple DMA channels which can be
638 DMA controller is having multiple DMA channel which can be
651 DMA controller has multiple DMA channels and is used to service
762 comment "DMA Clients"
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/linux/Documentation/devicetree/bindings/powerpc/fsl/
A Ddma.txt1 * Freescale DMA Controllers
3 ** Freescale Elo DMA Controller
13 DMA channels and the address space of the DMA controller
17 - DMA channel nodes:
68 ** Freescale EloPlus DMA Controller
81 DMA channels and the address space of the DMA controller
83 - DMA channel nodes:
128 ** Freescale Elo3 DMA Controller
140 DMA channels and the address space of the DMA controller
142 - DMA channel nodes:
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/linux/Documentation/devicetree/bindings/dma/
A Dfsl-imx-dma.txt1 * Freescale Direct Memory Access (DMA) Controller for i.MX
3 This document will only describe differences to the generic DMA Controller and
4 DMA request bindings as described in dma/dma.txt .
6 * DMA controller
10 - reg : Should contain DMA registers location and length
12 should contain DMA Error interrupt
16 - #dma-channels : Number of DMA channels supported. Should be 16.
17 - #dma-requests : Number of DMA requests supported.
30 * DMA client
32 Clients have to specify the DMA requests with phandles in a list.
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A Dti-dma-crossbar.txt1 Texas Instruments DMA Crossbar (DMA request router)
4 - compatible: "ti,dra7-dma-crossbar" for DRA7xx DMA crossbar
9 - dma-requests: Number of DMA requests the crossbar can receive
10 - dma-masters: phandle pointing to the DMA controller
12 The DMA controller node need to have the following poroperties:
13 - dma-requests: Number of DMA requests the controller can handle
18 when mapping xbar input to DMA request, they are either
24 the DMA event number as crossbar ID (input to the DMA crossbar).
33 /* DMA controller */
46 /* DMA crossbar */
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A Dst,stm32-dma.yaml7 title: STMicroelectronics STM32 DMA Controller bindings
10 The STM32 DMA is a general-purpose direct memory access controller capable of
11 supporting 8 independent DMA channels. Each channel can have up to 8 requests.
12 DMA clients connected to the STM32 DMA controller must use the format
17 3. A 32bit mask specifying the DMA channel configuration which are device
34 -bit 0-1: DMA FIFO threshold selection
39 -bit 2: DMA direct mode
41 0x1: Direct mode: each DMA request immediately initiates a transfer
43 -bit 4: alternative DMA request/acknowledge protocol
73 description: Should contain all of the per-channel DMA
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A Dmpc512x-dma.txt1 * Freescale MPC512x and MPC8308 DMA Controller
3 The DMA controller in Freescale MPC512x and MPC8308 SoCs can move
7 Refer to "Generic DMA Controller and DMA request bindings" in
12 - reg: should contain the DMA controller registers location and length;
13 - interrupt for the DMA controller: syntax of interrupt client node
15 - #dma-cells: the length of the DMA specifier, must be <1>.
16 Each channel of this DMA controller has a peripheral request line,
29 DMA clients must use the format described in dma/dma.txt file.
A Dmmp-dma.txt1 * MARVELL MMP DMA controller
3 Marvell Peripheral DMA Controller
8 - reg: Should contain DMA registers location and length.
9 - interrupts: Either contain all of the per-channel DMA interrupts
13 - #dma-channels: Number of DMA channels supported by the controller (defaults
15 - #dma-requests: Number of DMA requestor lines supported by the controller
26 * while DMA controller may not able to distinguish the irq channel
41 * Dmaengine driver (DMA controller) distinguish irq channel via
52 Marvell Two Channel DMA Controller used specifically for audio
57 - reg: Should contain DMA registers location and length.
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A Dintel,ldma.yaml7 title: Lightning Mountain centralized DMA controllers.
34 The first cell is the peripheral's DMA request line.
61 DMA descriptor polling counter is used to control the poling mechanism
67 DMA byte enable is only valid for DMA write(RX).
68 Byte enable(1) means DMA write will be based on the number of dwords
74 DMA descriptor read back to make sure data and desc synchronization.
79 Enable RX dynamic burst write. When it is enabled, the DMA does RX dynamic burst;
80 if it is disabled, the DMA RX will still support programmable fixed burst size of 2,4,8,16.
81 It only applies to RX DMA and memcopy DMA.
A Dsprd-dma.txt1 * Spreadtrum DMA controller
3 This binding follows the generic DMA bindings defined in dma.txt.
7 - reg: Should contain DMA registers location and length.
11 - #dma-channels : Number of DMA channels supported. Should be 32.
12 - clock-names: Should contain the clock of the DMA controller.
30 DMA clients connected to the Spreadtrum DMA controller must use the format
33 1. A phandle pointing to the DMA controller.
A Ddma-common.yaml7 title: DMA Engine Generic Binding
13 Generic binding to provide a way for a driver using DMA Engine to
14 retrieve the DMA request or channel information that goes from a
15 hardware device to a DMA controller.
25 Used to provide DMA controller specific information.
29 Bitmask of available DMA channels in ascending order that are
43 Number of DMA channels supported by the controller.
48 Number of DMA request signals supported by the controller.
A Dsnps,dma-spear1340.yaml7 title: Synopsys Designware DMA Controller
24 First cell is a phandle pointing to the DMA controller. Second one is
25 the DMA request line number. Third cell is the memory master identifier
46 Number of DMA channels supported by the controller. In case if
59 Number of DMA masters supported by the controller. In case if
68 DMA channels allocation order specifier. Zero means ascending order
76 DMA channels priority order. Zero means ascending channels priority
84 description: Maximum block size supported by the DMA controller.
89 description: Data bus width per each DMA master in bytes.
119 each DMA channel.
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/linux/Documentation/core-api/
A Ddma-isa-lpc.rst2 DMA with ISA and LPC devices
7 This document describes how to do DMA transfers using the old ISA DMA
9 uses the same DMA system so it will be around for quite some time.
14 To do ISA style DMA you need to include two headers::
87 Now for the good stuff, the actual DMA transfer. :)
89 Before you use any ISA DMA routines you need to claim the DMA lock
94 The first time you use the DMA controller you should call
95 clear_dma_ff(). This clears an internal register in the DMA
109 The final step is enabling the DMA channel and releasing the DMA
140 printk(KERN_ERR "driver: Incomplete DMA transfer!"
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A Ddma-api-howto.rst2 Dynamic DMA mapping Guide
11 DMA-API.txt.
13 CPU and DMA addresses
109 everywhere you hold a DMA address returned from the DMA mapping functions.
125 returned from vmalloc() for DMA. It is possible to DMA to the
276 Types of DMA mappings
325 - Streaming DMA mappings which are usually mapped for one DMA
371 return > 32-bit addresses for DMA if the consistent DMA mask has been
439 DMA Direction
642 After the last DMA transfer call one of the DMA unmap routines
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/linux/Documentation/devicetree/bindings/soc/ti/
A Dkeystone-navigator-dma.txt1 Keystone Navigator DMA Controller
9 an internal packet DMA module which is used as an infrastructure DMA
12 Navigator DMA cloud layout:
17 |-> DMA instance #0
19 |-> DMA instance #1
23 |-> DMA instance #n
25 Navigator DMA properties:
34 into DMA and the DMA uses it as the physical addresses to reach queue
40 DMA instance properties:
94 Navigator DMA client:
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/linux/Documentation/driver-api/dmaengine/
A Dclient.rst2 DMA Engine API Guide
12 DMA Engine. This is applicable only for slave DMA usage only.
14 DMA usage
17 The slave DMA usage consists of following steps:
19 - Allocate a DMA slave channel
31 1. Allocate a DMA slave channel
56 DMA direction, DMA addresses, bus widths, DMA burst lengths etc
79 DMA-engine are:
141 case for slave/cyclic DMA.
149 DMA via dmaengine_terminate_async().
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/linux/drivers/dma/sh/
A DKconfig3 # DMA engine configuration for sh
11 # DMA Engine Helpers
15 bool "Renesas SuperH DMA Engine support"
22 Enable support for the Renesas SuperH DMA controllers.
25 # DMA Controllers
32 Enable support for the Renesas SuperH DMA controllers.
35 tristate "Renesas R-Car Gen{2,3} and RZ/G{1,2} DMA Controller"
39 This driver supports the general purpose DMA controller found in the
43 tristate "Renesas USB-DMA Controller"
48 This driver supports the USB-DMA controller found in the Renesas
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/linux/Documentation/i2c/
A Ddma-considerations.rst2 Linux I2C and DMA
6 transferred are small, it is not considered a prime user of DMA access. At this
7 time of writing, only 10% of I2C bus master drivers have DMA support
9 DMA for it will likely add more overhead than a plain PIO transfer.
11 Therefore, it is *not* mandatory that the buffer of an I2C message is DMA safe.
13 rarely used. However, it is recommended to use a DMA-safe buffer if your
14 message size is likely applicable for DMA. Most drivers have this threshold
18 I2C bus master driver is using USB as a bridge, then you need to have DMA
24 For clients, if you use a DMA safe buffer in i2c_msg, set the I2C_M_DMA_SAFE
34 of i2c_master_send() and i2c_master_recv() functions can now use DMA safe
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/linux/Documentation/driver-api/
A Ddma-buf.rst17 Shared DMA Buffers
112 DMA-BUF statistics
117 DMA Buffer ioctls
152 DMA Fences
156 :doc: DMA fences overview
179 DMA Fence Array
188 DMA Fence Chain
197 DMA Fence uABI/Sync File
206 Indefinite DMA Fences
225 batch DMA fences for memory management instead of context preemption DMA
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/linux/Documentation/driver-api/usb/
A Ddma.rst1 USB DMA
5 over how DMA may be used to perform I/O operations. The APIs are detailed
11 The big picture is that USB drivers can continue to ignore most DMA issues,
12 though they still must provide DMA-ready buffers (see
14 the 2.4 (and earlier) kernels, or they can now be DMA-aware.
16 DMA-aware usb drivers:
18 - New calls enable DMA-aware drivers, letting them allocate dma buffers and
25 - "usbcore" will map this DMA address, if a DMA-aware driver didn't do
64 "streaming" DMA mappings.)
73 lines to prevent DMA conflicts.
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/linux/drivers/dma/ti/
A DKconfig3 # Texas Instruments DMA drivers
7 tristate "Texas Instruments CPPI 4.1 DMA support"
11 The Communications Port Programming Interface (CPPI) 4.1 DMA engine
22 Enable support for the TI EDMA (Enhanced DMA) controller. This DMA
34 Enable support for the TI sDMA (System DMA or DMA4) controller. This
35 DMA engine is found on OMAP and DRA7xx parts.
47 Enable support for the TI UDMA (Unified DMA) controller. This
48 DMA engine is used in AM65x and j721e.
55 Say y here to support the K3 NAVSS DMA glue interface
/linux/drivers/dma/qcom/
A DKconfig8 Enable support for the Qualcomm Application Data Mover (ADM) DMA
10 This controller provides DMA capabilities for both general purpose
14 tristate "QCOM BAM DMA support"
19 Enable support for the QCOM BAM DMA controller. This controller
20 provides DMA capabilities for a variety of on-chip devices.
23 tristate "Qualcomm Technologies GPI DMA support"
28 Enable support for the QCOM GPI DMA controller. This controller
29 provides DMA capabilities for a variety of peripheral buses such
40 Each DMA device requires one management interface driver
54 purpose slave DMA.
/linux/Documentation/devicetree/bindings/powerpc/4xx/
A Dppc440spe-adma.txt1 PPC440SPe DMA/XOR (DMA Controller and XOR Accelerator)
4 are specified hereby. These are I2O/DMA, DMA and XOR nodes
5 for DMA engines and Memory Queue Module node. The latter is used
9 DMA devices.
28 ii) The DMA node
33 - cell-index : 1 cell, hardware index of the DMA engine
39 and DMA Error IRQ (on UIC1). The latter is common
40 for both DMA engines>.
/linux/Documentation/driver-api/rapidio/
A Dtsi721.rst12 To generate SRIO maintenance transactions this driver uses one of Tsi721 DMA
34 descriptors allocated for each registered Tsi721 DMA channel.
38 - DMA transactions queue size. Defines number of pending
39 transaction requests that can be accepted by each DMA channel.
43 - DMA channel selection mask. Bitmask that defines which hardware
44 DMA channels (0 ... 6) will be registered with DmaEngine core.
45 If bit is set to 1, the corresponding DMA channel will be registered.
68 3. DMA Engine Support
73 mode API defined by common Linux kernel DMA Engine framework.
77 out of eight available BDMA channels to support DMA data transfers.
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