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Searched refs:EMC_XM2DQSPADCTRL3 (Results 1 – 8 of 8) sorted by relevance

/linux/arch/arm/boot/dts/
A Dtegra30-asus-nexus7-grouper-memory-timings.dtsi408 0x08000000 /* EMC_XM2DQSPADCTRL3 */
512 0x08000000 /* EMC_XM2DQSPADCTRL3 */
616 0x08000000 /* EMC_XM2DQSPADCTRL3 */
720 0x08000000 /* EMC_XM2DQSPADCTRL3 */
822 0x08000021 /* EMC_XM2DQSPADCTRL3 */
925 0x0a000021 /* EMC_XM2DQSPADCTRL3 */
1033 0x08000000 /* EMC_XM2DQSPADCTRL3 */
1137 0x08000000 /* EMC_XM2DQSPADCTRL3 */
1241 0x08000000 /* EMC_XM2DQSPADCTRL3 */
1345 0x08000000 /* EMC_XM2DQSPADCTRL3 */
[all …]
A Dtegra30-asus-nexus7-tilapia-memory-timings.dtsi103 0x08000021 /* EMC_XM2DQSPADCTRL3 */
207 0x08000021 /* EMC_XM2DQSPADCTRL3 */
310 0x0c000021 /* EMC_XM2DQSPADCTRL3 */
A Dtegra124-nyan-big-emc.dtsi377 0x51451400 /* EMC_XM2DQSPADCTRL3 */
545 0x51451400 /* EMC_XM2DQSPADCTRL3 */
713 0x51451400 /* EMC_XM2DQSPADCTRL3 */
881 0x51451400 /* EMC_XM2DQSPADCTRL3 */
1049 0x51451400 /* EMC_XM2DQSPADCTRL3 */
1217 0x51451400 /* EMC_XM2DQSPADCTRL3 */
1385 0x51451420 /* EMC_XM2DQSPADCTRL3 */
1553 0x51451420 /* EMC_XM2DQSPADCTRL3 */
1721 0x51451420 /* EMC_XM2DQSPADCTRL3 */
1889 0x51451420 /* EMC_XM2DQSPADCTRL3 */
[all …]
A Dtegra30-ouya.dts1111 0x08000000 /* EMC_XM2DQSPADCTRL3 */
1212 0x08000000 /* EMC_XM2DQSPADCTRL3 */
1313 0x08000000 /* EMC_XM2DQSPADCTRL3 */
1414 0x08000000 /* EMC_XM2DQSPADCTRL3 */
1513 0x08000021 /* EMC_XM2DQSPADCTRL3 */
1613 0x08000021 /* EMC_XM2DQSPADCTRL3 */
1717 0x08000000 /* EMC_XM2DQSPADCTRL3 */
1818 0x08000000 /* EMC_XM2DQSPADCTRL3 */
1919 0x08000000 /* EMC_XM2DQSPADCTRL3 */
2020 0x08000000 /* EMC_XM2DQSPADCTRL3 */
[all …]
/linux/Documentation/devicetree/bindings/memory-controllers/
A Dnvidia,tegra30-emc.yaml196 - description: EMC_XM2DQSPADCTRL3
341 0x0c000021 /* EMC_XM2DQSPADCTRL3 */
A Dnvidia,tegra124-emc.yaml299 - description: EMC_XM2DQSPADCTRL3
532 0x51451400 /* EMC_XM2DQSPADCTRL3 */
/linux/drivers/memory/tegra/
A Dtegra30-emc.c84 #define EMC_XM2DQSPADCTRL3 0x0f8 macro
304 [78] = EMC_XM2DQSPADCTRL3,
461 val = readl_relaxed(emc->regs + EMC_XM2DQSPADCTRL3); in emc_dqs_preset()
465 writel_relaxed(val, emc->regs + EMC_XM2DQSPADCTRL3); in emc_dqs_preset()
A Dtegra124-emc.c116 #define EMC_XM2DQSPADCTRL3 0xf8 macro
430 EMC_XM2DQSPADCTRL3,

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