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Searched refs:FIELD_PREP (Results 1 – 25 of 435) sorted by relevance

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/linux/drivers/misc/habanalabs/include/gaudi/
A Dgaudi_masks.h15 (FIELD_PREP(DMA0_QM_GLBL_CFG0_PQF_EN_MASK, 0xF)) | \
16 (FIELD_PREP(DMA0_QM_GLBL_CFG0_CQF_EN_MASK, 0xF)) | \
17 (FIELD_PREP(DMA0_QM_GLBL_CFG0_CP_EN_MASK, 0xF)))
20 (FIELD_PREP(DMA0_QM_GLBL_PROT_PQF_MASK, 0xF)) | \
21 (FIELD_PREP(DMA0_QM_GLBL_PROT_CQF_MASK, 0xF)) | \
22 (FIELD_PREP(DMA0_QM_GLBL_PROT_CP_MASK, 0xF)) | \
23 (FIELD_PREP(DMA0_QM_GLBL_PROT_ERR_MASK, 0x1)))
26 (FIELD_PREP(DMA0_QM_GLBL_PROT_PQF_MASK, 0xF)) | \
27 (FIELD_PREP(DMA0_QM_GLBL_PROT_ERR_MASK, 0x1)))
53 (FIELD_PREP(DMA0_QM_CGM_CFG_EN_MASK, 0x1)))
[all …]
/linux/drivers/iio/adc/
A Dstm32-dfsdm.h111 #define DFSDM_CR1_DFEN(v) FIELD_PREP(DFSDM_CR1_DFEN_MASK, v)
133 #define DFSDM_CR1_RCH(v) FIELD_PREP(DFSDM_CR1_RCH_MASK, v)
135 #define DFSDM_CR1_FAST(v) FIELD_PREP(DFSDM_CR1_FAST_MASK, v)
141 #define DFSDM_CR2_IE(v) FIELD_PREP(DFSDM_CR2_IE_MASK, v)
157 #define DFSDM_CR2_EXCH(v) FIELD_PREP(DFSDM_CR2_EXCH_MASK, v)
171 #define DFSDM_ISR_AWDF(v) FIELD_PREP(DFSDM_ISR_AWDF_MASK, v)
173 #define DFSDM_ISR_JCIP(v) FIELD_PREP(DFSDM_ISR_JCIP_MASK, v)
175 #define DFSDM_ISR_RCIP(v) FIELD_PREP(DFSDM_ISR_RCIP, v)
179 #define DFSDM_ISR_SCDF(v) FIELD_PREP(DFSDM_ISR_SCDF_MASK, v)
199 #define DFSDM_FCR_IOSR(v) FIELD_PREP(DFSDM_FCR_IOSR_MASK, v)
[all …]
A Dimx8qxp-adc.c141 adc_cfg = FIELD_PREP(IMX8QXP_ADC_CFG_PWREN_MASK, 1) | in imx8qxp_adc_reg_config()
142 FIELD_PREP(IMX8QXP_ADC_CFG_PUDLY_MASK, 0x80)| in imx8qxp_adc_reg_config()
143 FIELD_PREP(IMX8QXP_ADC_CFG_REFSEL_MASK, 0) | in imx8qxp_adc_reg_config()
144 FIELD_PREP(IMX8QXP_ADC_CFG_PWRSEL_MASK, 3) | in imx8qxp_adc_reg_config()
145 FIELD_PREP(IMX8QXP_ADC_CFG_TPRICTRL_MASK, 0); in imx8qxp_adc_reg_config()
150 FIELD_PREP(IMX8QXP_ADC_TCTRL_TDLY_MASK, 0) | in imx8qxp_adc_reg_config()
160 FIELD_PREP(IMX8QXP_ADC_CMDL_ADCH_MASK, channel); in imx8qxp_adc_reg_config()
164 FIELD_PREP(IMX8QXP_ADC_CMDH_LOOP_MASK, 0) | in imx8qxp_adc_reg_config()
165 FIELD_PREP(IMX8QXP_ADC_CMDH_AVGS_MASK, 7) | in imx8qxp_adc_reg_config()
166 FIELD_PREP(IMX8QXP_ADC_CMDH_STS_MASK, 0) | in imx8qxp_adc_reg_config()
[all …]
/linux/drivers/phy/microchip/
A Dsparx5_serdes_regs.h42 FIELD_PREP(SD10G_LANE_LANE_01_CFG_RXDET_EN, x)
57 FIELD_PREP(SD10G_LANE_LANE_02_CFG_EN_ADV, x)
63 FIELD_PREP(SD10G_LANE_LANE_02_CFG_EN_MAIN, x)
69 FIELD_PREP(SD10G_LANE_LANE_02_CFG_EN_DLY, x)
75 FIELD_PREP(SD10G_LANE_LANE_02_CFG_EN_DLY2, x)
942 FIELD_PREP(SD10G_LANE_LANE_DF_LOL, x)
2094 FIELD_PREP(SD6G_LANE_LANE_DF_LOL, x)
2169 FIELD_PREP(SD_CMU_CMU_09_CFG_SW_8G, x)
2289 FIELD_PREP(SD_CMU_CMU_45_RESERVED, x)
2457 FIELD_PREP(SD_LANE_MISC_RX_ENA, x)
[all …]
/linux/drivers/net/ethernet/microchip/sparx5/
A Dsparx5_main_regs.h61 FIELD_PREP(ANA_AC_RAM_INIT_RAM_INIT, x)
1054 FIELD_PREP(CPU_PROC_CTRL_CFGTE, x)
2727 FIELD_PREP(FDMA_CH_CFG_CH_MEM, x)
2904 FIELD_PREP(FDMA_CTRL_NRESET, x)
2913 FIELD_PREP(GCB_CHIP_ID_REV_ID, x)
2925 FIELD_PREP(GCB_CHIP_ID_MFG_ID, x)
2931 FIELD_PREP(GCB_CHIP_ID_ONE, x)
4314 FIELD_PREP(QS_INJ_CTRL_ABORT, x)
4320 FIELD_PREP(QS_INJ_CTRL_EOF, x)
4326 FIELD_PREP(QS_INJ_CTRL_SOF, x)
[all …]
/linux/drivers/infiniband/hw/irdma/
A Duda.c31 qw1 = FIELD_PREP(IRDMA_UDA_CQPSQ_MAV_PDINDEXLO, info->pd_idx) | in irdma_sc_access_ah()
32 FIELD_PREP(IRDMA_UDA_CQPSQ_MAV_TC, info->tc_tos) | in irdma_sc_access_ah()
33 FIELD_PREP(IRDMA_UDAQPC_VLANTAG, info->vlan_tag); in irdma_sc_access_ah()
37 FIELD_PREP(IRDMA_UDA_CQPSQ_MAV_HOPLIMIT, info->hop_ttl) | in irdma_sc_access_ah()
69 FIELD_PREP(IRDMA_UDA_CQPSQ_MAV_WQEVALID, cqp->polarity) | in irdma_sc_access_ah()
70 FIELD_PREP(IRDMA_UDA_CQPSQ_MAV_OPCODE, op) | in irdma_sc_access_ah()
71 FIELD_PREP(IRDMA_UDA_CQPSQ_MAV_DOLOOPBACKK, info->do_lpbk) | in irdma_sc_access_ah()
72 FIELD_PREP(IRDMA_UDA_CQPSQ_MAV_IPV4VALID, info->ipv4_valid) | in irdma_sc_access_ah()
73 FIELD_PREP(IRDMA_UDA_CQPSQ_MAV_AVIDX, info->ah_idx) | in irdma_sc_access_ah()
164 FIELD_PREP(IRDMA_UDA_CQPSQ_MG_OPCODE, op) | in irdma_access_mcast_grp()
[all …]
A Dctrl.c328 FIELD_PREP(IRDMA_CQPSQ_QHASH_OPCODE, in irdma_sc_manage_qhash_table_entry()
657 FIELD_PREP(IRDMAQPC_TTL, udp->ttl) | FIELD_PREP(IRDMAQPC_TOS, udp->tos) | in irdma_sc_qp_setctx_roce()
751 hdr = FIELD_PREP(IRDMA_CQPSQ_OPCODE, in irdma_sc_alloc_local_mac_entry()
790 FIELD_PREP(IRDMA_CQPSQ_OPCODE, in irdma_sc_add_local_mac_entry()
825 FIELD_PREP(IRDMA_CQPSQ_OPCODE, in irdma_sc_del_local_mac_entry()
913 FIELD_PREP(IRDMAQPC_RTOMIN, iw->rtomin); in irdma_sc_qp_setctx()
2228 FIELD_PREP(IRDMA_CQPSQ_FWQE_RQMJERR, in irdma_sc_qp_flush_wqes()
2233 FIELD_PREP(IRDMA_CQPSQ_FWQE_SQMJERR, in irdma_sc_qp_flush_wqes()
3162 FIELD_PREP(IRDMA_CQPHC_PROTOCOL_USED, in irdma_sc_cqp_create()
3465 FIELD_PREP(IRDMA_CQPSQ_OPCODE, in irdma_sc_manage_hmc_pm_func_table()
[all …]
A Duk.c21 FIELD_PREP(IRDMAQPSQ_FRAG_TO, sge->addr)); in irdma_set_fragment()
23 FIELD_PREP(IRDMAQPSQ_VALID, valid) | in irdma_set_fragment()
24 FIELD_PREP(IRDMAQPSQ_FRAG_LEN, sge->length) | in irdma_set_fragment()
25 FIELD_PREP(IRDMAQPSQ_FRAG_STAG, sge->lkey)); in irdma_set_fragment()
29 FIELD_PREP(IRDMAQPSQ_VALID, valid)); in irdma_set_fragment()
45 FIELD_PREP(IRDMAQPSQ_FRAG_TO, sge->addr)); in irdma_set_fragment_gen_1()
79 FIELD_PREP(IRDMAQPSQ_SIGCOMPL, signaled) | in irdma_nop_1()
433 FIELD_PREP(IRDMAQPSQ_OPCODE, in irdma_uk_rdma_read()
529 FIELD_PREP(IRDMAQPSQ_IMMDATAFLAG, in irdma_uk_send()
714 FIELD_PREP(IRDMAQPSQ_INLINEDATAFLAG, 1) | in irdma_uk_inline_rdma_write()
[all …]
/linux/drivers/net/wireless/ath/ath11k/
A Dhal_tx.c42 FIELD_PREP(BUFFER_ADDR_INFO0_ADDR, ti->paddr); in ath11k_hal_tx_cmd_desc_setup()
44 FIELD_PREP(BUFFER_ADDR_INFO1_ADDR, in ath11k_hal_tx_cmd_desc_setup()
47 FIELD_PREP(BUFFER_ADDR_INFO1_RET_BUF_MGR, in ath11k_hal_tx_cmd_desc_setup()
54 FIELD_PREP(HAL_TCL_DATA_CMD_INFO0_ENCRYPT_TYPE, in ath11k_hal_tx_cmd_desc_setup()
56 FIELD_PREP(HAL_TCL_DATA_CMD_INFO0_SEARCH_TYPE, in ath11k_hal_tx_cmd_desc_setup()
58 FIELD_PREP(HAL_TCL_DATA_CMD_INFO0_ADDR_EN, in ath11k_hal_tx_cmd_desc_setup()
60 FIELD_PREP(HAL_TCL_DATA_CMD_INFO0_CMD_NUM, in ath11k_hal_tx_cmd_desc_setup()
108 FIELD_PREP(HAL_TCL1_RING_FIELD_DSCP_TID_MAP1, in ath11k_hal_tx_set_dscp_tid_map()
110 FIELD_PREP(HAL_TCL1_RING_FIELD_DSCP_TID_MAP2, in ath11k_hal_tx_set_dscp_tid_map()
112 FIELD_PREP(HAL_TCL1_RING_FIELD_DSCP_TID_MAP3, in ath11k_hal_tx_set_dscp_tid_map()
[all …]
A Dhal_rx.c29 FIELD_PREP(HAL_TLV_HDR_LEN, sizeof(*desc)); in ath11k_hal_reo_cmd_queue_stats()
62 FIELD_PREP(HAL_TLV_HDR_LEN, sizeof(*desc)); in ath11k_hal_reo_cmd_flush_cache()
101 FIELD_PREP(HAL_TLV_HDR_LEN, sizeof(*desc)); in ath11k_hal_reo_cmd_update_rx_queue()
125 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_AC, in ath11k_hal_reo_cmd_update_rx_queue()
157 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN, in ath11k_hal_reo_cmd_update_rx_queue()
163 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO1_VLD, in ath11k_hal_reo_cmd_update_rx_queue()
171 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO1_AC, in ath11k_hal_reo_cmd_update_rx_queue()
173 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO1_BAR, in ath11k_hal_reo_cmd_update_rx_queue()
177 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO1_RETRY, in ath11k_hal_reo_cmd_update_rx_queue()
209 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO2_SVLD, in ath11k_hal_reo_cmd_update_rx_queue()
[all …]
/linux/drivers/phy/amlogic/
A Dphy-meson-g12a-usb2.c187 FIELD_PREP(PHY_CTRL_R16_MPLL_M, 20) | in phy_meson_g12a_usb2_init()
188 FIELD_PREP(PHY_CTRL_R16_MPLL_N, 1) | in phy_meson_g12a_usb2_init()
203 FIELD_PREP(PHY_CTRL_R18_MPLL_LK_W, 9) | in phy_meson_g12a_usb2_init()
204 FIELD_PREP(PHY_CTRL_R18_MPLL_LK_S, 0x27) | in phy_meson_g12a_usb2_init()
205 FIELD_PREP(PHY_CTRL_R18_MPLL_PFD_GAIN, 1) | in phy_meson_g12a_usb2_init()
206 FIELD_PREP(PHY_CTRL_R18_MPLL_ROU, 7) | in phy_meson_g12a_usb2_init()
209 FIELD_PREP(PHY_CTRL_R18_MPLL_BB_MODE, 0) | in phy_meson_g12a_usb2_init()
210 FIELD_PREP(PHY_CTRL_R18_MPLL_ALPHA, 3) | in phy_meson_g12a_usb2_init()
211 FIELD_PREP(PHY_CTRL_R18_MPLL_ADJ_LDO, 1) | in phy_meson_g12a_usb2_init()
223 FIELD_PREP(PHY_CTRL_R16_MPLL_M, 20) | in phy_meson_g12a_usb2_init()
[all …]
/linux/drivers/crypto/ccree/
A Dcc_hw_queue_defs.h245 FIELD_PREP(WORD1_DIN_SIZE, size) | in set_din_type()
246 FIELD_PREP(WORD1_NS_BIT, axi_sec); in set_din_type()
292 FIELD_PREP(WORD1_DIN_DMA_MODE, DMA_SRAM); in set_din_sram()
306 FIELD_PREP(WORD1_DIN_DMA_MODE, DMA_SRAM) | in set_din_const()
307 FIELD_PREP(WORD1_DIN_SIZE, size); in set_din_const()
338 FIELD_PREP(WORD3_DOUT_SIZE, size) | in set_dout_type()
339 FIELD_PREP(WORD3_NS_BIT, axi_sec); in set_dout_type()
450 FIELD_PREP(WORD3_DOUT_SIZE, size); in set_dout_sram()
548 pdesc->word[4] |= FIELD_PREP(WORD4_CIPHER_DO, in set_hw_crypto_key()
550 FIELD_PREP(WORD4_CIPHER_CONF2, in set_hw_crypto_key()
[all …]
/linux/drivers/i3c/master/mipi-i3c-hci/
A Dcmd_v1.c23 #define CMD_0_ATTR_A FIELD_PREP(CMD_0_ATTR, 0x2)
29 #define CMD_A0_CMD(v) FIELD_PREP(W0_MASK(14, 7), v)
30 #define CMD_A0_TID(v) FIELD_PREP(W0_MASK( 6, 3), v)
36 #define CMD_0_ATTR_I FIELD_PREP(CMD_0_ATTR, 0x1)
46 #define CMD_I0_MODE(v) FIELD_PREP(W0_MASK(28, 26), v)
47 #define CMD_I0_DTT(v) FIELD_PREP(W0_MASK(25, 23), v)
50 #define CMD_I0_CMD(v) FIELD_PREP(W0_MASK(14, 7), v)
51 #define CMD_I0_TID(v) FIELD_PREP(W0_MASK( 6, 3), v)
57 #define CMD_0_ATTR_R FIELD_PREP(CMD_0_ATTR, 0x0)
75 #define CMD_0_ATTR_C FIELD_PREP(CMD_0_ATTR, 0x3)
[all …]
A Dcmd_v2.c24 #define CMD_0_ATTR_U FIELD_PREP(CMD_0_ATTR, 0x4)
27 #define CMD_U3_IDB4(v) FIELD_PREP(W3_MASK(103, 96), v)
28 #define CMD_U3_HDR_CMD(v) FIELD_PREP(W3_MASK(103, 96), v)
29 #define CMD_U2_IDB3(v) FIELD_PREP(W2_MASK( 95, 88), v)
30 #define CMD_U2_HDR_BT(v) FIELD_PREP(W2_MASK( 95, 88), v)
31 #define CMD_U2_IDB2(v) FIELD_PREP(W2_MASK( 87, 80), v)
33 #define CMD_U2_IDB1(v) FIELD_PREP(W2_MASK( 79, 72), v)
35 #define CMD_U2_IDB0(v) FIELD_PREP(W2_MASK( 71, 64), v)
50 #define CMD_U0_TID(v) FIELD_PREP(W0_MASK( 6, 3), v)
56 #define CMD_0_ATTR_A FIELD_PREP(CMD_0_ATTR, 0x2)
[all …]
/linux/drivers/gpu/drm/meson/
A Dmeson_overlay.c36 #define CANVAS_ADDR2(addr) FIELD_PREP(GENMASK(23, 16), addr)
37 #define CANVAS_ADDR1(addr) FIELD_PREP(GENMASK(15, 8), addr)
38 #define CANVAS_ADDR0(addr) FIELD_PREP(GENMASK(7, 0), addr)
41 #define VD_X_START(value) FIELD_PREP(GENMASK(14, 0), value)
42 #define VD_X_END(value) FIELD_PREP(GENMASK(30, 16), value)
45 #define VD_Y_START(value) FIELD_PREP(GENMASK(12, 0), value)
46 #define VD_Y_END(value) FIELD_PREP(GENMASK(28, 16), value)
60 #define VD_H_END(value) FIELD_PREP(GENMASK(11, 0), value)
61 #define VD_H_START(value) FIELD_PREP(GENMASK(27, 16), \
65 #define VD_V_END(value) FIELD_PREP(GENMASK(11, 0), value)
[all …]
/linux/drivers/net/wireless/mediatek/mt76/mt7603/
A Dinit.c60 FIELD_PREP(MT_PSE_FRP_P0, 7) | in mt7603_dma_sched_init()
61 FIELD_PREP(MT_PSE_FRP_P1, 6) | in mt7603_dma_sched_init()
62 FIELD_PREP(MT_PSE_FRP_P2_RQ2, 4)); in mt7603_dma_sched_init()
152 FIELD_PREP(MT_AGG_LIMIT_AC(0), 24) | in mt7603_mac_init()
153 FIELD_PREP(MT_AGG_LIMIT_AC(1), 24) | in mt7603_mac_init()
154 FIELD_PREP(MT_AGG_LIMIT_AC(2), 24) | in mt7603_mac_init()
155 FIELD_PREP(MT_AGG_LIMIT_AC(3), 24)); in mt7603_mac_init()
158 FIELD_PREP(MT_AGG_LIMIT_AC(0), 24) | in mt7603_mac_init()
159 FIELD_PREP(MT_AGG_LIMIT_AC(1), 24) | in mt7603_mac_init()
160 FIELD_PREP(MT_AGG_LIMIT_AC(2), 24) | in mt7603_mac_init()
[all …]
/linux/drivers/net/wireless/mediatek/mt76/mt76x2/
A Dusb_phy.c64 [0] = FIELD_PREP(MT_EXT_CCA_CFG_CCA0, 0) | in mt76x2u_phy_set_channel()
65 FIELD_PREP(MT_EXT_CCA_CFG_CCA1, 1) | in mt76x2u_phy_set_channel()
66 FIELD_PREP(MT_EXT_CCA_CFG_CCA2, 2) | in mt76x2u_phy_set_channel()
67 FIELD_PREP(MT_EXT_CCA_CFG_CCA3, 3) | in mt76x2u_phy_set_channel()
69 [1] = FIELD_PREP(MT_EXT_CCA_CFG_CCA0, 1) | in mt76x2u_phy_set_channel()
70 FIELD_PREP(MT_EXT_CCA_CFG_CCA1, 0) | in mt76x2u_phy_set_channel()
71 FIELD_PREP(MT_EXT_CCA_CFG_CCA2, 2) | in mt76x2u_phy_set_channel()
72 FIELD_PREP(MT_EXT_CCA_CFG_CCA3, 3) | in mt76x2u_phy_set_channel()
74 [2] = FIELD_PREP(MT_EXT_CCA_CFG_CCA0, 2) | in mt76x2u_phy_set_channel()
75 FIELD_PREP(MT_EXT_CCA_CFG_CCA1, 3) | in mt76x2u_phy_set_channel()
[all …]
A Dinit.c57 (FIELD_PREP(MT_PROT_CFG_RATE, 0x3) | \ in mt76_write_mac_initvals()
58 FIELD_PREP(MT_PROT_CFG_NAV, 1) | \ in mt76_write_mac_initvals()
63 (FIELD_PREP(MT_PROT_CFG_RATE, 0x2004) | \ in mt76_write_mac_initvals()
64 FIELD_PREP(MT_PROT_CFG_NAV, 1) | \ in mt76_write_mac_initvals()
69 (FIELD_PREP(MT_PROT_CFG_RATE, 0x2004) | \ in mt76_write_mac_initvals()
70 FIELD_PREP(MT_PROT_CFG_CTRL, 1) | \ in mt76_write_mac_initvals()
71 FIELD_PREP(MT_PROT_CFG_NAV, 1) | \ in mt76_write_mac_initvals()
72 FIELD_PREP(MT_PROT_CFG_TXOP_ALLOW, 0x17)) in mt76_write_mac_initvals()
75 (FIELD_PREP(MT_PROT_CFG_RATE, 0x2084) | \ in mt76_write_mac_initvals()
76 FIELD_PREP(MT_PROT_CFG_CTRL, 1) | \ in mt76_write_mac_initvals()
[all …]
A Dpci_phy.c126 [0] = FIELD_PREP(MT_EXT_CCA_CFG_CCA0, 0) | in mt76x2_phy_set_channel()
127 FIELD_PREP(MT_EXT_CCA_CFG_CCA1, 1) | in mt76x2_phy_set_channel()
128 FIELD_PREP(MT_EXT_CCA_CFG_CCA2, 2) | in mt76x2_phy_set_channel()
129 FIELD_PREP(MT_EXT_CCA_CFG_CCA3, 3) | in mt76x2_phy_set_channel()
131 [1] = FIELD_PREP(MT_EXT_CCA_CFG_CCA0, 1) | in mt76x2_phy_set_channel()
132 FIELD_PREP(MT_EXT_CCA_CFG_CCA1, 0) | in mt76x2_phy_set_channel()
133 FIELD_PREP(MT_EXT_CCA_CFG_CCA2, 2) | in mt76x2_phy_set_channel()
134 FIELD_PREP(MT_EXT_CCA_CFG_CCA3, 3) | in mt76x2_phy_set_channel()
136 [2] = FIELD_PREP(MT_EXT_CCA_CFG_CCA0, 2) | in mt76x2_phy_set_channel()
137 FIELD_PREP(MT_EXT_CCA_CFG_CCA1, 3) | in mt76x2_phy_set_channel()
[all …]
/linux/drivers/media/platform/allegro-dvt/
A Dallegro-mail.c99 FIELD_PREP(GENMASK(15, 0), param->width); in allegro_encode_config_blob()
108 dst[i++] = FIELD_PREP(GENMASK(31, 24), codec) | in allegro_encode_config_blob()
110 FIELD_PREP(GENMASK(7, 0), param->profile); in allegro_encode_config_blob()
112 FIELD_PREP(GENMASK(15, 0), param->level); in allegro_encode_config_blob()
146 FIELD_PREP(GENMASK(7, 0), param->tc_offset); in allegro_encode_config_blob()
178 FIELD_PREP(GENMASK(15, 0), param->max_qp); in allegro_encode_config_blob()
180 FIELD_PREP(GENMASK(15, 0), param->pb_delta); in allegro_encode_config_blob()
191 FIELD_PREP(GENMASK(15, 0), param->max_psnr); in allegro_encode_config_blob()
203 FIELD_PREP(GENMASK(23, 16), param->num_b) | in allegro_encode_config_blob()
328 FIELD_PREP(GENMASK(15, 0), msg->pps_qp); in allegro_enc_encode_frame()
[all …]
/linux/drivers/fpga/
A Ddfl-n3000-nios.c104 (FIELD_PREP(N3000_NIOS_INIT_REQ_FEC_MODE_A0_MSK, \
106 FIELD_PREP(N3000_NIOS_INIT_REQ_FEC_MODE_A1_MSK, \
108 FIELD_PREP(N3000_NIOS_INIT_REQ_FEC_MODE_A2_MSK, \
110 FIELD_PREP(N3000_NIOS_INIT_REQ_FEC_MODE_A3_MSK, \
112 FIELD_PREP(N3000_NIOS_INIT_REQ_FEC_MODE_B0_MSK, \
114 FIELD_PREP(N3000_NIOS_INIT_REQ_FEC_MODE_B1_MSK, \
116 FIELD_PREP(N3000_NIOS_INIT_REQ_FEC_MODE_B2_MSK, \
118 FIELD_PREP(N3000_NIOS_INIT_REQ_FEC_MODE_B3_MSK, \
485 FIELD_PREP(N3000_NS_CTRL_ADDR, reg) | in n3000_nios_reg_write()
486 FIELD_PREP(N3000_NS_CTRL_WR_DATA, val); in n3000_nios_reg_write()
[all …]
/linux/drivers/net/ethernet/stmicro/stmmac/
A Ddwmac-ingenic.c96 FIELD_PREP(MACPHYC_PHY_INFT_MASK, MACPHYC_PHY_INFT_MII); in jz4775_mac_set_mode()
102 FIELD_PREP(MACPHYC_PHY_INFT_MASK, MACPHYC_PHY_INFT_GMII); in jz4775_mac_set_mode()
108 FIELD_PREP(MACPHYC_PHY_INFT_MASK, MACPHYC_PHY_INFT_RMII); in jz4775_mac_set_mode()
117 FIELD_PREP(MACPHYC_PHY_INFT_MASK, MACPHYC_PHY_INFT_RGMII); in jz4775_mac_set_mode()
155 val = FIELD_PREP(MACPHYC_PHY_INFT_MASK, MACPHYC_PHY_INFT_RMII); in x1600_mac_set_mode()
176 FIELD_PREP(MACPHYC_PHY_INFT_MASK, MACPHYC_PHY_INFT_RMII); in x1830_mac_set_mode()
196 val = FIELD_PREP(MACPHYC_TX_SEL_MASK, MACPHYC_TX_SEL_ORIGIN) | in x2000_mac_set_mode()
197 FIELD_PREP(MACPHYC_RX_SEL_MASK, MACPHYC_RX_SEL_ORIGIN) | in x2000_mac_set_mode()
198 FIELD_PREP(MACPHYC_PHY_INFT_MASK, MACPHYC_PHY_INFT_RMII); in x2000_mac_set_mode()
209 val |= FIELD_PREP(MACPHYC_TX_SEL_MASK, MACPHYC_TX_SEL_ORIGIN); in x2000_mac_set_mode()
[all …]
A Ddwmac-mediatek.c182 delay_val |= FIELD_PREP(ETH_DLY_TXC_STAGES, mac_delay->tx_delay); in mt2712_set_delay()
183 delay_val |= FIELD_PREP(ETH_DLY_TXC_INV, mac_delay->tx_inv); in mt2712_set_delay()
186 delay_val |= FIELD_PREP(ETH_DLY_RXC_STAGES, mac_delay->rx_delay); in mt2712_set_delay()
187 delay_val |= FIELD_PREP(ETH_DLY_RXC_INV, mac_delay->rx_inv); in mt2712_set_delay()
198 delay_val |= FIELD_PREP(ETH_DLY_TXC_INV, mac_delay->rx_inv); in mt2712_set_delay()
202 delay_val |= FIELD_PREP(ETH_DLY_GTXC_INV, mac_delay->tx_inv); in mt2712_set_delay()
217 delay_val |= FIELD_PREP(ETH_DLY_RXC_INV, mac_delay->rx_inv); in mt2712_set_delay()
225 delay_val |= FIELD_PREP(ETH_DLY_TXC_INV, mac_delay->rx_inv); in mt2712_set_delay()
243 delay_val |= FIELD_PREP(ETH_DLY_GTXC_INV, mac_delay->tx_inv); in mt2712_set_delay()
246 delay_val |= FIELD_PREP(ETH_DLY_RXC_STAGES, mac_delay->rx_delay); in mt2712_set_delay()
[all …]
/linux/include/linux/mfd/
A Dti_am335x_tscadc.h55 #define STEPCONFIG_MODE(val) FIELD_PREP(GENMASK(1, 0), (val))
58 #define STEPCONFIG_AVG(val) FIELD_PREP(GENMASK(4, 2), (val))
66 #define STEPCONFIG_RFP(val) FIELD_PREP(GENMASK(13, 12), (val))
68 #define STEPCONFIG_INM(val) FIELD_PREP(GENMASK(18, 15), (val))
70 #define STEPCONFIG_INP(val) FIELD_PREP(GENMASK(22, 19), (val))
74 #define STEPCONFIG_RFM(val) FIELD_PREP(GENMASK(24, 23), (val))
78 #define STEPDELAY_OPEN(val) FIELD_PREP(GENMASK(17, 0), (val))
86 #define STEPCHARGE_RFP(val) FIELD_PREP(GENMASK(14, 12), (val))
88 #define STEPCHARGE_INM(val) FIELD_PREP(GENMASK(18, 15), (val))
90 #define STEPCHARGE_INP(val) FIELD_PREP(GENMASK(22, 19), (val))
[all …]
/linux/drivers/net/wireless/mediatek/mt76/mt7615/
A Dusb_sdio.c83 w5 |= FIELD_PREP(MT_WTBL_W5_BW_CAP, rate->bw) | in mt7663_usb_sdio_set_rates()
84 FIELD_PREP(MT_WTBL_W5_CHANGE_BW_RATE, in mt7663_usb_sdio_set_rates()
91 FIELD_PREP(MT_WTBL_RIUCR1_RATE1, rate->val[0]) | in mt7663_usb_sdio_set_rates()
96 FIELD_PREP(MT_WTBL_RIUCR2_RATE3, rate->val[1]) | in mt7663_usb_sdio_set_rates()
97 FIELD_PREP(MT_WTBL_RIUCR2_RATE4, rate->val[2]) | in mt7663_usb_sdio_set_rates()
232 FIELD_PREP(MT_DMASHDL_PKT_MAX_SIZE_PLE, 1) | in mt7663u_dma_sched_init()
233 FIELD_PREP(MT_DMASHDL_PKT_MAX_SIZE_PSE, 8)); in mt7663u_dma_sched_init()
259 FIELD_PREP(MT_WL_TX_TMOUT_LMT, 80000) | in mt7663u_dma_sched_init()
260 FIELD_PREP(MT_WL_RX_AGG_PKT_LMT, 1)); in mt7663u_dma_sched_init()
272 FIELD_PREP(MT_WL_RX_AGG_LMT, 32) | in mt7663u_dma_sched_init()
[all …]

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