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Searched refs:GATE (Results 1 – 25 of 37) sorted by relevance

12

/linux/drivers/clk/samsung/
A Dclk-exynos5433.c2268 GATE(CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK,
2272 GATE(CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK,
2291 GATE(CLK_PHYCLK_USBHOST20_PHY_CLK48MOHCI,
2295 GATE(CLK_PHYCLK_USBHOST20_PHY_PHYCLOCK,
2299 GATE(CLK_PHYCLK_USBHOST20_PHY_FREECLK,
2303 GATE(CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK,
2307 GATE(CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK,
3893 GATE(CLK_ATCLK, "atclk", "div_atclk_atlas",
4425 GATE(CLK_ACLK_AXIUS_DRC, "aclk_axius_drc",
5223 GATE(CLK_ACLK_FD, "aclk_fd", "div_aclk_fd",
[all …]
A Dclk-exynos5250.c454 GATE(CLK_SCLK_CAM0, "sclk_cam0", "div_cam0",
456 GATE(CLK_SCLK_CAM1, "sclk_cam1", "div_cam1",
467 GATE(CLK_SCLK_DP, "sclk_dp", "div_dp",
483 GATE(CLK_SCLK_SATA, "sclk_sata", "div_sata",
485 GATE(CLK_SCLK_USB3, "sclk_usb3", "div_usb3",
488 GATE(CLK_SCLK_JPEG, "sclk_jpeg", "div_jpeg",
499 GATE(CLK_SCLK_PWM, "sclk_pwm", "div_pwm",
604 GATE(CLK_SYSREG, "sysreg", "div_aclk66",
608 GATE(CLK_CMU_TOP, "cmu_top", "div_aclk66",
610 GATE(CLK_CMU_CORE, "cmu_core", "div_aclk66",
[all …]
A Dclk-exynos3250.c515 GATE(CLK_SCLK_MFC, "sclk_mfc", "div_mfc",
519 GATE(CLK_SCLK_G3D, "sclk_g3d", "div_g3d",
531 GATE(CLK_SCLK_CAM1, "sclk_cam1", "div_cam1",
544 GATE(CLK_SCLK_EBI, "sclk_ebi", "div_ebi",
554 GATE(CLK_SCLK_I2S, "sclk_i2s", "div_i2s",
556 GATE(CLK_SCLK_PCM, "sclk_pcm", "div_pcm",
1029 GATE(CLK_FD, "fd", "mout_aclk_266_sub",
1031 GATE(CLK_DRC, "drc", "mout_aclk_266_sub",
1033 GATE(CLK_ISP, "isp", "mout_aclk_266_sub",
1047 GATE(CLK_SCALERP, "scalerp", "uart_isp_top",
[all …]
A Dclk-s5pv210.c559 GATE(CLK_VP, "vp", "dout_hclkd", CLK_GATE_IP1, 8, 0, 0),
571 GATE(CLK_PWM, "pwm", "dout_pclkp", CLK_GATE_IP3, 23, 0, 0),
578 GATE(CLK_RTC, "rtc", "dout_pclkp", CLK_GATE_IP3, 15, 0, 0),
592 GATE(SCLK_PWM, "sclk_pwm", "dout_pwm", CLK_SRC_MASK0, 19,
604 GATE(SCLK_MMC1, "sclk_mmc1", "dout_mmc1", CLK_SRC_MASK0, 9,
630 GATE(CLK_G3D, "g3d", "dout_hclkm", CLK_GATE_IP0, 8, 0, 0),
648 GATE(CLK_SDM, "sdm", "dout_pclkm", CLK_GATE_IP2, 1, 0, 0),
653 GATE(CLK_I2C_HDMI_PHY, "i2c_hdmi_phy", "dout_pclkd",
681 GATE(SCLK_DAC, "sclk_dac", "mout_dac", CLK_SRC_MASK0, 2,
692 GATE(CLK_G3D, "g3d", "dout_hclkd", CLK_GATE_IP0, 8, 0, 0),
[all …]
A Dclk-exynos4.c741 GATE(CLK_SCLK_MIPI0, "sclk_mipi0", "div_mipi_pre0",
747 GATE(CLK_VP, "vp", "aclk160", GATE_IP_TV, 0, 0, 0),
795 GATE(CLK_FIMC0, "fimc0", "aclk160", GATE_IP_CAM, 0,
797 GATE(CLK_FIMC1, "fimc1", "aclk160", GATE_IP_CAM, 1,
904 GATE(CLK_OUT_TOP, "clkout_top", "div_clkout_top",
906 GATE(CLK_OUT_DMC, "clkout_dmc", "div_clkout_dmc",
908 GATE(CLK_OUT_CPU, "clkout_cpu", "div_clkout_cpu",
935 GATE(CLK_SMMU_ROTATOR, "smmu_rotator", "aclk200",
939 GATE(CLK_SCLK_SATA, "sclk_sata", "div_sata",
977 GATE(CLK_SCLK_MDNIE0, "sclk_mdnie0", "div_mdnie0",
[all …]
A Dclk-exynos7.c794 GATE(SCLK_I2S1, "sclk_i2s1_user", "sclk_i2s1",
851 GATE(SCLK_CHIPID, "sclk_chipid", "fin_pll",
951 GATE(PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER,
955 GATE(PHYCLK_USBDRD300_UDRD30_PHYCLK_USER,
1084 GATE(OSCCLK_PHY_CLKOUT_EMBEDDED_COMBO_PHY,
1189 GATE(PCLK_G2D, "pclk_g2d", "dout_pclk_mscl",
1271 GATE(SCLK_PCM, "sclk_pcm", "dout_sclk_pcm",
1273 GATE(SCLK_I2S, "sclk_i2s", "dout_sclk_i2s",
1276 GATE(0, "sclk_slimbus", "dout_sclk_slimbus",
1285 GATE(PCLK_PCM, "pclk_pcm", "dout_aclk_aud",
[all …]
A Dclk-exynos5420.c960 GATE(0, "aclk166", "mout_user_aclk166",
995 GATE(CLK_SCLK_PWM, "sclk_pwm", "dout_pwm",
997 GATE(CLK_SCLK_PCM1, "sclk_pcm1", "dout_pcm1",
999 GATE(CLK_SCLK_PCM2, "sclk_pcm2", "dout_pcm2",
1001 GATE(CLK_SCLK_I2S1, "sclk_i2s1", "dout_i2s1",
1003 GATE(CLK_SCLK_I2S2, "sclk_i2s2", "dout_i2s2",
1006 GATE(CLK_SCLK_MMC0, "sclk_mmc0", "dout_mmc0",
1030 GATE(CLK_SCLK_DP1, "sclk_dp1", "dout_dp1",
1042 GATE(CLK_SROMC, "sromc", "aclk200_fsys2",
1108 GATE(CLK_CHIPID, "chipid", "aclk66_psgen",
[all …]
A Dclk-exynos5260.c729 GATE(GSCL_CLK_PIXEL_GSCL0, "clk_pixel_gscl0",
732 GATE(GSCL_CLK_PIXEL_GSCL1, "clk_pixel_gscl1",
749 GATE(GSCL_CLK_FIMC_LITE_A, "clk_fimc_lite_a",
752 GATE(GSCL_CLK_FIMC_LITE_B, "clk_fimc_lite_b",
755 GATE(GSCL_CLK_FIMC_LITE_D, "clk_fimc_lite_d",
759 GATE(GSCL_CLK_SMMU3_GSCL0, "clk_smmu3_gscl0",
764 GATE(GSCL_CLK_SMMU3_MSCL0, "clk_smmu3_mscl0",
767 GATE(GSCL_CLK_SMMU3_MSCL1, "clk_smmu3_mscl1",
1795 GATE(TOP_SCLK_MMC0, "sclk_fsys_mmc0_sdclkin",
1798 GATE(TOP_SCLK_MMC1, "sclk_fsys_mmc1_sdclkin",
[all …]
A Dclk-exynos5410.c166 GATE(CLK_SSS, "sss", "aclk266", GATE_IP_G2D, 2, 0, 0),
172 GATE(CLK_SCLK_MMC0, "sclk_mmc0", "div_mmc_pre0",
174 GATE(CLK_SCLK_MMC1, "sclk_mmc1", "div_mmc_pre1",
176 GATE(CLK_SCLK_MMC2, "sclk_mmc2", "div_mmc_pre2",
189 GATE(CLK_SCLK_USBD300, "sclk_usbd300", "dout_usbd300",
191 GATE(CLK_SCLK_USBD301, "sclk_usbd301", "dout_usbd301",
194 GATE(CLK_SCLK_PWM, "sclk_pwm", "dout_pwm",
212 GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0",
214 GATE(CLK_SCLK_UART1, "sclk_uart1", "div_uart1",
216 GATE(CLK_SCLK_UART2, "sclk_uart2", "div_uart2",
[all …]
A Dclk-exynos4412-isp.c48 GATE(CLK_ISP_FIMC_ISP, "isp", "aclk200", E4X12_GATE_ISP0, 0, 0, 0),
49 GATE(CLK_ISP_FIMC_DRC, "drc", "aclk200", E4X12_GATE_ISP0, 1, 0, 0),
50 GATE(CLK_ISP_FIMC_FD, "fd", "aclk200", E4X12_GATE_ISP0, 2, 0, 0),
53 GATE(CLK_ISP_MCUISP, "mcuisp", "aclk200", E4X12_GATE_ISP0, 5, 0, 0),
64 GATE(CLK_ISP_PPMUISPX, "ppmuispx", "aclk200", E4X12_GATE_ISP0, 21,
68 GATE(CLK_ISP_MPWM_ISP, "mpwm_isp", "aclk200", E4X12_GATE_ISP0, 24,
70 GATE(CLK_ISP_I2C0_ISP, "i2c0_isp", "aclk200", E4X12_GATE_ISP0, 25,
72 GATE(CLK_ISP_I2C1_ISP, "i2c1_isp", "aclk200", E4X12_GATE_ISP0, 26,
78 GATE(CLK_ISP_UART_ISP, "uart_isp", "aclk200", E4X12_GATE_ISP0, 31,
84 GATE(CLK_ISP_SPI0_ISP, "spi0_isp", "aclk200", E4X12_GATE_ISP1, 12,
[all …]
A Dclk-s3c2443.c123 GATE(HCLK_LCD, "lcd", "hclk", HCLKCON, 9, 0, 0),
131 GATE(PCLK_RTC, "rtc", "pclk", PCLKCON, 12, 0, 0),
132 GATE(PCLK_WDT, "wdt", "pclk", PCLKCON, 11, 0, 0),
133 GATE(PCLK_PWM, "pwm", "pclk", PCLKCON, 10, 0, 0),
134 GATE(PCLK_I2S0, "i2s0", "pclk", PCLKCON, 9, 0, 0),
135 GATE(PCLK_AC97, "ac97", "pclk", PCLKCON, 8, 0, 0),
136 GATE(PCLK_ADC, "adc", "pclk", PCLKCON, 7, 0, 0),
216 GATE(HCLK_2D, "2d", "hclk", HCLKCON, 20, 0, 0),
259 GATE(HCLK_CAM, "cam", "hclk", HCLKCON, 8, 0, 0),
261 GATE(PCLK_SDI, "sdi", "pclk", PCLKCON, 5, 0, 0),
[all …]
A Dclk-exynos850.c304 GATE(CLK_GOUT_CORE_BUS, "gout_core_bus", "mout_core_bus",
306 GATE(CLK_GOUT_CORE_CCI, "gout_core_cci", "mout_core_cci",
314 GATE(CLK_GOUT_DPU, "gout_dpu", "mout_dpu",
318 GATE(CLK_GOUT_HSI_BUS, "gout_hsi_bus", "mout_hsi_bus",
330 GATE(CLK_GOUT_PERI_IP, "gout_peri_ip", "mout_peri_ip",
420 GATE(CLK_GOUT_MMC_CARD_SDCLKIN, "gout_mmc_card_sdclkin",
423 GATE(CLK_GOUT_SYSREG_HSI_PCLK, "gout_sysreg_hsi_pclk",
428 GATE(CLK_GOUT_USB_BUS_EARLY_CLK, "gout_usb_bus_early",
582 GATE(CLK_GOUT_PWM_MOTOR_PCLK, "gout_pwm_motor_pclk",
600 GATE(CLK_GOUT_GPIO_PERI_PCLK, "gout_gpio_peri_pclk",
[all …]
/linux/drivers/clk/rockchip/
A Dclk-rk3368.c308 GATE(0, "apllb_cs", "apllb", CLK_IGNORE_UNUSED,
310 GATE(0, "aplll_cs", "aplll", CLK_IGNORE_UNUSED,
312 GATE(0, "gpll_cs", "gpll", CLK_IGNORE_UNUSED,
325 GATE(0, "dpll_ddr", "dpll", CLK_IGNORE_UNUSED,
327 GATE(0, "gpll_ddr", "gpll", 0,
401 GATE(0, "sclk_hsadc_tsp", "ext_hsadc_tsp", 0,
461 GATE(0, "pclk_isp_in", "ext_isp", 0,
466 GATE(0, "pclk_vip_in", "ext_vip", 0,
628 GATE(SCLK_MACREF, "sclk_macref", "mac_clk", 0,
630 GATE(SCLK_MAC_RX, "sclk_mac_rx", "mac_clk", 0,
[all …]
A Dclk-rk3399.c725 GATE(0, "cpll_cs", "cpll", CLK_IGNORE_UNUSED,
727 GATE(0, "gpll_cs", "gpll", CLK_IGNORE_UNUSED,
729 GATE(0, "npll_cs", "npll", CLK_IGNORE_UNUSED,
769 GATE(HCLK_VDU, "hclk_vdu", "hclk_vdu_pre", 0,
774 GATE(ACLK_VDU, "aclk_vdu", "aclk_vdu_pre", 0,
786 GATE(HCLK_IEP, "hclk_iep", "hclk_iep_pre", 0,
791 GATE(ACLK_IEP, "aclk_iep", "aclk_iep_pre", 0,
889 GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_sd", 0,
993 GATE(0, "cpll_fclk_cm0s_src", "cpll", 0,
995 GATE(0, "gpll_fclk_cm0s_src", "gpll", 0,
[all …]
A Dclk-rk3228.c265 GATE(ACLK_CPU, "aclk_cpu", "aclk_cpu_src", 0,
273 GATE(PCLK_CPU, "pclk_cpu", "pclk_bus_src", 0,
275 GATE(0, "pclk_phy_pre", "pclk_bus_src", 0,
277 GATE(0, "pclk_ddr_pre", "pclk_bus_src", 0,
354 GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 0,
356 GATE(SCLK_TIMER1, "sclk_timer1", "xin24m", 0,
358 GATE(SCLK_TIMER2, "sclk_timer2", "xin24m", 0,
360 GATE(SCLK_TIMER3, "sclk_timer3", "xin24m", 0,
362 GATE(SCLK_TIMER4, "sclk_timer4", "xin24m", 0,
402 GATE(0, "gpll_vop", "gpll", 0,
[all …]
A Dclk-rk3328.c300 GATE(0, "aclk_core_niu", "aclk_core", 0,
314 GATE(0, "aclk_gpu_niu", "aclk_gpu_pre", 0,
358 GATE(0, "pclk_bus", "pclk_bus_pre", 0,
360 GATE(0, "pclk_phy_pre", "pclk_bus_pre", 0,
366 GATE(0, "clk_hsadc_tsp", "ext_gpio3a2", 0,
478 GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 0,
480 GATE(SCLK_TIMER1, "sclk_timer1", "xin24m", 0,
531 GATE(0, "aclk_vpu_niu", "aclk_vpu_pre", 0,
533 GATE(0, "hclk_vpu_niu", "hclk_vpu_pre", 0,
541 GATE(0, "aclk_rkvenc_niu", "aclk_rkvenc", 0,
[all …]
A Dclk-rv1108.c201 GATE(0, "dpll_core", "dpll", CLK_IGNORE_UNUSED,
254 GATE(ACLK_VPU, "aclk_vpu", "aclk_vpu_pre", 0,
413 GATE(HCLK_VIO, "hclk_vio", "hclk_vio_pre", 0,
418 GATE(PCLK_VIO, "pclk_vio", "pclk_vio_pre", 0,
446 GATE(HCLK_VOP, "hclk_vop", "hclk_vio_pre", 0,
450 GATE(HCLK_IEP, "hclk_iep", "hclk_vio_pre", 0,
455 GATE(HCLK_RGA, "hclk_rga", "hclk_vio_pre", 0,
479 GATE(HCLK_ISP, "hclk_isp", "hclk_vio_pre", 0,
549 GATE(PCLK_BUS, "pclk_bus", "pclk_bus_pre", 0,
555 GATE(SCLK_TIMER0, "clk_timer0", "xin24m", 0,
[all …]
A Dclk-rk3288.c319 GATE(0, "pclk_dbg", "pclk_dbg_pre", 0,
323 GATE(0, "pclk_core_niu", "pclk_dbg_pre", 0,
328 GATE(0, "gpll_ddr", "gpll", 0,
350 GATE(0, "c2c_host", "aclk_cpu_src", 0,
394 GATE(0, "sclk_acc_efuse", "xin24m", 0,
397 GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 0,
399 GATE(SCLK_TIMER1, "sclk_timer1", "xin24m", 0,
401 GATE(SCLK_TIMER2, "sclk_timer2", "xin24m", 0,
575 GATE(SCLK_PS2C, "sclk_ps2c", "xin24m", 0,
645 GATE(0, "jtag", "ext_jtag", 0,
[all …]
A Dclk-rk3128.c209 GATE(0, "dpll_ddr", "dpll", CLK_IGNORE_UNUSED,
219 GATE(0, "apll_core", "apll", CLK_IGNORE_UNUSED,
238 GATE(ACLK_CPU, "aclk_cpu", "aclk_cpu_src", 0,
278 GATE(0, "gpll_peri", "gpll", CLK_IGNORE_UNUSED,
297 GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 0,
299 GATE(SCLK_TIMER1, "sclk_timer1", "xin24m", 0,
301 GATE(SCLK_TIMER2, "sclk_timer2", "xin24m", 0,
303 GATE(SCLK_TIMER3, "sclk_timer3", "xin24m", 0,
305 GATE(SCLK_TIMER4, "sclk_timer4", "xin24m", 0,
307 GATE(SCLK_TIMER5, "sclk_timer5", "xin24m", 0,
[all …]
A Dclk-px30.c301 GATE(SCLK_PVTM, "clk_pvtm", "xin24m", 0,
332 GATE(0, "dpll_ddr", "dpll", CLK_IGNORE_UNUSED,
334 GATE(0, "gpll_ddr", "gpll", CLK_IGNORE_UNUSED,
396 GATE(PCLK_ISP, "pclkin_isp", "ext_pclkin", 0,
398 GATE(PCLK_CIF, "pclkin_cif", "ext_pclkin", 0,
524 GATE(0, "hclk_sdmmc_pre", "hclk_peri_pre", 0,
559 GATE(0, "aclk_gmac_pre", "aclk_peri_pre", 0,
751 GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 0,
753 GATE(SCLK_TIMER1, "sclk_timer1", "xin24m", 0,
755 GATE(SCLK_TIMER2, "sclk_timer2", "xin24m", 0,
[all …]
A Dclk-rk3188.c290 GATE(HCLK_VEPU, "hclk_vepu", "aclk_vepu", 0,
295 GATE(HCLK_VDPU, "hclk_vdpu", "aclk_vdpu", 0,
298 GATE(0, "gpll_ddr", "gpll", CLK_IGNORE_UNUSED,
304 GATE(ACLK_CPU, "aclk_cpu", "aclk_cpu_pre", 0,
307 GATE(0, "atclk_cpu", "pclk_cpu_pre", 0,
309 GATE(PCLK_CPU, "pclk_cpu", "pclk_cpu_pre", 0,
338 GATE(0, "pclkin_cif0", "ext_cif0", 0,
359 GATE(0, "sclk_mac_lbtest", "sclk_macref", 0,
388 GATE(SCLK_SMC, "sclk_smc", "hclk_peri", 0,
596 GATE(0, "pclkin_cif1", "ext_cif1", 0,
[all …]
A Dclk-rk3568.c790 GATE(TCLK_EMMC, "tclk_emmc", "xin24m", 0,
1005 GATE(ACLK_ISP, "aclk_isp", "aclk_vi", 0,
1007 GATE(HCLK_ISP, "hclk_isp", "hclk_vi", 0,
1039 GATE(HCLK_VOP, "hclk_vop", "hclk_vo", 0,
1052 GATE(ACLK_HDCP, "aclk_hdcp", "aclk_vo", 0,
1321 GATE(CLK_I2C1, "clk_i2c1", "clk_i2c", 0,
1325 GATE(CLK_I2C2, "clk_i2c2", "clk_i2c", 0,
1329 GATE(CLK_I2C3, "clk_i2c3", "clk_i2c", 0,
1333 GATE(CLK_I2C4, "clk_i2c4", "clk_i2c", 0,
1337 GATE(CLK_I2C5, "clk_i2c5", "clk_i2c", 0,
[all …]
A Dclk-rk3308.c413 GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 0,
415 GATE(SCLK_TIMER1, "sclk_timer1", "xin24m", 0,
417 GATE(SCLK_TIMER2, "sclk_timer2", "xin24m", 0,
419 GATE(SCLK_TIMER3, "sclk_timer3", "xin24m", 0,
421 GATE(SCLK_TIMER4, "sclk_timer4", "xin24m", 0,
423 GATE(SCLK_TIMER5, "sclk_timer5", "xin24m", 0,
457 GATE(DCLK_VOP, "dclk_vop", "dclk_vop_mux", 0,
601 GATE(0, "clk_wifi_dpll", "dpll", 0,
603 GATE(0, "clk_wifi_vpll0", "vpll0", 0,
605 GATE(0, "clk_wifi_osc", "xin24m", 0,
[all …]
A Dclk-rk3036.c174 GATE(0, "gpll_armclk", "gpll", CLK_IGNORE_UNUSED,
183 GATE(0, "dpll_ddr", "dpll", CLK_IGNORE_UNUSED,
185 GATE(0, "gpll_ddr", "gpll", CLK_IGNORE_UNUSED,
198 GATE(0, "dpll_cpu", "dpll", 0, RK2928_CLKGATE_CON(10), 8, GFLAGS),
199 GATE(0, "gpll_cpu", "gpll", 0, RK2928_CLKGATE_CON(0), 1, GFLAGS),
202 GATE(ACLK_CPU, "aclk_cpu", "aclk_cpu_src", CLK_IGNORE_UNUSED,
215 GATE(ACLK_PERI, "aclk_peri", "aclk_peri_src", 0,
219 GATE(PCLK_PERI, "pclk_peri", "pclk_peri_src", 0,
223 GATE(HCLK_PERI, "hclk_peri", "hclk_peri_src", 0,
318 GATE(SCLK_I2S, "sclk_i2s", "i2s_pre", CLK_SET_RATE_PARENT,
[all …]
/linux/drivers/clk/pistachio/
A Dclk-pistachio.c19 GATE(CLK_MIPS, "mips", "mips_div", 0x104, 0),
21 GATE(CLK_AUDIO, "audio", "audio_div", 0x104, 2),
22 GATE(CLK_I2S, "i2s", "i2s_div", 0x104, 3),
23 GATE(CLK_SPDIF, "spdif", "spdif_div", 0x104, 4),
25 GATE(CLK_RPU_V, "rpu_v", "rpu_v_div", 0x104, 6),
26 GATE(CLK_RPU_L, "rpu_l", "rpu_l_div", 0x104, 7),
34 GATE(CLK_ENET, "enet", "enet_div", 0x104, 15),
38 GATE(CLK_SPI0, "spi0", "spi0_div", 0x104, 19),
39 GATE(CLK_SPI1, "spi1", "spi1_div", 0x104, 20),
45 GATE(CLK_BT, "bt", "bt_div", 0x104, 25),
[all …]

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