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Searched refs:GENMASK (Results 1 – 25 of 1715) sorted by relevance

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/linux/include/soc/mscc/
A Docelot_ana.h16 #define ANA_ANAGEFIL_PID_VAL_M GENMASK(18, 14)
20 #define ANA_ANAGEFIL_VID_VAL_M GENMASK(12, 0)
25 #define ANA_STORMLIMIT_CFG_STORM_RATE_M GENMASK(6, 3)
29 #define ANA_STORMLIMIT_CFG_STORM_MODE_M GENMASK(1, 0)
33 #define ANA_AUTOAGE_AGE_PERIOD_M GENMASK(20, 1)
41 #define ANA_AGENCTRL_FID_MASK_M GENMASK(23, 12)
62 #define ANA_FLOODING_FLD_BROADCAST_M GENMASK(11, 6)
65 #define ANA_FLOODING_FLD_MULTICAST_M GENMASK(5, 0)
74 #define ANA_FLOODING_IPMC_FLD_MC6_CTRL_M GENMASK(11, 6)
77 #define ANA_FLOODING_IPMC_FLD_MC6_DATA_M GENMASK(5, 0)
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A Docelot_hsio.h91 #define HSIO_PLL5G_CFG0_SELBGV820_M GENMASK(26, 23)
94 #define HSIO_PLL5G_CFG0_LOOP_BW_RES_M GENMASK(22, 18)
97 #define HSIO_PLL5G_CFG0_SELCPI_M GENMASK(17, 16)
104 #define HSIO_PLL5G_CFG0_CPU_CLK_DIV_M GENMASK(11, 6)
107 #define HSIO_PLL5G_CFG0_CORE_CLK_DIV_M GENMASK(5, 0)
115 #define HSIO_PLL5G_CFG1_RC_CTRL_DATA_M GENMASK(13, 6)
141 #define HSIO_PLL5G_CFG2_GAIN_TEST_M GENMASK(9, 5)
167 #define HSIO_PLL5G_CFG3_FBDIVSEL_M GENMASK(7, 0)
195 #define HSIO_PLL5G_CFG6_DDR_CLK_DIV_M GENMASK(5, 0)
202 #define HSIO_PLL5G_STATUS0_READBACK_DATA_M GENMASK(8, 1)
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A Docelot_qsys.h26 #define QSYS_EEE_THRES_EEE_HIGH_BYTES_M GENMASK(15, 8)
29 #define QSYS_EEE_THRES_EEE_HIGH_FRAMES_M GENMASK(7, 0)
34 #define QSYS_EXT_CPU_CFG_EXT_CPU_PORT_M GENMASK(12, 8)
37 #define QSYS_EXT_CPU_CFG_EXT_CPUQ_MSK_M GENMASK(7, 0)
42 #define QSYS_QMAP_SE_BASE_M GENMASK(12, 5)
45 #define QSYS_QMAP_SE_IDX_SEL_M GENMASK(4, 2)
48 #define QSYS_QMAP_SE_INP_SEL_M GENMASK(1, 0)
55 #define QSYS_TFRM_MISC_TIMED_CANCEL_SLOT_M GENMASK(18, 9)
60 #define QSYS_TFRM_MISC_TIMED_ENTRY_FAST_CNT_M GENMASK(6, 0)
68 #define QSYS_RED_PROFILE_WM_RED_HIGH_M GENMASK(7, 0)
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A Docelot_sys.h21 #define SYS_FRM_AGING_MAX_AGE_M GENMASK(19, 0)
24 #define SYS_STAT_CFG_STAT_CLEAR_SHOT_M GENMASK(16, 10)
27 #define SYS_STAT_CFG_STAT_VIEW_M GENMASK(9, 0)
41 #define SYS_TIMESTAMP_OFFSET_ETH_TYPE_CFG_M GENMASK(21, 6)
44 #define SYS_TIMESTAMP_OFFSET_TIMESTAMP_OFFSET_M GENMASK(5, 0)
47 #define SYS_PAUSE_TOT_CFG_PAUSE_TOT_START_M GENMASK(17, 9)
50 #define SYS_PAUSE_TOT_CFG_PAUSE_TOT_STOP_M GENMASK(8, 0)
75 #define SYS_MMGT_FAST_FREEVLD_M GENMASK(7, 4)
78 #define SYS_MMGT_FAST_RELVLD_M GENMASK(3, 0)
83 #define SYS_EVENTS_DIF_EV_DRX_M GENMASK(8, 6)
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A Docelot_dev.h18 #define DEV_CLOCK_CFG_LINK_SPEED_M GENMASK(1, 0)
28 #define DEV_EEE_CFG_EEE_TIMER_AGE_M GENMASK(21, 15)
31 #define DEV_EEE_CFG_EEE_TIMER_WAKEUP_M GENMASK(14, 8)
34 #define DEV_EEE_CFG_EEE_TIMER_HOLDOFF_M GENMASK(7, 1)
39 #define DEV_PTP_PREDICT_CFG_PTP_PHY_PREDICT_CFG_M GENMASK(11, 4)
42 #define DEV_PTP_PREDICT_CFG_PTP_PHASE_PREDICT_CFG_M GENMASK(3, 0)
52 #define DEV_MAC_TAGS_CFG_TAG_ID_M GENMASK(31, 16)
63 #define DEV_MAC_IFG_CFG_TX_IFG_M GENMASK(12, 8)
66 #define DEV_MAC_IFG_CFG_RX_IFG2_M GENMASK(7, 4)
69 #define DEV_MAC_IFG_CFG_RX_IFG1_M GENMASK(3, 0)
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/linux/drivers/net/ipa/
A Dipa_reg.h128 #define RX_FMASK GENMASK(0, 0)
129 #define PROC_FMASK GENMASK(1, 1)
131 #define MISC_FMASK GENMASK(3, 3)
135 #define HPS_FMASK GENMASK(7, 7)
136 #define DPS_FMASK GENMASK(8, 8)
491 return legacy ? GENMASK(9, 5) : GENMASK(10, 5); in aggr_byte_limit_fmask()
497 return legacy ? GENMASK(14, 10) : GENMASK(16, 12); in aggr_time_limit_fmask()
503 return legacy ? GENMASK(20, 15) : GENMASK(22, 17); in aggr_pkt_limit_fmask()
509 return legacy ? GENMASK(21, 21) : GENMASK(23, 23); in aggr_sw_eof_active_fmask()
515 return legacy ? GENMASK(22, 22) : GENMASK(24, 24); in aggr_force_close_fmask()
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/linux/drivers/net/wireless/realtek/rtw89/
A Dreg.h26 #define B_AX_EF_PGPD_MASK GENMASK(30, 28)
56 #define B_AX_BTMODE_MASK GENMASK(7, 6)
67 #define B_AX_DBG_SEL1 GENMASK(23, 16)
70 #define B_AX_DBG_SEL0 GENMASK(7, 0)
119 #define PS_CPWM_STATE GENMASK(2, 0)
1572 #define RR_TM_VAL GENMASK(6, 1)
1602 #define RR_BIASA_A GENMASK(2, 0)
1622 #define RR_RXA_DPK GENMASK(9, 8)
1624 #define RR_RXA2_C2 GENMASK(9, 3)
1787 #define B_TXAGC_TP GENMASK(2, 0)
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A Dfw.h299 GENMASK(8, 0)); \
397 GENMASK(8, 0)); \
453 GENMASK(5, 0)); \
530 GENMASK(7, 0)); \
537 GENMASK(9, 8)); \
579 GENMASK(2, 0)); \
593 GENMASK(7, 4)); \
698 GENMASK(8, 0)); \
782 GENMASK(7, 0)); \
836 GENMASK(2, 0)); \
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A Dcam.h13 le32p_replace_bits((__le32 *)(cmd) + 1, value, GENMASK(7, 0))
15 le32p_replace_bits((__le32 *)(cmd) + 1, value, GENMASK(15, 8))
17 le32p_replace_bits((__le32 *)(cmd) + 1, value, GENMASK(23, 16))
21 le32p_replace_bits((__le32 *)(cmd) + 2, value, GENMASK(2, 1))
23 le32p_replace_bits((__le32 *)(cmd) + 2, value, GENMASK(4, 3))
25 le32p_replace_bits((__le32 *)(cmd) + 2, value, GENMASK(6, 5))
29 le32p_replace_bits((__le32 *)(cmd) + 2, value, GENMASK(13, 8))
31 le32p_replace_bits((__le32 *)(cmd) + 2, value, GENMASK(15, 14))
37 le32p_replace_bits((__le32 *)(cmd) + 3, value, GENMASK(5, 0))
39 le32p_replace_bits((__le32 *)(cmd) + 4, value, GENMASK(7, 0))
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/linux/drivers/net/wireless/mediatek/mt76/mt7915/
A Dmac.h10 #define MT_RXD0_LENGTH GENMASK(15, 0)
11 #define MT_RXD0_PKT_TYPE GENMASK(31, 27)
108 #define MT_RXD7_TA_HI GENMASK(31, 0)
119 #define MT_PRXV_NSTS GENMASK(9, 7)
127 #define MT_PRXV_RCPI0 GENMASK(7, 0)
156 #define MT_CRXV_SNR GENMASK(18, 13)
158 #define MT_CRXV_FOE_HI GENMASK(6, 0)
206 #define MT_TXD1_TID GENMASK(22, 20)
252 #define MT_TXD5_PID GENMASK(7, 0)
264 #define MT_TXD6_BW GENMASK(1, 0)
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A Dregs.h83 #define MT_IFS_EIFS_OFDM GENMASK(8, 0)
84 #define MT_IFS_RIFS GENMASK(14, 10)
85 #define MT_IFS_SIFS GENMASK(22, 16)
86 #define MT_IFS_SLOT GENMASK(30, 24)
89 #define MT_IFS_EIFS_CCK GENMASK(8, 0)
114 #define MT_ETBF_RX_FB_BW GENMASK(7, 6)
115 #define MT_ETBF_RX_FB_NC GENMASK(5, 3)
116 #define MT_ETBF_RX_FB_NR GENMASK(2, 0)
126 #define MT_ETBF_RX_FB_HT GENMASK(7, 0)
285 #define MT_WTBL_LMAC_DW GENMASK(7, 2)
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/linux/drivers/net/wireless/mediatek/mt76/mt7603/
A Dmac.h6 #define MT_RXD0_LENGTH GENMASK(15, 0)
7 #define MT_RXD0_PKT_TYPE GENMASK(31, 29)
94 #define MT_RXV3_RCPI0 GENMASK(15, 8)
109 #define MT_RXV5_FOE GENMASK(18, 7)
117 #define MT_RXV6_NF2 GENMASK(23, 16)
118 #define MT_RXV6_NF1 GENMASK(15, 8)
119 #define MT_RXV6_NF0 GENMASK(7, 0)
141 #define MT_TXD1_TID GENMASK(22, 20)
181 #define MT_TXD5_PID GENMASK(7, 0)
192 #define MT_TXD6_BW GENMASK(9, 8)
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A Dregs.h29 #define MT_INT_RX_DONE_ALL GENMASK(1, 0)
30 #define MT_INT_TX_DONE_ALL GENMASK(19, 4)
108 #define MT_PSE_FRP_P0 GENMASK(2, 0)
109 #define MT_PSE_FRP_P1 GENMASK(5, 3)
143 #define MT_AGC_41_RSSI_1 GENMASK(7, 0)
148 #define MT_RXTD_6_ACI_TH GENMASK(4, 0)
229 #define MT_AGG_BWCR_BW GENMASK(3, 2)
388 #define MT_IFS_EIFS GENMASK(8, 0)
389 #define MT_IFS_RIFS GENMASK(14, 10)
390 #define MT_IFS_SIFS GENMASK(22, 16)
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/linux/drivers/net/wireless/mediatek/mt76/mt7921/
A Dmac.h10 #define MT_RXD0_LENGTH GENMASK(15, 0)
12 #define MT_RXD0_PKT_TYPE GENMASK(31, 27)
107 #define MT_RXD7_TA_HI GENMASK(31, 0)
118 #define MT_PRXV_NSTS GENMASK(9, 7)
122 #define MT_PRXV_SGI GENMASK(16, 15)
131 #define MT_PRXV_RCPI0 GENMASK(7, 0)
161 #define MT_CRXV_SNR GENMASK(18, 13)
163 #define MT_CRXV_FOE_HI GENMASK(6, 0)
261 #define MT_TXD5_PID GENMASK(7, 0)
273 #define MT_TXD6_BW GENMASK(1, 0)
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/linux/drivers/net/wireless/mediatek/mt76/mt7615/
A Dmac.h10 #define MT_RXD0_LENGTH GENMASK(15, 0)
12 #define MT_RXD0_PKT_TYPE GENMASK(31, 29)
117 #define MT_RXV4_RCPI0 GENMASK(7, 0)
119 #define MT_RXV5_FOE GENMASK(11, 0)
121 #define MT_RXV6_NF3 GENMASK(31, 24)
122 #define MT_RXV6_NF2 GENMASK(23, 16)
123 #define MT_RXV6_NF1 GENMASK(15, 8)
124 #define MT_RXV6_NF0 GENMASK(7, 0)
181 #define MT_TXD1_TID GENMASK(23, 21)
224 #define MT_TXD5_PID GENMASK(7, 0)
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A Dregs.h46 #define MT_TOP_MISC2_FW_STATE GENMASK(2, 0)
111 #define MT_INT_RX_DONE_ALL GENMASK(1, 0)
112 #define MT_INT_TX_DONE_ALL GENMASK(19, 4)
150 #define MT_MCU_CMD_ERROR_MASK (GENMASK(5, 1) | GENMASK(28, 24))
187 #define MT_PSE_SRC_CNT GENMASK(27, 16)
217 GENMASK(28, 20))
230 GENMASK(8, 1)
310 #define MT_IFS_EIFS GENMASK(8, 0)
311 #define MT_IFS_RIFS GENMASK(14, 10)
312 #define MT_IFS_SIFS GENMASK(22, 16)
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/linux/drivers/media/platform/ti-vpe/
A Dcal_regs.h100 #define CAL_HL_HWINFO_WFIFO_MASK GENMASK(3, 0)
101 #define CAL_HL_HWINFO_RFIFO_MASK GENMASK(7, 4)
102 #define CAL_HL_HWINFO_PCTX_MASK GENMASK(12, 8)
149 #define CAL_PIX_PROC_DPCMD_MASK GENMASK(9, 5)
185 #define CAL_CTRL_TAGCNT_MASK GENMASK(4, 1)
192 #define CAL_CTRL_MFLAGL_MASK GENMASK(20, 13)
197 #define CAL_CTRL_MFLAGH_MASK GENMASK(31, 24)
317 #define CAL_WR_DMA_ADDR_MASK GENMASK(31, 4)
319 #define CAL_WR_DMA_OFST_MASK GENMASK(18, 4)
416 #define CAL_CSI2_CTX_DT_MASK GENMASK(5, 0)
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/linux/drivers/net/wireless/mediatek/mt76/
A Dmt76x02_regs.h19 #define MT_EFUSE_CTRL_AOUT GENMASK(5, 0)
20 #define MT_EFUSE_CTRL_MODE GENMASK(7, 6)
23 #define MT_EFUSE_CTRL_AIN GENMASK(25, 16)
68 #define MT_XO_CTRL5_C2_VAL GENMASK(14, 8)
110 #define MT_INT_RX_DONE_ALL GENMASK(1, 0)
142 #define MT_WMM_AIFSN_MASK GENMASK(3, 0)
146 #define MT_WMM_CWMIN_MASK GENMASK(3, 0)
150 #define MT_WMM_CWMAX_MASK GENMASK(3, 0)
156 #define MT_WMM_TXOP_MASK GENMASK(15, 0)
167 #define MT_US_CYC_CNT GENMASK(7, 0)
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/linux/drivers/mtd/nand/raw/
A Ddenali.h24 #define LOAD_WAIT_CNT__VALUE GENMASK(15, 0)
30 #define ERASE_WAIT_CNT__VALUE GENMASK(15, 0)
33 #define INT_MON_CYCCNT__VALUE GENMASK(15, 0)
76 #define RE_2_WE__VALUE GENMASK(5, 0)
79 #define ACC_CLKS__VALUE GENMASK(3, 0)
107 #define READ_MODE__VALUE GENMASK(3, 0)
110 #define WRITE_MODE__VALUE GENMASK(3, 0)
138 #define DIE_MASK__VALUE GENMASK(7, 0)
147 #define RE_2_RE__VALUE GENMASK(5, 0)
153 #define DEVICE_ID__VALUE GENMASK(7, 0)
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/linux/drivers/net/wireless/ath/ath11k/
A Dhal_desc.h10 #define BUFFER_ADDR_INFO0_ADDR GENMASK(31, 0)
12 #define BUFFER_ADDR_INFO1_ADDR GENMASK(7, 0)
13 #define BUFFER_ADDR_INFO1_RET_BUF_MGR GENMASK(10, 8)
14 #define BUFFER_ADDR_INFO1_SW_COOKIE GENMASK(31, 11)
475 #define HAL_TLV_HDR_TAG GENMASK(9, 1)
476 #define HAL_TLV_HDR_LEN GENMASK(25, 10)
486 #define RX_MPDU_DESC_INFO0_SEQ_NUM GENMASK(19, 8)
1508 #define HAL_TX_RATE_STATS_INFO0_BW GENMASK(2, 1)
1870 #define HAL_DESC_HDR_INFO0_OWNER GENMASK(3, 0)
1871 #define HAL_DESC_HDR_INFO0_BUF_TYPE GENMASK(7, 4)
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/linux/drivers/net/wireless/mediatek/mt7601u/
A Dregs.h22 #define MT_EFUSE_CTRL_AOUT GENMASK(5, 0)
23 #define MT_EFUSE_CTRL_MODE GENMASK(7, 6)
26 #define MT_EFUSE_CTRL_AIN GENMASK(25, 16)
63 #define MT_XO_CTRL5_C2_VAL GENMASK(14, 8)
88 #define MT_INT_RX_DONE_ALL GENMASK(1, 0)
120 #define MT_WMM_AIFSN_MASK GENMASK(3, 0)
124 #define MT_WMM_CWMIN_MASK GENMASK(3, 0)
128 #define MT_WMM_CWMAX_MASK GENMASK(3, 0)
134 #define MT_WMM_TXOP_MASK GENMASK(15, 0)
157 #define MT_US_CYC_CNT GENMASK(7, 0)
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/linux/drivers/net/wireless/realtek/rtw88/
A Drtw8822c.h168 #define XCAP_MASK GENMASK(6, 0)
176 #define BIT_ANT_PATH GENMASK(1, 0)
220 #define BIT_BBMODE GENMASK(2, 1)
243 #define BIT_SUBPAGE GENMASK(3, 0)
265 #define BIT_Q_GAIN GENMASK(11, 0)
279 #define BIT_DPD_CLK GENMASK(7, 4)
319 #define BIT_ANTSEG GENMASK(3, 0)
323 #define BIT_STOP_TX GENMASK(3, 0)
351 #define BIT_RXAGC GENMASK(9, 5)
352 #define BIT_TXAGC GENMASK(4, 0)
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/linux/drivers/pinctrl/visconti/
A Dpinctrl-tmpv7700.c281 tmpv7700_GPIO_MUX(REG_PINMUX2, GENMASK(3, 0)),
282 tmpv7700_GPIO_MUX(REG_PINMUX2, GENMASK(7, 4)),
283 tmpv7700_GPIO_MUX(REG_PINMUX2, GENMASK(11, 8)),
289 tmpv7700_GPIO_MUX(REG_PINMUX3, GENMASK(3, 0)),
290 tmpv7700_GPIO_MUX(REG_PINMUX3, GENMASK(7, 4)),
291 tmpv7700_GPIO_MUX(REG_PINMUX3, GENMASK(11, 8)),
297 tmpv7700_GPIO_MUX(REG_PINMUX4, GENMASK(3, 0)),
298 tmpv7700_GPIO_MUX(REG_PINMUX4, GENMASK(7, 4)),
299 tmpv7700_GPIO_MUX(REG_PINMUX4, GENMASK(11, 8)),
305 tmpv7700_GPIO_MUX(REG_PINMUX5, GENMASK(3, 0)),
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/linux/drivers/mmc/host/
A Dmeson-mx-sdhc.h14 #define MESON_SDHC_SEND_CMD_INDEX GENMASK(5, 0)
22 #define MESON_SDHC_SEND_TOTAL_PACK GENMASK(31, 16)
25 #define MESON_SDHC_CTRL_DAT_TYPE GENMASK(1, 0)
28 #define MESON_SDHC_CTRL_PACK_LEN GENMASK(12, 4)
30 #define MESON_SDHC_CTRL_RX_PERIOD GENMASK(23, 20)
31 #define MESON_SDHC_CTRL_RX_ENDIAN GENMASK(26, 24)
34 #define MESON_SDHC_CTRL_TX_ENDIAN GENMASK(31, 29)
38 #define MESON_SDHC_STAT_DAT3_0 GENMASK(4, 1)
42 #define MESON_SDHC_STAT_DAT7_4 GENMASK(23, 20)
45 #define MESON_SDHC_CLKC_CLK_DIV GENMASK(11, 0)
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/linux/drivers/net/ethernet/stmicro/stmmac/
A Ddwxgmac2.h77 #define XGMAC_RQ GENMASK(7, 4)
92 #define XGMAC_PT GENMASK(31, 16)
164 #define XGMAC_DCS GENMASK(19, 16)
168 #define XGMAC_IDDR GENMASK(15, 8)
269 #define XGMAC_NVE GENMASK(7, 0)
273 #define XGMAC_ADDR GENMASK(9, 0)
290 #define XGMAC_TTC GENMASK(6, 4)
301 #define XGMAC_TSA GENMASK(1, 0)
310 #define XGMAC_RTC GENMASK(1, 0)
315 #define XGMAC_RFA GENMASK(15, 1)
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