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Searched refs:GENMASK_ULL (Results 1 – 25 of 205) sorted by relevance

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/linux/drivers/infiniband/hw/irdma/
A Ddefs.h483 #define IRDMACQ_QPID GENMASK_ULL(55, 32)
490 #define IRDMACQ_OP GENMASK_ULL(61, 56)
729 #define IRDMAQPC_TTL GENMASK_ULL(7, 0)
734 #define IRDMAQPC_TOS GENMASK_ULL(31, 24)
755 #define IRDMAQPC_PKEY GENMASK_ULL(47, 32)
757 #define IRDMAQPC_QKEY GENMASK_ULL(63, 32)
764 #define IRDMAQPC_ISN GENMASK_ULL(55, 32)
766 #define IRDMAQPC_LSN GENMASK_ULL(55, 32)
769 #define IRDMAQPC_EPSN GENMASK_ULL(23, 0)
775 #define IRDMAQPC_SRTT GENMASK_ULL(31, 0)
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A Duda_d.h25 #define IRDMA_UDA_QPSQ_AHIDX GENMASK_ULL(16, 0)
26 #define IRDMA_UDA_QPSQ_PROTOCOL GENMASK_ULL(23, 16)
29 #define IRDMA_UDA_QPSQ_MACLEN GENMASK_ULL(62, 56)
31 #define IRDMA_UDA_QPSQ_IPLEN GENMASK_ULL(54, 48)
33 #define IRDMA_UDA_QPSQ_L4T GENMASK_ULL(31, 30)
35 #define IRDMA_UDA_QPSQ_IIPT GENMASK_ULL(29, 28)
41 #define IRDMA_UDA_QPSQ_IMMDATA GENMASK_ULL(63, 0)
78 #define IRDMA_UDAQPC_IPID GENMASK_ULL(47, 32)
79 #define IRDMA_UDAQPC_SNDMSS GENMASK_ULL(29, 16)
80 #define IRDMA_UDAQPC_VLANTAG GENMASK_ULL(15, 0)
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A Dicrdma_hw.h54 #define ICRDMA_CQPSQ_STAG_PDID GENMASK_ULL(63, 46)
56 #define ICRDMA_CQPSQ_CQ_CEQID GENMASK_ULL(31, 22)
58 #define ICRDMA_CQPSQ_CQ_CQID GENMASK_ULL(18, 0)
60 #define ICRDMA_COMMIT_FPM_CQCNT GENMASK_ULL(19, 0)
/linux/drivers/iommu/arm/arm-smmu-v3/
A Darm-smmu-v3.h205 #define STRTAB_STE_0_CFG GENMASK_ULL(3, 1)
324 #define CMDQ_0_OP GENMASK_ULL(7, 0)
379 #define EVTQ_0_ID GENMASK_ULL(7, 0)
387 #define EVTQ_0_SSID GENMASK_ULL(31, 12)
388 #define EVTQ_0_SID GENMASK_ULL(63, 32)
389 #define EVTQ_1_STAG GENMASK_ULL(15, 0)
395 #define EVTQ_1_CLASS GENMASK_ULL(41, 40)
397 #define EVTQ_2_ADDR GENMASK_ULL(63, 0)
398 #define EVTQ_3_IPA GENMASK_ULL(51, 12)
405 #define PRIQ_0_SID GENMASK_ULL(31, 0)
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/linux/drivers/net/ethernet/marvell/octeontx2/af/
A Dcgx_fw_if.h170 #define EVTREG_ID GENMASK_ULL(8, 3)
177 #define EVTREG_ERRTYPE GENMASK_ULL(18, 9)
182 #define RESP_MAJOR_VER GENMASK_ULL(12, 9)
183 #define RESP_MINOR_VER GENMASK_ULL(16, 13)
188 #define RESP_MAC_ADDR GENMASK_ULL(56, 9)
203 #define RESP_FWD_BASE GENMASK_ULL(56, 9)
228 #define RESP_LINKSTAT_UP GENMASK_ULL(9, 9)
232 #define RESP_LINKSTAT_AN GENMASK_ULL(25, 25)
240 #define CMDREG_ID GENMASK_ULL(7, 2)
249 #define CMDMTU_SIZE GENMASK_ULL(23, 8)
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A Dnpc.h384 #define NPC_PARSE_NIBBLE GENMASK_ULL(30, 0)
426 #define RX_VTAG0_TYPE_MASK GENMASK_ULL(14, 12)
427 #define RX_VTAG0_LID_MASK GENMASK_ULL(10, 8)
428 #define RX_VTAG0_RELPTR_MASK GENMASK_ULL(7, 0)
431 #define RX_VTAG1_LID_MASK GENMASK_ULL(42, 40)
435 #define TX_VTAG0_DEF_MASK GENMASK_ULL(25, 16)
436 #define TX_VTAG0_OP_MASK GENMASK_ULL(13, 12)
437 #define TX_VTAG0_LID_MASK GENMASK_ULL(10, 8)
439 #define TX_VTAG1_DEF_MASK GENMASK_ULL(57, 48)
440 #define TX_VTAG1_OP_MASK GENMASK_ULL(45, 44)
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/linux/drivers/platform/mellanox/
A Dmlxbf-tmfifo-regs.h18 #define MLXBF_TMFIFO_TX_STS__COUNT_RMASK GENMASK_ULL(8, 0)
19 #define MLXBF_TMFIFO_TX_STS__COUNT_MASK GENMASK_ULL(8, 0)
25 #define MLXBF_TMFIFO_TX_CTL__LWM_RMASK GENMASK_ULL(7, 0)
26 #define MLXBF_TMFIFO_TX_CTL__LWM_MASK GENMASK_ULL(7, 0)
30 #define MLXBF_TMFIFO_TX_CTL__HWM_RMASK GENMASK_ULL(7, 0)
31 #define MLXBF_TMFIFO_TX_CTL__HWM_MASK GENMASK_ULL(15, 8)
43 #define MLXBF_TMFIFO_RX_STS__COUNT_RMASK GENMASK_ULL(8, 0)
50 #define MLXBF_TMFIFO_RX_CTL__LWM_RMASK GENMASK_ULL(7, 0)
51 #define MLXBF_TMFIFO_RX_CTL__LWM_MASK GENMASK_ULL(7, 0)
55 #define MLXBF_TMFIFO_RX_CTL__HWM_RMASK GENMASK_ULL(7, 0)
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/linux/drivers/mmc/host/
A Dcavium.h133 #define MIO_EMM_CMD_BUS_ID GENMASK_ULL(61, 60)
136 #define MIO_EMM_CMD_OFFSET GENMASK_ULL(54, 49)
137 #define MIO_EMM_CMD_CTYPE_XOR GENMASK_ULL(42, 41)
139 #define MIO_EMM_CMD_IDX GENMASK_ULL(37, 32)
140 #define MIO_EMM_CMD_ARG GENMASK_ULL(31, 0)
143 #define MIO_EMM_DMA_BUS_ID GENMASK_ULL(61, 60)
147 #define MIO_EMM_DMA_THRES GENMASK_ULL(56, 51)
152 #define MIO_EMM_DMA_CARD_ADDR GENMASK_ULL(31, 0)
161 #define MIO_EMM_DMA_CFG_SIZE GENMASK_ULL(55, 36)
162 #define MIO_EMM_DMA_CFG_ADR GENMASK_ULL(35, 0)
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/linux/tools/perf/util/arm-spe-decoder/
A Darm-spe-pkt-decoder.h44 #define SPE_HEADER0_MASK1 (GENMASK_ULL(7, 6) | GENMASK_ULL(3, 0))
48 #define SPE_HEADER0_MASK2 GENMASK_ULL(7, 2)
54 #define SPE_HEADER0_MASK3 GENMASK_ULL(7, 3)
59 #define SPE_HDR_SHORT_INDEX(h) ((h) & GENMASK_ULL(2, 0))
71 #define SPE_ADDR_PKT_ADDR_GET_BYTES_0_6(v) ((v) & GENMASK_ULL(55, 0))
75 #define SPE_ADDR_PKT_GET_EL(v) (((v) & GENMASK_ULL(62, 61)) >> 61)
77 #define SPE_ADDR_PKT_GET_PAT(v) (((v) & GENMASK_ULL(59, 56)) >> 56)
85 #define SPE_CTX_PKT_HDR_INDEX(h) ((h) & GENMASK_ULL(1, 0))
111 #define SPE_OP_PKT_HDR_CLASS(h) ((h) & GENMASK_ULL(1, 0))
120 #define SPE_OP_PKT_LDST_SUBCLASS_GET(v) ((v) & GENMASK_ULL(7, 1))
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/linux/drivers/fpga/
A Ddfl.h71 #define DFH_ID GENMASK_ULL(11, 0) /* Feature ID */
74 #define DFH_REVISION GENMASK_ULL(15, 12) /* Feature revision */
75 #define DFH_NEXT_HDR_OFST GENMASK_ULL(39, 16) /* Offset to next DFH */
77 #define DFH_TYPE GENMASK_ULL(63, 60) /* Feature type */
102 #define FME_CAP_NUM_PORTS GENMASK_ULL(19, 17) /* Number of ports */
104 #define FME_CAP_CACHE_SIZE GENMASK_ULL(43, 32) /* cache size in KB */
105 #define FME_CAP_CACHE_ASSOC GENMASK_ULL(47, 44) /* Associativity */
109 #define FME_PORT_OFST_DFH_OFST GENMASK_ULL(23, 0)
111 #define FME_PORT_OFST_BAR_ID GENMASK_ULL(34, 32)
139 #define PORT_CAP_PORT_NUM GENMASK_ULL(1, 0) /* ID of this port */
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A Ddfl-fme-perf.c31 #define CACHE_CTRL_EVNT GENMASK_ULL(19, 16)
50 #define CACHE_CNTR_EVNT GENMASK_ULL(63, 60)
60 #define FAB_CTRL_EVNT GENMASK_ULL(19, 16)
70 #define FAB_PORT_ID GENMASK_ULL(21, 20)
75 #define FAB_CNTR_EVNT_CNTR GENMASK_ULL(59, 0)
76 #define FAB_CNTR_EVNT GENMASK_ULL(63, 60)
95 #define VTD_CTRL_EVNT GENMASK_ULL(19, 16)
106 #define VTD_CNTR_EVNT GENMASK_ULL(63, 60)
199 #define FME_EVENT_MASK GENMASK_ULL(11, 0)
201 #define FME_EVTYPE_MASK GENMASK_ULL(15, 12)
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/linux/drivers/net/wireless/realtek/rtw89/
A Dphy.h30 #define RA_MASK_CCK_RATES GENMASK_ULL(3, 0)
31 #define RA_MASK_OFDM_RATES GENMASK_ULL(11, 4)
34 #define RA_MASK_HT_1SS_RATES GENMASK_ULL(19, 12)
35 #define RA_MASK_HT_2SS_RATES GENMASK_ULL(31, 24)
36 #define RA_MASK_HT_3SS_RATES GENMASK_ULL(43, 36)
37 #define RA_MASK_HT_4SS_RATES GENMASK_ULL(55, 48)
38 #define RA_MASK_HT_RATES GENMASK_ULL(55, 12)
43 #define RA_MASK_VHT_RATES GENMASK_ULL(57, 12)
44 #define RA_MASK_HE_1SS_RATES GENMASK_ULL(23, 12)
45 #define RA_MASK_HE_2SS_RATES GENMASK_ULL(35, 24)
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/linux/drivers/iommu/intel/
A Dcap_audit.h18 #define CAP_MAMV_MASK GENMASK_ULL(53, 48)
19 #define CAP_NFR_MASK GENMASK_ULL(47, 40)
21 #define CAP_SLLPS_MASK GENMASK_ULL(37, 34)
22 #define CAP_FRO_MASK GENMASK_ULL(33, 24)
24 #define CAP_MGAW_MASK GENMASK_ULL(21, 16)
25 #define CAP_SAGAW_MASK GENMASK_ULL(12, 8)
31 #define CAP_NDOMS_MASK GENMASK_ULL(2, 0)
46 #define ECAP_PSS_MASK GENMASK_ULL(39, 35)
54 #define ECAP_MHMV_MASK GENMASK_ULL(23, 20)
55 #define ECAP_IRO_MASK GENMASK_ULL(17, 8)
/linux/lib/
A Dtest_bits.c29 KUNIT_EXPECT_EQ(test, 1ull, GENMASK_ULL(0, 0)); in genmask_ull_test()
30 KUNIT_EXPECT_EQ(test, 3ull, GENMASK_ULL(1, 0)); in genmask_ull_test()
31 KUNIT_EXPECT_EQ(test, 0x000000ffffe00000ull, GENMASK_ULL(39, 21)); in genmask_ull_test()
32 KUNIT_EXPECT_EQ(test, 0xffffffffffffffffull, GENMASK_ULL(63, 0)); in genmask_ull_test()
36 GENMASK_ULL(0, 1); in genmask_ull_test()
37 GENMASK_ULL(0, 10); in genmask_ull_test()
38 GENMASK_ULL(9, 10); in genmask_ull_test()
/linux/include/linux/irqchip/
A Darm-gic-v3.h247 #define GICR_TYPER_AFFINITY GENMASK_ULL(63, 32)
249 #define GICR_INVLPIR_INTID GENMASK_ULL(31, 0)
250 #define GICR_INVLPIR_VPEID GENMASK_ULL(47, 32)
251 #define GICR_INVLPIR_V GENMASK_ULL(63, 63)
302 #define GICR_VPROPBASER_4_1_ADDR GENMASK_ULL(51, 12)
303 #define GICR_VPROPBASER_4_1_SIZE GENMASK_ULL(6, 0)
382 #define GITS_SGIR_VPEID GENMASK_ULL(47, 32)
383 #define GITS_SGIR_VINTID GENMASK_ULL(3, 0)
394 #define GITS_TYPER_ITT_ENTRY_SIZE GENMASK_ULL(7, 4)
397 #define GITS_TYPER_DEVBITS GENMASK_ULL(17, 13)
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/linux/arch/arm64/kvm/vgic/
A Dvgic.h72 #define KVM_ITS_CTE_ICID_MASK GENMASK_ULL(15, 0)
75 #define KVM_ITS_ITE_PINTID_MASK GENMASK_ULL(47, 16)
76 #define KVM_ITS_ITE_ICID_MASK GENMASK_ULL(15, 0)
80 #define KVM_ITS_DTE_NEXT_MASK GENMASK_ULL(62, 49)
82 #define KVM_ITS_DTE_ITTADDR_MASK GENMASK_ULL(48, 5)
83 #define KVM_ITS_DTE_SIZE_MASK GENMASK_ULL(4, 0)
86 #define KVM_ITS_L1E_ADDR_MASK GENMASK_ULL(51, 16)
88 #define KVM_VGIC_V3_RDIST_INDEX_MASK GENMASK_ULL(11, 0)
89 #define KVM_VGIC_V3_RDIST_FLAGS_MASK GENMASK_ULL(15, 12)
91 #define KVM_VGIC_V3_RDIST_BASE_MASK GENMASK_ULL(51, 16)
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/linux/drivers/firmware/efi/
A Dcper-x86.c13 #define VALID_PROC_ERR_INFO_NUM(bits) (((bits) & GENMASK_ULL(7, 2)) >> 2)
14 #define VALID_PROC_CXT_INFO_NUM(bits) (((bits) & GENMASK_ULL(13, 8)) >> 8)
48 #define CHECK_VALID_BITS(check) (((check) & GENMASK_ULL(15, 0)))
49 #define CHECK_TRANS_TYPE(check) (((check) & GENMASK_ULL(17, 16)) >> 16)
50 #define CHECK_OPERATION(check) (((check) & GENMASK_ULL(21, 18)) >> 18)
51 #define CHECK_LEVEL(check) (((check) & GENMASK_ULL(24, 22)) >> 22)
58 #define CHECK_BUS_PART_TYPE(check) (((check) & GENMASK_ULL(31, 30)) >> 30)
60 #define CHECK_BUS_ADDR_SPACE(check) (((check) & GENMASK_ULL(34, 33)) >> 33)
69 #define CHECK_MS_ERR_TYPE(check) (((check) & GENMASK_ULL(18, 16)) >> 16)
/linux/drivers/gpu/drm/i915/
A Di915_buddy.h16 #define I915_BUDDY_HEADER_OFFSET GENMASK_ULL(63, 12)
17 #define I915_BUDDY_HEADER_STATE GENMASK_ULL(11, 10)
22 #define I915_BUDDY_HEADER_UNUSED GENMASK_ULL(9, 6)
23 #define I915_BUDDY_HEADER_ORDER GENMASK_ULL(5, 0)
/linux/drivers/spi/
A Dspi-altera-dfl.c32 #define DATA_WIDTH GENMASK_ULL(7, 2)
33 #define NUM_CHIPSELECT GENMASK_ULL(13, 8)
36 #define PERIPHERAL_ID GENMASK_ULL(47, 32)
37 #define SPI_CLK GENMASK_ULL(31, 22)
44 #define INDIRECT_DATA_MASK GENMASK_ULL(31, 0)
/linux/include/linux/i3c/
A Ddevice.h79 #define I3C_PID_MANUF_ID(pid) (((pid) & GENMASK_ULL(47, 33)) >> 33)
81 #define I3C_PID_RND_VAL(pid) ((pid) & GENMASK_ULL(31, 0))
82 #define I3C_PID_PART_ID(pid) (((pid) & GENMASK_ULL(31, 16)) >> 16)
83 #define I3C_PID_INSTANCE_ID(pid) (((pid) & GENMASK_ULL(15, 12)) >> 12)
84 #define I3C_PID_EXTRA_INFO(pid) ((pid) & GENMASK_ULL(11, 0))
/linux/drivers/net/ethernet/netronome/nfp/nfpcore/
A Dnfp_nsp_eth.c24 #define NSP_ETH_PORT_LANES GENMASK_ULL(3, 0)
25 #define NSP_ETH_PORT_INDEX GENMASK_ULL(15, 8)
26 #define NSP_ETH_PORT_LABEL GENMASK_ULL(53, 48)
27 #define NSP_ETH_PORT_PHYLABEL GENMASK_ULL(59, 54)
37 #define NSP_ETH_STATE_RATE GENMASK_ULL(11, 8)
38 #define NSP_ETH_STATE_INTERFACE GENMASK_ULL(19, 12)
39 #define NSP_ETH_STATE_MEDIA GENMASK_ULL(21, 20)
41 #define NSP_ETH_STATE_ANEG GENMASK_ULL(25, 23)
42 #define NSP_ETH_STATE_FEC GENMASK_ULL(27, 26)
A Dnfp_nsp.c31 #define NSP_STATUS_MAGIC GENMASK_ULL(63, 48)
32 #define NSP_STATUS_MAJOR GENMASK_ULL(47, 44)
33 #define NSP_STATUS_MINOR GENMASK_ULL(43, 32)
34 #define NSP_STATUS_CODE GENMASK_ULL(31, 16)
35 #define NSP_STATUS_RESULT GENMASK_ULL(15, 8)
39 #define NSP_COMMAND_OPTION GENMASK_ULL(63, 32)
40 #define NSP_COMMAND_CODE GENMASK_ULL(31, 16)
46 #define NSP_BUFFER_CPP GENMASK_ULL(63, 40)
47 #define NSP_BUFFER_ADDRESS GENMASK_ULL(39, 0)
50 #define NSP_DFLT_BUFFER_CPP GENMASK_ULL(63, 40)
[all …]
/linux/drivers/cxl/
A Dcxl.h55 #define CXLDEV_CAP_ARRAY_ID_MASK GENMASK_ULL(15, 0)
56 #define CXLDEV_CAP_ARRAY_COUNT_MASK GENMASK_ULL(47, 32)
71 #define CXLDEV_MBOX_CMD_COMMAND_OPCODE_MASK GENMASK_ULL(15, 0)
72 #define CXLDEV_MBOX_CMD_PAYLOAD_LENGTH_MASK GENMASK_ULL(36, 16)
74 #define CXLDEV_MBOX_STATUS_RET_CODE_MASK GENMASK_ULL(47, 32)
/linux/drivers/gpu/drm/amd/amdgpu/
A Damdgpu_debugfs.c102 me = (*pos & GENMASK_ULL(33, 24)) >> 24; in amdgpu_debugfs_process_reg_op()
103 pipe = (*pos & GENMASK_ULL(43, 34)) >> 34; in amdgpu_debugfs_process_reg_op()
104 queue = (*pos & GENMASK_ULL(53, 44)) >> 44; in amdgpu_debugfs_process_reg_op()
105 vmid = (*pos & GENMASK_ULL(58, 54)) >> 54; in amdgpu_debugfs_process_reg_op()
897 offset = (*pos & GENMASK_ULL(6, 0)); in amdgpu_debugfs_wave_read()
898 se = (*pos & GENMASK_ULL(14, 7)) >> 7; in amdgpu_debugfs_wave_read()
899 sh = (*pos & GENMASK_ULL(22, 15)) >> 15; in amdgpu_debugfs_wave_read()
900 cu = (*pos & GENMASK_ULL(30, 23)) >> 23; in amdgpu_debugfs_wave_read()
990 se = (*pos & GENMASK_ULL(19, 12)) >> 12; in amdgpu_debugfs_gpr_read()
991 sh = (*pos & GENMASK_ULL(27, 20)) >> 20; in amdgpu_debugfs_gpr_read()
[all …]
/linux/arch/x86/include/asm/
A Dsgx.h79 #define SGX_MISC_RESERVED_MASK GENMASK_ULL(63, 1)
105 #define SGX_ATTR_RESERVED_MASK (BIT_ULL(3) | BIT_ULL(6) | GENMASK_ULL(63, 8))
157 #define SGX_TCS_RESERVED_MASK GENMASK_ULL(63, 1)
253 #define SGX_SECINFO_PERMISSION_MASK GENMASK_ULL(2, 0)

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